UNIT 4 LINEAR INTEGRATED CIRCUITS-DIGITAL ICS

LIC UNIT IV

1. UNIT–IV- Digital Integrated Circuits Digital Integrated Circuits: Classification of Integrated Circuits, Comparison of Various Logic Families, CMOS Transmission Gate, IC interfacing. TTL Driving CMOS & CMOS Driving TTL, Combinational Logic ICs – Specifications and Applications of TTL-74XX & CMOS 40XX Series ICs – Code Converters, Decoders, Demultiplexers, LED & LCD Decoders with Drivers, Encoders, Priority Encoders, Multiplexers, Demultiplexers, Parity Generators/Checkers, Parallel Binary Adder/ Subtractor , Magnitude Comparators.

2. I n t r odu c tion WHAT IS INTEGRATED CIRCUITS ? A complex set of electronic components and their interconnections that are imprinted onto a tiny slice of semiconducting material. Integrated Circuits are usually called ICs or chips.

3. Integrated circuits were made possible by experimental discoveries which showed that semiconductor devices could perform the functions of vacuum tubes and by mid- 20th- c entury technology advancements in semiconductor device fabrication. Contd …

4. The integration of large numbers of tiny transistors into a small chip was an enormous improvement over the manual assembly of circuits using electronic components. The integrated circuit's mass production capability , reliability, and building-block approach to circuit design ensured the rapid adoption of standardized ICs in place of designs using discrete transistors.

5. Structure of IC

6. 1 Monolithic IC’s 2 Thick and Thin film IC’s 3 Hybrid IC’s Classification of IC

7. Monolithic IC’s A Monolithic Microwave Integrated Circuit, or MMIC is a type of integrated circuit (IC) device that operates at microwave frequencies . devices typically s uch a s m i crow a ve pe r f orm m i xi n g , These fu n ct i ons power a m pl i f ic ati o n, lo w - n oise a n d hig h - freq u e n cy a m p l i f ic ati o n , switching.

8. Inputs and outputs on MMIC devices are frequently matched to a characteristic impedance of 50 ohms. This makes them easier to use, as cascading of MMICs does not then require an external matching network .

9. Thick & Thin Film IC’s The general characteristic, and app e ar a nce of thin and p r o p erti e s, thi c k - film simila r , although integrated t h ey both circuits are d i f fer in m any r e s p e c t f r om monolithic integrated circuits. They are not formed within a semiconductor wafer but on the surface of an insulating substrate such as glass or an appropriate ceramic material.

10. The primary difference between the thin-and-thick-film techniques is the process employed for the forming the passive component and the metallic conduction pattern. The thin-film circuit employs an evaporation or cathode- sputtering technique; the thick film employs silk-screen techniques.

11. A hybrid integrated circuit, HIC, hybrid microcircuit, or simply hybrid is a miniaturized electronic circuit constructed of individual devices, such as semiconductor devices (e.g. transistors and diodes ) and passive components (e.g. resistors , inductors, transformers, and capacitors ), bonded to a substrate or printed circuit board (PCB). H y b r i d I C ’ s ( H I C )

12. Hybrid circuits are often encapsulated in epoxy , as shown in the photo. A hybrid circuit serves as a component on a PCB in the same way as a monolithic integrated circuit . The difference between the two types of devices is in how they are constructed and manufactured.

13. Comparison of Various ICs

14. Generations of IC’s SSI MSI LSI VLSI VVLSI WSI NANO TECHNOLOGY

15. Scale of integration

16. Small Scale Integration (SSI) Normally it has about 20 components. The Minuteman missile and Apollo program needed lightweight digital computers for their initially-guided flight computers. The Apollo guidance computer led and motivated the integrated-circuit technology, while the Minuteman missile forced it into mass-production.

17. Medium Scale Integration (MSI) It can have about 100 components. Medium Scale Integration came in to industry in late 1960s. MSI is the next step in the development of integrated circuits after 'Small Scale Integration'. Medium-Scale Integration allowed more complex systems to be produced using smaller circuit boards than in SSI (Small Scale Integration).

18. Large Scale integration (LSI) It have about 1000 components. LSI is the process of integrating or embedding thousands of transistors on single silicon semiconductor microchip. LSI technology was conceived in mid-1970s when computer processor microchips were under development

19. V ery Large Scale Integration ( V LSI ) Very large scale integration. It can have about 10,000 components. VLSI began in the 1970s , when c omp lex semic o nd u c t or and co m munication technologies were being developed.

20. Wafer Scale Integration(WSI) The evolution in semiconductor technology that builds a gigantic circuit on an entire wafer. Just as the integrated circuit eliminated cutting apart thousands of transistors from the wafer only to wire them back again on circuit boards, wafer scale integration eliminates cutting apart the chips.

21. Advantages of Integrate Circuit It is quite small in size practically around 20,000 electronic components can be incorporated in a single square inch of IC chip. Many complex circuits are fabricated in a single chip and hence this simplifies the designing of a complex electronic circuit. Also it improves the performance. Reliability of ICs is high These are available at low cost due to bulk production. ICs consume very tiny power. Higher operating speed due to absence of parasitic capacitance effect. Very easily replaceable from the mother circuit.

22. Disadvantages of Integrate Circuit or IC IC is unable to dissipate heat in required rate when  current  in it increased. That is why ICs are often damaged due to over current flowing through them. Inductors  and  Transformers  cannot be incorporated in  ICs .

23. IC’s Packages Single Inline Packaging Dual Inline Packaging Zigzag Inline packaging

24. Single Inline Packaging (SIP) A single in-line (pin) package (SIP or SIPP) has one row of connecting pins. It is not as popular as the DIP, but has been used for packaging RAM chips and multiple resistors with a common pin. SIPs group RAM chips together on a small board either by the DIP process or surface mounting SMD process.

25. Dual Inline Packaging (DIP) A dual in-line package is an electronic component package with a rectangular housing and two parallel rows of electrical connecting pins. The package may be through-hole mounted to a printed circuit board or inserted in a socket.

26. Zigzag Inline Packaging The zigzag in-line package or ZIP was a short-lived packaging technology for integrated circuits , particularly dynamic RAM chips. A ZIP is an integrated circuit encapsulated in a slab of plastic with 20 or 40 pins, measuring (for the ZIP-20 package) about 3 mm x 30 mm x 10 mm. The package's pins protrude in two rows from one of the long edges. The two rows are staggered by 1.27 mm (0.05"), giving them a zigzag appearance, and allowing them to be spaced more closely than a rectangular grid would allow

27. Zigzag Inline Packaging

28. Logic Family Logic Families indicate the type of logic circuit used in the IC. A Circuit configuration or arrangement of the circuit elements in a special manner will result in a particular Logic Family. The set of digital ICs belonging to the same logic family are electrically compatible with each other

29. Logic Families Logic Family : A collection of different IC’s that have similar circuit characteristics The circuit design of the basic gate of each logic family is the same The most important parameters for evaluating and comparing logic families include : Logic Levels Power Dissipation Propagation delay Noise margin Fan-out ( loading )

30. Example Logic Families General comparison or three commonly available logic families. the most important to understand

31. Implementing Logic Circuits There are several varieties of transistors – the building blocks of logic gates – the most important are: BJT (bipolar junction transistors) one of the first to be invented FET (field effect transistors) especially Metal-Oxide Semiconductor types (MOSFET’s) MOSFET’s are of two types: NMOS and PMOS

32. Transistor Size Scaling Performance improves as size is decreased: shorter switching time, lower power consumption. 2 orders of magnitude reduction in transistor size in 30 years.

33. Moore’s Law In 1965, Gordon Moore predicted that the number of transistors that can be integrated on a die would double every 18 to 24 months i.e., grow exponentially with time Considered a visionary – million transistor/chip barrier was crossed in the 1980’s 2300 transistors, 1 MHz clock (Intel 4004/4040) - 1971 42 Million transistors, 2 GHz clock (Intel P4) - 2001 140 Million transistors, (HP PA-8500)

34. Moore’s Law and Intel From Intel’s 4040 (2300 transistors) to Pentium II (7,500,000 transistors) and beyond

35. TTL and CMOS Connecting BJT’s together gives rise to a family of logic gates known as TTL Connecting NMOS and PMOS transistors together gives rise to the CMOS family of logic gates BJT MOSFET (NMOS, PMOS) TTL CMOS transistor types logic gate families

36. Electrical Parameters And Interpretation Of Data Sheets Voltages and Currents Noise Margin Power Dissipation Propagation Delay Speed-Power Product Fan-In, Fan-Out Comparison of Logic Families Interpretation of Data Sheets

37. Electrical Characteristics TTL faster (some versions) strong drive capability rugged CMOS lower power consumption simpler to make greater packing density better noise immunity Complex IC’s contain many millions of transistors If constructed entirely from TTL type gates would melt A combination of technologies (families) may be used CMOS has become most popular and has had greatest development

38. For a Low-state gate driving a second gate, we define: V OL (max), low-level output voltage, the maximum voltage level that a logic gate will produce as a logic 0 output . V IL (max), low-level input voltage, the maximum voltage level that a logic gate will recognize as a logic 0 input . Voltage above this value will not be accepted as low. I OL , low-level output current, current that flows from an output in the logic 0 state under specified load conditions. I IL , low-level input current, current that flows into an input when a logic 0 voltage is applied to that input. Voltage & Current Inputs are connected to V cc instead of Ground Ground V IL V OL I OL I IL

39. Electrical Characteristics Important characteristics are: V OHmin min value of output recognized as a ‘1’ V IHmin min value input recognized as a ‘1’ V ILmax max value of input recognized as a ‘0’ V OLmax max value of output recognized as a ‘0’ Values outside the given range are not allowed. logic 0 logic 1 indeterminate input voltage

40. Typical acceptable voltage ranges for positive logic 1 and logic 0 are shown below A logic gate with an input at a voltage level within the ‘indeterminate’ range will produce an unpredictable output level. Logic Level & Voltage Range Logic 1 Logic 0 5.0 V V 2.5 V Indeterminate 0.8 V TTL Logic 1 Logic 0 5.0 V Indeterminate V 1.5 V CMOS 3.5 V

41. Noise Margin If noise in the circuit is high enough it can push a logic 0 up or drop a logic 1 down into the indeterminate or “illegal” region The magnitude of the voltage required to reach this level is the noise margin Noise margin for logic high is: N MH = V OHmin – V IHmin V OHmin V IHmin V ILmax V OLmax logic 0 logic 1 indeterminate input voltage

42. Noise Margin Difference between the worst case output voltage of one stage and worst case input voltage of next stage Greater the difference, the more unwanted signal that can be added without causing incorrect gate operation NM high = V OHmin - V IHmin NM low = V ILmax - V OLmax

43. Given the following parameters, calculate the noise margin of 74LS series. Solution: High Level Noise Margin, V NH = V OH (min) - V IH (min)=2.7V-2.0V=0.7V Low Level Noise Margin, V NL = V IL (max) - V OL (max)=0.8V-0.4V=0.4V Worked Example

44. Noise immunity of a logic circuit refers to the circuit’s ability to tolerate noise voltages on its inputs. A quantitative measure of noise immunity is called noise margin High Level Noise Margin, V NH = V OH (min) - V IH (min) Low Level Noise Margin, V NL = V IL (max) - V OL (max) Noise Margin & Noise Immunity Logic 1 Logic 0 Logic 0 Logic 1 V OH (min) V OL (max) V IH (min) V IL (max) V NH V NL Output Voltage Ranges Input Voltage Ranges

45. Further Important Characteristics The propagation delay (t pd ) which is the time taken for a change at the input to appear at the output The fan-out , which is the maximum number of inputs that can be driven successfully to either logic level before the output becomes invalid

46. Speed: Rise & Fall Times Rise Time Time from 10% to 90% of signal, Low to High Fall Time Time from 90% to 10% of signal, High to Low rise time 10% 90% 90% 10% fall time

47. A logic gate always takes some time to change states t PLH is the delay time before output changes from low to high t PHL is the delay time before output changes from high to low both t PLH & t PHL are measured between the 50% points on the input and output transitions Speed: Propagation Delay 50% Input Output t PHL t PLH

48. Power Dissipation Static I 2 R losses due to passive components, no input signal Dynamic I 2 R losses due to charging and discharging capacitances through resistances, due to input signal

49. Speed (propagation delay) and power consumption are the two most important performance parameters of a digital IC. A simple means for measuring and comparing the overall performance of an IC family is the speed-power product (the smaller, the better). For example, an IC has an average propagation delay of 10 ns an average power dissipation of 5 mW the speed-power product = (10 ns) x (5 mW) = 50 picoJoules (pJ) Speed-Power Product

50. Logic Family Tradeoffs Looking for the best speed/power product t p and Pd are normally included in the data sheet for each device Older logic families are the worst CMOS is one of the best FPGAs use CMOS

51. Comparison of Logic Families

52. TTL - Example SN74LS00 Recommended operating conditions V cc supply voltage 5V ± 0.5 V input voltages V IH = 2V V IL = 0.8V Electrical Characteristics output voltage V OH = 2.7V (worst case) V OL = 0.5V max input currents I IH = 20µA I IL = -0.4mA propagation delay t pd = 15 nS noise margins for a logic 0 = 0.3V for a logic 1 = 0.7V Fan-out 20 TTL loads 5 Volt 0 Volt 0.8 0.5 2.0 2.7 Input Range for 1 Input Range for 0 Output Range for 0 Output Range for 1

53. Fan-In Number of input signals to a gate Not an electrical property Function of the manufacturing process NAND gate with a Fan-in of 8

54. Fan-Out A measure of the ability of the output of one gate to drive the input(s) of subsequent gates Usually specified as standard loads within a single family e.g., an input to an inverter in the same family May have to compute based on current drive requirements when mixing families Although mixing families is not usually recommended

55. V OH I IH Low V OL I IL High Current Sourcing and Sinking Current-source : the driving gate produces a outgoing current Current-sinking : the driving gate receives an incoming current

56. Fan-Out An illustration of fan-out and the associated source and sink currents

57. SSI Devices Each package contains a code identifying the package N74LS00 Manufacturers Code N = National Semiconductors SN = Signetics Specification Family L LS H Member 00 = Quad 2 input NAND 02 = Quad 2 input Nor 04 = Hex Invertors 20 = Dual 4 Input NAND

58. 7400 Series History 1960s space program drove development of 7400 series Consumed all available devices for internal flight computer $1000 / device (1960 dollars) 10:1 integration improvement over discrete transistors 1963 Minuteman missile forced 7400 into mass production Drove pricing down to $25 / circuit (1963 dollars)

59. 7400 Series Evolution BJT storage time reduction by using a BC Schottky diode. Schottky diode has a Vfw =0.25V. When BC junction becomes forward biased Schottky diode will bypass base current. B C

60. Characteristics: TTL and MOS TTL stands for Transistor-Transistor Logic uses BJTs MOS stands for Metal Oxide Semiconductor uses FETs MOS can be classified into three sub-families: PMOS (P-channel) NMOS (N-channel) CMOS (Complementary MOS, most common) Remember:

61. A standard TTL NAND gate circuit Table explaining the operation of the TTL NAND gate circuit TTL Circuit Operation

62. Transistor-Transistor Logic Families T ransistor- T ransistor L ogic Families: 74L L ow power 74H H igh speed 74S S chottky 74LS L ow power S chottky 74AS A dvanced S chottky 74ALS A dvance L ow power S chottky

63. Table explaining the operation of the CMOS inverter circuit A CMOS inverter circuit MOS Circuit Operation

64. CMOS Logic Families CMOS Logic Families 40 xx/45xx Metal-gate CMOS 74C TTL-compatible C MOS 74HC H igh speed C MOS 74ACT A dvanced C MOS - T TL compatible

65. CMOS Family Evolution CMOS Logic Trend: Reduction of dynamic losses (cross-conduction, capacitive charge/discharge cycles) by decreasing supply voltages: 12V→5V →3.3V →2.5V → 1.8V → 1.5V … Reduction of IC power dissipation is the key to: lower cost (packaging) higher integration improved reliability

66. Comparison of Logic Families v i v o

67. A t r ans m is sion g a te i s si m ply a di g it a l co n tro l led CMOS switch. The CMOS transmission gate consists of one nMOS and one pMOS transistor connected in parallel.The gate voltages applied to these two transistors are also set to be complementary signals. A s such, t h e CM O S T G op e rat e s as a b i d ire c tion a l sw i tch between the nodes A and B which is controlled by signal C. Here ,the substrate terminal of the nMOS transistor is connected to ground and the substrate terminal of the pMOS transistor is connected to VDD.

68. CASE I : When the CONTROL input is high Here, the g ate of the pMOS t r a n si st o r i s h i gh and n M OS transistor is low. If the data input is low, V GS1 is positive and V GS2 is 0V ; so neither transistor is ON. If data input is high, V GS1 is 0V and V GS2 is negative; so again neither transistor is ON. Therefore, when CONTROL input is high, the device is in the high impedance state.

69. The figure below shows the operation of transmission gate when CONTROL input is high.

70. CASE II : When the CONTROL input is low Here, the gate of the pMOS transistor is low and nMOS transistor is high. If the data input is low, V GS1 is 0V and V GS2 is positive; therefore Q1 is OFF and Q2 is ON. If data input is high, V GS1 is negative and V GS2 is 0V; so Q1 is ON and Q2 is OFF. Thus, there is always a conduction path from input to output when control input is low.

71. The figure below shows the operation of transmission gate when CONTROL input is low :

72. For the DC analysis of the CMOS TG, we will consider the following bias conditions, as shown in figure below: DC analysis of the CMOS TG

73. The input node(A) is connected to a constant logic-high voltage, Vin=Vdd. The control signal is also logic high, thus ensuring that both transistors are turned ON. The output node (B) may be connected to a capacitor, which represents capacitive loading of the subsequent logic stages driven by TG. The drain-to-source and the gate-to-source voltages of the nMOS transistor are V DS,n =V DD -V out V GS,n = V DD - V out

74. Thus, the nMOS transistor will be turned OFF for V out >V DD -V T,n and will operate in the saturation mode for V out <V DD -V T,n . The V DS and V GS voltages of the pMOS transistor are V DS,p = V ou t - V DD V GS,p =-V DD Consequently, the pMOS transistor is in saturation for Vout<VT,p and it operates in the linear region for Vout>VT,p The total current flowing through TG is the sum of the nMOS drain current and the pMOS drain current. I D =I DS,n +I SD,p

75. The equivalent resistance for each transistor is given by R eq,n = V DD -V out I DS,p Req,p= V DD -V out I SD,p The total equivalent resistance of the CMOS Tgwill then be the parallel equivalent of these two resistances.

76. Here control input is separated into C and Ć. Input C is connected directly to nMOS gate whereas input Ć is connected to pMOS gate.

77. TTL and CMOS ICs When interfacing digital devices, in addition to understanding the voltage levels, it is also important to know the input and output current characteristics of the devices. Important characteristics are the amount of current a device can source (produce) when the output is high and the amount of current the device can sink (draw) when the output voltage is low. I OL – “low-level output current” for sinking capability when the output voltage is low I OH – “high-level output current” for sourcing capability when the output voltage is high

78. Advantages of CMOS devices When an output is unloaded or connected to other CMOS devices, CMOS requires power only when an output switches its logic state. Therefore, CMOS is useful in battery-operated applications where power is limited The wide power supply range of CMOS (3-18 V) provides more design flexibility and allows use of less tightly regulated power supplies. Disadvantages of CMOS: CMOS is sensitive to static discharge ; the devices are easily damaged CMOS requires negligible input current, but its output current is also small compared to TTL. This limits the ability of CMOS to drive large TTL fan-out or other high current devices.

79. CMOS and TTL Interfaces To achieve optimum performance in a digital system, devices from more than one logic family can be used, taking advantages of the superior characteristics of each family for different parts of the system. For example, CMOS logic ICs can be used in those parts of the system where low power dissipation is required, whereas TTL can be used for those portions of the system which require high speed of operation . Also, some function may be easily available in TTL and others may be available in CMOS. Therefore, it is necessary to examine the interface between CMOS and TTL devices . CMOS and TTL are the two most widely used logic families. Although ICs belonging to the same logic family have no special interface requirements The output of one can directly feed the input of the other, the same is not true if we have to interconnect digital ICs belonging to different logic families. Incompatibility of ICs belonging to different families mainly arises from different voltage levels and current requirements associated with LOW and HIGH logic states at the inputs and outputs.

80. Interfacing Interfacing: Sourcing/Sinking Current Output Low -> Input Low: Output sinks current <- Input sources current Output High -> Input High: Output sources current -> Input sinks current The good news: CMOS inputs require very small currents

81. CSE 477 Interfacing 84 Data Book for CMOS

82. CSE 477 Interfacing 85 TTL Databook Bad news: inputs source/sink substantial current

83. CMOS driving TTL CMOS-to-TTL interface with both devices operating from 5V supply and the CMOS IC driving a low-power TTL or a low-power Schottky TTL device . CMOS-to-TTL interface where the TTL device in use is either a standard TTL or a Schottky TTL. CSE 477 Interfacing 86

84. TTL Driving CMOS In the TTL-to-CMOS interface, current compatibility is always there. The voltage level compatibility in the two states is a problem. VOH (min.) of TTL devices is too low as regards the VIH (min.) requirement of CMOS devices. When the two devices are operating on the same power supply voltage, that is, 5 V, a pull-up resistor of 10 k_ achieves compatibility  The pull-up resistor causes the TTL output to rise to about 5V when HIGH. When the two are operating on different power supplies, one of the simplest interface techniques is to use a transistor (as a switch) in-between the two, as shown below. CSE 477 Interfacing 87

85. Interfacing TTL and CMOS devices The output of a TTL device sinks current when it is low and sources current when it is high. The TTL low sink current (IoJ is the limiting factor when interfacing to mul- tiple TTL inputs. A TTL output can drive up to 10 standard TTL inputs or up to 40 Low-power Schottky (LS) TTL inputs. TTL outputs are easy to interface to CMOS due to the insulating gate input, which draws no steady state current. It is necessary only to ensure voltages match when connecting TTL outputs to CMOS inputs.

86. Interfacing TTL and CMOS devices When using ICs of one logic family exclusively, you need not be concerned with voltage levels and current drives as long as the fan-out is less than 10 for TTL (CMOS can be higher). CMOS is better for general use because it draws no current unless switching, and the output swings nearly from ground to the positive supply value. However, at high frequency, CMOS can dissipate nearly the power required by an equivalent TTL circuit. Department of Mechanical Engineering

87. CSE 477 Interfacing 90 TTL/CMOS Interfacing HCT/ACT directly compatible with TTL HC/AC is not

88. CSE 477 Interfacing 91 CMOS/TTL Interfacing

89. CSE 477 Interfacing 92 CMOS/TTL Interfacing In the LOW state, a  TTL  output  can drive CMOS  directly. However, the guaranteed  TTL  HIGH output level of 2.4 volts is not a valid input level for  CMOS . If the  TTL  output  drives  only  CMOS  inputs, then essentially no current is drawn and the HIGH output may be 3.5 V or higher.

90. Combinational Logic ICs – Specifications and Applications of TTL-74XX & CMOS 40XX Series ICs CSE 477 Interfacing 93

91. 74 series families The  74LS  (Low-power Schottky ) family (like the original) uses TTL (Transistor-Transistor Logic) circuitry which is fast but requires more power than later families. The 74 series is often still called the 'TTL series' even though the latest ICs do not use TTL! The  74HC  family has High-speed CMOS circuitry, combining the speed of TTL with the very low power consumption of the  4000 series . They are CMOS ICs with the same pin arrangements as the older 74LS family. Note that 74HC inputs cannot be reliably driven by 74LS outputs because the voltage ranges used for logic 0 are not quite compatible, use 74HCT instead. The  74HCT  family is a special version of 74HC with 74LS TTL-compatible inputs so 74HCT can be safely mixed with 74LS in the same system. In fact 74HCT can be used as low-power direct replacements for the older 74LS ICs in most circuits. The minor disadvantage of 74HCT is a lower immunity to noise, but this is unlikely to be a problem in most situations. For most new projects the 74HC family is the best choice.  The 74LS and 74HCT families require a 5V supply so they are not convenient for battery operation.

92. 74LS family TTL characteristics Supply:  5V ±0.25V, it must be very smooth, a regulated supply is best. In addition to the normal supply smoothing, a 0.1µF capacitor should be connected across the supply near the IC to remove the 'spikes' generated as it switches state, one capacitor is needed for every 4 ICs . Inputs  'float' high to logic 1 if unconnected, but do not rely on this in a permanent (soldered) circuit because the inputs may pick up electrical noise. 1mA must be drawn out to hold inputs at logic 0. In a permanent circuit it is wise to connect any unused inputs to + Vs to ensure good immunity to noise. Outputs  can  sink  up to 16mA (enough to light an LED), but they can  source  only about 2mA. To switch larger currents you can  connect a transistor . Fan-out : one output can drive up to 10 74LS inputs, but many more 74HCT inputs. Gate propagation time : about 10ns for a signal to travel through a gate. Frequency : up to about 35MHz (under the right conditions). Power consumption  (of the IC itself) is a few mW .

93. 74HC and 74HCT family characteristics The CMOS circuitry used in the  74HC  and  74HCT  series ICs means that they are  static sensitive . Touching a pin while charged with static electricity (from your clothes for example) may damage the IC. In fact most ICs in regular use are quite tolerant and earthing your hands by touching a metal water pipe or window frame before handling them will be adequate. ICs should be left in their protective packaging until you are ready to use them. 74HC Supply:  2 to 6V, small fluctuations are tolerated. 74HCT Supply:  5V ±0.5V, a regulated supply is best. Inputs  have very high impedance (resistance), this is good because it means they will not affect the part of the circuit where they are connected. However, it also means that unconnected inputs can easily pick up electrical noise and rapidly change between high and low states in an unpredictable way. This is likely to make the IC behave erratically and it will significantly increase the supply current. To prevent problems  all unused inputs MUST be connected to the supply (either + Vs or 0V) , this applies even if that part of the IC is not being used in the circuit! Note that 74HC inputs cannot be reliably driven by 74LS outputs  because the voltage ranges used for logic 0 are not quite compatible. For reliability use  74HCT  if the system includes some 74LS ICs.

94. Outputs  can  sink and source  about 4mA if you wish to maintain the correct output voltage to drive logic inputs, but if there is no need to drive any inputs the maximum current is about 20mA. To switch larger currents you can  connect a transistor . Fan-out:  one output can drive many inputs (50+), except 74LS inputs because these require a higher current and only 10 can be driven. Gate propagation time : about 10ns for a signal to travel through a gate. Frequency : up to 25MHz. Power consumption  (of the IC itself) is very low, a few µW. It is much greater at high frequencies, a few mW at 1MHz for example.

95. 7400 quad 2-input NAND 7403 quad 2-input NAND with open collector outputs 7408 quad 2-input AND 7409 quad 2-input AND with open collector outputs 7432 quad 2-input OR 7486 quad 2-input EX-OR 74132 quad 2-input NAND with Schmitt trigger inputs The 74132 has  Schmitt trigger  inputs to provide good noise immunity. They are ideal for slowly changing or noisy signals

96. 7402 quad 2-input NOR

97. 7490 decade (0-9) ripple counter

98. TTL family evolution Widely used today 102

99. CMOS Complimentary MOS (CMOS) Other variants: NMOS, PMOS (obsolete) Very low static power consumption Scaling capabilities (large integration all MOS) Full swing: rail-to-rail output 103

100. CMOS/TTL power requirements TTL power essentially constant (no frequency dependence) CMOS power scales as  f  C  V 2 At high frequencies (>> MHz) CMOS dissipates more power than TTL Overall advantage is still for CMOS even for very fast chips – only a relatively small portion of complicated circuitry operates at highest frequencies frequency supply volt. eff. capacitance 104

101. CMOS family evolution obsolete Reduction of dynamic losses through successively decreasing supply voltages: 12V  5V 3.3V 2.5V 1.8V CD4000 LVC/ALVC/AVC Power reduction is one of the keys to progressive growth of integration General trend: 105

102. Overview TTL Logic Family CMOS Values typical for V cc /V dd = 5V When interfacing different families, pay attention to their input/output voltage, current (fanout) specs. T PD T rise/fall V IH,min V IL,max V OH,min V OL,max Noise Margin 106

103. COMBINATIONAL CIRCUITS USING TTL 74XX ICS Decoder(IC 74138,IC74139, IC 74154), BCD-to-7-segment decoder(IC 7447), Encoder(IC 74147),

104. Decoder(IC 74138,IC74139, IC 74154) Basic function: To detect the presence of a specified combination of bits(code) on its inputs and to indicate the presence of that code by a specified output level. It has n inputs to handle n bits and from one to 2 n output lines to indicate the presence of one or more n-bit combinations. Applications: It is used to implement Combinational circuit. It is used to convert BCD to 7-segment code. It is used in memories to select particular register.

105. 3 74x139 dual 2-to-4 decoder

106. 3-line to 8-line decoder(3 X 8)-74HC138 Pin Diagram Logic Diagram

107. Function table

108. 6 74x138 3-8 Decoder

109. 4-line to 16-line decoder(4 X 16)-74HC154 Pin Diagram Logic Diagram Function table

110. Cascading Decoders-cascading 5-bit number A 4 74HC154 can handle only 4 bits. 5 th bit,A4 is connected to chip s ele c t input s , C S 1 an d C S 2 of one decoder is connected to chip select inputs, CS 1 and CS 2 of other decoder . A 4

111. Application-In computers for Input/Output selection

112. BCD to Decimal Decoder

113. Contd…

114. BCD-to-7 segment Decoder (IC 7447) Logic diagram of Basic 7-segment decoder Pin Diagram Pin Diagram-7447 = lamp test LT RBI = ripple blanking input BI RBO =blanking input/ripple blanking output Logic Diagram-7447

115. 14 Encoder Encoder: the inverse operation of a decoder. Has 2 n input lines and n output lines. The output lines generate the binary equivalent of the input line whose value is 1. I I 1 I 2 I 3 z 1 z 2 4-2 Binary Encoder

116. 15 Encoder A B C A B C O S 2 O 1 O 2 S 1 3:8 O 3 S decoder O 4 O 5 O 6 O 7 I I 1 Z 2 I 2 I 3 8:3 Z 1 I 4 encoder Z I 5 I 6 I 7

117. Encoder(IC 74147) It has 2 n input lines and n output lines. Logic diagram of Decimal to BCD encoder Gate level diagram of Decimal to BCD encoder Truth table for Decimal to BCD encoder

118. 17 Encoder Circuit Design Example: – 8-3 Binary Encoder A = D 1 + D 3 + D 5 + D 7 A 1 = D 2 + D 3 + D 6 + D 7 A 2 = D 4 + D 5 + D 6 + D 7

119. 18 Encoder Circuit

120. 19 Encoder Design Issues Only one input can be active at any given time. If two inputs are active simultaneously, the output produces an undefined combination (for example, if D 3 and D 6 are 1 simultaneously, the output of the encoder will be 111. An output with all 0's can be generated when all the inputs are 0's,or when D is equal to 1. A = D 1 + D 3 + D 5 + D 7 A 1 = D 2 + D 3 + D 6 + D 7 A 2 = D 4 + D 5 + D 6 + D 7

121. 20 Priority Encoder Solves the ambiguities mentioned above. Multiple asserted inputs are allowed; one has priority over all others. Separate indication of no asserted inputs.

122. 24-Oct-19 PJF - 21 4-to-2 Priority Encoder (cont.) The operation of the priority encoder is such that: If two or more inputs are equal to 1 at the same time, the input in the highest-numbered position will take precedence. A valid output indicator , designated by V, is set to 1 only when one or more inputs are equal to 1. V = D 3 + D 2 + D 1 + D by inspection.

123. 22 K-Ma p s

124. 23 Circuit

125. 24 8-3 Priority Encoder

126. 25 74 x148 Features: inputs and outputs are active low. EI_L must be asserted for any of its outputs to be asserted. GS_L is asserted when the device is enabled and one or more of the request inputs is asserted. (“Group Select” or “Got Something.” ) EO_L is an enable output designed to be connected to the EI_L input of another ’148 that handles lower- priority requests. It is asserted if EI_L is asserted but no request input is asserted; thus, a lower-priority ’148 may be enabled.

127. 26 74x148 Truth Table

128. 74HC147- priority encoder It is also called as 10-line-to-4-line encoder. 74HC147 is a priority encoder with active-low inputs (0) for decimal digits 1 to 9 and active-low BCD outputs. Pin Diagram-74147 Logic Diagram-74147

129. Truth table-74147

130. Application-Keyboard Keys are represented by 10 push-button switches, each with a pull-up resistor to +v. When key is not pressed, line is HIGH. When key is pressed, line is connected to ground making a LOW to the corresponding encoder input.

131. Multiplexer(IC 74151) “It is a device that allows digital information from several sources to one line”. Gate level Diagram Truth table Waveforms Logic Diagram

132. Contd …

133. 8 to 1 MUX-74LS151 • indicates AND relationship between data select inputs and each of the data inputs through 7. Pin Diagram-74LS151 Logic Diagram G 7 Enable =LOW, allows the selected input data to pass through to the output. 7 G

134. Truth table

135. Quad 2-input Multiplexer-IC 74HC157 G1=indicates AND relationship between data select input and data inputs. When data slect=HIGH, B inputs of the multiplexer are selected. When data slect=LOW, A inputs of the multiplexer are selected It contains 4-separate 2-input multiplexers. All the multiplexers share common data select line and a common Enable. Enable =LOW, allows selected input data to pass through to the output. Enable =HIGH, prevents data from going through to the output (disables the Logic Diagram multiplexer). Pin Diagram

136. Applications 1) 7-segment display multiplexer

137. 2) Logic function generator It is used in generation of combinational logic functions in sum-of-product form. a) Implement the logic function specified in truth table by using 74LS151 8- input data selector. Compare this method with a discrete logic gate implementation Sol:

138. b) Implement the logic function specified in truth table by using 74LS151 8-input data selector. Compare this method with a discrete logic gate implementation Sol:

139. Demultiplexer 1 to 4 line Demultiplexer

140. 1 to 16 line demultiplexer-74154 Logic Diagram

141. Four-bit Parallel Adder/Su b t r ac t or IC 7483

142. C o n t d… 4 BIT ADDER: A binary adder is a digital circuit that produces the arithmetic sum of two binary numbers. It can be constructed with full adders connected in cascade, with the output carry from each full adder connected to the input carry of next full adder in chain. 4 BIT SUBTRACTOR: The circuit for subtracting A-B consists of an adder with inverters, placed between each data input ‘B’ and the corresponding input of full adder. The input carry C0 must be equal to 1 when performing subtraction. 4 BIT ADDER/SUBTRACTOR: The addition and subtraction operation can be combined into one circuit with one common binary adder. The mode input M controls the operation. When M=0, the circuit is adder circuit. When M=1, it becomes subtractor.

143. 1-bit Full adder Logic Symbol Truth Table Logic Diagram

144. Four-bit parallel adder Block diagram Logic symbol

145. Truth table LS:Low power Schottky TTL IC’s used are: 1) 74LS83A 2) 74LS283

146. Pin Diagram Logic Diagram

147. Adder Expansion 4-bit Parallel adder can be expanded to handle the addition of two 8-bit numbers by using two 4-bit adders. Carry input of Low-order adder(co) is connected to ground because there is no carry into least significant bit position. Carry output of Low-order adder is connected to carry input of high-order adder.

148. E x ample Show how two 74LS83A adders can be connected to form an 8-bit parallel adder. Show output bits for the following 8-bit input numbers: A 8 A 7 A 6 A 5 A 4 A 3 A 2 A 1 =10111001, B 8 B 7 B 6 B 5 B 4 B 3 B 2 B 1 =10011110

149. Appli c a tion Simple Voting system

150. 4-bit subtractor

151. 4-BIT ADDER/SUBTRACTOR When M= 1, the circuit is a subtractor and when M=0, the circuit becomes adder. The Ex-OR gate consists of two inputs to which one is connected to the B and other to input M. When M = 0, B Ex-OR of produce B . T h en f u l l a d d e r s a d d th e B w i t h A w i t h c ar r y inpu t z e r o a n d h e n c e an a d d i t i o n o p e r a t i o n i s p e r f o rm e d . When M = 1, B Ex-OR of produce B complement and also carry input is 1. Hence the complemented B inputs are added to A and 1 is added through the input carry, nothing but a 2’s complement operation. Therefore, the subtraction operation is performed .

152. 4-BIT ADDER/SUBTRACTOR

153. Comparator (IC 7485) Cascading inputs: These inputs allow several comparators to be cascaded for comparison of any number of bits greater than four. Basic function: Compare the magnitudes of two binary numbers to determine relationship of those quantities. 74HC85 is a 4-bit comparator Pin diagram Logic diagram

154. Functional table for 74LS85

155. Cascading comparator To expand the comparator, A<B, A=B and A>B outputs of Lower-order comparator are connected to the corresponding cascading inputs of the next higher-order comparator. Condition: Lower-order comparator A=B input=HIGH A<B and A>B inputs=LOW Use 74HC85 comparators to compare the magnitudes of two 8-bit numbers. Show the comparator with proper interconnections Expand for 16-bit comparator?