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1. 1 UNIT-I Design with HDL

2. 2 TOPICS Design flow Language Constructs, Modeling styles Data objects, Data types, Operators Sequential statements Concurrent statements Packages and Libraries Attributes Operator overloading, Resolution functions ( Notes ) Mealy and Moore machine sequence detector and other state machine examples Compilation, Simulation, and Synthesis Hierarchical and flat designs Partitioning for synthesis Resource sharing Pipelining Efficient coding styles

3. 3 Book Sources T1: Charles Roth, and Lizy John “Digital System Design using VHDL,” 2 nd Ed., Cengage Learning. T3: Steve Kilts “Advanced FPGA Design Architecture, Implementation and Optimization,” Wiley. R3: John F. Wakerly, “Digital Design Principles and Practices,” 4 th Ed., Prentice Hall R6: Jayaram Bhasker, “A VHDL Primer,” 3 rd Ed., PHI.

4. 4 SYSTEM’s Abstraction Levels

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8. 8 DESIGN FLOW

9. Basic Design Methodology 9 Requirements Simulate RTL Model Gate-level Model Synthesize Simulate Test Bench ASIC or FPGA Place & Route Timing Model Simulate

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11. 11 CADENCE / SYNOPSYS Design Flow

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13. 13 HDL ( H ardware D escription L anguage )

14. 14 Need of HDLs Arguments : Why ONE More language ? Can’t our CHAMPs do everything ? FORTRAN , PASCAL , COBOL C , C++ , VB , JAVA

15. Strengths & Limitations of C Strengths… C is an extremely powerful Language. In fact even JAVA Compiler has been written Using C Language. Limitations… C is a sequential language & the statements are executed in the order in which they are written. But Electronic Hardware is CONCURRENT in Nature, which means it functions on the occurrence of EVENTS. eg. In Asynchronous Counter when LSB F/F outputs a 1  0 then middle F/F changes state and so on…till MSB F/F. C LANGUAGE cannot represent the CONCURRENT Nature of Electronic Hardware EFFICIENTLY. Thus there is a need of a Special language which can efficiently represent the behavior of Electronics Hardware.

16. VHDL VHDL = V + H.D.L. H ardware D escription L anguage V.H.S.I.C. means V ery H igh S peed I ntegrated C ircuit Thus….. V.H.D.L. = V ery H igh S peed I ntegrated C ircuit H ardware D escription L anguage

17. History of V.H.D.L. DOD-USA needed Very High SPEED ICs ( VHSICs ) Contract Given to different vendors Incompatibility Issues while Integrating Designs Need of common standard to describe Digital Designs IBM , Texas Instruments , Intermetrics collaborate Standardized in 1987 as IEEE STD 1076 / VHDL-87 Standardized in 1993 as IEEE STD 1164 / VHDL-93 So , we will be studying VHDL-93 & Not VHDL-87 VHDL : VERBOSE , Strongly Typed , Form-Free , Case-Insensitive VHDL is a combination of …. Sequential Language , Concurrent Language , Net-List Language , Waveform Generation Language & Timing Specifications

18. VHDL… I s used to “ MODEL the PDS ( Proposed Digital System )“ Modeling means 2 Things : a) To define signals through which PDS interacts with Real World b) To define the Logical relationship between I/P & O/P Signals Primary usage is to describe DIGITAL HARDWARE . Digital Circuits are ultimately made up of LOGIC GATES. Keywords : AND,OR,NOT,XOR,XNOR ,describe LOGIC GATES. Hence VHDL can efficiently represent a DIGITAL SYSTEM. Cannot Model Digital System if expressed on TRANSISTOR Level

19. D Flip-Flop D Flip-Flop D A D B Q B Q A

20. Things common to all Languages… Basic Program Constructs. Grammar ( called as SYNTAX ). Variables & ways of declaring them. Data Types ( What values the variables can hold ) Language Compiler ( Converts English-Like Program into Machine-Language ) Thus Learning VHDL is nothing but learning NEWer ways of doing the above things.

21. Need of a Compiler… main( ) { int x=10,y=20,z; z = x + y ; printf ( “ %d “, z ); getch( ) ; } What’s That ? Give me only 1010001111 Oh ! That’s ENGLISH-LIKE !! Turbo C- Compiler 101000111... That’s delicious !!

22. C - Program main( ) { int x=10,y=20,z; z = x + y ; printf ( “ %d “, z ); getch( ) ; } C-Compiler ( Software ) Syntax Check Generates .obj File ie. Program into machine language (11000011….) Processor ( Hardware ) The ALU Then Adds the 2 nos. 10 & 20 and Generates the result 30. VHDL Program For Half-Adder , MUX , Counter , µ Controller SYNTHESIS TOOL ( XILINX Software ) Syntax Check Converts VHDL Code Program into a GATE-LEVEL NETLIST (11000011….) CPLD / FPGA ( Programmable H/W ) The above device then operates as the desired Digital Circuit ( Half-Adder , MUX , Counter , Or even a MicroController ) Programming Instructions On your PC HARDWARE

23. A VHDL Program may consist of…. LIBRARY STATEMENTS (LS) ENTITY Declaration (ED) ARCHITECTURE Body (AB) Configuration Declaration (CD) Package * Package Body (PB) * Package Declaration (PD) All Declarations are called P.D.U’s ( Primary Design Units ) All Body’s are called S.D.U’s ( Secondary Design Units ) OPTIONAL COMPULSORY

24. Syntax For LIBRARY STATEMENTS (LS) --SYNTAX LIBRARY library_name; USE library_name.package_name.function_name; --ACTUAL Library Statements in a VHDL Model LIBRARY IEEE ; USE IEEE.STD_LOGIC_1164.ALL ; USE IEEE.STD_LOGIC_UNSIGNED.ALL ; USE IEEE.NUMERIC_STD.ALL ;

25. Syntax For Entity Declaration ENTITY entity_name IS PORT ( signalname_1 : [ MODE ] [ DATATYPE ] ; signalname_2 : [ MODE ] [ DATATYPE ] ; signalname_3 : [ MODE ] [ DATATYPE ] ; . . signalname_n : [ MODE ] [ DATATYPE ] ) ; END entity_name ; NO Semi-colon after Last Signal IN / OUT / INOUT 1) BIT ( 2-Valued Logic ) 2) STD_LOGIC ( 9-Valued LOGIC ) -- Preferred

26. Example of ED For an AND Gate and_gate A B Y ENTITY and_gate IS PORT ( A : IN STD_LOGIC ; B : IN STD_LOGIC ; Y : OUT STD_LOGIC ) ; END and_gate ;

27. Syntax For ARCHITECTURE BODY ARCHITECTURE arch_name OF entity_name IS Local variables / Global Variables / Constants / ….. Don’t write anything if not needed BEGIN END arch_name ; Here you …. Express “ The Logical Relationship between your I/Ps & O/Ps as Boolean Equation(s) Various Modeling Styles Various Constructs Declaration Section LOGIC Section

28. Example of AB For AND Gate ARCHITECTURE andgate_arch OF and_gate IS BEGIN Y < = A and B ; -- VHDL equivalent of Y = A.B END arch_name ;

29. The Complete VHDL Program For AND Gate LIBRARY IEEE ; USE IEEE.STD_LOGIC_1164.ALL ; USE IEEE.STD_LOGIC_UNSIGNED.ALL ; USE IEEE.NUMERIC_STD.ALL ; ENTITY and_gate IS PORT ( A : IN STD_LOGIC ; B : IN STD_LOGIC ; Y : OUT STD_LOGIC ) ; END and_gate ; ARCHITECTURE andgate_arch OF and_gate IS BEGIN Y < = A and B ; END arch_name ;

30. 31 DATA TYPES DATA OBJECTS

31. 32 Data Types Types Access Scalar Composite Array Record Integer Real Enumerated Physical All declarations of VHDL ports, signals, and variables must specify their corresponding type or subtype

32. VHDL Data Types Scalar Types Integer Minimum range for any implementation as defined by standard: - 2,147,483,647 to 2,147,483,647 Example assignments to a variable of type integer : 33 ARCHITECTURE test_int OF test IS BEGIN PROCESS (X) VARIABLE a: INTEGER; BEGIN a := 1; -- OK a := -1; -- OK a := 1.0; -- illegal END PROCESS; END test_int;

33. VHDL Data Types Scalar Types (Cont.) Real Minimum range for any implementation as defined by standard: -1.0E38 to 1.0E38 Example assignments to a variable of type real : 34 ARCHITECTURE test_real OF test IS BEGIN PROCESS (X) VARIABLE a: REAL; BEGIN a := 1.3; -- OK a := -7.5; -- OK a := 1; -- illegal a := 1.7E13; -- OK a := 5.3 ns; -- illegal END PROCESS; END test_real;

34. VHDL Data Types Scalar Types (Cont.) Enumerated User specifies list of possible values Example declaration and usage of enumerated data type : 35 TYPE binary IS ( ON, OFF ); ... some statements ... ARCHITECTURE test_enum OF test IS BEGIN PROCESS (X) VARIABLE a: binary; BEGIN a := ON; -- OK ... more statements ... a := OFF; -- OK ... more statements ... END PROCESS; END test_enum;

35. VHDL Data Types Scalar Types (Cont.) Physical Require associated units Range must be specified Example of physical type declaration : Time is the only physical type predefined in VHDL standard 36 TYPE resistance IS RANGE 0 TO 10000000 UNITS ohm; -- ohm Kohm = 1000 ohm; -- i.e. 1 K W Mohm = 1000 kohm; -- i.e. 1 M W END UNITS;

36. VHDL Data Types Composite Types Array Used to group elements of the same type into a single VHDL object Range may be unconstrained in declaration Range would then be constrained when array is used Example declaration for one-dimensional array (vector) : 37 TYPE data_bus IS ARRAY(0 TO 31) OF BIT; VARIABLE X : data_bus; VARIABLE Y : BIT; Y := X(12); -- Y gets value of element at index 12 31 1 ...element indices... ...array values...

37. 38 Example one-dimensional array using DOWNTO : TYPE reg_type IS ARRAY(15 DOWNTO 0) OF BIT; VARIABLE X : reg_type; VARIABLE Y : BIT; Y := X(4); -- Y gets value of element at index 4 15 1 ...element indices... ...array values... VHDL Data Types Composite Types (Cont.) DOWNTO keyword must be used if leftmost index is greater than rightmost index e.g. ‘Big- Endian ’ bit ordering

38. VHDL Data Types Composite Types (Cont.) Records Used to group elements of possibly different types into a single VHDL object Elements are indexed via field names Examples of record declaration and usage : 39 TYPE binary IS ( ON, OFF ); TYPE switch_info IS RECORD status : BINARY; IDnumber : INTEGER; END RECORD; VARIABLE switch : switch_info; switch.status := ON; -- status of the switch switch.IDnumber := 30; -- e.g. number of the switch

39. 40 VHDL Data Types Access Type Access Analogous to pointers in other languages Allows for dynamic allocation of storage Useful for implementing queues, fifos, etc.

40. 41 Subtype Allows for user defined constraints on a data type e.g. a subtype based on an unconstrained VHDL type May include entire range of base type Assignments that are out of the subtype range are illegal Range violation detected at run time rather than compile time because only base type is checked at compile time Subtype declaration syntax : Subtype example : SUBTYPE name IS base_type RANGE <user range> ; VHDL Data Types Subtypes SUBTYPE first_ten IS INTEGER RANGE 0 TO 9;

41. 42 VHDL Data Types Summary All declarations of VHDL ports, signals, and variables must include their associated type or subtype Three forms of VHDL data types are : Access -- pointers for dynamic storage allocation Scalar -- includes Integer, Real, Enumerated, and Physical Composite -- includes Array, and Record A set of built-in data types are defined in VHDL standard User can also define own data types and subtypes

42. 43 VHDL Objects There are four types of objects in VHDL Constants Variables Signals Files The scope of an object is as follows : Objects declared in a package are available to all VHDL descriptions that use that package Objects declared in an entity are available to all architectures associated with that entity Objects declared in an architecture are available to all statements in that architecture Objects declared in a process are available only within that process

43. 44 VHDL Objects Constants Name assigned to a specific value of a type Allow for easy update and readability Declaration of constant may omit value so that the value assignment may be deferred Facilitates reconfiguration Declaration syntax : CONSTANT constant_name : type_name [:= value ]; CONSTANT PI : REAL := 3.14; CONSTANT SPEED : INTEGER;

44. 45 VHDL Objects Variables Provide convenient mechanism for local storage E.g. loop counters, intermediate values Scope is process in which they are declared VHDL ‘93 provides for global variables, to be discussed in the Advanced Concepts in VHDL module All variable assignments take place immediately No delta or user specified delay is incurred Declaration syntax: Declaration examples : VARIABLE opcode : BIT_VECTOR(3 DOWNTO 0) := "0000"; VARIABLE freq : INTEGER; VARIABLE variable_name : type_name [:= value ];

45. VHDL Objects Signals Used for communication between VHDL components Real, physical signals in system often mapped to VHDL signals ALL VHDL signal assignments require either delta cycle or user-specified delay before new value is assumed Declaration syntax : Declaration and assignment examples : 46 SIGNAL signal_name : type_name [:= value ]; SIGNAL brdy : BIT; brdy <= '0' AFTER 5ns, '1' AFTER 10ns;

46. 47 Signals and Variables This example highlights the difference between signals and variables ARCHITECTURE test1 OF mux IS SIGNAL x : BIT := '1'; SIGNAL y : BIT := '0'; BEGIN PROCESS (in_sig, x, y) BEGIN x <= in_sig XOR y; y <= in_sig XOR x; END PROCESS; END test1; ARCHITECTURE test2 OF mux IS SIGNAL y : BIT := '0'; BEGIN PROCESS (in_sig, y) VARIABLE x : BIT := '1'; BEGIN x := in_sig XOR y; y <= in_sig XOR x; END PROCESS; END test2; Assuming a 1 to 0 transition on in_sig , what are the resulting values for y in the both cases?

47. 48 VHDL Objects Signals vs Variables A key difference between variables and signals is the assignment delay ARCHITECTURE sig_ex OF test IS PROCESS (a, b, c, out_1) BEGIN out_1 <= a NAND b; out_2 <= out_1 XOR c; END PROCESS; END sig_ex; Time a b c out_1 out_2 0 0 1 1 1 0 1 1 1 1 1 0 1+d 1 1 1 0 0 1+2d 1 1 1 0 1

48. 49 Time a b c out_3 out_4 0 0 1 1 1 0 1 1 1 1 0 0 1+d 1 1 1 0 1 VHDL Objects Signals vs Variables (Cont.) ARCHITECTURE var_ex OF test IS BEGIN PROCESS (a, b, c) VARIABLE out_3 : BIT; BEGIN out_3 := a NAND b; out_4 <= out_3 XOR c; END PROCESS; END var_ex;

49. 50 Types of Statements Concurrent Statements PROCESS Clause ( Most Frequently used ) WHEN-ELSE Construct ( Frequently used ) WITH-SELECT Construct ( Sparingly used ) Sequential Statements IF-THEN-ELSE-END IF Construct ( 2 conditions ) IF-THEN-ELSIF-END IF Construct ( > 2 conditions) ( Most Frequently used ) CASE Construct ( Frequently used ) Sequential Statements are always embedded within Concurrent statements Concurrent Statements are Stand-Alone

50. 51 VHDL Constructs

51. 52 PROCESS Clause & CASE Construct

52. Syntax For PROCESS Clause ARCHITECTURE arch_name OF entity_name IS BEGIN PROCESS ( Sensitivity List ) BEGIN -- LOGIC expressed using Sequential Statements -- IF – THEN – ELSE - END IF -- IF – THEN –ELSIF - END IF -- CASE – END CASE Construct END PROCESS ; END arch_name ; SENSITIVITY List ( SL ) : It is a list of all those Signals on which the O/P is dependent ( Sensitive ) Naturally , this List will contain “ ALL I/P Signals “ Eg. SL for 2:1 MUX will contain all I/P Signals : I0 , I1 ,I2 , I3 , S1 , S0

53. 4:1 MUX ( Using PROCESS Clause) LIBRARY IEEE ; USE IEEE.STD_LOGIC_1164.ALL ; USE IEEE.STD_LOGIC_UNSIGNED.ALL ; USE IEEE.NUMERIC_STD.ALL ; entity mux41_bms_CASE is Port ( I : in STD_LOGIC_VECTOR (0 to 3); S : in STD_LOGIC_VECTOR (1 downto 0); Y : out STD_LOGIC ); end mux41_bms_CASE;   architecture mux41_bms_CASE_arch of mux41_bms_CASE is begin PROCESS ( I , S ) BEGIN CASE S IS WHEN "00" => Y <= I(0); WHEN "01" => Y <= I(1); WHEN "10" => Y <= I(2); WHEN OTHERS => Y <= I(3); END CASE; END PROCESS; end mux41_bms_CASE_arch;

54. 55 WHEN-ELSE Construct

55. 4:1 MUX ( Using WHEN-ELSE Construct ) library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity mux41_dms is Port ( I : in STD_LOGIC_VECTOR (0 to 3); S : in STD_LOGIC_VECTOR (1 downto 0); Y : out STD_LOGIC ); end mux41_dms;   architecture mux41_dms _arch of mux41_dms is begin Y <= I(0) WHEN S=“000” ELSE I(1) WHEN S=“001” ELSE I(2) WHEN S=“010” ELSE I(3) ; end mux41_dms _arch;

56. 57 IF-THEN-ELSE-END IF IF-THEN-ELSIF-END IF Constructs

57. 2:1 MUX ( Using IF-THEN-ELSE-END IF) library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity mux21 is Port ( I0 , I1 : in STD_LOGIC ; S : in STD_LOGIC ; Y : out STD_LOGIC ); end mux21; architecture mux21 _arch of mux21 is begin PROCESS ( I0 , I1 , S ) BEGIN IF S=‘0’ THEN ----- Do not FORGET to write “ THEN “ Y <= I0 ; ELSE Y <= I1 ; END IF ; ----- ENDIF is not allowed END PROCESS; end mux21 _arch;

58. 4:1 MUX ( Using IF-THEN-ELSIF-END IF) --LS entity mux41 is Port ( I : in STD_LOGIC_VECTOR ( 0 TO 3) ; S : in STD_LOGIC_VECTOR ( 1 DOWNTO 0 ) ; Y : out STD_LOGIC ); end mux41; architecture mux41 _arch of mux41 is begin PROCESS ( I , S ) BEGIN IF S= “00” THEN Y <= I(0) ; -- (0) accesses 1 st bit of the 4-bit Sugnal “I” & 1 st I/P of MUX ELSIF S= “01” THEN -- ELSE IF is not allowed Y <= I(1) ; ELSIF S= “10” THEN Y <= I(2) ; ELSE Y <= I(3) ; END IF ; END PROCESS; end mux41 _arch;

59. 60 Modeling Styles ( MS ) in VHDL What is a MS ? It is a way of expressing functionality of PDS We can write Multiple Programs to model same PDS Functionality remains same , H/W inferred may change 4 Styles ( B , D , S , M ) B : Behavioral ( BMS ) D : Dataflow ( DMS ) S : Structural ( SMS ) M : Mixed ( MMS ) How to identify which MS has been used ? By looking for specific KEYWORDS / Constructs in the VHDL Program

60. 61 How to Identify the Modeling Style If you find “PROCESS” clause Its B ehavioral MS If you find following Constructs : With Select When-Else Its D ataflow MS If you find following Constructs : COMPONENT – END COMPONENT PORT MAP ( ) Its S tructural MS If you find Two / More of above in Same Program Its M ixed MS

61. 62 B EHAVIORAL M ODELING S TYLE

62. VHDL Program For 4:1 MUX mux41_bms_CASE I0 I1 Y I2 I3 s1 s0

63. 4:1 MUX ( Behavioral Modeling Style ) LIBRARY IEEE ; USE IEEE.STD_LOGIC_1164.ALL ; USE IEEE.STD_LOGIC_UNSIGNED.ALL ; USE IEEE.NUMERIC_STD.ALL ; entity mux41_bms_CASE is Port ( I : in STD_LOGIC_VECTOR (0 to 3); S : in STD_LOGIC_VECTOR (1 downto 0); Y : out STD_LOGIC ); end mux41_bms_CASE;   architecture mux41_bms_CASE_arch of mux41_bms_CASE is begin PROCESS ( I , S ) BEGIN CASE S IS WHEN "00" => Y <= I(0); WHEN "01" => Y <= I(1); WHEN "10" => Y <= I(2); WHEN OTHERS => Y <= I(3); END CASE; END PROCESS; end mux41_bms_CASE_arch;

64. 65 D ATAFLOW M ODELING S TYLE

65. VHDL Program For 4:1 MUX mux41_bms_CASE I0 I1 Y I2 I3 s1 s0

66. 4:1 MUX ( DMS ) : WHEN-ELSE library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity mux41_dms is Port ( I : in STD_LOGIC_VECTOR (0 to 3); S : in STD_LOGIC_VECTOR (1 downto 0); Y : out STD_LOGIC ); end mux41_dms;   architecture mux41_dms _arch of mux41_dms is begin Y <= I(0) WHEN S=“000” ELSE I(1) WHEN S=“001” ELSE I(2) WHEN S=“010” ELSE I(3) ; end mux41_dms _arch;

67. 68 S TRUCTURAL M ODELING S TYLE

68. 69 Structural Modeling Style (SMS) VHDL Program using SMS has 4 Parts : SR.NO. Part Name Location 1) COMPONENT Creation Declaration Section of AB 2) Declaration of Connecting Signals Declaration Section of AB 3) COMPONENT Instantiation Logic Section of AB 4) Port Mapping Logic Section of AB

69. STRUCTURAL Modeling Style FULL ADDER a b cin cout sum

70. STRUCTURAL Modeling Style… a b cin cout sum x1 c1 add1 x2 s1 x1 c1 add2 x2 s1 carry1 sum1 carry2

71. VHDL Program For FULL-ADDER LIBRARY IEEE ; USE IEEE.STD_LOGIC_1164.ALL ; USE IEEE.STD_LOGIC_UNSIGNED.ALL ; USE IEEE.NUMERIC_STD.ALL ;

72. ENTITY FA IS Port ( a : in std_logic; b : in std_logic; cin : in std_logic; sum : out std_logic; cout : out std_logic ); END FA ; ARCHITECTURE FA_arch IS COMPONENT add IS PORT ( x1,x2 : in std_logic; s1,c1 : out std_logic ); END COMPONENT ; SIGNAL sum1,carry1,carry2 : std_logic ; BEGIN add1 : add PORT MAP (x1=>a,x2=>b,c1=>carry1,s1=>sum1); add2 : add PORT MAP (x1=>sum1,x2=>c,c1=>carry2,s1=>sum); cout<=carry1 OR carry2; END FA_arch ; ED for Main Entity “ THE FULL-ADDER “ Creating COMPONENT “add” ( Half-Adder ) Intermediate Signals Connecting the 2 Half-Adders add1 & add2 The Carry output of FA

73. library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY add IS PORT ( x1,x2 : in std_logic; s1,c1 : out std_logic ); END add; ARCHITECTURE add_struct OF add IS begin s1 <= x1 XOR x2; c1 <= x1 AND x2; END add_struct; ED for the COMPONENT “add” ( Half-Adder ) AB for the COMPONENT “add” ( Half-Adder )

74. 75 PACKAGES LIBRARIES

75. 76 Packages and Libraries User defined constructs declared inside architectures and entities are not visible to other VHDL components Scope of subprograms, user defined data types, constants, and signals is limited to the VHDL components in which they are declared Packages and libraries provide the ability to reuse constructs in multiple entities and architectures Items declared in packages can be used (i.e. included) in other VHDL components

76. 77 Packages consist of two parts Package declaration -- contains declarations of objects defined in the package Package body -- contains necessary definitions for certain objects in package declaration e.g. subprogram descriptions Examples of VHDL items included in packages Basic declarations Types, subtypes Constants Subprograms Use clause Signal declarations Attribute declarations Component declarations Packages

77. 78 Packages Declaration An example of a package declaration : Note some items only require declaration while others need further detail provided in subsequent package body for type and subtype definitions, declaration is sufficient subprograms require declarations and descriptions PACKAGE my_stuff IS TYPE binary IS ( ON, OFF ); CONSTANT PI : REAL := 3.14; CONSTANT My_ID : INTEGER; PROCEDURE add_bits3(SIGNAL a, b, en : IN BIT; SIGNAL temp_result, temp_carry : OUT BIT); END my_stuff;

78. 79 Packages Package Body The package body includes the necessary functional descriptions needed for objects declared in the package declaration e.g. subprogram descriptions, assignments to constants PACKAGE BODY my_stuff IS CONSTANT My_ID : INTEGER := 2; PROCEDURE add_bits3(SIGNAL a, b, en : IN BIT; SIGNAL temp_result, temp_carry : OUT BIT) IS BEGIN -- this function can return a carry temp_result <= (a XOR b) AND en; temp_carry <= a AND b AND en; END add_bits3; END my_stuff;

79. 80 Packages Use Clause Packages must be made visible before their contents can be used The USE clause makes packages visible to entities, architectures, and other packages -- use only the binary and add_bits3 declarations USE my_stuff.binary, my_stuff.add_bits3; ... ENTITY declaration... ... ARCHITECTURE declaration ... -- use all of the declarations in package my_stuff USE my_stuff.ALL; ... ENTITY declaration... ... ARCHITECTURE declaration ...

80. 81 Libraries Analogous to directories of files VHDL libraries contain analyzed (i.e. compiled ) VHDL entities, architectures, and packages Facilitate administration of configuration and revision control E.g. libraries of previous designs Libraries accessed via an assigned logical name Current design unit is compiled into the Work library Both Work and STD libraries are always available Many other libraries usually supplied by VHDL simulator vendor E.g. proprietary libraries and IEEE standard libraries

81. 82 Signals and Variables This example highlights the difference between signals and variables ARCHITECTURE test1 OF mux IS SIGNAL x : BIT := '1'; SIGNAL y : BIT := '0'; BEGIN PROCESS (in_sig, x, y) BEGIN x <= in_sig XOR y; y <= in_sig XOR x; END PROCESS; END test1; ARCHITECTURE test2 OF mux IS SIGNAL y : BIT := '0'; BEGIN PROCESS (in_sig, y) VARIABLE x : BIT := '1'; BEGIN x := in_sig XOR y; y <= in_sig XOR x; END PROCESS; END test2; Assuming a 1 to 0 transition on in_sig , what are the resulting values for y in the both cases?

82. 83 FUNCTIONS PROCEDURES

83. 84 ATTRIBUTES OPERATORS

84. 85 Attributes Attributes provide information about certain items in VHDL E.g. types, subtypes, procedures, functions, signals, variables, constants, entities, architectures, configurations, packages, components General form of attribute use : VHDL has several predefined, e.g : X'EVENT -- TRUE when there is an event on signal X X'LAST_VALUE -- returns the previous value of signal X Y'HIGH -- returns the highest value in the range of Y X'STABLE(t) -- TRUE when no event has occurred on signal X in the past ‘t’ time name'attribute_identifier -- read as "tick"

85. 86 Attributes Register Example The following example shows how attributes can be used to make an 8-bit register Specifications : Triggers on rising clock edge Latches only on enable high Has a data setup time of x_setup Has propagation delay of prop_delay ENTITY 8_bit_reg IS GENERIC (x_setup, prop_delay : TIME); PORT(enable, clk : IN qsim_state; a : IN qsim_state_vector(7 DOWNTO 0); b : OUT qsim_state_vector(7 DOWNTO 0)); END 8_bit_reg; qsim_state type is being used - includes logic values 0, 1, X, and Z

86. 87 Attributes Register Example (Cont.) ARCHITECTURE first_attempt OF 8_bit_reg IS BEGIN PROCESS (clk) BEGIN IF (enable = '1') AND a'STABLE(x_setup) AND (clk = '1') THEN b <= a AFTER prop_delay; END IF; END PROCESS; END first_attempt; The following architecture is a first attempt at the register The use of 'STABLE is to used to detect setup violations in the data input What happens if a does not satisfy its setup time requirement of x_setup ?

87. 88 Attributes Register Example (Cont.) ARCHITECTURE behavior OF 8_bit_reg IS BEGIN PROCESS (clk) BEGIN IF (enable = '1') AND a'STABLE(x_setup) AND (clk = '1') AND (clk'LAST_VALUE = '0') THEN b <= a AFTER prop_delay; END IF; END PROCESS; END behavior; The following architecture is a second and more robust attempt The use of 'LAST_VALUE ensures the clock is rising from a value of ‘0’ An ELSE clause could be added to define the behavior when the requirements are not satisfied

88. 89 Operators Operators can be chained to form complex expressions, e.g. : Can use parentheses for readability and to control the association of operators and operands Defined precedence levels in decreasing order : Miscellaneous operators -- **, abs, not Multiplication operators -- *, /, mod, rem Sign operator -- +, - Addition operators -- +, -, & Shift operators -- sll, srl, sla, sra, rol, ror Relational operators -- =, /=, <, <=, >, >= Logical operators -- AND, OR, NAND, NOR, XOR, XNOR res <= a AND NOT(B) OR NOT(a) AND b;

89. 90 Operators Examples The concatenation operator & VARIABLE shifted, shiftin : BIT_VECTOR(0 TO 3); ... shifted := shiftin(1 TO 3) & '0'; 1 1 2 3 The exponentiation operator ** SHIFTIN SHIFTED x := 5**5 -- 5^5, OK y := 0.5**3 -- 0.5^3, OK x := 4**0.5 -- 4^0.5, Illegal y := 0.5**(-2) -- 0.5^(-2), OK 1 1

90. 91 VHDL Modeling Of STATE Machines

91. 92 Generic Steps Create a Block Diagram Out of State Diagram Create New Datatype in DS of AB Define Signal belonging to Datatype Use PROCESS Clause ( LS of AB ) Use CASE Construct within IF-THEN-ELSIF-END IF within

92. 93 MOORE_MC w z clk rst statemc Name of our State Machine

93. VHDL Model of State m/c library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity MOORE_MC is Port ( rst : in std_logic; clk : in std_logic; W : in std_logic; Z : out std_logic); end MOORE_MC; architecture MOORE_MC_arch of MOORE_MC is TYPE state_name IS ( A , B , C ); SIGNAL statemc : state_name; begin

94. VHDL Model of State m/c….. PROCESS( rst , clk , W ) BEGIN IF rst='1' THEN statemc<=A ; ELSIF ( clk'EVENT AND clk='0' ) THEN CASE statemc IS WHEN A => IF W='1' THEN statemc<= B; ELSE statemc<= A; END IF;

95. WHEN B => IF W='1' THEN statemc<= C; ELSE statemc<= A; END IF; WHEN C => IF W='1' THEN statemc<= C; ELSE statemc<= A; END IF; END CASE;

96. VHDL Model of State m/c….. END IF; END PROCESS; Z <= '1' WHEN statemc=C ELSE '0'; end MOORE_MC_arch;

97. 98 SIMULATION

98. 99 Testing the functionality of PDS If I write in AND Gate Model : Y <= A OR B ; Will it generate a SYNTHESIS Error ? NO Download this Model into FPGA , you get OR Gate If I would have Simulated my MODEL … I would have caught LOGIC Error in my Design Done by writing a TestBench (TB) for PDS TB is 2 nd VHDL MODEL in FPGA Design Flow TB uses a Blank Entity & Structural MS TB uses Multiple PROCESS’es w/o SL As many I/Ps , those many PROCESS’es Simulator ( ISim in XILINX ISE ) runs TB W/Fs show the Functional Correctness of MODEL You will Appreciate it better , during Practical Session

99. STIMULUS DRIVER DUT ( Device Under Test ) O/P Comparison KNOWN CORRECT RESULTS O/P W/Fs ERROR YES NO FPGA Prototyping Modify Model PDS ( Main Program ) TB Program NO Real World I/Ps Hence BLANK ED Test Vectors We will Re-Visit the Above Flow-Model During LAB Assignments

100. 101 LIVE Tool Demo Simulation of AND Gate Simulation of XOR Gate Simulation of 2:1 MUX Simulation of 3-Bit Up Counter

101. 102 SYNTHESIS

102. SYNTHESIS TOOL ( XILINX ISE ) Design Entry User Constraints Technology Library Gate Level Netlist HDL ( VHDL / VeriLog ) Schematic EDIF NGC / NGO PLD -Family --Member ---Capacity ---No. of Pins AREA ( Area ) TIMING ( Speed ) POWER ( Power ) Balanced Basic Gates ( AND , OR ,NOT ) Multiplexer Latch ( Not Preferred ) Flip-Flop It is an Automated process of converting a High Level Of Abstraction Into a Gate-Level Netlist ( Interconnection between BASIC Gates / D F/F / Multiplexers )

103. 104 LIVE Tool Demo Synthesis of AND Gate Synthesis of NAND Gate Synthesis of XOR Gate Synthesis of 2:1 MUX Synthesis of D F/F

104. 105 Hierarchical & Flat Designs

105. Hierarchy in Design is achieved by : Component Creation Component Instantiation Structural MS Top-Down Design Approach

106. 108 Partitioning for Synthesis ( PFS )

107. METHOD -1 : Partitioning between Datapath and Control

108. METHOD -2 : Clock and Reset Structures With One type of Clock and One type of Reset. Problem of Hazards ( Static / Dynamic ) is rare With M ultiple clock domains and / or Reset structures partition the hierarchy to separate them by different modules. Problem of Hazards appears by mixing Clock and Reset types in procedural descriptions.

109. METHOD -3 : Multiple Instantiations VeriLog Model Multiple Instantiations Instance-1 Instance-2 Instance-3

110. 112 RESOURCE SHARING

111. Consider the following Code Section… process (SEL, A, B, C, D) begin if (SEL = ‘1’) then Y <= A + B; else Y <= C + D; end if ; end process; ADDER -1 ADDER -2 MUX A , B are n-bit signals Let us compute the MOSFET Count if CMOS Logic is used

112. We need : Two BINARY ADDERS Single 2:1 MUX 3) Single BINARY ADDER = 4 Full-Adders 4) 1-bit Full-Adder = 2 XOR , 3 AND , 2 OR Gates 5) 1 XOR = 22 MOSFETs , 1 AND = 6 MOSFETs , 1 OR = 6 MOSFETs 6) 1-bit Full-Adder = 44 + 18 + 12 = 74 MOSFETs 7) Single BINARY ADDER = 74*4 = 296 MOSFETs 8) TWO BINARY ADDERS = 296*2 = 592 MOSFETs 9) Single MUX = 1 NOT , 2 AND , 1 OR Gate 10) Hence Single MUX = 2 + (2*6) + 6 = 20 MOSFETs 11) The Above H/W will need = 592 + 20 = 612 MOSFETs If A , B are 4-bit signals

113. Revised Code with same functionality Y1 <= A when SEL = ‘1’ else C; Y2 <= B when SEL = ‘1’ else D; Y <= Y1 + Y2; MUX -1 MUX-2 ADDER We need : **Single BINARY ADDER=296 TWO 2:1 MUX = 20*2 =40 ** H/W will need = 336 MOSFETs % Saving = 45 % Y1 Y2 Y C B WHEN-ELSE & IF-THEN-ELSE infer MUX in H/W Advice : Write VHDL Models for Both versions of Code

114. 116 PIPELINING

115. Speed Optimisation of Design done by Pipelining F/F to F/F throughput increased by adding Register stages Total latency with a small in AREA ( Trade-Off ) F/Fs are moved @ logic to balance delay bet’n Register stages Also known as ReTiming , Register balancing Regular structures like pipelined memories / Multipliers are identified by Synthesis Tool Structures are Re-Architected with redistributed logic to achieve Load Balancing Pipelining….

116. Pipelining….

117. 119 EFFICIENT CODING STYLES

118. 120 Removal of FALSE Paths Control over Critical path Synthesis Checking of Redundant conditions in IF if (A) then if (C) then if (A) then -- avoid Unnecessary Calculations in “ for” Loops Placing unchanging expressions in “ for ” loops Optimisation of Redundant Logic Avoid using Complex operators Relational operators ( > , < ) Arranging Expression Trees for Minimum delay EFFICIENT CODING STYLES….

119. EFFICIENT CODING STYLES….

120. 122 CODING EXAMPLES

121. 123 Coding on XILINX Tool 4:1 MUX 4:1 MUX with Enable 3:8 Decoder 74LS138 ALU D Latch ( Incomplete IF Statement ) D F/F D F/F with Reset D F/F with Reset & Preset 3-Bit UP Counter , 3-bit DOWN Counter 3-Bit UP Counter , 3-bit DOWN Counter with Reset , Preset 4-Bit UP Down Counter with Asynchronous Reset Preset

122. 124 Coding on XILINX Tool Full-Adder Using Half-Adder as Component ( SMS ) 4:1 MUX Using 2:1 MUX as Component ( SMS ) 16:1 MUX Using 4:1 MUX as Component ( SMS ) 7483 ( 4-Bit Binary Adder ) using SMS 3-Bit Asynchronous Counter using SMS 2:1 MUX Using SMS Logic Gates Using MUX ( AND , OR ,……XNOR ) Logic Gates Using MUX ( SMS ) NOT Gate using NAND / NOR as Component 4-Bit PRBS using SMS