Verilog HDL

This presentation contain Verilog HDL language

1. Dr. HasmukhP Koringa,
EC Dept.
Government Engineering College Rajkot
VerilogHDL

2. Acknowledgment
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Thispresentationissummarizeandtaken
referencesfromvariousbooks,papers,websites
andpresentationonVerilogHDL.Iwouldliketo
thankstoallprofessors,researchersandauthors
whohavecreatedsuchgoodworkonthisVerilog
HDL.MyspecialthankstoVerilogHDLbook
authorSamirpalnitkar.

3.  Verilog/VHDL is Used
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4. What is Verilog?
It is a Hardware Description Language ( HDL )to design the digital
system.
Two major HDL languages:
-Verilog
-VHDL
Verilog is easier to learn and use (It is like the C language).
VerilogHDL is both behavioral and structural language
It is case sensitive language
Models of verilogHDL can describe both function of design and the
components
It can also define connection of components in design
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5. History
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Verilogwas invented by PhilMoorbyand PrabhuGoelin
1983/1984 at Gateway Design automation.
GDA was purchased by CandenceDesign system in 1990.
Originally, verilogwas intended for describe and simulation
only.
Later support for synthesis added.
Cadence transferred Veriloginto the public domain under the
Open VerilogInternational (OVI).

Verilogwas later submitted to IEEE and became IEEE
standard 1364-1995, commonly referred to as Verilog-95.

6. History
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Verilog2001 Extensions to Verilog-95 were submitted back to
IEEE to cover few limitation of Verilog-95.
This extension become IEEE Standard 1364-2001 known as
Verilog-2001.
Verilog-2001 is the dominant flavorof Verilogsupported by the
majority of commercial EDA software packages.
Today all EDA developer companies are using Verilog-2001.
Verilog2005 : Don’t be confused with System Verilog, Verilog
2005 (IEEE Standard 1364-2005) consists of minor corrections.

A separate part of the Verilogstandard, Verilog-AMS, attemmpts
to integrate analogand mixed signal modelingwith traditional
Verilog.

7. History
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System Verilogis a superset of Verilog-2005 with new features and
capabilities to aid design-verification and design- modeling.
As of 2009, the System Verilogand Veriloglanguage standards
were merged into System Verilog2009 (IEEE Standard 1800-
2009).
The advent of hardware verification language such as Open Vera,
System C encouraged the development of Superlogby Co-Design
Automation Inc.
Co-Design Automation Inc was later purchased by Synopsys.
The foundations of Superlogand Vera were donated to Accellera,
which later became the IEEE standard 1800- 2005: System Verilog.

8. Design Methodology
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Based on Design Hierarchy
Based on Abstraction

9. Based on Design Hierarchy
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Top Down Design Methodology
Bottom Up Design Methodology

10. Top Down Design Methodology
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11. Verilogcode for 4 bit binary parallel
adder
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module adder4 (A,B,S,C); //module name and port list
input [3..0] A,B; // port declaration
output [3..0] S;
output c;
fulladderadd0 (.A[0](a), .B[0](b), .S[0](s),

12. Bottom Up Design Methodology
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13. Based on Abstraction Level
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BehavioralLevel
Data Flow Level
Gate Level
Switch Level

14. Based on Abstraction Level
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BehavioralLevel
Data Flow Level
Gate Level
Switch Level

15. Lexical Conventions
Close to C / C++.
Comments:
// Single line comment
/* multiple
lines
comments */
/b Black Space
/t Tab Space
/n New line

CaseSensitive:
Keywords:
-Reserved.
-lower case.
-Examples: module, case, initial, always.

Number:
decimal, hex, octal, binary
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16. Identifier
•A ... Z ,a ... z ,0 ... 9 , Underscore , $
Strings are limited to 1024 chars
First char of identifier must not be a digit and $
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17. Numbers:
<size>’<base format><number>
-Size: No. of bits (optional)( default size is 32 bits).
-Base format: b: binary
d : decimal
o : octal
h : hexadecimal
(DEFAULT IS DECIMAL)
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18. Verilog HDL Dr. H P Koringa
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Underscore character
-Underscore can be place between digit of number
Data= 16’b 1010_1100_0011 _0101;
-Note: Never put starting digit as underscore
String:
var= " Enclose between quotes on a single line“;
Verilogsupport string data type assignment and treated as
ASCII character.

19. Program Structure
Verilog describes a system as a set of modules.
Each module has an interface to other modules.
Usually:
-Each module is put in a separate file.
-One top level module that contains:
Instances of hardware modules.
Test data.

Modules can be specified:
-Behaviorally.
-Structurally.
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20. Module
General definition
module module_name( port_list);
port declarations;
…
variable declaration;
…
description of behavior;
…
task and function;
endmodule
module HalfAdder(A, B, Sum Carry);
inputA, B;
outputSum, Carry;
assignSum = A ^ B;
//^ denotes XOR
assignCarry = A & B; // & denotes AND
endmodule
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21. Port
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input
output
inout

22. regand wiredata objects may have a value of:
-0: logical zero
-1: logical one
-x: unknown
-z: high impedance
Registers are initialized to x at the start of simulation.
Any wire not connected to something has the value x .
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23. Physical Data Types
Registers (reg ):
-Store values
reg[7:0] A;// 8-bit register
regX; // 1-bit register
How to declare a memory in verilog?
reg[7:0] A [1023:0];// A is 1K words each 8-bits

Wires ( wire ):
-Do not store a value.
-Represent physical connections between entities.
wire [7:0] A;
wireX;
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24. Nets/Wire
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In Verilogdefault declaration of any variable is net/wire type.
A net/wire does not store value except for trireg net.
Net/wire must be driven by such as gate or continuous
assignment.
If no driver connected to net, it value will be high impedance
(z).
Multi bit wire: wire [31..0] data_bus32

25. Advanced Net types
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tri: it is similar to wire as syntax wise as well as functionally
Only difference between tri and wire is, wire denote single
driver, while tri means multiple driver.

26. Advanced Net Types
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trireg: triregis wire except that when the net having capacitive
effect.
Capacitive effect means it can store previous value.
Therefore it work on two state.
Driver state: when the driver net having value 1,0,x then the driver
net follow the driver net.

Capacitive state: when driver net unconnected or having high
impedance then driver net hold last value.

27. Advanced Net Types
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trio & tri1 : trio & tri1 are resistive Pulldownand pullup
devices.
when the value of the driving net is high then driven net will
get a value of the input.
When the value of the driving net is low the driven net get a
value of pulldown or pullup.
Ex: trio y;
buff tristate(y,a,ctrl); // when control signal is high, y=a;
// when control signal is low ; y=0 instead of high impedence.

28. Advanced Net Types
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supply0 & supply1 : these are used to model ground and
power.
Ex: supply1 VDD;
supply0 GND;
wor, wand, triorand triand:
When one single net is driven by two net having same signal
strength then it is difficult to determine the output of driven
net.
In this case we can use the output oringor andingon both the
nets.

29. Register
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Declaration
reg<signed><range><list_of_register_variables>;
regdata; // single bit variable
regsigned [7..0] data_bus;// multiple bit signed variable
reg[7..0] data_bus // multiple bit unsigned variable
Integer: This is general regtype variable. Use to manipulate
mathematical calculation.
This is 32 bit integer sign number
Ex: integer data; // 32 bit signed value;

30. Real
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real: This is real register data type.
Default value of real data type is zero.
Ex: real data=3.34;
real data 2e6;//2*10^6
Note: real value can not be passed from one module to another
module.

31. Vector
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Vector bit select: reg[31..0] data;
bit_select=data[7];
Vector part select: reg[31..0] data;
part_select=data[7..0];
reg[0..31] data_bus;
part_select= data_bus[0..7];
Variable vector part select:
variable_name[<starting_bit>+:width]
byte_select= data_bus[16+:8]; //starting from 16 to 23
variable_name[<starting_bit- >:width];
byte_select= data_bus[16-:8]; //starting from 9 to 16

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Memory: memory is multi bit array
Ex. reg[7..0] mem_data[0..N-1];
Parameter: To declare constant value in Verilogparameter is
used.
Localparam:
LocalparamWD=32

33. Verilogsystem task
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To perform routing operation (to display output value, simulation
time etc.)
System task start with $
Ex. $display
$monitor
$strobe
$write
$time
$finish
$recordfile
$dumpfile

34. Display
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Display Information: Value can be display in binary,
hexadecimal, octal or decimal.

35. VerilogCompiler Directive
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Compiler directive: compiler directive are define in
Verilogor macro.
These macro are define like ‘<keyword>
Ex. ‘timescale 1ns/1ns
‘define data_width8
‘include‘ifdefine

36. Timescale
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‘timescale <reference time unit>/<precision>;
Ex. ‘timescale 1ns/1ps;
#1.003; //will be consider as valid delay
#1.0009; // will be consider as 1ns delay

37. Gate level abstraction
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This is also know as structural abstraction.
Design is describe in terms of gates.
Very easy to write code if design in structural form.
For large circuit its very difficult to implement using gate
level.

38. Basic gate primitive in Verilog
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39. Basic gate primitive in Verilog
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40. Basic gate primitive in Verilog
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41. Example Verilogdesign using
gate level abstraction
1-bit full adder circuit
Expression
Sum = (in1 xorin2 xorcin)
Carryout = (in1 and in2 ) or (in2 and cin) or
(in1 and cin)
in1
in2
cin
sum
cout
1-bit Full adder circuit
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42. Structural model of a full adder circuit
modulefadd(in1, in2, cin, sum,cout);
inputin1,in2, cin;
output sum, cout;
wirex1,a1,a2,a3,o1,o2;
xor(x1,in1,in2);
xor(sum,x1,cin);
and(a1,in1,in2);
and(a2,in1,cin);
and(a3,in2,cin);
or(o1, a1,a2);
or(cout,o1,a3);
endmodule
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43. Gate Delay
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Rise delay
Fall delay
Turn-off delay
Gate output transition to high impedance state (z).

44. Gate delay examples
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and # (5) a1 (out,in1 ,in2); //delay 5 for all transition.
and # (4,5) a2(out,in1 ,in2); //rise =4, fall =5 and turn-
off=min (4,5)

Bufif0 #(3,4,5) b1(out,in,cntr); //rise=3,fall=4 and turn-
off=5;

45. Min/Typ/Max values
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For each type of delay-rise, fall and turn- off-three values
min, typand max can be specified.
Min/Typ/Max values are used to model devices whose
delays varies within min to max range because of IC
fabrication process variations.
Ex. and #(3:4:5) a1(out,in1 ,in2); // when one delay is
specified.
and # (3:4:5, 4:5:6) a2(out,in1 ,in2); // when two delays are
specified.
and #(3:4:5, 3:4:5, 4:5:6) a3(out,in1 ,in2); //when all three
delays are specified.

46. Data Flow level abstraction
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The gate level approach is very well for small scale logic.
With the synthesis tool we can convert data level code to
gate level code.
All the booleanfunction can be implemented using data flow
level.
Expressed using continuous assignment.
Expressions, Operators, Operands.

47. Continuous Assignment
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This is used to drive a value onto a net.
This is equivalent to gate after synthesis.
Define by key word assign
Ex . assign out = in1 & in2;
The left hand side value know as output net and it must be
net data type.
Operands on right hand side can be reg as well wire.
Delay can be specified in term of #time_unit
assign sum #10 = a+b;

48. Delay Type
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Three ways to define delay in continuous assignment
statement
Regular assignment delay
ex. assign #10 dout= in1$in2;
Implicit assignment delay
ex. wire #10 dout= in1$in2;
Net declaration delay.
ex. wire #10 dout;
assign dout= in1$in2;

49. Operators
Binary Arithmetic Operators:
Operator
Type
Operator SymbolOperation
Performed
Number of
Operands
Arithmetic
* multiply two
/ divide two
+ add two
- subtract two
% modulus two
** power one
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50. Relational Operators:
Operator
Type
Operator SymbolOperation
Performed
Number of Operands
Relational
> greater than two
< less than two
>=
greater than
or equal
two
<=
less than or
equal
two
== equality two
!= inequality two
=== Case equality two
!==
Case
inequality
two
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51. Logical Operators:
Operator TypeOperator SymbolOperation
Performed
Number of
Operands
Logical
! logical negationone
&& logical and two
|| logical or two
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52. Operator TypeOperator
Symbol
Operation
Performed
Number of
Operands
Bitwise
~ bitwise negationone
& bitwise and two
| bitwise or two
^ bitwise xor two
^~or ~^ bitwise xnor two
Bitwise Operators:
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53. Other operators:
Unary Reduction Operators
Unaryreductionoperatorsproduceasinglebitresultfromapplyingthe
operatortoallofthebitsoftheoperand.
Forexample,&AwillANDallthebitsofA.
Concatenation:
C = {A[0], B[1:7]}
Shift Left:
A = A << 2 ; // right >>
Conditional:
A = C > D ?B + 3 :B –2 ; ex 2x1 muxassign out=control?in1:in0
4x1 mux: assign out = s1? (s0? I3 : i2) : (s0? i1: i0);
Replication:
A = {4{B}}; // will replicate value of B four times and
assign to A
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54. Data flow Level Model
4x1 multiplexer
moduleMUX_4x1 (out ,in4 , in3 , in2, in1 , cntrl2, cntrl1);
outputout;
inputin1, in2, in3, in4, cntrl1, cntrl2;
wire out;
assignout = (in1 & ~cntrl1 & ~cntrl2) |
(in2 & ~cntrl1 &cntrl2)|
(in3 &cntrl1 & ~cntrl2)|
(in4 &cntrl1 &cntrl2);
endmodule
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55. Data Flow model of a full adder
circuit
modulefadd(in1, in2, cin, sum,cout);
inputin1,in2, cin;
outputsum, cout;
assign {cout, sum}=in1 +in2 +cin;
endmodule
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56. Behaviorallevel Abstraction
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Modelling circuit with logic gate and continuous assignments
is quite complex.
Behaviorallevel is the higher level of abstraction in which
model can be defined as its functional behavioral.
Verilogbehavioralmodels contain structured procedural
statements that control the simulation and manipulate
variables.
Two types of structured procedure constructs

Initial and always

57. initialStatement
alwaysStatement
initialStatement : Executes only once
alwaysStatement : Executes in a loop
Example:
…
initial begin
Sum = 0;
Carry = 0;
end
…
…
always@(A or B) begin
Sum = A ^ B;
Carry = A & B;
end
…
Two Procedural Constructs
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58. Procedural Assignment
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Procedural assignment , are used or updating reg, integer,
time and memory variables.
Continuous assignmentProcedural assignment
Drives net/wire variables onlyDrive reg, integer, time and
memory variables
Updateoutput whenever an
input operand changes its value
Procedural assignment update
the value of regvariables under
the control of procedural flow
constructs that surround them

59. Blocking assignments
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Blocking assignments statements are executed in the order
they are specified in a sequential block.
The = operator is used for blocking assignments.
Ex. rega,b,c,d;
initial
begin
a=1’b0; b=1’b1;
# 5 c = a&b;
#10 d = a| b;
end

60. Nonblockingassignments
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Nonblockingassignments allows scheduling of assignments
without blocking execution of the statements that follow in
sequential block.
The <= operator is used to specify nonblocking assignments.
Ex. rega,b,c,d;
initial
begin
a=1’b0; b=1’b1;
c <= # 5 a&b;
d <= #10 a| b;
end

61. Nonblockingassignments
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Operation of nonblockingassignments
1. The right hand side expressions are evaluated, results are
stored internally in simulator.
2. At the end of time step, in which the given delay has
expired or the appropriate event has taken place, the
simulator executes the assignments by assigning the stored
value to the left-hand side.
Ex. a<=b;
b <= a;
Sequence to write statements is not important.

62. Timing control
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Delay based Timing Control
Intra-Assignment Timing Controls
Inter-Assignment Timing Controls
Zero-Assignment Delay
Even based Timing Control
Regular Event Control
Named Event Control
Event OR Control
Level Sensitive Timing Control

63. Conditional Statement
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Theif statement
Syntax:
if (conditional_expression)
statement;
else
statement;
modulemux(out,in0,in1,sel);
input in1,in2,sel;
output out;
regout;
alway@(in1 @ in2 @ sel )
if (sel==1)
out=in1;
else
out = in0;
endmodule

64. The if else statement
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65. Case Statement
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Thecase statement
Syntax:
case(Expression )
Alternative 1: statement1;
Alternative 1: statement1;
Alternative 1: statement1;
Default: statement_default;
endcase
modulemux(out,in0,in1,sel);
input in1,in2,sel;
output out;
regout;
alway@(in1 @ in2 @ sel )
case (sel)
1’b0: out = in0;
1’b1: out = in1;
default: $display(“Invalid”);
endcase
endmoule

66. Looping Constructs
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TherearefourloopingconstructsinVerilogarewhile,for,
repeatandforever.
Allofthesecanonlyappearinsideinitialandalwaysblocks.
while:executesastatementorsetofstatementswhileacondition
istrue.
for:executesastatementorasetofstatements.Thisloopcan
initialise,testandincrementtheindexvariableinaneatfashion.
repeat:executesastatementorasetofstatementsafixedumber
oftimes.
forever:executesastatementorasetofstatementsforeverand
even,oruntilthesimulationishalted.

67. While Loop
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Syntax:
while(condition)
begin
statement1;
statement2;
statement3;
---
end
the while loop executes while
condition is true, the conditional
can be consist of logical expression.
‘define jugvol100;
modulejug_and_cup;
variable jug, cup;
initial
begin
jug = 0;
cup = 10;
while( jug<jugvol)
begin
jug = jug +cup;
end
end
endmodule

68. for Loop
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Syntax:
for(initialisation; conditional;
update)
begin
statement1;
statement2;
statement3;
---
end
same as the for loop of C
modulefor_loop_ex;
variable data, index;
initial
begin
data =0;
for( index=0;index<10; index
= index+1)
begin
data= data+5;
end
end
endmoule

69. repeat Loop
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Syntax:
repeat(conditional)
begin
statement1;
statement2;
statement3;
---
end
•repeat loop execute fixed number of
times.
•Conditional can be constant, variable or
signal value but must be number.
•If conditional is x or z then it treated as
zero.
modulejug_and_cup;
variable jug, cup, count;
initial
begin
jug =0;
cup=10;
count = 5;
repeat( count)
begin
jug = jug +cup;
end
end
endmodule

70. forever Loop
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Syntax:
forever statement;
•Forever loop executes
continuously until end of simulation
is requested by a $finish.
•It is similar to while loop whose
condition is always true.
•The forever statement must be
used with timing control to limit
the execution.
regclock;
initial
begin
clock=1’b0;
forever #5clock = ~clock;
end
initial
#2000
$finish;

71. Tasks and Functions
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Tasks and functions provide the ability to execute common
procedures from several different places in a description.
They also provide a means of breaking up large procedures
into smaller ones to make it easier to read and debug the
source descriptions.

Input, output and inoutargument values can be passed into
and out of both tasks and functions.

72. Tasks and Functions
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Afunctionmustexecuteinonesimulationtimeunit;ataskcan
containtimecontrollingstatements.
Afunctioncannotenableataskbittaskcanenableothertaskand
functions.
Afunctionmusthaveatlistoneinputargumentwhiletaskcanhave
zeroormoreargumentsofanytype.
Afunctionreturnasinglevaluewhiletaskdoesnotreturnavalue
Thepurposeoffunctionistorespondtoaninputvaluebyreturninga
singlevalue.
Ataskcansupportmultiplegoalsandcancalculatemultipleresult
values.However,onlytheoutputorinoutargumentspassresult
valuesbackfrotheinvocationofatask.

AVerilogmodelusesafunctionalasanoperandinanexpression. The
valueofthatoperandisthevaluereturnedbythefunction.

73. Task
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Syntax:
Syntax:
task <name_of_task>
<parameter_declaration>
<input_declaration>
<output_declaration>
<inout_declaration>
<reg_declaration>
<time_declaration>
<integer_declaration>
<real_declaration>
<event_declaration>
<task body>
endtask
Example:
task clk_gen;
input integer clk_period;
begin
clk= 1’b0;
forever #clk_period/2
clk= ~clk;
end
endtask

74. Function
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Syntax:
function<range_or_type?><name_of_function>
<parameter_declaration>
<input_declaration>
<output_declaration>
<inout_declaration>
<reg_declaration>
<time_declaration>
<integer_declaration>
<real_declaration>
<event_declaration>
endtask
Example:
Function integeradd;
input integer data1;
input integer data2;
begin
add = data1 +data2;
end
endfunction

75. Calling a task and Function
Verilog HDL Dr. H P Koringa
75
moduletask_funct_test;
integer data_type;
initial
begin
task_name(task_parameter);
data_type= function_name(funct_parameter);
end
assignfunct_value= function_name(funct_parameter);
endmodule

76. Q ?
Verilog HDL Dr. H P Koringa
76