Verilog TASKS & FUNCTIONS

Explains the VERILOG Tasks & Functions ,its importance, system tasks wit examples.Also explains the differences between Tasks & Functions.

1. VERILOG TASKS & FUNCTIONS

2. INTRODUCTION The Tasks & Functions in Verilog help to reduce the complexity by breaking up the large behavioural designs into smaller pieces and make the overall code simple and clean. Tasks and functions allow the designer to abstract Verilog code that is used at many places in the design . Tasks have input, output, & inout arguments where as Functions have input arguments . So , values can be passed into and out from tasks and functions .

3. contd A task is similar to a function, but unlike a function it has both input and output ports. Therefore tasks do not return values. Tasks are similar to procedures in most programming languages. The purpose of a function is to respond to an input value by returning a single value . A task can support multiple goals and can calculate multiple result values. It cannot be used in an expression. Parameters may be passed to it and results are returned.

4. A Verilog task is similar to a software procedure. It is called from a calling statement and after execution, returns to the next statement. A task is defined within a module using the keywords task and endtask and it is called from within the always statement. Local variables may be declared within it and their scope will be the task . The order of task parameters at the calling site must correspond to the order of definitions within the task TASK

5. contd A task may call itself, or be called from tasks that it has called. However , as in a hardware implementation, there is only one set of registers to hold the task variables. Thus, the registers used after the second call to the task are the same physical entities as those in the previous call(s). The simulator maintains the thread of control so that the returns from a task called multiple times are handled correctly . 23 June 2020 [email protected] 5

6. Basic structure of a task module this_task ; task my_task ; input a, b; inout c; output d, e; reg foo1, foo2, foo3; begin < statements > // the set of statements that performs the work of the task 23 June 2020 [email protected] 6

7. contd c = foo1; // the assignments that initialize d = foo2; // the results variables e = foo3 ; end endtask endmodule 23 June 2020 [email protected] 7

8. Ex:Task (Procedure) task average; // task declaration input a; // declaration of ports input b; // output Av ; wire s ; reg Av; assign s = ( a+b+c ); assign Av= s / 3; endtask 23 June 2020 [email protected] 8

9. System Tasks Verilog provides standard system tasks for certain routine operations. All system tasks appear in the form $<keyword>. Operations such as displaying on the screen, monitoring values of nets, stopping, and finishing are done by system tasks. For ex: $display ; $stop; $finish ; $ monitor etc. 23 June 2020 [email protected] 9

10. $display $ display is the main system task for displaying values of variables or strings or expressions . Usage: $ display(s1 , s2 , s 3,....., sn ); s1 , s2 , s3 ,..., sn can be quoted strings or variables or expressions. Note: The format of $display is very similar to printf in C. A $display inserts a newline at the end of the string by default. A $display without any arguments produces a newline. 23 June 2020 [email protected] 10

11. Examples $display ("Hello Verilog World"); -- Hello Verilog World //To display value of current simulation time 230 $display($time); -- 230 //Display the value of port_id 5 in binary reg [4:0] port_id ; $display("ID of the port is %b", port_id ); -- ID of the port is 00101 23 June 2020 [email protected] 11

12. contd //Display x characters //Display value of 4-bit bus 10xx (signal contention) in binary reg [3:0] bus; $display("Bus value is %b", bus); -- Bus value is 10xx. 23 June 2020 [email protected] 12

13. Monitor Verilog provides a mechanism to monitor a signal when its value changes and this is provided by the task $monitor. Usage: $monitor(p1,p2,p3,...., pn );The parameters p1, p2, ... , pn can be variables, signal names, or quoted strings. Only one monitoring list is active at a time. If there is more than one $monitor statement in the simulation, the last $monitor will only be active. The earlier $monitor statements will be ignored. 23 June 2020 [email protected] 13

14. contd Two tasks are used to switch the monitoring on and off. For ex: $ monitoron ; $ monitoroff ; The task $ monitoron enables monitoring, and the $ monitoroff task disables monitoring during a simulation. Monitoring is turned on by default at the beginning of the simulation and can be controlled during the simulation with the $ monitoron and $ monitoroff tasks. 23 June 2020 [email protected] 14

15. $stop The task , $ stop is used to stop the simulation. Usage : $stop ; The $stop task puts the simulation in an interactive mode. The $stop task is used whenever the designer wish to suspend the simulation and examine the values of signals in the design. The $finish task terminates or finishes the simulation. Usage : $finish; 23 June 2020 [email protected] 15

16. Ex: Stop &Finish // Stop at time 100 in the simulation and examine the results.// Finish the simulation at time 1000. initial begin clock = 0; reset = 1; # 100 $stop; // suspend the simulation at time = 100 # 900 $finish; // terminate the simulation at time = 1000 end 23 June 2020 [email protected] 16

17. FUNCTIONS Functions are similar to tasks, except that functions return only a single value to the expression from which they are called. Like tasks, functions provide the ability to execute common procedures from within a module. A function can be invoked from a continuous assignment statement or from within a procedural statement and is represented by an operand in an expression. 23 June 2020 [email protected] 17

18. contd Functions cannot contain delays, timing, or event control statements and execute in zero simulation time. Although functions can invoke other functions, they are not recursive . Functions cannot invoke a task. Functions must have at least one input argument , but cannot have output or inout arguments . A function is invoked from an expression. The function is invoked by specifying the function name together with the input parameters. The syntax is as below. function name ( expr1 , expr2 , . . . , exprN ); 23 June 2020 [email protected] 18

19. Function Syntax function [range or type] function name input declaration other declarations begin statements end endfunction 23 June 2020 [email protected] 19

20. Function-Example function mux; input a, b, c, d; input [1:0] select; case (select) 2'b00 : mux = a; 2'b01 : mux = b; 2'b10 : mux = c; 2'b11 : mux = d; default : mux = ' bx ; endcase endfunction 23 June 2020 [email protected] 20

21. Function for a half adder //module for a half adder using a function module funct_half_add ; reg a, b; reg [1:0] sum ; initial begin sum = half_add (1'b0, 1'b0); $ display ("a=0, b=0, cout , sum = %b", sum); sum = half_add (1'b0, 1'b1 ); 23 June 2020 [email protected] 21

22. contd $ display ("a=0, b=1, cout , sum = %b", sum); sum = half_add (1'b1, 1'b0); $ display ("a=1, b=0, cout , sum = %b", sum); sum = half_add (1'b1, 1'b1); $ display ("a=1, b=1, cout , sum = %b", sum); end function [1:0] half_add ; input a, b; reg [1:0] sum; begin 23 June 2020 [email protected] 22

23. contd case ({ a,b }) 2'b00 : sum = 2'b00; 2'b01 : sum = 2'b01; 2'b10 : sum = 2'b01; 2'b11 : sum = 2'b10 ; default:sum = 2'bxx; endcase half_add = sum; end endfunction endmodule 23 June 2020 [email protected] 23

24. Differences

25. 23 June 2020 25 [email protected] THANQ FOR WATCHINIG GOOD LUCK !!