VLSI DESIGN BASICS TRANSISTOR THEORY AND MOS TRANSISTOR.pptx

VLSI BASICS

1. 20EC501- VLSI DESIGN Class: III ECE Academic Year:2022-2023 (Odd Sem) Module 1: Issues and Challenges in Digital IC Design Course handling faculty: Ms. Yamini Shanmugam , Mr.R.Thirrunavukkarasu , Dr.N.Vijayalakshmi .

2. 2 Outline A Brief History CMOS Gate Design Pass Transistors CMOS Latches & Flip-Flops Standard Cell Layouts Stick Diagrams

3. 3 A Brief History 1958: First integrated circuit Flip-flop using two transistors Built by Jack Kilby at Texas Instruments 2010 Intel Core i7 m processor 2.3 billion transistors 64 Gb Flash memory > 16 billion transistors Courtesy Texas Instruments [Trinh09] © 2009 IEEE

4. 4 Growth Rate 53% compound annual growth rate over 50 years No other technology has grown so fast so long Driven by miniaturization of transistors Smaller is cheaper, faster, lower in power! Revolutionary effects on society [Moore65] Electronics Magazine

5. 5 Annual Sales >10 19 transistors manufactured in 2008 1 billion for every human on the planet

6. 6 Invention of the Transistor Vacuum tubes ruled in first half of 20 th century Large, expensive, power-hungry, unreliable 1947: first point contact transistor John Bardeen and Walter Brattain at Bell Labs See Crystal Fire by Riordan, Hoddeson AT&T Archives. Reprinted with permission.

7. 7 Transistor Types Bipolar transistors npn or pnp silicon structure Small current into very thin base layer controls large currents between emitter and collector Base currents limit integration density Metal Oxide Semiconductor Field Effect Transistors nMOS and pMOS MOSFETS Voltage applied to insulated gate controls current between source and drain Low power allows very high integration

8. 8 1970’s processes usually had only nMOS transistors Inexpensive, but consume power while idle 1980s-present: CMOS processes for low idle power MOS Integrated Circuits Intel 1101 256-bit SRAM Intel 4004 4-bit m Proc [Vadasz69] © 1969 IEEE. Intel Museum. Reprinted with permission.

9. 9 Moore’s Law: Then 1965: Gordon Moore plotted transistor on each chip Fit straight line on semilog scale Transistor counts have doubled every 26 months Integration Levels SSI : 10 gates MSI : 1000 gates LSI : 10,000 gates VLSI : > 10k gates [Moore65] Electronics Magazine

10. 10 And Now…

11. 11 Feature Size Minimum feature size shrinking 30% every 2-3 years

12. 12 Corollaries Many other factors grow exponentially Ex: clock frequency, processor performance

13. 13 Introduction Integrated circuits: many transistors on one chip. Very Large Scale Integration (VLSI): bucketloads! Complementary Metal Oxide Semiconductor Fast, cheap, low power transistors Today: How to build your own simple CMOS chip CMOS transistors Building logic gates from transistors Transistor layout and fabrication Rest of the course: How to build a good CMOS chip

14. 14 Silicon Lattice Transistors are built on a silicon substrate Silicon is a Group IV material Forms crystal lattice with bonds to four neighbors

15. 15 Dopants Silicon is a semiconductor Pure silicon has no free carriers and conducts poorly Adding dopants increases the conductivity Group V: extra electron (n-type) Group III: missing electron, called hole (p-type)

16. 16 p-n Junctions A junction between p-type and n-type semiconductor forms a diode. Current flows only in one direction

17. 17 nMOS Transistor Four terminals: gate, source, drain, body Gate – oxide – body stack looks like a capacitor Gate and body are conductors SiO 2 (oxide) is a very good insulator Called metal – oxide – semiconductor (MOS) capacitor Even though gate is no longer made of metal* * Metal gates are returning today!

18. 0: Introduction 18 nMOS Operation Body is usually tied to ground (0 V) When the gate is at a low voltage: P-type body is at low voltage Source-body and drain-body diodes are OFF No current flows, transistor is OFF

19. 19 nMOS Operation Cont. When the gate is at a high voltage: Positive charge on gate of MOS capacitor Negative charge attracted to body Inverts a channel under gate to n-type Now current can flow through n-type silicon from source through channel to drain, transistor is ON

20. 20 pMOS Transistor Similar, but doping and voltages reversed Body tied to high voltage (V DD ) Gate low: transistor ON Gate high: transistor OFF Bubble indicates inverted behavior

21. 21 Power Supply Voltage GND = 0 V In 1980’s, V DD = 5V V DD has decreased in modern processes High V DD would damage modern tiny transistors Lower V DD saves power V DD = 3.3, 2.5, 1.8, 1.5, 1.2, 1.0, …

22. 22 Transistors as Switches We can view MOS transistors as electrically controlled switches Voltage at gate controls path from source to drain

23. 23 CMOS Inverter A Y 1 1 OFF ON 1 ON OFF

24. 24 CMOS NAND Gate A B Y 1 1 1 1 1 1 1 OFF OFF ON ON 1 1 OFF ON OFF ON 1 ON OFF ON OFF 1 ON ON OFF OFF

25. 27 CMOS NOR Gate A B Y 1 1 1 1 1

26. 29 3-input NAND Gate Y pulls low if ALL inputs are 1 Y pulls high if ANY input is 0

27. 30 CMOS Fabrication CMOS transistors are fabricated on silicon wafer Lithography process similar to printing press On each step, different materials are deposited or etched Easiest to understand by viewing both top and cross-section of wafer in a simplified manufacturing process

28. 31 Inverter Cross-section Typically use p-type substrate for nMOS transistors Requires n-well for body of pMOS transistors

29. 32 Well and Substrate Taps Substrate must be tied to GND and n-well to V DD Metal to lightly-doped semiconductor forms poor connection called Shottky Diode Use heavily doped well and substrate contacts / taps

30. 33 Inverter Mask Set Transistors and wires are defined by masks Cross-section taken along dashed line

31. 34 Detailed Mask Views Six masks n-well Polysilicon n+ diffusion p+ diffusion Contact Metal

32. 35 Fabrication Chips are built in huge factories called fabs Contain clean rooms as large as football fields Courtesy of International Business Machines Corporation. Unauthorized use not permitted.

33. 36 Fabrication Steps Start with blank wafer Build inverter from the bottom up First step will be to form the n-well Cover wafer with protective layer of SiO 2 (oxide) Remove layer where n-well should be built Implant or diffuse n dopants into exposed wafer Strip off SiO 2

34. 37 Oxidation Grow SiO 2 on top of Si wafer 900 – 1200 C with H 2 O or O 2 in oxidation furnace

35. 38 Photoresist Spin on photoresist Photoresist is a light-sensitive organic polymer Softens where exposed to light

36. 39 Lithography Expose photoresist through n-well mask Strip off exposed photoresist

37. 40 Etch Etch oxide with hydrofluoric acid (HF) Seeps through skin and eats bone; nasty stuff!!! Only attacks oxide where resist has been exposed

38. 41 Strip Photoresist Strip off remaining photoresist Use mixture of acids called piranah etch Necessary so resist doesn’t melt in next step

39. 42 n-well n-well is formed with diffusion or ion implantation Diffusion Place wafer in furnace with arsenic gas Heat until As atoms diffuse into exposed Si Ion Implanatation Blast wafer with beam of As ions Ions blocked by SiO 2 , only enter exposed Si

40. 43 Strip Oxide Strip off the remaining oxide using HF Back to bare wafer with n-well Subsequent steps involve similar series of steps

41. 44 Polysilicon Deposit very thin layer of gate oxide < 20 Å (6-7 atomic layers) Chemical Vapor Deposition (CVD) of silicon layer Place wafer in furnace with Silane gas (SiH 4 ) Forms many small crystals called polysilicon Heavily doped to be good conductor

42. 45 Polysilicon Patterning Use same lithography process to pattern polysilicon

43. 46 Self-Aligned Process Use oxide and masking to expose where n+ dopants should be diffused or implanted N-diffusion forms nMOS source, drain, and n-well contact

44. 47 N-diffusion Pattern oxide and form n+ regions Self-aligned process where gate blocks diffusion Polysilicon is better than metal for self-aligned gates because it doesn’t melt during later processing

45. 48 N-diffusion cont. Historically dopants were diffused Usually ion implantation today But regions are still called diffusion

46. 49 N-diffusion cont. Strip off oxide to complete patterning step

47. 50 P-Diffusion Similar set of steps form p+ diffusion regions for pMOS source and drain and substrate contact

48. 51 Contacts Now we need to wire together the devices Cover chip with thick field oxide Etch oxide where contact cuts are needed

49. 52 Metalization Sputter on aluminum over whole wafer Pattern to remove excess metal, leaving wires

50. 53 Layout Chips are specified with set of masks Minimum dimensions of masks determine transistor size (and hence speed, cost, and power) Feature size f = distance between source and drain Set by minimum width of polysilicon Feature size improves 30% every 3 years or so Normalize for feature size when describing design rules Express rules in terms of l = f /2 E.g. l = 0.3 m m in 0.6 m m process

51. 54 Simplified Design Rules Conservative rules to get you started

52. 55 Inverter Layout Transistor dimensions specified as Width / Length Minimum size is 4 l / 2 l, sometimes called 1 unit In f = 0.6 m m process, this is 1.2 m m wide, 0.6 m m long

53. 56 Summary MOS transistors are stacks of gate, oxide, silicon Act as electrically controlled switches Build logic gates out of switches Draw masks to specify layout of transistors Now you know everything necessary to start designing schematics and layout for a simple chip!

54. 57 CMOS Gate Design Activity: Sketch a 4-input CMOS NOR gate

55. 58 Complementary CMOS Complementary CMOS logic gates nMOS pull-down network pMOS pull-up network a.k.a. static CMOS Pull-up OFF Pull-up ON Pull-down OFF Z (float) 1 Pull-down ON X (crowbar)

56. 59 Series and Parallel nMOS: 1 = ON pMOS: 0 = ON Series : both must be ON Parallel : either can be ON

57. 60 Conduction Complement Complementary CMOS gates always produce 0 or 1 Ex: NAND gate Series nMOS : Y=0 when both inputs are 1 Thus Y=1 when either input is 0 Requires parallel pMOS Rule of Conduction Complements Pull-up network is complement of pull-down Parallel -> series, series -> parallel

58. 61 Compound Gates Compound gates can do any inverting function Ex:

59. 62 Example: O3AI

60. 63 Signal Strength Strength of signal How close it approximates ideal voltage source V DD and GND rails are strongest 1 and 0 nMOS pass strong 0 But degraded or weak 1 pMOS pass strong 1 But degraded or weak 0 Thus nMOS are best for pull-down network

61. 64 Pass Transistors Transistors can be used as switches

62. 65 Transmission Gates Pass transistors produce degraded outputs Transmission gates pass both 0 and 1 well

63. 66 Tristates Tristate buffer produces Z when not enabled EN A Y Z 1 Z 1 1 1 1

64. 67 Nonrestoring Tristate Transmission gate acts as tristate buffer Only two transistors But nonrestoring Noise on A is passed on to Y

65. 68 Tristate Inverter Tristate inverter produces restored output Violates conduction complement rule Because we want a Z output

66. 69 Multiplexers 2:1 multiplexer chooses between two inputs S D1 D0 Y X X 1 1 1 X 1 1 X 1

67. 70 Gate-Level Mux Design How many transistors are needed? 20

68. 71 Transmission Gate Mux Nonrestoring mux uses two transmission gates Only 4 transistors

69. 72 Inverting Mux Inverting multiplexer Use compound AOI22 Or pair of tristate inverters Essentially the same thing Noninverting multiplexer adds an inverter

70. 73 4:1 Multiplexer 4:1 mux chooses one of 4 inputs using two selects Two levels of 2:1 muxes Or four tristates

71. 74 D Latch When CLK = 1, latch is transparent D flows through to Q like a buffer When CLK = 0, the latch is opaque Q holds its old value independent of D a.k.a. transparent latch or level-sensitive latch

72. 75 D Latch Design Multiplexer chooses D or old Q

73. 76 D Latch Operation

74. 77 D Flip-flop When CLK rises, D is copied to Q At all other times, Q holds its value a.k.a. positive edge-triggered flip-flop , master-slave flip-flop

75. 78 D Flip-flop Design Built from master and slave D latches

76. 79 D Flip-flop Operation

77. 80 Race Condition Back-to-back flops can malfunction from clock skew Second flip-flop fires late Sees first flip-flop change and captures its result Called hold-time failure or race condition

78. 81 Nonoverlapping Clocks Nonoverlapping clocks can prevent races As long as nonoverlap exceeds clock skew We will use them in this class for safe design Industry manages skew more carefully instead

79. 82 Gate Layout Layout can be very time consuming Design gates to fit together nicely Build a library of standard cells Standard cell design methodology V DD and GND should abut (standard height) Adjacent gates should satisfy design rules nMOS at bottom and pMOS at top All gates include well and substrate contacts

80. Engineered for Tomorrow MOS circuits are formed on four basic layers: N-diffusion P-diffusion Polysilicon Metal These layers are isolated by one another by thick or thin silicon dioxide insulating layers. Thin oxide mask region includes n-diffusion / p-diffusion and transistor channel. MOS layers

81. Stick diagrams Stick diagrams may be used to convey layer information through the use of a color code. For example: n-diffusion -- green poly -- red blue -- metal yellow -- implant black --contact areas

82. Encodings for NMOS process:

83. CMOS inverter diagrams schematic stick diagram layout

84. NAND gate implementation using CMOS stick diagram schematic

85. NOR gate implementation using CMOS stick diagram schematic

86. Engineered for Tomorrow SCHEMATIC AND LAYOUT OF BASIC GATES a) CMOS INVERTER NOT GATE Schematic Stick diagram Layout

87. b) NAND GATE Schematic Stick diagram Layout

88. Engineered for Tomorrow TRANSMISSION GATE Symbol schematic stick diagram layout

89. 96 Example: Inverter

90. 97 Example: NAND3 Horizontal N-diffusion and p-diffusion strips Vertical polysilicon gates Metal1 V DD rail at top Metal1 GND rail at bottom 32 l by 40 l

91. 98 Stick Diagrams Stick diagrams help plan layout quickly Need not be to scale Draw with color pencils or dry-erase markers

92. 99 Wiring Tracks A wiring track is the space required for a wire 4 l width, 4 l spacing from neighbor = 8 l pitch Transistors also consume one wiring track

93. 100 Well spacing Wells must surround transistors by 6 l Implies 12 l between opposite transistor flavors Leaves room for one wire track

94. 101 Area Estimation Estimate area by counting wiring tracks Multiply by 8 to express in l

95. 102 Example: O3AI Sketch a stick diagram for O3AI and estimate area

96. 103 Outline Design Partitioning MIPS Processor Example Architecture Microarchitecture Logic Design Circuit Design Physical Design Fabrication, Packaging, Testing

97. 104 Activity 2 Sketch a stick diagram for a 4-input NOR gate

98. 105 Coping with Complexity How to design System-on-Chip? Many millions (even billions!) of transistors Tens to hundreds of engineers Structured Design Design Partitioning

99. 106 Structured Design Hierarchy : Divide and Conquer Recursively system into modules Regularity Reuse modules wherever possible Ex: Standard cell library Modularity : well-formed interfaces Allows modules to be treated as black boxes Locality Physical and temporal

100. 107 Design Partitioning Architecture : User’s perspective, what does it do? Instruction set, registers MIPS, x86, Alpha, PIC, ARM, … Microarchitecture Single cycle, multcycle, pipelined, superscalar? Logic : how are functional blocks constructed Ripple carry, carry lookahead, carry select adders Circuit : how are transistors used Complementary CMOS, pass transistors, domino Physical : chip layout Datapaths, memories, random logic

101. 108 Gajski Y-Chart

102. 109 MIPS Architecture Example: subset of MIPS processor architecture Drawn from Patterson & Hennessy MIPS is a 32-bit architecture with 32 registers Consider 8-bit subset using 8-bit datapath Only implement 8 registers ($0 - $7) $0 hardwired to 00000000 8-bit program counter You’ll build this processor in the labs Illustrate the key concepts in VLSI design

103. 110 Instruction Set

104. 111 Instruction Encoding 32-bit instruction encoding Requires four cycles to fetch on 8-bit datapath

105. 112 Fibonacci (C) f = 1; f -1 = -1 f n = f n-1 + f n-2 f = 1, 1, 2, 3, 5, 8, 13, …

106. 113 Fibonacci (Assembly) 1 st statement: n = 8 How do we translate this to assembly?

107. 114 Fibonacci (Binary) 1 st statement: addi $3, $0, 8 How do we translate this to machine language? Hint: use instruction encodings below

108. 115 Fibonacci (Binary) Machine language program

109. 116 MIPS Microarchitecture Multicycle m architecture ( [Paterson04], [Harris07] )

110. 117 Multicycle Controller

111. 118 Logic Design Start at top level Hierarchically decompose MIPS into units Top-level interface

112. 119 Block Diagram

113. 120 Hierarchical Design

114. 121 HDLs Hardware Description Languages Widely used in logic design Verilog and VHDL Describe hardware using code Document logic functions Simulate logic before building Synthesize code into gates and layout Requires a library of standard cells

115. 122 Verilog Example module fulladder( input a, b, c, output s, cout);   sum s1(a, b, c, s); carry c1(a, b, c, cout); endmodule   module carry( input a, b, c, output cout)   assign cout = (a&b) | (a&c) | (b&c); endmodule

116. 123 Circuit Design How should logic be implemented? NANDs and NORs vs. ANDs and ORs? Fan-in and fan-out? How wide should transistors be? These choices affect speed, area, power Logic synthesis makes these choices for you Good enough for many applications Hand-crafted circuits are still better

117. 124 Example: Carry Logic assign cout = (a&b) | (a&c) | (b&c); Transistors? Gate Delays?

118. 125 Gate-level Netlist module carry( input a, b, c, output cout)   wire x, y, z;   and g1(x, a, b); and g2(y, a, c); and g3(z, b, c); or g4(cout, x, y, z); endmodule

119. 126 Transistor-Level Netlist module carry( input a, b, c, output cout)   wire i1, i2, i3, i4, cn;   tranif1 n1(i1, 0, a); tranif1 n2(i1, 0, b); tranif1 n3(cn, i1, c); tranif1 n4(i2, 0, b); tranif1 n5(cn, i2, a); tranif0 p1(i3, 1, a); tranif0 p2(i3, 1, b); tranif0 p3(cn, i3, c); tranif0 p4(i4, 1, b); tranif0 p5(cn, i4, a); tranif1 n6(cout, 0, cn); tranif0 p6(cout, 1, cn); endmodule

120. 127 SPICE Netlist . SUBCKT CARRY A B C COUT VDD GND MN1 I1 A GND GND NMOS W=1U L=0.18U AD=0.3P AS=0.5P MN2 I1 B GND GND NMOS W=1U L=0.18U AD=0.3P AS=0.5P MN3 CN C I1 GND NMOS W=1U L=0.18U AD=0.5P AS=0.5P MN4 I2 B GND GND NMOS W=1U L=0.18U AD=0.15P AS=0.5P MN5 CN A I2 GND NMOS W=1U L=0.18U AD=0.5P AS=0.15P MP1 I3 A VDD VDD PMOS W=2U L=0.18U AD=0.6P AS=1 P MP2 I3 B VDD VDD PMOS W=2U L=0.18U AD=0.6P AS=1P MP3 CN C I3 VDD PMOS W=2U L=0.18U AD=1P AS=1P MP4 I4 B VDD VDD PMOS W=2U L=0.18U AD=0.3P AS=1P MP5 CN A I4 VDD PMOS W=2U L=0.18U AD=1P AS=0.3P MN6 COUT CN GND GND NMOS W=2U L=0.18U AD=1P AS=1P MP6 COUT CN VDD VDD PMOS W=4U L=0.18U AD=2P AS=2P CI1 I1 GND 2FF CI3 I3 GND 3FF CA A GND 4FF CB B GND 4FF CC C GND 2FF CCN CN GND 4FF CCOUT COUT GND 2FF . ENDS

121. 128 Physical Design Floorplan Standard cells Place & route Datapaths Slice planning Area estimation

122. 129 MIPS Floorplan

123. 130 MIPS Layout

124. 131 Standard Cells Uniform cell height Uniform well height M1 V DD and GND rails M2 Access to I/Os Well / substrate taps Exploits regularity

125. 132 Synthesized Controller Synthesize HDL into gate-level netlist Place & Route using standard cell library

126. 133 Pitch Matching Synthesized controller area is mostly wires Design is smaller if wires run through/over cells Smaller = faster, lower power as well! Design snap-together cells for datapaths and arrays Plan wires into cells Connect by abutment Exploits locality Takes lots of effort

127. 134 MIPS Datapath 8-bit datapath built from 8 bitslices (regularity) Zipper at top drives control signals to datapath

128. 135 Slice Plans Slice plan for bitslice Cell ordering, dimensions, wiring tracks Arrange cells for wiring locality

129. 136 Area Estimation Need area estimates to make floorplan Compare to another block you already designed Or estimate from transistor counts Budget room for large wiring tracks Your mileage may vary; derate by 2x for class.

130. 137 Design Verification Fabrication is slow & expensive MOSIS 0.6 m m: $1000, 3 months 65 nm: $3M, 1 month Debugging chips is very hard Limited visibility into operation Prove design is right before building! Logic simulation Ckt. simulation / formal verification Layout vs. schematic comparison Design & electrical rule checks Verification is > 50% of effort on most chips!

131. 138 Fabrication & Packaging Tapeout final layout Fabrication 6, 8, 12” wafers Optimized for throughput, not latency (10 weeks!) Cut into individual dice Packaging Bond gold wires from die I/O pads to package

132. 139 Testing Test that chip operates Design errors Manufacturing errors A single dust particle or wafer defect kills a die Yields from 90% to < 10% Depends on die size, maturity of process Test each part before shipping to customer

133. 140 Custom vs. Synthesis 8-bit Implementations

134. 141 MIPS R3000 Processor 32-bit 2 nd generation commercial processor (1988) Led by John Hennessy (Stanford, MIPS Founder) 32-64 KB Caches 1.2 m m process 111K Transistors Up to 12-40 MHz 66 mm 2 die 145 I/O Pins V DD = 5 V 4 Watts SGI Workstations http://gecko54000.free.fr/?documentations=1988_MIPS_R3000