VLSI Design_ Stick Diagrams_slidess.pptx

Stick Diagrams

1. Layout - Recap

2. Stick Diagram Stick diagrams are used to display topography and layer information using simple diagram – abstract model. display layer information through colour coding. If single colour is used, then line width and dashes are used to show different layers. An interface between symbolic circuit diagram and layout diagram. show all components and via, and their relative placements. need not to be of scale. Stick diagrams do not show: transistor sizes. exact placement of components. lengths, widths, well boundaries. Metal 2 Metal 1 Metal 3 Poly-Si N-diff P-diff Metal Poly-Si N-diff P-diff A stick diagram is a cartoon of a layout.

3. Stick Diagram Rules Rule 1: When two or more sticks of same type (or layer) cross or touch each other, there is an electrical contact between them. Rule 2: When two or more sticks of different type cross or touch each other, there is NO electrical contact between them. If electrical contact is required, then show the connection explicitly.

4. Stick Diagram Rules (contd.) Rule 3: When a poly cross the diffusion layer, then it represent a transistor. If contact is shown, then it is not a transistor. Rule 4: In CMOS a demarcation line is drawn to avoid touching of p-diff with n-diff. All PMOS must lie on one side of the line and all NMOS will have to be on the other side. pMOS at the top – pull-up network nMOS at the bottom – pull-down network

5. How to draw Stick Diagram First we’ll write the logic/Boolean expression in the complementary format. Draw a static CMOS diagram. Convert the design to stick diagram. p-MOS n-MOS CMOS Inverter S D S D

6. Euler Graph Technique can be used to determine if any complex CMOS gate can be physically laid out in an optimum fashion! Euler’s Path : path through all nodes in the graph such that each edge in the graph is only visited once. CMOS circuit equivalent: Vertices – Source/Drain connections Edges – Transistor gates that connect the S/D ‘Vertices’. Diffusion – 1 row PolySi runs vertically Each transistor must “touch” electrically ones next to it – metal may be used. To form an uninterrupted strip of diffusion, all transistors must be visited in sequence. Both Euler paths for PUN and PDN must have the same sequence. The sequence of edges in the Euler path equals the ordering of the inputs in the gate layout. Euler’s Path Implement Boolean expression in the complementary format or CMOS Logic. Draw a static CMOS diagram, and its logic graph. Find a Euler path that cover the graph, sequence for PUN and PDN should be same. Convert the design to stick diagram, keeping sequence of Euler path as the sequence of the inputs.

7. Euler’s Path (Example) A B C

8. Stick Diagram - Examples CMOS NAND B A V DD GND V out D D S S Y D D S S A B GND V DD (topological placement)

9. Stick Diagram - Examples CMOS NOR

10. Stick Diagram - Examples

11. MOS Transistor Characteristics So far, we have treated transistors as ideal switches MOS transistor is majority-carrier device. Current in the conducting channel is controlled by V G . An ON transistor passes a finite amount of current Depends on terminal voltages Derive current-voltage (I-V) relationships Transit times, Charge, carrier mobility, gate capacitance, Electric field, permittivity of gate dielectric. Transistor gate, source, drain all have capacitance I = C (DV/Dt) -> Dt = (C/I) DV Capacitance and current determine speed

12. MOS Capacitor Gate and body form MOS capacitor Operating mods Accumulation Depletion Inversion Threshold Voltage Doping level Thickness of oxide

13. Terminal Voltages Mode of operation depends on V g , V d , V s V gs = V g – V s V gd = V g – V d V ds = V d – V s = V gs – V gd Source and drain are symmetric diffusion terminals By convention, source is terminal at lower voltage Hence V ds  0 nMOS body is grounded. First assume source is 0 too.

14. nMOS Operation Three regions of operation Cutoff No channel I ds ≈ Linear Channel forms Current flows from d to s e - from s to d I ds increases with V ds Similar to linear resistor Saturation Channel pinches off I ds independent of V ds We say current saturates Similar to current source

15. Long Channel I-V Characteristic In Linear region, I ds depends on How much charge is in the channel? How fast is the charge moving? I ds = Q channel /t t= time for charge to transit the channel Assumption: Channel length is long enough to have minimal lateral electric field. Long-channel, Ideal, First-order, Shockley model. Current (OFF) = 0.

16. Channel Charge MOS structure looks like parallel plate capacitor while operating in inversions (Q = CV) Gate – oxide – channel Q channel = C g ( V gc – V t ) C g = e ox WL /t ox = C ox WL ; C ox = e ox / t ox V = V gc – V t = ( V gs – V ds /2) – V t On the left of channel, V gs On the right of Channel, V gd = V gs – V ds Computing the Average: V gc = ( V gs + ( V gs – V ds ))/2 = V gs – V ds /2 Q channel = C ox WL *(( V gs -V ds /2)-V t )

17. Carrier Velocity Charge is carried by e- Carrier velocity, v , proportional to lateral E-field v = m E m called mobility Electron mobility ~ 2-3 times higher than hole mobility Typical m e- ~ 500-700 cm 2 /V.s Electrons are propelled by the lateral electric field between source and drain E = V ds /L Time for carrier to cross channel: t = L / v

18. nMOS I-V: Linear Now we know How much charge Q channel is in the channel How much time t each carrier takes to cross Linear Region: Vgs > Vt Vds ~ relatively small

19. nMOS I-V: Saturation V gd < V t , channel pinches off near drain V ds = V GT = V gs -V t Channel no longer inverted in the vicinity of drain When V ds > V dsat = V gs – V t V dsat : Drain Saturation Voltage Now drain voltage no longer increases current

20. Long Channel I-V ( nMOS ) Shockley 1 st order transistor models

21. Example Fabrication process is 0.6 µm. From AMI Semiconductor t ox = 100 Å m = 350 cm 2 /V*s V t = 0.7 V Plot I ds vs. V ds V gs = 0, 1, 2, 3, 4, 5 Use W/L = 4/2 l

22. Capacitance Any two conductors separated by an insulator have capacitance Gate to channel capacitor is very important Creates channel charge necessary for operation Source and drain have capacitance to body Across reverse-biased diodes Called diffusion capacitance because it is associated with source/drain diffusion

23. Gate Capacitance Approximate channel as connected to source C gs = e ox WL /t ox = C ox WL = C permicron W C permicron is typically about 2 fF / m m

24. Diffusion Capacitance C sb , C db Undesirable, called parasitic capacitance Capacitance depends on area and perimeter Use small diffusion nodes Comparable to C g for contacted diff ½ C g for uncontacted Varies with process