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About This Presentation
ff
Slide Content
VLSI Design (EC 302)
Dr. Sumit Kale
Assistant Professor
Department of Electronics and Communication Engineering
DTU Delhi
1VLSI Design (EC-302)
Dr. Sumit Kale
Assistant Professor
Department of Electronics and Communication Engineering
DTU Delhi
1VLSI Design (EC-302)
Course introduction
2VLSI Design (EC-302)
2VLSI Design (EC-302)
UNITTOPICS HOURS
I
Introduction to VLSI, Manufacturing process of CMOS integrated circuits, CMOS n-well process design rules packaging
integrated circuits, stick diagram, IC layout design and tools, trends in process technology,
MOS transistor, Energy band diagram of MOS system, MOS under external bias, derivation of threshold voltage equation,
gradual channel approximation, MOS I-V characteristics, secondary effects in MOSFETS, MOSFET scaling and small
geometry effects, MOS capacitances, MOS C-V characteristics
8
II
MOS inverters: Resistive load inverter, inverter with n-type MOSFET load, CMOS inverter: Switching Threshold, Noise
Margin,
Dynamic behaviour of CMOS inverter, computing capacitances, Propagation delay, Inverter Design with Delay Constraints,
Estimation of Interconnect Parasitics, Calculation of Interconnect Delay, Static and dynamic power consumption, energy,
and energy delay product calculations
8
III
Designing Combinational Logic Gates in MOS and CMOS: MOS logic circuits with depletion MOS load.
Static CMOS Design: Complementary CMOS, Ratioed logic, Pass transistor logic, pseudo nMOS logic, DCVSL Logic
Dynamic CMOS logic, clocked CMOS logic CMOS domino logic, NP domino logic, speed and power dissipation of Dynamic
logic, cascading dynamic gates.
8
I
Introduction to VLSI, Manufacturing process of CMOS integrated circuits, CMOS n-well process design rules packaging
integrated circuits, stick diagram, IC layout design and tools, trends in process technology,
MOS transistor, Energy band diagram of MOS system, MOS under external bias, derivation of threshold voltage equation,
gradual channel approximation, MOS I-V characteristics, secondary effects in MOSFETS, MOSFET scaling and small
geometry effects, MOS capacitances, MOS C-V characteristics
8
II
MOS inverters: Resistive load inverter, inverter with n-type MOSFET load, CMOS inverter: Switching Threshold, Noise
Margin,
Dynamic behaviour of CMOS inverter, computing capacitances, Propagation delay, Inverter Design with Delay Constraints,
Estimation of Interconnect Parasitics, Calculation of Interconnect Delay, Static and dynamic power consumption, energy,
and energy delay product calculations
8
III
Designing Combinational Logic Gates in MOS and CMOS: MOS logic circuits with depletion MOS load.
Static CMOS Design: Complementary CMOS, Ratioed logic, Pass transistor logic, pseudo nMOS logic, DCVSL Logic
Dynamic CMOS logic, clocked CMOS logic CMOS domino logic, NP domino logic, speed and power dissipation of Dynamic
logic, cascading dynamic gates.
8
UNITTOPICS HOURS
IV
Designing sequential logic circuits: Timing matrices for sequential circuits, classification of memory elements,
static latches and registers, the bistability principle, multiplexer based latches, Master slave Edge triggered register, staticSR
flip flops,
dynamic latches and registers, dynamic transmission gate edge triggered register, the C2MOS register, TSPC register , Pulse
registers, sense amplifier based registers, Pipelining, Latch verses Register based pipelines, NORA-CMOS. Two-phase logic
structure
10
V Semiconductor Memories: DRAM, SRAM , Nonvolatilememory, Flash memory, Introduction to memory peripheral circuits
(Added)
VLSI designing methodology –Introduction, VLSI designs flow, Computer aided design technology: Design capture and
verification tools
Design Hierarchy Concept of regularity, Modularity & Locality, VLSI design style, Design quality
8
Total Lecture Hours 42
IV
Designing sequential logic circuits: Timing matrices for sequential circuits, classification of memory elements,
static latches and registers, the bistability principle, multiplexer based latches, Master slave Edge triggered register, staticSR
flip flops,
dynamic latches and registers, dynamic transmission gate edge triggered register, the C2MOS register, TSPC register , Pulse
registers, sense amplifier based registers, Pipelining, Latch verses Register based pipelines, NORA-CMOS. Two-phase logic
structure
10
V Semiconductor Memories: DRAM, SRAM , Nonvolatilememory, Flash memory, Introduction to memory peripheral circuits
(Added)
VLSI designing methodology –Introduction, VLSI designs flow, Computer aided design technology: Design capture and
verification tools
Design Hierarchy Concept of regularity, Modularity & Locality, VLSI design style, Design quality
8
Total Lecture Hours 42
Suggested Books
5VLSI Design (EC-302)
5VLSI Design (EC-302)
What is VLSI?
•Very-large-scaleintegration(VLSI)istheprocessofcreating
anintegratedcircuit(IC)bycombiningthousandsoftransistorsintoa
singlechip.
•VLSIbeganinthe1970swhencomplexsemiconductorand
communicationtechnologieswerebeingdeveloped.
•ThemicroprocessorisaVLSIdevice.
•BeforetheintroductionofVLSItechnologymostICshadalimitedset
offunctionstheycouldperform.
•AnelectroniccircuitmightconsistofaCPU,ROM,RAMand
othergluelogic.VLSIletsICdesignersaddalloftheseintoonechip.
7VLSI Design (EC-302)
•Very-large-scaleintegration(VLSI)istheprocessofcreating
anintegratedcircuit(IC)bycombiningthousandsoftransistorsintoa
singlechip.
•VLSIbeganinthe1970swhencomplexsemiconductorand
communicationtechnologieswerebeingdeveloped.
•ThemicroprocessorisaVLSIdevice.
•BeforetheintroductionofVLSItechnologymostICshadalimitedset
offunctionstheycouldperform.
•AnelectroniccircuitmightconsistofaCPU,ROM,RAMand
othergluelogic.VLSIletsICdesignersaddalloftheseintoonechip.
7VLSI Design (EC-302)
•Verylarge-scaleintegration(VLSI)istheprocessofintegratingor
embeddinghundredsofthousandsoftransistorsonasinglesilicon
semiconductormicrochip.
•VLSItechnologywasconceivedinthelate1970swhenadvancedlevel
computerprocessormicrochipswereunderdevelopment.
•VLSIisasuccessortolarge-scaleintegration(LSI),medium-scale
integration(MSI)andsmall-scaleintegration(SSI)technologies.
8VLSI Design (EC-302)
embeddinghundredsofthousandsoftransistorsonasinglesilicon
semiconductormicrochip.
•VLSItechnologywasconceivedinthelate1970swhenadvancedlevel
computerprocessormicrochipswereunderdevelopment.
•VLSIisasuccessortolarge-scaleintegration(LSI),medium-scale
integration(MSI)andsmall-scaleintegration(SSI)technologies.
8VLSI Design (EC-302)
Integrated circuit classification
Name Signification Year
Number of
Transistors
Number of
Logic Gates
SSI
small-scale
integration
1964 1 to 10 1 to 12
MSI
medium-scale
integration
1968 10 to 500 13 to 99
LSI
large-scale
integration
1971 500 to 20,000100 to 9,999
VLSI
very large-scale
integration
1980
20,000 to
1,000,000
10,000 to
99,999
ULSI
ultra-large-scale
integration
1984
1,000,000 and
more
100,000 and
more
9VLSI Design (EC-302)
Name Signification Year
Number of
Transistors
Number of
Logic Gates
SSI
small-scale
integration
1964 1 to 10 1 to 12
MSI
medium-scale
integration
1968 10 to 500 13 to 99
LSI
large-scale
integration
1971 500 to 20,000100 to 9,999
VLSI
very large-scale
integration
1980
20,000 to
1,000,000
10,000 to
99,999
ULSI
ultra-large-scale
integration
1984
1,000,000 and
more
100,000 and
more
9VLSI Design (EC-302)
Why VLSI?
❑Integrationimprovesthedesign
❑Lowerparasitic=higherspeed
❑Lowerpowerconsumption
❑Physicallysmaller
❑Integrationreducesmanufacturingcost-(almost)nomanual
assembly
10VLSI Design (EC-302)
❑Integrationimprovesthedesign
❑Lowerparasitic=higherspeed
❑Lowerpowerconsumption
❑Physicallysmaller
❑Integrationreducesmanufacturingcost-(almost)nomanual
assembly
10VLSI Design (EC-302)
VLSI advantages
❑Reduces the Size of Circuits.
❑Reduces the effective cost of the devices.
❑Increases the Operating speed of circuits
❑Requires less power than Discrete components.
❑Higher Reliability
❑Occupies a relatively smaller area.
11VLSI Design (EC-302)
❑Reduces the Size of Circuits.
❑Reduces the effective cost of the devices.
❑Increases the Operating speed of circuits
❑Requires less power than Discrete components.
❑Higher Reliability
❑Occupies a relatively smaller area.
11VLSI Design (EC-302)
VLSI Applications
•VLSIisanimplementationtechnologyforelectroniccircuitry-analogueor
digitalItisconcernedwithformingapatternofinterconnectedswitches
andgatesonthesurfaceofacrystalofsemiconductor
•Microprocessors
•personal computers
•microcontrollers
•Memory-DRAM/SRAM
•SpecialPurposeProcessors-ASICS(CDplayers,DSPapplications)
•OpticalSwitches
•Hasmadehighlysophisticatedcontrolsystemsmass-producableand
thereforecheap
12VLSI Design (EC-302)
•VLSIisanimplementationtechnologyforelectroniccircuitry-analogueor
digitalItisconcernedwithformingapatternofinterconnectedswitches
andgatesonthesurfaceofacrystalofsemiconductor
•Microprocessors
•personal computers
•microcontrollers
•Memory-DRAM/SRAM
•SpecialPurposeProcessors-ASICS(CDplayers,DSPapplications)
•OpticalSwitches
•Hasmadehighlysophisticatedcontrolsystemsmass-producableand
thereforecheap
12VLSI Design (EC-302)
In today's world VLSI chips are widely used in various branches of
Engineering like:
❑Voice and Data Communication networks
❑Digital Signal Processing
❑Computers
❑Commercial Electronics
❑Automobiles
❑Medicine and many more.
13VLSI Design (EC-302)
Engineering like:
❑Voice and Data Communication networks
❑Digital Signal Processing
❑Computers
❑Commercial Electronics
❑Automobiles
❑Medicine and many more.
13VLSI Design (EC-302)
Top 10 VLSI Companies in India
1 | Texas Instruments
Corporate office–Dallas, United State |Establishment–1951 |
Business–Semiconductor |Website–www.ti.com|
Texas Instruments is world’s third largest semiconductor company and a chip
producer for mobile phones. The company is among the top 10 semiconductor
companies in India and its product offering includes analog electronics, calculators,
integrated circuits and radio frequency identification. It was founded in year 1951
and headquartered in Dallas, United states.
2 | Analog Device Inc.
Corporate office–Norwood, USA |Establishment–1965 |
Business–Semiconductor |Website–www.analog.com|
Analog Device Inc is a semiconductor design and manufacturing company which is
a market leader in data conversion and signal technology. Analog device is founded
in year 1965 and its design center is located in Australia, Canada, Israel, Japan,
Scotland, Taiwan, Germany, UK, China, Scotland and India.
14VLSI Design (EC-302)
1 | Texas Instruments
Corporate office–Dallas, United State |Establishment–1951 |
Business–Semiconductor |Website–www.ti.com|
Texas Instruments is world’s third largest semiconductor company and a chip
producer for mobile phones. The company is among the top 10 semiconductor
companies in India and its product offering includes analog electronics, calculators,
integrated circuits and radio frequency identification. It was founded in year 1951
and headquartered in Dallas, United states.
2 | Analog Device Inc.
Corporate office–Norwood, USA |Establishment–1965 |
Business–Semiconductor |Website–www.analog.com|
Analog Device Inc is a semiconductor design and manufacturing company which is
a market leader in data conversion and signal technology. Analog device is founded
in year 1965 and its design center is located in Australia, Canada, Israel, Japan,
Scotland, Taiwan, Germany, UK, China, Scotland and India.
14VLSI Design (EC-302)
3 | Cypress Semiconductor Corporation
Corporate office–San Jose, USA |Establishment–1982 |
Business–Semiconductor |Website–www.cypress.com|
Cypress semiconductor is a semiconductor manufacturing and design
company established in year 1982. The US based company has total 14
design centers and more than 40 sales offices located all across the globe. Its
product offering includes capacitance sensing systems, Psoc, optical sensor
and wireless solution.
4 | Broadcom Corporation
Corporate office–Irvine, USA |Establishment–1991 |
Business–Semiconductor |Website–www.broadcom.com|
Broad corporation is rated among the top 10 semiconductor manufacturers
in India; an American company which was established in 1991 by professor
and student duo Henry Samueliand Henry T Nicholas. Its product portfolio
includes Integrated circuits, cable converter boxes, wireless networks, cable
modems, professors, Bluetooth, VIOP, GPS, server farms, digital subscriber
line.
15VLSI Design (EC-302)
Corporate office–San Jose, USA |Establishment–1982 |
Business–Semiconductor |Website–www.cypress.com|
Cypress semiconductor is a semiconductor manufacturing and design
company established in year 1982. The US based company has total 14
design centers and more than 40 sales offices located all across the globe. Its
product offering includes capacitance sensing systems, Psoc, optical sensor
and wireless solution.
4 | Broadcom Corporation
Corporate office–Irvine, USA |Establishment–1991 |
Business–Semiconductor |Website–www.broadcom.com|
Broad corporation is rated among the top 10 semiconductor manufacturers
in India; an American company which was established in 1991 by professor
and student duo Henry Samueliand Henry T Nicholas. Its product portfolio
includes Integrated circuits, cable converter boxes, wireless networks, cable
modems, professors, Bluetooth, VIOP, GPS, server farms, digital subscriber
line.
15VLSI Design (EC-302)
5 | Cisco Systems
Corporate office–San Jose, USA |Establishment–1984 |
Business–Network Equipments|Website–www.cisco.com|
Cisco Systems is a MNC and one of the leading design and manufacturer of
networking equipment. Its major product offering includes Networking
device, Optical networking, storage area networks, wireless, VOIP, IOS and
NX OS software etc. It is headquartered in San Jose, USA and has employed
more than 75000 people all across the globe.
6 | Bit Mapper Integration Technologies Private Limited
Corporate office–Pune, Maharashtra |Establishment–1985 |
Business–Electronic Design |Website–www.bitmapper.com|
Bit Mapper is a technology company offering electronic system design using
PCB and FPGA design. The company is offering design solution to various
sector such as defense, aerospace, telecommunication and software. It is a
leading VLSI company in India and its expertise includes PCB design, Flexible
circuits, Thermal analysis, ADC based board and many more.
16VLSI Design (EC-302)
Corporate office–San Jose, USA |Establishment–1984 |
Business–Network Equipments|Website–www.cisco.com|
Cisco Systems is a MNC and one of the leading design and manufacturer of
networking equipment. Its major product offering includes Networking
device, Optical networking, storage area networks, wireless, VOIP, IOS and
NX OS software etc. It is headquartered in San Jose, USA and has employed
more than 75000 people all across the globe.
6 | Bit Mapper Integration Technologies Private Limited
Corporate office–Pune, Maharashtra |Establishment–1985 |
Business–Electronic Design |Website–www.bitmapper.com|
Bit Mapper is a technology company offering electronic system design using
PCB and FPGA design. The company is offering design solution to various
sector such as defense, aerospace, telecommunication and software. It is a
leading VLSI company in India and its expertise includes PCB design, Flexible
circuits, Thermal analysis, ADC based board and many more.
16VLSI Design (EC-302)
7 | Horizon Semiconductors
Corporate office–Bangalore, Karnataka |Establishment–1815|
Business–Semiconductor |Website–www.horizonsemi.com|
Horizon Semiconductors is an integrated silicon solution provider and
its product offering includes single chip cable, Satellite set-top box, dual
channel HD channel, 2d & 3d graphics, Single chip Blu-ray, trans coder
and encoder ICs. It is one among the top semiconductor companies in
India.
8 | Einfochipslimited
Corporate office–Ahmadabad, Gujarat |Establishment–1994 |
Business–Semiconductor |Website–www.einfochips.com|
Among the top 10 VLSI companies in India, Einfochipsis one of the
most trusted brands in product engineering and semiconductor service;
and serves to Aerospace & defense, energy, healthcare, retail and
software sector. It is headquartered in Ahmadabad, Gujarat.
17VLSI Design (EC-302)
Corporate office–Bangalore, Karnataka |Establishment–1815|
Business–Semiconductor |Website–www.horizonsemi.com|
Horizon Semiconductors is an integrated silicon solution provider and
its product offering includes single chip cable, Satellite set-top box, dual
channel HD channel, 2d & 3d graphics, Single chip Blu-ray, trans coder
and encoder ICs. It is one among the top semiconductor companies in
India.
8 | Einfochipslimited
Corporate office–Ahmadabad, Gujarat |Establishment–1994 |
Business–Semiconductor |Website–www.einfochips.com|
Among the top 10 VLSI companies in India, Einfochipsis one of the
most trusted brands in product engineering and semiconductor service;
and serves to Aerospace & defense, energy, healthcare, retail and
software sector. It is headquartered in Ahmadabad, Gujarat.
17VLSI Design (EC-302)
•9 | Trident Tech Labs
Corporate office–New Delhi, India |Establishment–2000 |
Business–Electronic Design |Website–www.tridenttechlabs.com|
Established in year 2000, Trident Techlabsis a knowledge based technology
organization which offers electronic design solution. The company is a
leading computer aided engineering provider and reputed name in Very
Large Scale Integration companies in India.
•10 | HCL technologies
Corporate office–Noida, Uttar Pradesh |Establishment–1991 |
Business–IT and Software |Website–www.hcltech.com|
HCL technologies is a software, KPO and IT service provider headquartered
in Noida, Uttar Pradesh. The company has office in 26 countries worldwide
to provide support and consultancy to industry verticals including defense
& aviation industry, energy, power, software, manufacturing,
semiconductor, retail etc. It has also well known name in VLSI companies in
India and its engineering & Research division provides support to
semiconductor industry.
18VLSI Design (EC-302)
Corporate office–New Delhi, India |Establishment–2000 |
Business–Electronic Design |Website–www.tridenttechlabs.com|
Established in year 2000, Trident Techlabsis a knowledge based technology
organization which offers electronic design solution. The company is a
leading computer aided engineering provider and reputed name in Very
Large Scale Integration companies in India.
•10 | HCL technologies
Corporate office–Noida, Uttar Pradesh |Establishment–1991 |
Business–IT and Software |Website–www.hcltech.com|
HCL technologies is a software, KPO and IT service provider headquartered
in Noida, Uttar Pradesh. The company has office in 26 countries worldwide
to provide support and consultancy to industry verticals including defense
& aviation industry, energy, power, software, manufacturing,
semiconductor, retail etc. It has also well known name in VLSI companies in
India and its engineering & Research division provides support to
semiconductor industry.
18VLSI Design (EC-302)
List of Experiment
VLSI Design (EC-302) 19
VLSI Design (EC-302) 19
IV Characteristics of MOSFET
VLSI Design (EC-302) 20
VLSI Design (EC-302) 20
VLSI Design (EC-302) 21
Manufacturing of CMOS Integrated Circuits
VLSI Design (EC-302) 22
Cross section of an n-well CMOS process
Cross section of modern dual-well CMOS process
VLSI Design (EC-302) 22
Cross section of an n-well CMOS process
Cross section of modern dual-well CMOS process
The Silicon Wafer
VLSI Design (EC-302) 23
Single-crystal ingot and sliced wafers
The base material for the manufacturing process comes
in the form of a single-crystalline, lightly doped wafer.
These wafers have typical diameters between 4 and 12
inches (10 and 30 cm, respectively) and a thickness of
at most 1 mm, and are obtained by cutting a single crystal ingot
into thin slices.
A starting wafer of the p--type might be doped around the
levels of 2×10
21
impurities/m
3
.
VLSI Design (EC-302) 23
Single-crystal ingot and sliced wafers
The base material for the manufacturing process comes
in the form of a single-crystalline, lightly doped wafer.
These wafers have typical diameters between 4 and 12
inches (10 and 30 cm, respectively) and a thickness of
at most 1 mm, and are obtained by cutting a single crystal ingot
into thin slices.
A starting wafer of the p--type might be doped around the
levels of 2×10
21
impurities/m
3
.
Photolithography
Ineachprocessingstep,acertain
areaonthechipismaskedout
usingtheappropriateoptical
masksothatadesiredprocessing
stepcanbeselectivelyappliedto
theremainingregions.The
processingstepcanbeanyofa
widerangeoftasksincluding
oxidation,etching,metaland
polysilicondeposition,andion
implantation.Thetechniqueto
accomplishthisselective
masking,calledphotolithography.
VLSI Design (EC-302) 24
Ineachprocessingstep,acertain
areaonthechipismaskedout
usingtheappropriateoptical
masksothatadesiredprocessing
stepcanbeselectivelyappliedto
theremainingregions.The
processingstepcanbeanyofa
widerangeoftasksincluding
oxidation,etching,metaland
polysilicondeposition,andion
implantation.Thetechniqueto
accomplishthisselective
masking,calledphotolithography.
VLSI Design (EC-302) 24
1.Oxidationlayering—thisoptionalstepdepositsathinlayerofSiO
2overthecomplete
waferbyexposingittoamixtureofhigh-purityoxygenandhydrogenatapproximately
1000°C.Theoxideisusedasaninsulationlayerandalsoformstransistorgates.
2.Photoresistcoating—alight-sensitivepolymerisevenlyappliedwhilespinningthe
wafertoathicknessofapproximately1mm.Thismaterialisoriginallysolubleinan
organicsolvent,buthasthepropertythatthepolymerscrosslinkwhenexposedto
light,makingtheaffectedregionsinsoluble.Aphotoresistofthistypeiscalled
negative.Apositivephotoresisthastheoppositeproperties;originallyinsoluble,but
solubleafterexposure.
3.Stepperexposure—aglassmask(orreticle),containingthepatternsthatwewantto
transfertothesilicon,isbroughtincloseproximitytothewafer.Themaskis
opaqueintheregionsthatwewanttoprocess,andtransparentintheothers
(assuminganegativephotoresist).Theglassmaskcanbethoughtofasthenegativeof
onelayerofthemicrocircuit.Thecombinationofmaskandwaferisnowexposedto
ultra-violetlight.Wherethemaskistransparent,thephotoresistbecomesinsoluble.
4.Photoresistdevelopmentandbake—thewafersaredevelopedineitheranacidor
basesolutiontoremovethenon-exposedareasofphotoresist.Oncetheexposed
photoresistisremoved,thewaferis“soft-baked”atalowtemperaturetohardenthe
remainingphotoresist.
5.AcidEtching—materialisselectivelyremovedfromareasofthewaferthatarenot
coveredbyphotoresist.Thisisaccomplishedthroughtheuseofmanydifferenttypes
ofacid,baseandcausticsolutionsasafunctionofthematerialthatistoberemoved.
6.
VLSI Design (EC-302) 25
2overthecomplete
waferbyexposingittoamixtureofhigh-purityoxygenandhydrogenatapproximately
1000°C.Theoxideisusedasaninsulationlayerandalsoformstransistorgates.
2.Photoresistcoating—alight-sensitivepolymerisevenlyappliedwhilespinningthe
wafertoathicknessofapproximately1mm.Thismaterialisoriginallysolubleinan
organicsolvent,buthasthepropertythatthepolymerscrosslinkwhenexposedto
light,makingtheaffectedregionsinsoluble.Aphotoresistofthistypeiscalled
negative.Apositivephotoresisthastheoppositeproperties;originallyinsoluble,but
solubleafterexposure.
3.Stepperexposure—aglassmask(orreticle),containingthepatternsthatwewantto
transfertothesilicon,isbroughtincloseproximitytothewafer.Themaskis
opaqueintheregionsthatwewanttoprocess,andtransparentintheothers
(assuminganegativephotoresist).Theglassmaskcanbethoughtofasthenegativeof
onelayerofthemicrocircuit.Thecombinationofmaskandwaferisnowexposedto
ultra-violetlight.Wherethemaskistransparent,thephotoresistbecomesinsoluble.
4.Photoresistdevelopmentandbake—thewafersaredevelopedineitheranacidor
basesolutiontoremovethenon-exposedareasofphotoresist.Oncetheexposed
photoresistisremoved,thewaferis“soft-baked”atalowtemperaturetohardenthe
remainingphotoresist.
5.AcidEtching—materialisselectivelyremovedfromareasofthewaferthatarenot
coveredbyphotoresist.Thisisaccomplishedthroughtheuseofmanydifferenttypes
ofacid,baseandcausticsolutionsasafunctionofthematerialthatistoberemoved.
6.
VLSI Design (EC-302) 25
6.Spin,rinse,anddry—aspecialtool(calledSRD)cleansthewafer
withdeionizedwateranddriesitwithnitrogen.Themicroscopicscale
ofmodernsemiconductordevicesmeansthateventhesmallest
particleofdustordirtcandestroythecircuitry.Topreventthisfrom
happening,theprocessingstepsareperformedinultra-cleanrooms
wherethenumberofdustparticlespercubicfootofairranges
between1and10.
7.Variousprocesssteps—theexposedareacannowbesubjectedtoa
widerangeofprocesssteps,suchasionimplantation,plasmaetching,
ormetaldeposition.Thesearethesubjectsofthesubsequentsection.
8.Photoresistremoval(orashing)—ahigh-temperatureplasmaisused
toselectivelyremovetheremainingphotoresistwithoutdamaging
devicelayers.
VLSI Design (EC-302) 26
withdeionizedwateranddriesitwithnitrogen.Themicroscopicscale
ofmodernsemiconductordevicesmeansthateventhesmallest
particleofdustordirtcandestroythecircuitry.Topreventthisfrom
happening,theprocessingstepsareperformedinultra-cleanrooms
wherethenumberofdustparticlespercubicfootofairranges
between1and10.
7.Variousprocesssteps—theexposedareacannowbesubjectedtoa
widerangeofprocesssteps,suchasionimplantation,plasmaetching,
ormetaldeposition.Thesearethesubjectsofthesubsequentsection.
8.Photoresistremoval(orashing)—ahigh-temperatureplasmaisused
toselectivelyremovetheremainingphotoresistwithoutdamaging
devicelayers.
VLSI Design (EC-302) 26
Patterning of SiO
2
VLSI Design (EC-302) 27
2
VLSI Design (EC-302) 27
Diffusion and Ion Implantation
Thecreationofthesourceanddrainregions,wellandsubstratecontacts,thedopingofthe
polysilicon,andtheadjustmentsofthedevicethresholdarerequiredforfabrication.There
existtwoapproachesforintroducingthesedopants—diffusionandionimplantation.
Indiffusionimplantation,thewafersareplacedinaquartztubeembeddedina
heatedfurnace.Agascontainingthedopantisintroducedinthetube.Thehigh
temperaturesofthefurnace,typically900to1100°C,causethedopantstodiffuseintothe
exposedsurfacebothverticallyandhorizontally.
Inionimplantation,dopantsareintroducedasionsintothematerial.Theion
implantationsystemdirectsandsweepsabeamofpurifiedionsoverthesemiconductor
surface.Theaccelerationoftheionsdetermineshowdeeptheywillpenetratethe
material,whilethebeamcurrentandtheexposuretimedeterminethedosage.
VLSI Design (EC-302) 28
Thecreationofthesourceanddrainregions,wellandsubstratecontacts,thedopingofthe
polysilicon,andtheadjustmentsofthedevicethresholdarerequiredforfabrication.There
existtwoapproachesforintroducingthesedopants—diffusionandionimplantation.
Indiffusionimplantation,thewafersareplacedinaquartztubeembeddedina
heatedfurnace.Agascontainingthedopantisintroducedinthetube.Thehigh
temperaturesofthefurnace,typically900to1100°C,causethedopantstodiffuseintothe
exposedsurfacebothverticallyandhorizontally.
Inionimplantation,dopantsareintroducedasionsintothematerial.Theion
implantationsystemdirectsandsweepsabeamofpurifiedionsoverthesemiconductor
surface.Theaccelerationoftheionsdetermineshowdeeptheywillpenetratethe
material,whilethebeamcurrentandtheexposuretimedeterminethedosage.
VLSI Design (EC-302) 28
Deposition
AnyCMOSprocessrequirestherepetitivedepositionoflayersofamaterialover
thecompletewafer,toeitheractasbuffersforaprocessingstep,orasinsulatingor
conductinglayers.
VLSI Design (EC-302) 29
AnyCMOSprocessrequirestherepetitivedepositionoflayersofamaterialover
thecompletewafer,toeitheractasbuffersforaprocessingstep,orasinsulatingor
conductinglayers.
VLSI Design (EC-302) 29
Etching
Etchingisusedtoselectivelyformpatternssuchaswiresandcontactholes.
Thewetetchingprocesswasdescribedearlier,andmakesuseofacidorbasicsolutions.
Forinstance,hydrofluoricacidbufferedwithammoniumfluorideistypicallyusedtoetch
SiO
2.
Inrecentyears,dryorplasmaetchinghasmadealotofinroad.Awaferisplacedintothe
etchtool'sprocessingchamberandgivenanegativeelectricalcharge.Thechamberis
heatedto100°Candbroughttoavacuumlevelof7.5Pa,thenfilledwithapositively
chargedplasma(usuallyamixofnitrogen,chlorineandborontrichloride).Theopposing
electricalchargescausetherapidlymovingplasmamoleculestoalignthemselvesina
verticaldirection,formingamicroscopicchemicalandphysical“sandblasting”actionwhich
removestheexposedmaterial.Plasmaetchinghastheadvantageofofferingawell-defined
directionalitytotheetchingaction,creatingpatternswithsharpverticalcontours.
VLSI Design (EC-302) 30
Etchingisusedtoselectivelyformpatternssuchaswiresandcontactholes.
Thewetetchingprocesswasdescribedearlier,andmakesuseofacidorbasicsolutions.
Forinstance,hydrofluoricacidbufferedwithammoniumfluorideistypicallyusedtoetch
SiO
2.
Inrecentyears,dryorplasmaetchinghasmadealotofinroad.Awaferisplacedintothe
etchtool'sprocessingchamberandgivenanegativeelectricalcharge.Thechamberis
heatedto100°Candbroughttoavacuumlevelof7.5Pa,thenfilledwithapositively
chargedplasma(usuallyamixofnitrogen,chlorineandborontrichloride).Theopposing
electricalchargescausetherapidlymovingplasmamoleculestoalignthemselvesina
verticaldirection,formingamicroscopicchemicalandphysical“sandblasting”actionwhich
removestheexposedmaterial.Plasmaetchinghastheadvantageofofferingawell-defined
directionalitytotheetchingaction,creatingpatternswithsharpverticalcontours.
VLSI Design (EC-302) 30
Planarization
Toreliablydepositalayerofmaterialontothesemiconductorsurface,itisessential
thatthesurfaceisapproximatelyflat.Ifnospecialstepsweretaken,thiswould
definitelynotbethecaseinmodernCMOSprocesses,wheremultiplepatterned
metalinterconnectlayersaresuperimposedontoeachother.
Chemical-mechanicalplanarization(CMP)stepisincludedbeforethedepositionof
anextrametallayerontopoftheinsulatingSiO
2layer.Thisprocessusesaslurry
compound—aliquidcarrierwithasuspendedabrasivecomponentsuchas
aluminumoxideorsilica—tomicroscopicallyplaneadevicelayerandtoreducethe
stepheights.
VLSI Design (EC-302) 31
Toreliablydepositalayerofmaterialontothesemiconductorsurface,itisessential
thatthesurfaceisapproximatelyflat.Ifnospecialstepsweretaken,thiswould
definitelynotbethecaseinmodernCMOSprocesses,wheremultiplepatterned
metalinterconnectlayersaresuperimposedontoeachother.
Chemical-mechanicalplanarization(CMP)stepisincludedbeforethedepositionof
anextrametallayerontopoftheinsulatingSiO
2layer.Thisprocessusesaslurry
compound—aliquidcarrierwithasuspendedabrasivecomponentsuchas
aluminumoxideorsilica—tomicroscopicallyplaneadevicelayerandtoreducethe
stepheights.
VLSI Design (EC-302) 31
Process flow for the fabrication of an n-type MOSFET on p-type
silicon
VLSI Design (EC-302) 32
silicon
VLSI Design (EC-302) 32
Cont..
VLSI Design (EC-302) 33
VLSI Design (EC-302) 33
Cont…`
VLSI Design (EC-302) 34
VLSI Design (EC-302) 34
Cont…..
VLSI Design (EC-302) 35
VLSI Design (EC-302) 35
CMOS Fabrication
•CMOS transistors are fabricated on silicon wafer
•Lithography process similar to printing press
•On each step, different materials are deposited or etched
•Easiest to understand by viewing both top and cross-section of wafer
in a simplified manufacturing process
36VLSI Design (EC-302)
•CMOS transistors are fabricated on silicon wafer
•Lithography process similar to printing press
•On each step, different materials are deposited or etched
•Easiest to understand by viewing both top and cross-section of wafer
in a simplified manufacturing process
36VLSI Design (EC-302)
CMOS n-well Process Inverter Cross-section
•Typically use p-type substrate for nMOS transistors
•Requires n-well for body of pMOStransistors
37VLSI Design (EC-302)
CMOS Inverter Schematic
•Typically use p-type substrate for nMOS transistors
•Requires n-well for body of pMOStransistors
37VLSI Design (EC-302)
CMOS Inverter Schematic
Well and Substrate Taps
•Substrate must be tied to GND and n-well to V
DD
•Metal to lightly-doped semiconductor forms poor
connection (used for Schottky Diode)
•Use heavily doped well and substrate contacts / tapsn+
p substrate
p+
n well
A
Y
GND
V
DD
n+p+
substrate tap well tap
n+ p+
38VLSI Design (EC-302)
•Substrate must be tied to GND and n-well to V
DD
•Metal to lightly-doped semiconductor forms poor
connection (used for Schottky Diode)
•Use heavily doped well and substrate contacts / tapsn+
p substrate
p+
n well
A
Y
GND
V
DD
n+p+
substrate tap well tap
n+ p+
38VLSI Design (EC-302)
Inverter Mask Set
•Transistors and wires are defined by masks
•Cross-section taken along dashed lineGND V
DD
Y
A
substrate tap well tap
nMOS transistor pMOS transistor
39VLSI Design (EC-302)
•Transistors and wires are defined by masks
•Cross-section taken along dashed lineGND V
DD
Y
A
substrate tap well tap
nMOS transistor pMOS transistor
39VLSI Design (EC-302)
Detailed Mask Views
•Six masks
•n-well
•Polysilicon
•n+ diffusion
•p+ diffusion
•Contact
•MetalMetal
Polysilicon
Contact
n+ Diffusion
p+ Diffusion
n well
40VLSI Design (EC-302)
•Six masks
•n-well
•Polysilicon
•n+ diffusion
•p+ diffusion
•Contact
•MetalMetal
Polysilicon
Contact
n+ Diffusion
p+ Diffusion
n well
40VLSI Design (EC-302)
Fabrication Steps
•Start with blank wafer
•Build inverter from the bottom up
•First step will be to form the n-well
•Cover wafer with protective layer of SiO
2(oxide)
•Remove layer where n-well should be built
•Implant or diffuse n dopants into exposed wafer
•Strip off SiO
2p substrate
41VLSI Design (EC-302)
•Start with blank wafer
•Build inverter from the bottom up
•First step will be to form the n-well
•Cover wafer with protective layer of SiO
2(oxide)
•Remove layer where n-well should be built
•Implant or diffuse n dopants into exposed wafer
•Strip off SiO
2p substrate
41VLSI Design (EC-302)
Oxidation
•Grow SiO
2on top of Si wafer
•900 –1200 C with H
2O or O
2in oxidation furnacep substrate
SiO
2
42VLSI Design (EC-302)
•Grow SiO
2on top of Si wafer
•900 –1200 C with H
2O or O
2in oxidation furnacep substrate
SiO
2
42VLSI Design (EC-302)
Photoresist
•Spin on photoresist
•Photoresistis a light-sensitive organic polymer
•Softens where exposed to lightp substrate
SiO
2
Photoresist
43VLSI Design (EC-302)
•Spin on photoresist
•Photoresistis a light-sensitive organic polymer
•Softens where exposed to lightp substrate
SiO
2
Photoresist
43VLSI Design (EC-302)
Lithography
•Expose photoresist through n-well mask
•Strip off exposed photoresistp substrate
SiO
2
Photoresist
44VLSI Design (EC-302)
•Expose photoresist through n-well mask
•Strip off exposed photoresistp substrate
SiO
2
Photoresist
44VLSI Design (EC-302)
Etch
•Etch oxide with hydrofluoric acid (HF)
•Seeps through skin and eats bone; nasty stuff!!!
•Only attacks oxide where resist has been exposedp substrate
SiO
2
Photoresist
45VLSI Design (EC-302)
•Etch oxide with hydrofluoric acid (HF)
•Seeps through skin and eats bone; nasty stuff!!!
•Only attacks oxide where resist has been exposedp substrate
SiO
2
Photoresist
45VLSI Design (EC-302)
Strip Photoresist
•Strip off remaining photoresist
•Use mixture of acids called piranahetch
•Necessary so resist doesn’t melt in next stepp substrate
SiO
2
46VLSI Design (EC-302)
•Strip off remaining photoresist
•Use mixture of acids called piranahetch
•Necessary so resist doesn’t melt in next stepp substrate
SiO
2
46VLSI Design (EC-302)
n-well
•n-well is formed with diffusion or ion implantation
•Diffusion
•Place wafer in furnace with arsenic gas
•Heat until As atoms diffuse into exposed Si
•Ion Implanatation
•Blast wafer with beam of As ions
•Ions blocked by SiO
2, only enter exposed Sin well
SiO
2
47VLSI Design (EC-302)
•n-well is formed with diffusion or ion implantation
•Diffusion
•Place wafer in furnace with arsenic gas
•Heat until As atoms diffuse into exposed Si
•Ion Implanatation
•Blast wafer with beam of As ions
•Ions blocked by SiO
2, only enter exposed Sin well
SiO
2
47VLSI Design (EC-302)
Strip Oxide
•Strip off the remaining oxide using HF
•Back to bare wafer with n-well
•Subsequent steps involve similar series of stepsp substrate
n well
48VLSI Design (EC-302)
•Strip off the remaining oxide using HF
•Back to bare wafer with n-well
•Subsequent steps involve similar series of stepsp substrate
n well
48VLSI Design (EC-302)
Polysilicon
•Deposit very thin layer of gate oxide
•< 20 Å(6-7 atomic layers)
•Chemical Vapor Deposition (CVD) of silicon layer
•Place wafer in furnace with Silanegas (SiH
4)
•Forms many small crystals called polysilicon
•Heavily doped to be good conductorThin gate oxide
Polysilicon
p substrate
n well
49VLSI Design (EC-302)
•Deposit very thin layer of gate oxide
•< 20 Å(6-7 atomic layers)
•Chemical Vapor Deposition (CVD) of silicon layer
•Place wafer in furnace with Silanegas (SiH
4)
•Forms many small crystals called polysilicon
•Heavily doped to be good conductorThin gate oxide
Polysilicon
p substrate
n well
49VLSI Design (EC-302)
Polysilicon Patterning
•Use same lithography process to pattern polysiliconPolysilicon p substrate
Thin gate oxide
Polysilicon
n well
50VLSI Design (EC-302)
•Use same lithography process to pattern polysiliconPolysilicon p substrate
Thin gate oxide
Polysilicon
n well
50VLSI Design (EC-302)
N-diffusion
•Use oxide and masking to expose where n+ dopants should be
diffused or implanted
•N-diffusion forms nMOS source, drain, and n-well contactp substrate
n well
51VLSI Design (EC-302)
•Use oxide and masking to expose where n+ dopants should be
diffused or implanted
•N-diffusion forms nMOS source, drain, and n-well contactp substrate
n well
51VLSI Design (EC-302)
N-diffusion (cont.)
•Pattern oxide and form n+ regionsp substrate
n well n+ Diffusion
52VLSI Design (EC-302)
•Pattern oxide and form n+ regionsp substrate
n well n+ Diffusion
52VLSI Design (EC-302)
N-diffusion (cont.)
•Historically dopants were diffused
•Usually ion implantation today
•But regions are still called diffusionn well
p substrate
n+n+ n+
53VLSI Design (EC-302)
•Historically dopants were diffused
•Usually ion implantation today
•But regions are still called diffusionn well
p substrate
n+n+ n+
53VLSI Design (EC-302)
N-diffusion (cont.)
•Strip off oxide to complete patterning stepn well
p substrate
n+n+ n+
54VLSI Design (EC-302)
•Strip off oxide to complete patterning stepn well
p substrate
n+n+ n+
54VLSI Design (EC-302)
P-Diffusion
•Similar set of steps form p+ diffusion regions for pMOS source and
drain and substrate contactp+ Diffusion p substrate
n well
n+n+ n+p+p+p+
55VLSI Design (EC-302)
•Similar set of steps form p+ diffusion regions for pMOS source and
drain and substrate contactp+ Diffusion p substrate
n well
n+n+ n+p+p+p+
55VLSI Design (EC-302)
Contacts
•Now we need to wire together the devices
•Cover chip with thick field oxide
•Etch oxide where contact cuts are neededp substrate
Thick field oxide
n well
n+n+ n+p+p+p+ Contact
56VLSI Design (EC-302)
•Now we need to wire together the devices
•Cover chip with thick field oxide
•Etch oxide where contact cuts are neededp substrate
Thick field oxide
n well
n+n+ n+p+p+p+ Contact
56VLSI Design (EC-302)
Metalization
•Sputter on aluminum over whole wafer
•Pattern to remove excess metal, leaving wiresp substrate
Metal
Thick field oxide
n well
n+n+ n+p+p+p+ Metal
57VLSI Design (EC-302)
•Sputter on aluminum over whole wafer
•Pattern to remove excess metal, leaving wiresp substrate
Metal
Thick field oxide
n well
n+n+ n+p+p+p+ Metal
57VLSI Design (EC-302)
Simplified process sequence for the fabrication of the n-well CMOS integrated
circuit with a single polysilicon layer, showing only major fabrication steps.
VLSI Design (EC-302) 58
circuit with a single polysilicon layer, showing only major fabrication steps.
VLSI Design (EC-302) 58
Layout Design Rules
Thephysicalmasklayoutofanycircuittobemanufacturedusingaparticular
processmustconformtoasetofgeometricconstraintsorrules,whichare
generallycalledlayoutdesignrules.
Thedesignrulesareusuallydescribedintwoways:
(i)Micronrules,inwhichthelayoutconstraintssuchasminimumfeaturesizes
andminimumallowablefeatureseparationsarestatedintermsofabsolute
dimensionsinmicrometers.
(ii)Lambdarules,whichspecifythelayoutconstraintsintermsofasingle
parameter(X)andthusallowlinear,proportionalscalingofallgeometrical
constraints.
VLSI Design (EC-302) 59
Thephysicalmasklayoutofanycircuittobemanufacturedusingaparticular
processmustconformtoasetofgeometricconstraintsorrules,whichare
generallycalledlayoutdesignrules.
Thedesignrulesareusuallydescribedintwoways:
(i)Micronrules,inwhichthelayoutconstraintssuchasminimumfeaturesizes
andminimumallowablefeatureseparationsarestatedintermsofabsolute
dimensionsinmicrometers.
(ii)Lambdarules,whichspecifythelayoutconstraintsintermsofasingle
parameter(X)andthusallowlinear,proportionalscalingofallgeometrical
constraints.
VLSI Design (EC-302) 59
VLSI Design (EC-302) 60
VLSI Design (EC-302) 61
VLSI Design (EC-302) 62
Layout
•Chips are specified with set of masks
•Minimum dimensions of masks determine transistor size (and hence
speed, cost, and power)
•Feature size f= distance between source and drain
•Set by minimum width of polysilicon
•Feature size improves 30% every 3 years or so
•Normalize for feature size when describing design rules
•Express rules in terms of l= f/2
•E.g. l= 0.3 mm in 0.6 mm process
63VLSI Design (EC-302)
•Chips are specified with set of masks
•Minimum dimensions of masks determine transistor size (and hence
speed, cost, and power)
•Feature size f= distance between source and drain
•Set by minimum width of polysilicon
•Feature size improves 30% every 3 years or so
•Normalize for feature size when describing design rules
•Express rules in terms of l= f/2
•E.g. l= 0.3 mm in 0.6 mm process
63VLSI Design (EC-302)
Simplified Design Rules
•Conservative rules to get you started
64VLSI Design (EC-302)
•Conservative rules to get you started
64VLSI Design (EC-302)
Inverter Layout
•Transistor dimensions specified as Width / Length
•Minimum size is 4l/ 2l, sometimes called 1 unit
•In f= 0.6 mm process, this is 1.2 mm wide, 0.6 mm long
VLSI Design (EC-302) 65
•Transistor dimensions specified as Width / Length
•Minimum size is 4l/ 2l, sometimes called 1 unit
•In f= 0.6 mm process, this is 1.2 mm wide, 0.6 mm long
VLSI Design (EC-302) 65
Stick Diagrams
VLSIdesignaimstotranslatecircuitconceptsontosilicon.
❑Stickdiagramsareameansofcapturingtopographyandlayer
informationusingsimplediagrams.
❑Stickdiagramsconveylayerinformationthroughcolorcodes(or
monochromeencoding).
❑Actsasaninterfacebetweensymboliccircuitandtheactuallayout.
VLSI Design (EC-302) 66
VLSIdesignaimstotranslatecircuitconceptsontosilicon.
❑Stickdiagramsareameansofcapturingtopographyandlayer
informationusingsimplediagrams.
❑Stickdiagramsconveylayerinformationthroughcolorcodes(or
monochromeencoding).
❑Actsasaninterfacebetweensymboliccircuitandtheactuallayout.
VLSI Design (EC-302) 66
Stick Diagram Notations
VLSI Design (EC-302) 67
VLSI Design (EC-302) 67
Stick Diagram-some rules
VLSI Design (EC-302) 68
VLSI Design (EC-302) 68
Stick Diagram-some rules
VLSI Design (EC-302) 69
VLSI Design (EC-302) 69
Stick Diagram-some rules
VLSI Design (EC-302) 70
VLSI Design (EC-302) 70
Stick Diagram-some rules
VLSI Design (EC-302) 71
VLSI Design (EC-302) 71
Examples of Stick Diagrams
VLSI Design (EC-302) 72
VLSI Design (EC-302) 72
Examples of Stick Diagrams
VLSI Design (EC-302) 73
VLSI Design (EC-302) 73
Examples of Stick Diagrams
VLSI Design (EC-302) 74
VLSI Design (EC-302) 74
Examples of Stick Diagrams
VLSI Design (EC-302) 75
VLSI Design (EC-302) 75
Examples of Stick Diagrams
VLSI Design (EC-302) 76
VLSI Design (EC-302) 76
Examples of Stick Diagrams
VLSI Design (EC-302) 77
VLSI Design (EC-302) 77
Examples of Stick Diagrams
VLSI Design (EC-302) 78
VLSI Design (EC-302) 78
IC Layout Design
VLSI Design (EC-302) 79
VLSI Design (EC-302) 79
VLSI Design (EC-302) 80
Design rules
VLSI Design (EC-302) 81
VLSI Design (EC-302) 81
Lambda based design rules
VLSI Design (EC-302) 82
VLSI Design (EC-302) 82
VLSI Design (EC-302) 83
VLSI Design (EC-302) 84
VLSI Design (EC-302) 85
VLSI Design (EC-302) 86
VLSI Design (EC-302) 87
VLSI Design (EC-302) 88
Top view
VLSI Design (EC-302) 89
VLSI Design (EC-302) 89
VLSI Design (EC-302) 90
VLSI Design (EC-302) 91
VLSI Design (EC-302) 92
VLSI Design (EC-302) 93
VLSI Design (EC-302) 94
VLSI Design (EC-302) 95
Packaging Integrated Circuit
TheICpackageplaysafundamentalroleintheoperationand
performanceofacomponent.
❑Bringingsignalandsupplywiresinandoutofthesilicondie
❑Removestheheatgenerated
❑Providesmechanicalsupport.
❑Protectsthedieagainstenvironmentalconditionssuchashumidity.
VLSI Design (EC-302) 96
TheICpackageplaysafundamentalroleintheoperationand
performanceofacomponent.
❑Bringingsignalandsupplywiresinandoutofthesilicondie
❑Removestheheatgenerated
❑Providesmechanicalsupport.
❑Protectsthedieagainstenvironmentalconditionssuchashumidity.
VLSI Design (EC-302) 96
Agoodpackagemustcomplywithalargevarietyofrequirements.
Electricalrequirements—
❑Pinsshouldexhibitlowcapacitance(bothinterwireandtothesubstrate),
resistance,andinductance.
❑Alargecharacteristicimpedanceshouldbetunedtooptimizetransmission
linebehavior.Observethatintrinsicintegrated-circuitimpedancesarehigh.
Mechanicalandthermalproperties—
❑Theheat-removalrateshouldbeashighaspossible.
❑Mechanicalreliabilityrequiresagoodmatchingbetweenthethermal
propertiesofthedieandthechipcarrier.
❑Long-termreliabilityrequiresastrongconnectionfromdietopackageas
wellasfrompackagetoboard.
❑
VLSI Design (EC-302) 97
Electricalrequirements—
❑Pinsshouldexhibitlowcapacitance(bothinterwireandtothesubstrate),
resistance,andinductance.
❑Alargecharacteristicimpedanceshouldbetunedtooptimizetransmission
linebehavior.Observethatintrinsicintegrated-circuitimpedancesarehigh.
Mechanicalandthermalproperties—
❑Theheat-removalrateshouldbeashighaspossible.
❑Mechanicalreliabilityrequiresagoodmatchingbetweenthethermal
propertiesofthedieandthechipcarrier.
❑Long-termreliabilityrequiresastrongconnectionfromdietopackageas
wellasfrompackagetoboard.
❑
VLSI Design (EC-302) 97
LowCost—Costisalwaysoneofthemoreimportantproperties.
❑Ceramicshaveasuperiorperformanceoverplasticpackages,theyarealsosubstantiallymore
expensive.Increasingtheheatremovalcapacityofapackagealsotendstoraisethepackagecost.
❑Theleastexpensiveplasticpackagingcandissipateupto1W.Somewhatmoreexpensive,butstill
cheap,plasticpackagescandissipateupto2W.Higherdissipationrequiresmoreexpensive
ceramicpackaging.
Packagescanbeclassifiedinmanydifferentways—bytheirmainmaterial,thenumberof
interconnectionlevels,andthemeansusedtoremoveheat.
1:Packagematerials
Themostcommonmaterialsusedforthepackagebodyareceramicandpolymers(plastics).The
latterhavetheadvantageofbeingsubstantiallycheaper,butsufferfrominferiorthermalproperties.
Forinstance,theceramicAl2O3(Alumina)conductsheatbetterthanSiO2andthePolyimideplastic,
byfactorsof30and100respectively.
2:InterconnectLevels
Thetraditionalpackagingapproachusesatwo-levelinterconnectionstrategy.Thedieisfirst
attachedtoanindividualchipcarrierorsubstrate.Thepackagebodycontainsaninternalcavity
wherethechipismounted.Thesecavitiesprovideampleroomformanyconnectionstothechip
leads(orpins).
VLSI Design (EC-302) 98
❑Ceramicshaveasuperiorperformanceoverplasticpackages,theyarealsosubstantiallymore
expensive.Increasingtheheatremovalcapacityofapackagealsotendstoraisethepackagecost.
❑Theleastexpensiveplasticpackagingcandissipateupto1W.Somewhatmoreexpensive,butstill
cheap,plasticpackagescandissipateupto2W.Higherdissipationrequiresmoreexpensive
ceramicpackaging.
Packagescanbeclassifiedinmanydifferentways—bytheirmainmaterial,thenumberof
interconnectionlevels,andthemeansusedtoremoveheat.
1:Packagematerials
Themostcommonmaterialsusedforthepackagebodyareceramicandpolymers(plastics).The
latterhavetheadvantageofbeingsubstantiallycheaper,butsufferfrominferiorthermalproperties.
Forinstance,theceramicAl2O3(Alumina)conductsheatbetterthanSiO2andthePolyimideplastic,
byfactorsof30and100respectively.
2:InterconnectLevels
Thetraditionalpackagingapproachusesatwo-levelinterconnectionstrategy.Thedieisfirst
attachedtoanindividualchipcarrierorsubstrate.Thepackagebodycontainsaninternalcavity
wherethechipismounted.Thesecavitiesprovideampleroomformanyconnectionstothechip
leads(orpins).
VLSI Design (EC-302) 98
VLSI Design (EC-302) 99
Interconnect hierarchy in traditional IC packaging.
Interconnect hierarchy in traditional IC packaging.
Interconnect Level 1 —Die-to-Package-Substrate
Foralongtime,wirebondingwasthetechniqueofchoicetoprovideanelectrical
connectionbetweendieandpackage.Inthisapproach,thebacksideofthedieis
attachedtothesubstrateusinggluewithagoodthermalconductance.Next,the
chippadsareindividuallyconnectedtotheleadframewithaluminumorgold
wires.Thewirebondingmachineuseforthispurposeoperatesmuchlikeasewing
machine.AnexampleofwirebondingisshowninFigure.
VLSI Design (EC-302) 100
Foralongtime,wirebondingwasthetechniqueofchoicetoprovideanelectrical
connectionbetweendieandpackage.Inthisapproach,thebacksideofthedieis
attachedtothesubstrateusinggluewithagoodthermalconductance.Next,the
chippadsareindividuallyconnectedtotheleadframewithaluminumorgold
wires.Thewirebondingmachineuseforthispurposeoperatesmuchlikeasewing
machine.AnexampleofwirebondingisshowninFigure.
VLSI Design (EC-302) 100
Although the wire-bonding process is automated to a large degree,
it has some major disadvantages.
1.Wires must be attached serially, one after the other. This leads to
longer manufacturing times with increasing pin counts.
2.Larger pin counts make it substantially more challenging to find
bonding patterns that avoid shorts between the wires.
3.The exact value of the parasitics is hard to predict because of the
manufacturing approach and irregular outlay.
VLSI Design (EC-302) 101
it has some major disadvantages.
1.Wires must be attached serially, one after the other. This leads to
longer manufacturing times with increasing pin counts.
2.Larger pin counts make it substantially more challenging to find
bonding patterns that avoid shorts between the wires.
3.The exact value of the parasitics is hard to predict because of the
manufacturing approach and irregular outlay.
VLSI Design (EC-302) 101
TapeAutomatedBonding(orTAB)
Thedieisattachedtoametalleadframethatisprintedonapolymerfilm(typically
polyimide)(Figurea).Theconnectionbetweenchippadsandpolymerfilmwiresis
madeusingsolderbumps(Figureb).Thetapecanthenbeconnectedtothe
packagebodyusinganumberoftechniques.Onepossibleapproachistouse
pressureconnectors.TheadvantageoftheTABprocessisthatitishighly
automated.
VLSI Design (EC-302) 102
Thedieisattachedtoametalleadframethatisprintedonapolymerfilm(typically
polyimide)(Figurea).Theconnectionbetweenchippadsandpolymerfilmwiresis
madeusingsolderbumps(Figureb).Thetapecanthenbeconnectedtothe
packagebodyusinganumberoftechniques.Onepossibleapproachistouse
pressureconnectors.TheadvantageoftheTABprocessisthatitishighly
automated.
VLSI Design (EC-302) 102
Flip-chipmounting
Anotherapproachistoflipthedieupside-downandattachitdirectlytothe
substrateusingsolderbumps.Thistechniquehastheadvantageofasuperior
electricalperformance(Figure2.13).InsteadofmakingalltheI/Oconnectionson
thedieboundary,padscanbeplacedatanypositiononthechip.Thiscanhelp
addressthepower-andclock-distributionproblems,sincetheinterconnect
materialsonthesubstrate(e.g.,CuorAu)aretypicallyofabetterqualitythanthe
Alonthechip.
VLSI Design (EC-302) 103
Anotherapproachistoflipthedieupside-downandattachitdirectlytothe
substrateusingsolderbumps.Thistechniquehastheadvantageofasuperior
electricalperformance(Figure2.13).InsteadofmakingalltheI/Oconnectionson
thedieboundary,padscanbeplacedatanypositiononthechip.Thiscanhelp
addressthepower-andclock-distributionproblems,sincetheinterconnect
materialsonthesubstrate(e.g.,CuorAu)aretypicallyofabetterqualitythanthe
Alonthechip.
VLSI Design (EC-302) 103
Interconnect Level 2—Package Substrate to Board
When connecting the package to the PC board, through-hole mounting has been the packaging style
of choice. A PC board is manufactured by stacking layers of copper and insulating epoxy glass. In the
through-hole mounting approach, holes are drilled through the board and plated with copper. The
package pins are inserted and electrical connection is made with solder (Figure 2.14a). The favored
package in this class was the dual-in-line package or DIP (Figure 2.15a). The packaging density of the
DIP degrades rapidly when the number of pins exceeds 64. This problem can be alleviated by using
the pin-grid-array (PGA) package that has leads on the entire bottom surface instead of only on the
periphery (Figure 2.15b). PGAs can extend to large pin counts (over 400 pins are possible)
VLSI Design (EC-302) 104
When connecting the package to the PC board, through-hole mounting has been the packaging style
of choice. A PC board is manufactured by stacking layers of copper and insulating epoxy glass. In the
through-hole mounting approach, holes are drilled through the board and plated with copper. The
package pins are inserted and electrical connection is made with solder (Figure 2.14a). The favored
package in this class was the dual-in-line package or DIP (Figure 2.15a). The packaging density of the
DIP degrades rapidly when the number of pins exceeds 64. This problem can be alleviated by using
the pin-grid-array (PGA) package that has leads on the entire bottom surface instead of only on the
periphery (Figure 2.15b). PGAs can extend to large pin counts (over 400 pins are possible)
VLSI Design (EC-302) 104
VLSI Design (EC-302) 105
Thermal Considerations in Packaging
Asthepowerconsumptionofintegratedcircuitsrises,itbecomesincreasingly
importanttoefficientlyremovetheheatgeneratedbythechips.Alargenumberof
failuremechanismsinICsareaccentuatedbyincreasedtemperatures.Examples
areleakageinreversebiaseddiodes,electromigration,andhot-electrontrapping.
Topreventfailure,thetemperatureofthediemustbekeptwithincertainranges.
Thesupportedtemperaturerangeforcommercialdevicesduringoperationequals
0°to70°C.Militarypartsaremoredemandingandrequireatemperaturerange
varyingfrom–55°to125°C.
VLSI Design (EC-302) 106
Asthepowerconsumptionofintegratedcircuitsrises,itbecomesincreasingly
importanttoefficientlyremovetheheatgeneratedbythechips.Alargenumberof
failuremechanismsinICsareaccentuatedbyincreasedtemperatures.Examples
areleakageinreversebiaseddiodes,electromigration,andhot-electrontrapping.
Topreventfailure,thetemperatureofthediemustbekeptwithincertainranges.
Thesupportedtemperaturerangeforcommercialdevicesduringoperationequals
0°to70°C.Militarypartsaremoredemandingandrequireatemperaturerange
varyingfrom–55°to125°C.
VLSI Design (EC-302) 106
Trends in Process Technology
ModernCMOSprocessesprettymuchtracktheflowdescribedintheprevious
sectionsalthoughanumberofthestepsmightbereversed,asinglewellapproach
mightbefollowed,agrownfieldoxideinsteadofthetrenchapproachmightbe
used,orextrastepssuchasLDD(LightlyDopedDrain)mightbeintroduced.Also,it
isquitecommontocoverthepolysiliconinterconnectionsaswellasthedrainand
sourceregionswithasilicidesuchasTiSi
2toimprovetheconductivity.
Short-TermDevelopments
CopperandLow-kDielectrics
Processengineersarecontinuouslyevaluatingalternativeoptionsforthe
traditional‘Aluminumconductor—SiO2insulator’combinationthathasbeenthe
normforthelastdecades.In1998,engineersatIBMintroducedanapproachthat
finallymadetheuseofCopperasaninterconnectmaterialinaCMOSprocess
viableandeconomical.
VLSI Design (EC-302) 107
ModernCMOSprocessesprettymuchtracktheflowdescribedintheprevious
sectionsalthoughanumberofthestepsmightbereversed,asinglewellapproach
mightbefollowed,agrownfieldoxideinsteadofthetrenchapproachmightbe
used,orextrastepssuchasLDD(LightlyDopedDrain)mightbeintroduced.Also,it
isquitecommontocoverthepolysiliconinterconnectionsaswellasthedrainand
sourceregionswithasilicidesuchasTiSi
2toimprovetheconductivity.
Short-TermDevelopments
CopperandLow-kDielectrics
Processengineersarecontinuouslyevaluatingalternativeoptionsforthe
traditional‘Aluminumconductor—SiO2insulator’combinationthathasbeenthe
normforthelastdecades.In1998,engineersatIBMintroducedanapproachthat
finallymadetheuseofCopperasaninterconnectmaterialinaCMOSprocess
viableandeconomical.
VLSI Design (EC-302) 107
Silicon-on-Insulator
Themaindifferenceliesinthestartmaterial:thetransistorsare
constructedinaverythinlayerofsilicon,depositedontopofathick
layerofinsulatingSiO2(Figure).TheprimaryadvantagesoftheSOI
processarereducedparasiticsandbettertransistoron-off
characteristics.
VLSI Design (EC-302) 108
Silicon-on-insulator process— schematic diagram (a) and SEM cross-section (b).
Themaindifferenceliesinthestartmaterial:thetransistorsare
constructedinaverythinlayerofsilicon,depositedontopofathick
layerofinsulatingSiO2(Figure).TheprimaryadvantagesoftheSOI
processarereducedparasiticsandbettertransistoron-off
characteristics.
VLSI Design (EC-302) 108
Silicon-on-insulator process— schematic diagram (a) and SEM cross-section (b).
In longer term
ExtendingthelifeofCMOStechnologybeyondthenextdecade,anddeeplybelow
the100nmchannellengthregionhoweverwillrequirere-engineeringofboththe
processtechnologyandthedevicestructure.Wealreadyarewitnessingthe
emergenceofawiderangeofnewdevices(suchasorganictransistors,molecular
switches,andquantumdevices).
Three-DimensionalIntegratedCircuits
VLSI Design (EC-302) 109
ExtendingthelifeofCMOStechnologybeyondthenextdecade,anddeeplybelow
the100nmchannellengthregionhoweverwillrequirere-engineeringofboththe
processtechnologyandthedevicestructure.Wealreadyarewitnessingthe
emergenceofawiderangeofnewdevices(suchasorganictransistors,molecular
switches,andquantumdevices).
Three-DimensionalIntegratedCircuits
VLSI Design (EC-302) 109
The Metal Oxide Semiconductor (MOS) Structure
VLSI Design (EC-302) 110
Two-terminal MOS structure Energy band diagram of a p-type silicon substrate
VLSI Design (EC-302) 110
Two-terminal MOS structure Energy band diagram of a p-type silicon substrate
TheFermipotentialwhichisafunctionoftemperatureanddoping,denotesthe
differencebetweentheintrinsicFermilevelE
j,andtheFermilevelE
F.
VLSI Design (EC-302) 111
For a p-type semiconductor, the Fermi potential can be approximated by
whereas for an n-type semiconductor (doped with a donor concentration N
D), the
Fermi potential is given by
The energy required for an electron to move from the Fermi level into free space
is called the work function and is given by
differencebetweentheintrinsicFermilevelE
j,andtheFermilevelE
F.
VLSI Design (EC-302) 111
For a p-type semiconductor, the Fermi potential can be approximated by
whereas for an n-type semiconductor (doped with a donor concentration N
D), the
Fermi potential is given by
The energy required for an electron to move from the Fermi level into free space
is called the work function and is given by
VLSI Design (EC-302) 112
Energy band diagrams of the components that make up the MOS system.
Energy band diagram of the combined MOS system.
Energy band diagrams of the components that make up the MOS system.
Energy band diagram of the combined MOS system.
The MOS System under External Bias
VLSI Design (EC-302) 113
The cross-sectional view and the energy band diagram of the
MOS structure operating in accumulation region.
The cross-sectional view and the energy band diagram of the
MOS structure operating in depletion mode, under small gate
bias.
VLSI Design (EC-302) 113
The cross-sectional view and the energy band diagram of the
MOS structure operating in accumulation region.
The cross-sectional view and the energy band diagram of the
MOS structure operating in depletion mode, under small gate
bias.
VLSI Design (EC-302) 114
The cross-sectional view and the energy band diagram of the MOS structure in
surface inversion, under larger gate bias voltage.
The cross-sectional view and the energy band diagram of the MOS structure in
surface inversion, under larger gate bias voltage.
MOS Transistor
VLSI Design (EC-302) 115
The physical structure of an n-channel enhancement-type MOSFET
Circuit symbols for n-channel and p-channel
enhancement-type MOSFETs
VLSI Design (EC-302) 115
The physical structure of an n-channel enhancement-type MOSFET
Circuit symbols for n-channel and p-channel
enhancement-type MOSFETs
VLSI Design (EC-302) 116
Formation of a depletion region in an n-channel enhancement-
type MOSFET.
Formation of a depletion region in an n-channel enhancement-
type MOSFET.
VLSI Design (EC-302) 117
Formation of an inversion layer (channel) in an n-channel
enhancement-type MOSFET.
Band diagram of the MOS structure
underneath the gate, at surface inversion.
Notice the band bending by at the surface.
The value of the gate-to-source voltage V
GS needed to cause surface inversion (to create the conducting channel) is
called the threshold voltage V
T0.
Formation of an inversion layer (channel) in an n-channel
enhancement-type MOSFET.
Band diagram of the MOS structure
underneath the gate, at surface inversion.
Notice the band bending by at the surface.
The value of the gate-to-source voltage V
GS needed to cause surface inversion (to create the conducting channel) is
called the threshold voltage V
T0.
The Threshold Voltage
Fourphysicalcomponentsofthethresholdvoltage:
(i)theworkfunctiondifferencebetweenthegateandthechannel
(ii)thegatevoltagecomponenttochangethesurfacepotential
(iii)thegatevoltagecomponenttooffsetthedepletionregioncharge
(iv)thevoltagecomponenttooffsetthefixedchargesinthegateoxide
andinthesilicon-oxideinterface.
VLSI Design (EC-302) 118
Fourphysicalcomponentsofthethresholdvoltage:
(i)theworkfunctiondifferencebetweenthegateandthechannel
(ii)thegatevoltagecomponenttochangethesurfacepotential
(iii)thegatevoltagecomponenttooffsetthedepletionregioncharge
(iv)thevoltagecomponenttooffsetthefixedchargesinthegateoxide
andinthesilicon-oxideinterface.
VLSI Design (EC-302) 118
Theworkfunctiondifferencebetweenthegateandthechannelreflectsthe
built-inpotentialoftheMOSsystem,whichconsistsofthep-typesubstrate,the
thinsilicondioxidelayer,andthegateelectrode.Dependingonthegatematerial,
theworkfunctiondifferenceis
Thisfirstcomponentofthethresholdvoltageaccountsforpartofthevoltagedrop
acrosstheMOSsystemthatisbuilt-in.Now,theexternallyappliedgatevoltage
mustbechangedtoachievesurfaceinversion,i.e.,tochangethesurfacepotential
by..Thiswillbethesecondcomponentofthethresholdvoltage.
VLSI Design (EC-302) 119
built-inpotentialoftheMOSsystem,whichconsistsofthep-typesubstrate,the
thinsilicondioxidelayer,andthegateelectrode.Dependingonthegatematerial,
theworkfunctiondifferenceis
Thisfirstcomponentofthethresholdvoltageaccountsforpartofthevoltagedrop
acrosstheMOSsystemthatisbuilt-in.Now,theexternallyappliedgatevoltage
mustbechangedtoachievesurfaceinversion,i.e.,tochangethesurfacepotential
by..Thiswillbethesecondcomponentofthethresholdvoltage.
VLSI Design (EC-302) 119
Anothercomponentoftheappliedgatevoltageisnecessarytooffsetthedepletion
regioncharge,whichisduetothefixedacceptorionslocatedinthedepletion
regionnearthesurface.Wecancalculatethedepletionregionchargedensityat
surfaceinversion
VLSI Design (EC-302) 120
if the substrate (body) is biased at a different voltage level than the source, which is at
ground potential (reference)
The component that offsets the depletion region charge is then equal to - Q
B/C
OX,
where C
OX is the gate oxide capacitance per unit area.
regioncharge,whichisduetothefixedacceptorionslocatedinthedepletion
regionnearthesurface.Wecancalculatethedepletionregionchargedensityat
surfaceinversion
VLSI Design (EC-302) 120
if the substrate (body) is biased at a different voltage level than the source, which is at
ground potential (reference)
The component that offsets the depletion region charge is then equal to - Q
B/C
OX,
where C
OX is the gate oxide capacitance per unit area.
VLSI Design (EC-302) 121
There always exists a fixed positive charge density Q
OX at the interface between the gate oxide and the
silicon substrate, due to impurities and/or lattice imperfections at the interface. The gate voltage
component that is necessary to offset this positive charge at the interface is - Q
OX/C
OX. For zero substrate
bias threshold voltage V
T0 expressed as
For nonzero substrate bias
There always exists a fixed positive charge density Q
OX at the interface between the gate oxide and the
silicon substrate, due to impurities and/or lattice imperfections at the interface. The gate voltage
component that is necessary to offset this positive charge at the interface is - Q
OX/C
OX. For zero substrate
bias threshold voltage V
T0 expressed as
For nonzero substrate bias
VLSI Design (EC-302) 122
In this case, the threshold voltage differs from V
T0 only by an additive term. This substrate-bias term is
a simple function of the material constants and of the source-to-substrate voltage V
SB.
The general expression of the threshold voltage V
T
In generalized form threshold Voltage can be written as
In this case, the threshold voltage differs from V
T0 only by an additive term. This substrate-bias term is
a simple function of the material constants and of the source-to-substrate voltage V
SB.
The general expression of the threshold voltage V
T
In generalized form threshold Voltage can be written as
VLSI Design (EC-302) 123
•The substrate Fermi potential ϕ
F is negative in nMOS, positive in pMOS.
•The depletion region charge densities Q
B0 and Q
B are negative in nMOS,
positive in pMOS.
•The substrate bias coefficient γ is positive in nMOS, negative in pMOS.
•The substrate bias voltage V
SB is positive in nMOS, negative in pMOS.
and
•The substrate Fermi potential ϕ
F is negative in nMOS, positive in pMOS.
•The depletion region charge densities Q
B0 and Q
B are negative in nMOS,
positive in pMOS.
•The substrate bias coefficient γ is positive in nMOS, negative in pMOS.
•The substrate bias voltage V
SB is positive in nMOS, negative in pMOS.
and
VLSI Design (EC-302) 124
Example
Fermi potentials for the p-type substrate and for the n-type polysilicon gate:
Example
Fermi potentials for the p-type substrate and for the n-type polysilicon gate:
VLSI Design (EC-302) 125
VLSI Design (EC-302) 126
Gradual Channel Approximation
VLSI Design (EC-302) 127
N-channel MOSFET operating in linear region
The boundary conditions for the channel voltage V
C are:
Eq. 1
Also, it is assumed that the entire channel region between the source and
the drain is inverted, i.e.,
Eq. 2
The channel current (drain current) I
D is due to the electrons in the
channel region traveling from the source to the drain under the influence
of the lateral electric field component E
y.
VLSI Design (EC-302) 127
N-channel MOSFET operating in linear region
The boundary conditions for the channel voltage V
C are:
Eq. 1
Also, it is assumed that the entire channel region between the source and
the drain is inverted, i.e.,
Eq. 2
The channel current (drain current) I
D is due to the electrons in the
channel region traveling from the source to the drain under the influence
of the lateral electric field component E
y.
VLSI Design (EC-302) 128
Simplified geometry of the surface inversion layer (channel region).
Q
I(y) is the total mobile electron charge in the surface inversion
layer. This charge can be expressed as
Eq. 3
Now consider the incremental resistance dR of the differential
channel segment. Assuming that all mobile electrons in the inversion
layer have a constant surface mobility µ
n, the incremental resistance
can be expressed as follows.
Eq. 4
Applying Ohm’s law for this segment yields the voltage drop
along the incremental segment dy, in the y direction.
Eq. 5
This equation can now be integrated along the channel, i.e., from y = 0 to y = L, using the
boundary conditions are given in Eq. 1.
Eq. 6
Simplified geometry of the surface inversion layer (channel region).
Q
I(y) is the total mobile electron charge in the surface inversion
layer. This charge can be expressed as
Eq. 3
Now consider the incremental resistance dR of the differential
channel segment. Assuming that all mobile electrons in the inversion
layer have a constant surface mobility µ
n, the incremental resistance
can be expressed as follows.
Eq. 4
Applying Ohm’s law for this segment yields the voltage drop
along the incremental segment dy, in the y direction.
Eq. 5
This equation can now be integrated along the channel, i.e., from y = 0 to y = L, using the
boundary conditions are given in Eq. 1.
Eq. 6
VLSI Design (EC-302) 129
Replacing Q
i(y) with Eq. 3.
Eq. 7
Assuming that the channel voltage V
C, is the only variable in (Eq. 7) that depends on the position y, the
drain current is found as follows.
Eq. 9
Equation 8 represents the drain current I
D as a simple second-order function of the two external voltages,
V
GS
and V
DS
This current equation can also be rewritten as
Eq. 8
or
Eq. 10
Replacing Q
i(y) with Eq. 3.
Eq. 7
Assuming that the channel voltage V
C, is the only variable in (Eq. 7) that depends on the position y, the
drain current is found as follows.
Eq. 9
Equation 8 represents the drain current I
D as a simple second-order function of the two external voltages,
V
GS
and V
DS
This current equation can also be rewritten as
Eq. 8
or
Eq. 10
VLSI Design (EC-302) 130
Where the parameter k and k’ are defined as
and
Now that the drain current equation (8) has been derived under the following voltage assumptions,
the current equation (8) is not valid beyond the linear region/ saturation region boundary, i.e., for
Eq. 14
Eq. 12
Eq. 13
Eq. 11
This saturation drain current level can be found simply by substituting Eq. 14 for V
DS in Eq. 8.
Eq. 15
Where the parameter k and k’ are defined as
and
Now that the drain current equation (8) has been derived under the following voltage assumptions,
the current equation (8) is not valid beyond the linear region/ saturation region boundary, i.e., for
Eq. 14
Eq. 12
Eq. 13
Eq. 11
This saturation drain current level can be found simply by substituting Eq. 14 for V
DS in Eq. 8.
Eq. 15
MOSFET I-V Characteristics
VLSI Design (EC-302) 131
Basic I-V Characteristics of n-channel MOSFET
VLSI Design (EC-302) 131
Basic I-V Characteristics of n-channel MOSFET
I
DVs V
DSRelationship
VLSI Design (EC-302) 132
DVs V
DSRelationship
VLSI Design (EC-302) 132
VLSI Design (EC-302) 133
VLSI Design (EC-302) 134
MOSFET Operation: A Qualitative View
VLSI Design (EC-302) 135
Cross-sectional view of an n-channel (nMOS) transistor, (a) operating in the linear region, (b) operating at the edge of
saturation, and (c) operating beyond saturation.
VLSI Design (EC-302) 135
Cross-sectional view of an n-channel (nMOS) transistor, (a) operating in the linear region, (b) operating at the edge of
saturation, and (c) operating beyond saturation.
Secondary Effects
Threshold Variations
VLSI Design (EC-302) 136
Eq. states that the threshold voltage is only a function of the
manufacturing technology and the applied body bias V
SB. As the
device dimensions are reduced, this model becomes
inaccurate, and the threshold potential becomes a function of
L, W, and V
DS.
A similar effect can be obtained by raising the
drain-source (bulk) voltage, as this increases the
width of the drain-junction depletion region.
Consequently, the threshold decreases with
increasing V
DS
. This effect, called the drain-induced
barrier lowering, or DIBL, causes the threshold
potential to be a function of the operating voltages.
DIBL
Threshold Variations
VLSI Design (EC-302) 136
Eq. states that the threshold voltage is only a function of the
manufacturing technology and the applied body bias V
SB. As the
device dimensions are reduced, this model becomes
inaccurate, and the threshold potential becomes a function of
L, W, and V
DS.
A similar effect can be obtained by raising the
drain-source (bulk) voltage, as this increases the
width of the drain-junction depletion region.
Consequently, the threshold decreases with
increasing V
DS
. This effect, called the drain-induced
barrier lowering, or DIBL, causes the threshold
potential to be a function of the operating voltages.
DIBL
Punch through
Forhighenoughvaluesofthedrainvoltage,thesourceanddrainregionscan
evenbeshortedtogether,andnormaltransistoroperationceasestoexist.The
sharpincreaseincurrentthatresultsfromthiseffect,whichiscalledpunch-
through,maycausepermanentdamagetothedeviceandshouldbeavoided.
VLSI Design (EC-302) 137
Forhighenoughvaluesofthedrainvoltage,thesourceanddrainregionscan
evenbeshortedtogether,andnormaltransistoroperationceasestoexist.The
sharpincreaseincurrentthatresultsfromthiseffect,whichiscalledpunch-
through,maycausepermanentdamagetothedeviceandshouldbeavoided.
VLSI Design (EC-302) 137
Narrow-channeleffects
Thedepletionregionofthechanneldoesnotstopabruptlyattheedgesofthetransistor,but
extendssomewhatundertheisolatingfield-oxide.Thegatevoltagemustsupportthisextra
depletionchargetoestablishaconductingchannel.Thiseffectisignorableforwidetransistors,but
becomessignificantforsmallvaluesofW,whereitresultsinanincreaseofthethresholdvoltage.
Forsmallgeometrytransistors,withsmallvaluesofLandW,theeffectsofshort-andnarrow
channelsmaytendtocanceleachotherout.
VLSI Design (EC-302) 138
Thedepletionregionofthechanneldoesnotstopabruptlyattheedgesofthetransistor,but
extendssomewhatundertheisolatingfield-oxide.Thegatevoltagemustsupportthisextra
depletionchargetoestablishaconductingchannel.Thiseffectisignorableforwidetransistors,but
becomessignificantforsmallvaluesofW,whereitresultsinanincreaseofthethresholdvoltage.
Forsmallgeometrytransistors,withsmallvaluesofLandW,theeffectsofshort-andnarrow
channelsmaytendtocanceleachotherout.
VLSI Design (EC-302) 138
Hot-Carrier Effects
Devicedimensionshavebeenscaleddowncontinuously,whilethe
powersupplyandtheoperatingvoltageswerekeptconstant.The
resultingincreaseintheelectricalfieldstrengthcausesan
increasingvelocityoftheelectrons,whichcanleavethesiliconand
tunnelintothegateoxideuponreachingahigh-enoughenergy
level.Electronstrappedintheoxidechangethethresholdvoltage,
typicallyincreasingthethresholdsofNMOSdevices,while
decreasingtheV
TofPMOStransistors.
•Foranelectrontobecomehot,anelectricalfieldofatleast10
4
V/cmisnecessary.
•Thehot-electronphenomenoncanleadtoalong-termreliability
problem,whereacircuitmightdegradeorfailafterbeinginuse
forawhile.
VLSI Design (EC-302) 139
Hot-carrier effects cause the I-V characteristics of an NMOS
transistor to degrade from extensive usage
Devicedimensionshavebeenscaleddowncontinuously,whilethe
powersupplyandtheoperatingvoltageswerekeptconstant.The
resultingincreaseintheelectricalfieldstrengthcausesan
increasingvelocityoftheelectrons,whichcanleavethesiliconand
tunnelintothegateoxideuponreachingahigh-enoughenergy
level.Electronstrappedintheoxidechangethethresholdvoltage,
typicallyincreasingthethresholdsofNMOSdevices,while
decreasingtheV
TofPMOStransistors.
•Foranelectrontobecomehot,anelectricalfieldofatleast10
4
V/cmisnecessary.
•Thehot-electronphenomenoncanleadtoalong-termreliability
problem,whereacircuitmightdegradeorfailafterbeinginuse
forawhile.
VLSI Design (EC-302) 139
Hot-carrier effects cause the I-V characteristics of an NMOS
transistor to degrade from extensive usage
CMOS Latchup
TheMOStechnologycontainsanumberofintrinsicbipolartransistors.Theseareespecially
troublesomeinCMOSprocesses,wherethecombinationofwellsandsubstratesresultsinthe
formationofparasiticn-p-n-pstructures.Triggeringthesethyristor-likedevicesleadstoashorting
oftheV
DDandV
SSlines,usuallyresultinginadestructionofthechip,oratbestasystemfailurethat
canonlyberesolvedbypower-down.
VLSI Design (EC-302) 140
TheMOStechnologycontainsanumberofintrinsicbipolartransistors.Theseareespecially
troublesomeinCMOSprocesses,wherethecombinationofwellsandsubstratesresultsinthe
formationofparasiticn-p-n-pstructures.Triggeringthesethyristor-likedevicesleadstoashorting
oftheV
DDandV
SSlines,usuallyresultinginadestructionofthechip,oratbestasystemfailurethat
canonlyberesolvedbypower-down.
VLSI Design (EC-302) 140
Latchup prevention
Fromtheaboveanalysisthemessagetothedesignerisclear—toavoidlatchup,theresistances
R
nwellandR
psubsshouldbeminimized.Thiscanbeachievedbyprovidingnumerouswelland
substratecontacts,placedclosetothesourceconnectionsoftheNMOS/PMOSdevices.Devices
carryingalotofcurrent(suchastransistorsintheI/Odrivers)shouldbesurroundedbyguardrings.
Thesecircularwell/substratecontacts,positionedaroundthetransistor,reducetheresistanceeven
furtherandreducethegainoftheparasiticbipolars.
VLSI Design (EC-302) 141
Fromtheaboveanalysisthemessagetothedesignerisclear—toavoidlatchup,theresistances
R
nwellandR
psubsshouldbeminimized.Thiscanbeachievedbyprovidingnumerouswelland
substratecontacts,placedclosetothesourceconnectionsoftheNMOS/PMOSdevices.Devices
carryingalotofcurrent(suchastransistorsintheI/Odrivers)shouldbesurroundedbyguardrings.
Thesecircularwell/substratecontacts,positionedaroundthetransistor,reducetheresistanceeven
furtherandreducethegainoftheparasiticbipolars.
VLSI Design (EC-302) 141
Channel Length modulation
VLSI Design (EC-302) 142
The saturation-region relationship between gate-to-source
voltage (V
GS) and drain current (I
D) is expressed as follows:
This brings us to our channel-length-modulation-compliant
expression for saturation-region drain current:
VLSI Design (EC-302) 142
The saturation-region relationship between gate-to-source
voltage (V
GS) and drain current (I
D) is expressed as follows:
This brings us to our channel-length-modulation-compliant
expression for saturation-region drain current:
Velocity Saturation
Velocitysaturationeffect.statesthatthevelocityofthecarriersisproportionaltotheelectrical
field,independentofthevalueofthatfield.Inotherwords,thecarriermobilityisaconstant.
However,athighfieldstrengths,thecarriersfailtofollowthislinearmodel.Infact,whenthe
electricalfieldalongthechannelreachesacriticalvaluexc,thevelocityofthecarrierstendsto
saturateduetoscatteringeffects(collisionssufferedbythecarriers).
VLSI Design (EC-302) 143
Velocitysaturationeffect.statesthatthevelocityofthecarriersisproportionaltotheelectrical
field,independentofthevalueofthatfield.Inotherwords,thecarriermobilityisaconstant.
However,athighfieldstrengths,thecarriersfailtofollowthislinearmodel.Infact,whenthe
electricalfieldalongthechannelreachesacriticalvaluexc,thevelocityofthecarrierstendsto
saturateduetoscatteringeffects(collisionssufferedbythecarriers).
VLSI Design (EC-302) 143
SubthresholdConduction
AcloserinspectionoftheI
D-V
GScurvesofFigurerevealsthatthecurrentdoesnotdropabruptlyto0
atV
GS=V
T.ItbecomesapparentthattheMOStransistorisalreadypartiallyconductingforvoltages
belowthethresholdvoltage.Thiseffectiscalledsubthresholdorweak-inversionconduction.
VLSI Design (EC-302) 144
ID current versus VGS (on logarithmic scale), showing the
exponential characteristic of the subthreshold region.
The (inverse) rate of decline of the current with respect to VGS
below VT hence is a quality measure of a device. It is often
quantified by the slope factor S, which measures by how much
VGS has to be reduced for the drain current to drop by a factor of
10.
with S is expressed in mV/decade. For an ideal transistor with
the sharpest possible roll-off, n = 1 and (kT/q)ln(10) evaluates to
60 mV/decade at room temperature, which means that the
subthreshold current drops by a factor of 10 for a reduction in
VGS of 60 mV.
AcloserinspectionoftheI
D-V
GScurvesofFigurerevealsthatthecurrentdoesnotdropabruptlyto0
atV
GS=V
T.ItbecomesapparentthattheMOStransistorisalreadypartiallyconductingforvoltages
belowthethresholdvoltage.Thiseffectiscalledsubthresholdorweak-inversionconduction.
VLSI Design (EC-302) 144
ID current versus VGS (on logarithmic scale), showing the
exponential characteristic of the subthreshold region.
The (inverse) rate of decline of the current with respect to VGS
below VT hence is a quality measure of a device. It is often
quantified by the slope factor S, which measures by how much
VGS has to be reduced for the drain current to drop by a factor of
10.
with S is expressed in mV/decade. For an ideal transistor with
the sharpest possible roll-off, n = 1 and (kT/q)ln(10) evaluates to
60 mV/decade at room temperature, which means that the
subthreshold current drops by a factor of 10 for a reduction in
VGS of 60 mV.
MOSFET Scaling and Small-Geometry Effects
Thereductionofthesize,i.e.,thedimensionsofMOSFETs,iscommonly
referredtoasscaling.
Twobasictypesofsize-reductionstrategies:
1.Fullscaling(alsocalledconstant-fieldscaling)
2.Constantvoltagescaling.
Todescribedevicescaling,introduceaconstantscalingfactorS>1.All
horizontalandverticaldimensionsofthelarge-sizetransistorarethen
dividedbythisscalingfactortoobtainthescaleddevice.
VLSI Design (EC-302) 145
Thereductionofthesize,i.e.,thedimensionsofMOSFETs,iscommonly
referredtoasscaling.
Twobasictypesofsize-reductionstrategies:
1.Fullscaling(alsocalledconstant-fieldscaling)
2.Constantvoltagescaling.
Todescribedevicescaling,introduceaconstantscalingfactorS>1.All
horizontalandverticaldimensionsofthelarge-sizetransistorarethen
dividedbythisscalingfactortoobtainthescaleddevice.
VLSI Design (EC-302) 145
Table1Itisseenthatanewgenerationofmanufacturingtechnologyreplacesthe
previousoneabouteverytwoorthreeyears,andthedown-scalingfactorSofthe
minimumfeaturesizefromonegenerationtothenextisabout1.2to1.5.
Table 1: Reduction of the minimum feature size (minimum dimensions that can be defined and
manufactured on chip) over the years, for a typical CMOS gate-array process.
VLSI Design (EC-302) 146
previousoneabouteverytwoorthreeyears,andthedown-scalingfactorSofthe
minimumfeaturesizefromonegenerationtothenextisabout1.2to1.5.
Table 1: Reduction of the minimum feature size (minimum dimensions that can be defined and
manufactured on chip) over the years, for a typical CMOS gate-array process.
VLSI Design (EC-302) 146
Weconsidertheproportionalscalingofallthreedimensionsbythesamescaling
factorS.FigureshowsthereductionofkeydimensionsonatypicalMOSFET,
togetherwiththecorrespondingincreaseofthedopingdensities.
VLSI Design (EC-302) 147
Scaling of a typical MOSFET by a scaling factor of S.
factorS.FigureshowsthereductionofkeydimensionsonatypicalMOSFET,
togetherwiththecorrespondingincreaseofthedopingdensities.
VLSI Design (EC-302) 147
Scaling of a typical MOSFET by a scaling factor of S.
Full Scaling (Constant-Field Scaling)
This scaling option attempts to preserve the magnitude of internal electric fields in
the MOSFET, while the dimensions are scaled down by a factor of S.
Table 2 lists the scaling factors for all significant dimensions, potentials, and doping
densities of the MOS transistor.
VLSI Design (EC-302) 148
Full scaling of MOSFET dimensions, potentials, and doping densities.
This scaling option attempts to preserve the magnitude of internal electric fields in
the MOSFET, while the dimensions are scaled down by a factor of S.
Table 2 lists the scaling factors for all significant dimensions, potentials, and doping
densities of the MOS transistor.
VLSI Design (EC-302) 148
Full scaling of MOSFET dimensions, potentials, and doping densities.
It will be assumed that the surface mobility µ
nis not significantly affected by the
scaled doping density. The gate oxide capacitance per unit area, on the other hand,
is changed as follows.
Thetransconductanceparameterk
nwillalsobescaledbyafactorofS.Thelinear-
modedraincurrentofthescaledMOSFETcannowbefoundas:
VLSI Design (EC-302) 149
nis not significantly affected by the
scaled doping density. The gate oxide capacitance per unit area, on the other hand,
is changed as follows.
Thetransconductanceparameterk
nwillalsobescaledbyafactorofS.Thelinear-
modedraincurrentofthescaledMOSFETcannowbefoundas:
VLSI Design (EC-302) 149
Similarly,thesaturation-modedraincurrentisalsoreducedbythesamescaling
factor.
NowconsiderthepowerdissipationoftheMOSFET.Theinstantaneouspower
dissipatedbythedevice(beforescaling)canbefoundas:
VLSI Design (EC-302) 150
The power dissipation of the transistor will be reduced by the factor S
2
.
factor.
NowconsiderthepowerdissipationoftheMOSFET.Theinstantaneouspower
dissipatedbythedevice(beforescaling)canbefoundas:
VLSI Design (EC-302) 150
The power dissipation of the transistor will be reduced by the factor S
2
.
SincethegateoxidecapacitanceCisscaleddownbyafactorofS,wecanpredict
thatthetransientcharacteristics,i.e.,thecharge-upandcharge-downtimes,ofthe
scaleddevicewillimproveaccordingly.
Table3summarizesthechangesinkeydevicecharacteristicsasaresultoffull
(constant-field)scaling.
VLSI Design (EC-302) 151
Effects of full scaling upon key device characteristics.
thatthetransientcharacteristics,i.e.,thecharge-upandcharge-downtimes,ofthe
scaleddevicewillimproveaccordingly.
Table3summarizesthechangesinkeydevicecharacteristicsasaresultoffull
(constant-field)scaling.
VLSI Design (EC-302) 151
Effects of full scaling upon key device characteristics.
Constant-Voltage Scaling
Inparticular,theperipheralandinterfacecircuitrymayrequirecertainvoltagelevelsforall
inputandoutputvoltages,whichinturnwouldnecessitatemultiplepowersupplyvoltages
andcomplicatedlevelshifterarrangements.Forthesereasons,constant-voltagescalingis
usuallypreferredoverfullscaling.
Inconstant-voltagescaling,thepowersupplyvoltageandtheterminalvoltages,onthe
otherhand,remainunchanged.ThedopingdensitiesmustbeincreasedbyafactorofS
2
in
ordertopreservethecharge-fieldrelations.
VLSI Design (EC-302) 152
Constant-voltage scaling of MOSFET dimensions, potentials, and doping densities.
Inparticular,theperipheralandinterfacecircuitrymayrequirecertainvoltagelevelsforall
inputandoutputvoltages,whichinturnwouldnecessitatemultiplepowersupplyvoltages
andcomplicatedlevelshifterarrangements.Forthesereasons,constant-voltagescalingis
usuallypreferredoverfullscaling.
Inconstant-voltagescaling,thepowersupplyvoltageandtheterminalvoltages,onthe
otherhand,remainunchanged.ThedopingdensitiesmustbeincreasedbyafactorofS
2
in
ordertopreservethecharge-fieldrelations.
VLSI Design (EC-302) 152
Constant-voltage scaling of MOSFET dimensions, potentials, and doping densities.
Sincetheterminalvoltagesremainunchanged,thelinearmodedraincurrent
ofthescaledMOSFETcanbewrittenas:
Also,thesaturation-modedraincurrentwillbeincreasedbyafactorofS
afterconstantvoltagescaling.
VLSI Design (EC-302) 153
ofthescaledMOSFETcanbewrittenas:
Also,thesaturation-modedraincurrentwillbeincreasedbyafactorofS
afterconstantvoltagescaling.
VLSI Design (EC-302) 153
VLSI Design (EC-302) 154
MOSFET Capacitances
Inordertoexaminethetransient(AC)responseofMOSFETsanddigital
circuitsconsistingofMOSFETs,wehavetodeterminethenatureandtheamountof
parasiticcapacitancesassociatedwiththeMOStransistor.
VLSI Design (EC-302) 155
Cross-sectional view and top view (mask view) of a typical n-channel MOSFET.
Inordertoexaminethetransient(AC)responseofMOSFETsanddigital
circuitsconsistingofMOSFETs,wehavetodeterminethenatureandtheamountof
parasiticcapacitancesassociatedwiththeMOStransistor.
VLSI Design (EC-302) 155
Cross-sectional view and top view (mask view) of a typical n-channel MOSFET.
Inthisfigure,themasklength(drawnlength)ofthegateisindicatedbyL
M,andthe
actualchannellengthisindicatedbyL.Theextentofboththegate-sourceandthe
gate-drainoverlapareL
D;thus,thechannellengthisgivenby
Basedontheirphysicalorigins,theparasiticdevicecapacitancescanbeclassified
intotwomajorgroups:oxide-relatedcapacitancesandjunctioncapacitances.
VLSI Design (EC-302) 156
Lumped representation of the parasitic MOSFET capacitances.
M,andthe
actualchannellengthisindicatedbyL.Theextentofboththegate-sourceandthe
gate-drainoverlapareL
D;thus,thechannellengthisgivenby
Basedontheirphysicalorigins,theparasiticdevicecapacitancescanbeclassified
intotwomajorgroups:oxide-relatedcapacitancesandjunctioncapacitances.
VLSI Design (EC-302) 156
Lumped representation of the parasitic MOSFET capacitances.
Thetwooverlapcapacitancesthatariseasaresultofthisstructural
arrangementarecalledC
GD(overlap)andC
GS(overlap),respectively.
Assumingthatboththesourceandthedraindiffusionregionshavethesame
widthW,theoverlapcapacitancescanbefoundas
with
bothoftheseoverlapcapacitancesdonotdependonthebiasconditions,
i.e.,theyarevoltage-independent.
VLSI Design (EC-302) 157
arrangementarecalledC
GD(overlap)andC
GS(overlap),respectively.
Assumingthatboththesourceandthedraindiffusionregionshavethesame
widthW,theoverlapcapacitancescanbefoundas
with
bothoftheseoverlapcapacitancesdonotdependonthebiasconditions,
i.e.,theyarevoltage-independent.
VLSI Design (EC-302) 157
Thecapacitanceswhichresultfromtheinteractionbetweenthegatevoltageandthe
channelcharge.Sincethechannelregionisconnectedtothesource,thedrain,andthe
substrate,wecanidentifythreecapacitancesbetweenthegateandtheseregions,i.e.,C
gs,
C
gdandC
gbrespectively.
Incut-offmode(Fig.(a)),thesurfaceisnotinverted.Consequently,thereisnoconducting
channelthatlinksthesurfacetothesourceandtothedrain.Therefore,thegate-to-source
andthegate-to-draincapacitancesarebothequaltozero:C
gs=C
gd=0.Thegate-to-
substratecapacitancecanbeapproximatedby
VLSI Design (EC-302) 158
channelcharge.Sincethechannelregionisconnectedtothesource,thedrain,andthe
substrate,wecanidentifythreecapacitancesbetweenthegateandtheseregions,i.e.,C
gs,
C
gdandC
gbrespectively.
Incut-offmode(Fig.(a)),thesurfaceisnotinverted.Consequently,thereisnoconducting
channelthatlinksthesurfacetothesourceandtothedrain.Therefore,thegate-to-source
andthegate-to-draincapacitancesarebothequaltozero:C
gs=C
gd=0.Thegate-to-
substratecapacitancecanbeapproximatedby
VLSI Design (EC-302) 158
VLSI Design (EC-302) 159
In linear-mode operation, the inverted channel extends across the MOSFET, between the source and the drain
(Fig. (b)). This conducting inversion layer on the surface effectively shields the substrate from the gate
electric field; thus, C
gb = 0.
When the MOSFET is operating in saturation mode, the inversion layer on the surface does not extend to the
drain, but it is pinched off (Fig. (c)). The gate-to-drain capacitance component is therefore equal to zero (C
gd
=0). Since the source is still linked to the conducting channel, its shielding effect also forces the gate-to-
substrate capacitance to be zero, C
gb = 0. Finally, the distributed gate-to-channel capacitance as seen
between the gate and the source can be approximated by
In linear-mode operation, the inverted channel extends across the MOSFET, between the source and the drain
(Fig. (b)). This conducting inversion layer on the surface effectively shields the substrate from the gate
electric field; thus, C
gb = 0.
When the MOSFET is operating in saturation mode, the inversion layer on the surface does not extend to the
drain, but it is pinched off (Fig. (c)). The gate-to-drain capacitance component is therefore equal to zero (C
gd
=0). Since the source is still linked to the conducting channel, its shielding effect also forces the gate-to-
substrate capacitance to be zero, C
gb = 0. Finally, the distributed gate-to-channel capacitance as seen
between the gate and the source can be approximated by
VLSI Design (EC-302) 160
Approximate oxide capacitance values for three operating modes of the MOS
Variation of the distributed (gate-to-channel) oxide capacitances as functions of gate-to-source voltage V
GS.
Approximate oxide capacitance values for three operating modes of the MOS
Variation of the distributed (gate-to-channel) oxide capacitances as functions of gate-to-source voltage V
GS.
Junction Capacitances
Now we consider the voltage-dependent source-substrate and drain-substrate
junction capacitances, C
sband C
db, respectively.
VLSI Design (EC-302) 161
Three-dimensional view of the n' diffusion region within the p-type substrate.
Now we consider the voltage-dependent source-substrate and drain-substrate
junction capacitances, C
sband C
db, respectively.
VLSI Design (EC-302) 161
Three-dimensional view of the n' diffusion region within the p-type substrate.
VLSI Design (EC-302) 162
Types and areas of the pn-junctions shown in Figure
To calculate the depletion capacitance of a reverse-biased abrupt pn-junction, consider first the depletion
region thickness, X
d. Assuming that the n-type and p-type doping densities are given by N
D and N
A,
respectively, and that the reverse bias voltage is given by V (negative), the depletion region thickness
can be found as follows:
Eq.1
Where the built in potential is calculated as
Eq. 2
Types and areas of the pn-junctions shown in Figure
To calculate the depletion capacitance of a reverse-biased abrupt pn-junction, consider first the depletion
region thickness, X
d. Assuming that the n-type and p-type doping densities are given by N
D and N
A,
respectively, and that the reverse bias voltage is given by V (negative), the depletion region thickness
can be found as follows:
Eq.1
Where the built in potential is calculated as
Eq. 2
Note that the junction is forward-biased for a positive bias voltage V, and reverse-biased
for a negative bias voltage. The depletion-region charge stored in this area can be written
in terms of the depletion region thickness, x
d.
Eq. 3
Here,Aindicatesthejunctionarea.Thejunctioncapacitanceassociatedwiththedepletion
regionisdefinedas
Eq.4
BydifferentiatingQ
jwithrespecttothebiasvoltageV,wecannowobtainthe
expressionforthejunctioncapacitanceasfollows.
Eq.5
VLSI Design (EC-302) 163
for a negative bias voltage. The depletion-region charge stored in this area can be written
in terms of the depletion region thickness, x
d.
Eq. 3
Here,Aindicatesthejunctionarea.Thejunctioncapacitanceassociatedwiththedepletion
regionisdefinedas
Eq.4
BydifferentiatingQ
jwithrespecttothebiasvoltageV,wecannowobtainthe
expressionforthejunctioncapacitanceasfollows.
Eq.5
VLSI Design (EC-302) 163
This expression can be rewritten in a more general form, to account for the junction grading.
Eq. 6
VLSI Design (EC-302) 164
The parameter m is called the grading coefficient. Its value is equal to 1/2 for an abrupt junction profile, and 1/3
for a linearly graded junction profile. Obviously, for an abrupt pn-junction profile, i.e., for m = 1/2, the equations
(3.103) and (3.104) become identical. The zero-bias junction capacitance per unit area C
jo is defined as
Eq. 7
The problem of estimating capacitance values under changing bias conditions can be simplified, if we
calculate a large-signal average (linear) junction capacitance instead, which, by definition, is independent of
the bias potential. This equivalent large-signal capacitance can be defined as follows:
Eq. 8
Eq. 6
VLSI Design (EC-302) 164
The parameter m is called the grading coefficient. Its value is equal to 1/2 for an abrupt junction profile, and 1/3
for a linearly graded junction profile. Obviously, for an abrupt pn-junction profile, i.e., for m = 1/2, the equations
(3.103) and (3.104) become identical. The zero-bias junction capacitance per unit area C
jo is defined as
Eq. 7
The problem of estimating capacitance values under changing bias conditions can be simplified, if we
calculate a large-signal average (linear) junction capacitance instead, which, by definition, is independent of
the bias potential. This equivalent large-signal capacitance can be defined as follows:
Eq. 8
Here, the reverse bias voltage across the pn-junction is assumed to change from V
Ito V
2. Hence, the
equivalent capacitance C
eqis always calculated for a transition between two known voltage levels.
By substituting Eq. 6 into Eq. 8, we obtain
Eq. 9
Eq. 10
ThisequationcanberewritteninasimplerformbydefiningadimensionlesscoefficientK
eqas
follows:
Eq.11
where
VLSI Design (EC-302) 165
where K
eq is the voltage equivalence factor(note that 0 < K
eq < 1). Thus, the coefficient K
eq allows us to
take into account the voltage-dependent variations of the junction capacitance.
Ito V
2. Hence, the
equivalent capacitance C
eqis always calculated for a transition between two known voltage levels.
By substituting Eq. 6 into Eq. 8, we obtain
Eq. 9
Eq. 10
ThisequationcanberewritteninasimplerformbydefiningadimensionlesscoefficientK
eqas
follows:
Eq.11
where
VLSI Design (EC-302) 165
where K
eq is the voltage equivalence factor(note that 0 < K
eq < 1). Thus, the coefficient K
eq allows us to
take into account the voltage-dependent variations of the junction capacitance.
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