VLSI Testing Techniques

Different testing techniques used in VLSI to test the circuit are explained here.

1. VLSI TESTINGTECHNIQUES
Mr. A. B. Shinde
Assistant Professor,
Electronics Engineering,
P.V.P.I.T., Budhgaon

2. BOOK: TESTING
2

3. NEEDOFTESTINGCIRCUIT
Thereareseveralreasonsfortestingalogiccircuit.
Whenthecircuitisfirstdeveloped,itisnecessarytoverifythat
thedesignedcircuitmeetstherequiredfunctionalandtiming
specifications.
Whenmultiplecopiesaremanufactured,itisessentialtotest
eachcopytoensurethatthemanufacturingprocesshasnot
introducedanyflaws.
Thebasisofalltestingtechniquesistoapplypredefinedsetsof
inputs,calledtests,toacircuitandcomparetheoutputsobserved
withthepatternsthatacorrectlyfunctioningcircuitissupposedto
produce.
Thechallengeistoderivearelativelysmallnumberofteststhat
provideanadequateindicationthatthecircuitiscorrect.
3

4. TESTINGTECHNIQUES
Types of Testing Circuits
Combinational Circuit Testing
Fault Model
Path Sensitizing
Random Test
Sequential Circuit Testing
Scan Path Test
Built-in Self Test (BIST)
Built-in Logic Block Observer (BIBLO)
Signature Analyzer
Boundary Scan Test (BST)
4

5. FAULT MODEL
Acircuitfunctionsincorrectlywhenthereissomethingwrongwith
it,suchasatransistorfaultoraninterconnectionwiringfault.
Atransistorswitchcanbreaksothatitispermanentlyeither
closedoropen.
AwireinthecircuitcanbeshortedtoV
DDortoground,oritcan
besimplybroken.
Therecanbeanunwantedconnectionbetweentwowires.
Fortunately,itispossibletorestrictthetestingprocesstosome
simplefaults,andobtaingenerallysatisfactoryresults.
5

6. STUCKATMODEL
Agoodmodelforrepresentingfaultsistoassumethatallfaults
manifestthemselvesassomewires(inputsoroutputsofgates)
beingpermanentlystuckatlogicvalue0or1.
Considerawire,w.
Ifwhasanundesirablesignalthatalwayscorrespondstothelogicvalue
0,bysayingthatwisstuck-at-O,whichisdenotedasw/0.
Ifwhasanundesirablesignalthatisalwaysequaltologic1,thenwis
stuck-at-1,whichisdenotedasw/1.
Acircuitcanhaveeitherasinglefaultorpossiblymanyfaults.
Dealingwithmultiplefaultsisdifficultbecauseeachfaultcan
occurinmanydifferentways.Apragmatic(practical)approachis
toconsidersinglefaultsonly.
6

7. STUCKATMODEL
7

8. PATH SENSITIZING
Previousapproachisnotfeasiblefromthepracticalpointofview,
becauseiftherearetoomanywiresthenitwillhavetoomany
faults.
Abetteralternativeistodealwithseveralwiresthatformapath
asanentitythatcanbetestedforseveralfaultsusingasingle
test.
Itispossibletoactivateapathsothatthechangesinthesignal
thatpropagatesalongthepathhaveadirectimpactontheoutput
signal.
8

9. PATH SENSITIZING
9
Thepathisactivatedbyensuringthatotherpathsinthecircuitdo
notdeterminethevalueoftheoutputf.
Ifw2=1thenbdependsonlyonthevaluea.
Ifw3=0sothatitdoesnotaffecttheNORgate,
Ifw4=1itnotaffecttheANDgate.
Thenifw1=0theoutputwillbef=1,
whereasw1=1willcausef=0.
Insteadofsayingthatthepathfromw1tofisactivated,amore
specifictermisused,whichsaysthatthepathissensitized.

10. PATH SENSITIZING
10
TosensitizeapaththroughaninputofanANDorNANDgate,all
otherinputsmustbesetto1.
TosensitizeapaththroughaninputofanORorNORgate,all
otherinputsmustbe0.

11. SCANPATHTESTING
11

12. SCANPATHTESTING
12
Scanpath,usesmultiplexersonflip-flop
inputstoallowtheflip-flopstobeused
eitherindependentlyduringnormal
operationofthesequentialcircuit,orasa
partofashiftregisterfortestingpurposes.
Figurepresentsthegeneralscan-path
structureforacircuitwiththreeflip-flops.
A2-to-lmultiplexerconnectstheDinputof
eachflip-flopeithertothecorresponding
next-statevariableortotheserialpaththat
connectsallflip-flopsintoashiftregister.
ThecontrolsignalNormal/Scanselectsthe
activeinputofthemultiplexer.
Duringthenormaloperationtheflip-flop
inputsaredrivenbythenext-state
variables,Y1,Y2,andY3•.

13. SCANPATHTESTING
13
Fortestingpurposestheshift-register
connectionisusedtoscanintheportion
ofeachtestvectorthatinvolvesthe
present-statevariables,Y1,Y2,andY3.
ThisconnectionhasQiconnectedto
Di+1.
Theinputtothefirstflip-flopisthe
externallyaccessiblepinScan-in.
Theoutputcomesfromthelastflip-flop,
whichisprovidedontheScan-outpin.

14. SCANPATHTESTING
Example
14

15. BUILT-INSELFTEST
15
Thecircuitwithself-testablefacility,iscalledasbuilt-inself-test
(BIST).
FigureshowsapossibleBISTarrangementinwhichatestvector
generatorproducesthetestvectorsthatmustbeappliedtothe
circuitundertest(CUT).

16. BUILT-INSELFTEST
LFSR (Linear Feedback Shift Register)
16
ThecircuitinFigureislinearfeedbackshiftregisters(LFSRs).
Usingfeedbackfromthevariousstagesofann-bitshiftregister,
connectedtothefirststagebymeansofXORgates,itispossibleto
generateasequenceof2
n
-1patternsthathavethecharacteristicsof
randomlygeneratednumbers.

17. BUILT-INSELFTEST
17
SIC (Single Input Compressor Circuit )

18. BUILT-INSELFTEST
18
MIC (Multiple Input Compressor Circuit)
Abovefigureillustrateshowfourinputs,P0throughP3,canbeaddedto
thebasiccircuitofpreviousfigure.
Againthefour-bitsignatureprovidesagoodmechanismfor
distinguishingamongdifferentsequencesoffour-bitpatternsthatmay
appearontheinputsofthismultiple-inputcompressorcircuit(MIC).

19. BUILT-INSELFTEST
19
MIC
(Multiple Input
Compressor
Circuit)
SIC
(SingleInput
Compressor
Circuit)
PRBSG
(Pseudorandom
Binary
Sequence
Generator)

20. BUILT-INSELFTEST
20
Example :
BIBLO: Built-In Logic Block Observer

21. BUILT-INSELFTEST
21
Example :
Signature Analysis
Signature Analysis using BIBLO

22. BOUNDARY SCAN TEST
Thetestingtechniquesdiscussedintheprevious
sectionsareequallyapplicabletocircuitsthatare
implementedonsinglechips.
Acircuitcanbetestedonlyifitispossibletoapplythe
teststoitandobservetheoutputsproduced.
Whenchipsaresolderedontoaprintedcircuitboard,it
oftenbecomesimpossibletoattachtestprobestopins.
Thisobstructsthetestingprocessunlesssomeindirect
accesstothepinsisprovided.Thescan-pathconcept
canbeextendedtotheboardleveltodealwiththe
problem.
22

23. BOUNDARY SCAN TEST
Supposethateachprimaryinputoroutputpinonachip
isconnectedthroughaDflip-flopandthataprovisionis
madeforatestmodeinwhichallflip-flopscanbe
connectedintoashiftregister.
Thenthetestinformationcanbescannedinand
scannedoutusingtheshift-registerpath,viatwopins
thatserveasserialinputandoutput.
Connectingtheserialoutputpinofonechiptotheserial
inputpinofanotherchipresultsinthepinsofallchips
beingconnectedintoaboard-wideshiftregisterfor
testingpurposes. 23

24. VLSI DESIGNFLOWWITHREFERENCETOXILINXTOOL
24

25. THANKYOU
25
[email protected]
This presentation is published only for educational purpose