Washing machine

1. Dr.Abaza.M.Gh Saffana adel bany mohammad Washing machine

2. A Wash machine Controller We are going to design a simple FSM that controls a wash machine using D-flops. The wash machine has the following states : off , fill water 1 , drain 1, fill water 2 , rinse , drain 2 . The user start the washer by plugging it to the power supply .

3. A Wash machine Controller Wash Machine Controller START L (0,1) OW WS DS R OW Hot water Cold water M { Wash machine Controller Specification }

4. A Wash machine Controller There is one contol line to its water feed (OW). Choice of hot or cold water wash done manually by the user for simplicity. In this simple washing machine there will be a drum motor that have two rotation speeds : low speed for wash cycle & high speed for the drain cycle. To contol the speed of the motor we have two outputs ( sighals ) from the wash contoller : WS for low speed , and DS for high speed .

5. Block Diagram Wash machine controller have two blocks : FSM block & timer block. Timer is a counter that have a logic circuit to reset it . FSM Timer OW WS DS R L (0,1) CLK START T

6. State Diagram Input / Outputs T / OW , WS , DS , R OFF 000 Fill water 001 wash 010 Drain 011 Fill water2 100 Rinse 101 drain2 0/0000 0/1000 1/1001 1/0101 0/0100 1/0011 0/0010 1/1001 0/1000 1/0101 0/0100 1/0011 0/0010 1/0010

7. Truth Table for the washing machine : For the FSM circuit , we will need: Three D flip-flops to represent the three state bits . The inputs for the 3 F/Fs will the next state because as we know D = Q+ . E become 1 when the user plug the machine to the power supply.

8. Truth Table for the washing machine : P . State i /p N .state o/p E s2 s1 s0 T s2 s1 s0 OW WS DS R 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 0 0 0 0 0 1 1 0 1 0 0 1 1 1 1 0 0 1 0 1 1 1 1 0 1 1 1 1 0 0 0 0 0 0 0 0 1 1 0 0 1 0 0 1 1 0 0 0 0 1 0 0 1 0 1 0 1 0 0 1 0 0 0 1 1 0 0 1 1 0 1 1 0 0 1 0 1 0 0 1 0 0 1 1 0 0 1 0 0 0 1 0 1 0 1 0 1 1 0 1 0 1 0 0 1 1 0 0 0 1 1 1 1 0 0 0 1 0 0 0 0 0 0 0 1 d d d d d d d d d d d d d d Note : That d means don’t care.

9. K . Maps for D.F/Fs implementation 00 01 11 10 00 01 11 10 0 0 0 0 0 0 1 0 1 0 X X 1 1 1 1 00 01 11 10 00 01 11 10 0 0 1 0 1 0 0 1 1 0 X X 0 0 1 0 s0T s2s1 Ds1 = S1.S0.T + S2.S1.S0 + S1 .T s0T s2s1 Ds2 = S1.S0.T + S2.S1 + S2 .T

10. K . Maps for D.F/Fs implementation 00 01 11 10 00 01 11 10 0 1 0 1 0 1 0 0 0 0 X X 0 1 0 1 s2s1 s0T Ds0 = S0.T + S2.S0 .T + S1.S0.T

11. K . Maps for 0/Ps implementation 00 01 11 10 00 01 11 10 0 1 0 1 0 0 1 0 0 0 X X 1 1 0 0 s2s1 s0T 00 01 11 10 00 01 11 10 0 0 1 0 1 0 0 0 0 0 X X 0 1 0 1 s2s1 s0T OW = S2.S1 + (S0 T + S1.S0.T + S2 .( S1+S0+T) WS = S2.S1.S0.T+ S2.S1.S0 .T + S2.S1.S0.T + S2.S0.T

12. K . Maps for 0/Ps implementation 00 01 11 10 00 01 11 10 0 0 0 0 0 1 0 1 1 0 X X 0 0 1 0 s2s1 s0T 00 01 11 10 00 01 11 10 0 1 1 0 0 1 1 0 0 1 X X 0 1 1 0 s2s1 s0T DS = S1.S0 .T + S2.S0.T + S2.S1.T +S2.S1+S0+T R=T

13. Logic circuit for F/Fs inputs : D S0 D S1 D S2 S0 S2 S0 S1 S0 S0 S1 S1 S0 S2 S1 S2 S1 S1 S0 S0 S0 S1 S1 S2 S2 CLK

14. Logic circuit for F/Fs outputs : S1 S2 S0 S1 S2 s0 T s0 S1 T

15. Logic circuit for F/Fs outputs : S1 S0 S2 T S2 S0 T S1 S0 T S1 S0 T S2 S2 WS

16. Logic circuit for F/Fs outputs : S0 T S1 S2 S1 T S0 ST S1 T S2 S2 DS S0 T R