3. CMOS Fabrication.ppt important to read

cmos

1. CMOS Inverter
AY
0
1V
DD
A Y
GND A Y

2. CMOS Inverter
AY
0
10V
DD
A=1 Y=0
GND
ON
OFF A Y

3. CMOS Inverter
AY
01
10V
DD
A=0 Y=1
GND
OFF
ON A Y

4. CMOS Fabrication
Different approaches to CMOS fabrication are
1.P-well
2.N-well
3.Twin tub or Twin well
4.SOI-Silicon On Insulator

5. P-well process
Thestructureconsistsofann-typesubstrateinwhichp-devicesmaybe
formedbysuitablemaskinganddiffusionand,inordertoaccommodaten-
typedevices,adeepp-wellisdiffusedintothen-typesubstrate.
Thediffusionmustbecarriedoutwithspecialcaresincethep-welldoping
concentrationanddepthwillaffectthethresholdvoltages.Weneedeither
deepwelldiffusionorhighwellresistivity.

6. P-well process
Definethethinoxregions,namelythoseareaswherethethickoxideistobe
strippedandthinoxidegrowntoaccommodatepandntransistorsand
patternthepolysiliconlayerwhichisdepositedafterthethinoxide.

7. P-well process
Applusmaskisnowusedtodefineallareaswherepdiffusionistotake
place.
Thenegativeformofthep-plusmaskisusedtodefinethoseareaswhere
n-typediffusionistotakeplace.

8. Summary of p-well process
Mask-1:Definestheareasinwhichthedeepp-welldiffusions
aretotakeplace.
Mask-2:Definesthethinoxregions,namelythoseareaswhere
thethickoxideistobestrippedandthinoxidegrownto
accommodatepandntransistorsanddiffusionwires.
Mask-3:Usedtopatternthepolysiliconlayerwhichis
depositedafterthethinoxide.
Mask-4:Applusmaskisnowusedtodefineallareaswherep
diffusionistotakeplace.
Mask-5:Thisisusuallyperformedusingthenegativeformof
thep-plusmaskand,withmask-2,definesthoseareaswheren-
typediffusionistotakeplace.

9. P-well process
Mask-6:Contactcutsarenowdefined.
Mask-7:Themetallayerpatternisdefinedbythismask.
Mask-8:Anoverallpassivation(overglass)layerisnow
appliedandmask8isneededtodefinetheopeningsforaccess
tobondingpads.

10. CMOS p-well inverter showing V
DD
and V
SS substrate connections

11. N-well Process
N-wellCMOScircuitsarealsosuperiortop-wellbecauseofthe
lowersubstratebiaseffectsontransistorthresholdvoltageand
inherentlylowerparasiticcapacitancesassociatedwithsource
anddrainregions.

12. N-well fabrication steps

13. Cross sectional view of n-well CMOS
inverter

14. Twin tub process
Twintubfabricationisalogicalextensionofp-wellandn-wellapproaches.
Ahighresistivityofn-typematerialistakenandthenbothn-wellandp-well
arecreatedinit.
Inthisprocess,separateoptimizationofthen-typeandp-type
transistorswillbeprovided.
Toprotectthelatchup,epitaxiallayerisused.

15. Silicon on insulator (SOI)
CompletelyisolatedNMOSandPMOStransistorscanbecreated
virtuallysidebysideonaninsulatingsubstrate(eg.Sapphireor
magnesiumaluminatespinel)byusingtheSOICMOStechnology.
Silayerontopofaninsulatorlayertobuildactivedevicesand
circuits.
ThetransistorswouldthenbebuiltontopofthisthinlayerofSOI.
ThebasicideaisthattheSOIlayerwillreducethecapacitanceof
theswitch,soitwilloperatefaster.
Thin Layer of Silicon
SiO
2or Al
2O
3(sapphire)

16. Silicon on insulator (SOI)
High speed
Low power
High device density
Easier device isolation structure
Absence of Latch up
Lower parasitic substrate capacitances

17. Silicon on insulator (SOI)
fabrication process
•SOS –Silicon-on-Sapphire
•SIMOX –Separation by Implantation of Oxygen

18. Silicon on insulator (SOI)
fabrication process
-BESOI –Bond and Etch-back SOI.