8 x 1 mux using 4x1 and 2x1 multiplexer

8 x1 mux presentation

1. 8x1 MULTIPLEXER USING 4X1 AND 2X1 MULTIPLEXER By – Om Dhar Dubey Cranes Varsity

2. Introduction This project focuses on designing an 8-to-1 multiplexer using a combination of 4-to-1 and 2-to-1 multiplexers in Verilog. An 8-to-1 MUX selects one of eight inputs based on three select lines, producing a single output. The design is modular: two 4-to-1 multiplexers manage four inputs each, and their outputs are directed into a 2-to-1 multiplexer, which ultimately provides the final output. This structure simplifies the complexity of the 8-to-1 MUX, making it more manageable and demonstrating the effectiveness of hierarchical digital design. The project highlights the practical application of Verilog in constructing complex logic circuits.

3. Diagram

4. module MUX_8(d, sel , out); input [7:0] d; input [2:0] sel ; output out; wire w1, w2; MUX_4 U1(d[0], d[1], d[2], d[3], sel [1], sel [0], w1); MUX_4 U2(d[4], d[5], d[6], d[7], sel [1], sel [0], w2); MUX_2 U3(w1, w2, sel [2], out); endmodule PROGRAM

5. module TB_MUX_8; reg [7:0] d; reg [2:0] sel ; wire out; // Basic Gates is what we are going to test. MUX_8 U1(d[0], d[1], d[2], d[3], d[4], d[5], d[6], d[7], sel [0], sel [1], sel [2], out); initial begin d[0] = 0; d[1] = 0; d[2] = 0; d[3] = 0; d[4] = 0; d[5] = 0; d[6] = 0; d[7] = 0; sel[0] = 0; sel[1] = 0; sel[2] = 0; end always #10 sel [2] = ~ sel [2]; always #20 sel [1] = ~ sel [1]; always #40 sel [0] = ~ sel [0]; always #80 d[7] = ~d[7]; always #160 d[6] = ~d[6]; always #320 d[5] = ~d[5]; always #640 d[4] = ~d[4]; always #1280 d[3] = ~d[3]; always #2560 d[2] = ~d[2]; always #5120 d[1] = ~d[1]; always #10240 d[0] = ~d[0]; initial #20480 $finish; endmodule test bench

6. output

7. THAN K YO U !