8085 timing.pptx microprocessor 8085 timing

Timing 8085

1. Bud A writer's I/O cycle is executed by the processor to write a data byte to an I/O port or peripheral that is I/O mapped in the system. The processor needs 3T states to execute this machine cycle. Bus Timing and Instruction Timing Timing Diagrams - 8085

2. What is a Timing Diagram? A time diagram is a graphical representation. The  8085  instruction timing diagram represents the execution time of each instruction in graphical format. Execution time is given in T-states. Clock Signal:  The time required to execute an instruction is called a clock cycle. Machine Cycle:  The time required to access memory or input/output devices is called a machine cycle. The 8085 has 5 basic machine cycles i.e., load opcode, read from memory, write to memory, read I/O, and write I/O. T-State:  A machine cycle and an instruction cycle take several clock periods. The portion of an operation performed in one system clock period is called a T-state. Control Signals:  The control signal controls the operations. Common signals are  ALE  (address block enable), RD (read), WR (write), and IO/M (input/output) memory.

3. Timing Diagram is a graphical representation. It represents the execution time taken by each instruction in a graphical format. The execution time is represented in T- states. Instruction Cycle: The time required to execute an instruction . Machine Cycle: The time required to access the memory or input/output devices . T- State: •The machine cycle and instruction cycle takes multiple clock periods. •A portion of an operation carried out in one system clock period is called as T- state.

4. Timing diagrams The 8085 microprocessor has 5 basic machine cycle. They are Op- code Fetch cycle(4T or 6T). Memory read cycle (3T) Memory write cycle(3T) I/O read cycle(3T) I/O write cycle(3T)

5. Machine Cycle of 8085 The 8085 microprocessor has 5 basic machine cycles. They are : Opcode Fetch {4T- state} Memory Read {3T- state} Memory Write {3T- state} I/O Read {3T- state} I/O Write {3T- state}

6. Opcode Fetch Machine Cycle of 8085 Each processor instruction has a one byte opcode. Operation codes are stored in memory. Thus, the processor performs an opcode load machine cycle to load the opcode from memory. Thus, each instruction begins with a machine cycle of opcodes . The time the processor takes to perform an opcode load cycle is 4T. At this time, the first, 3T-states are used to load the opcode from memory, and the remaining T-states are used for internal opcodes .

7. OPCODE FETCH The Opcode fetch cycle, fetches the instructions from memory and delivers it to the instruction register of the microprocessor Opcode fetch machine cycle consists of 4 T- states. T1 State: During the T1 state, the contents of the program counter are placed on the 16 bit address bus. The higher order 8 bits are transferred to address bus (A8- A15) and lower order 8 bits are transferred to multiplexed A/D (ADO- AD7) bus. ALE (address latch enable) signal goes high. As soon as ALE goes high, the memory latches the ADO- AD7 bus. At the middle of the T state the ALE goes low

8. T2 State: During the beginning of this state, the RD’ signal goes low to enable memory. It is during this state, the selected memory location is placed on DO- D7 of the Address/Data multiplexed bus. T3 State: In the previous state the Opcode is placed in DO- D7 of the A/D bus. In this state of the cycle, the Opcode of the A/D bus is transferred to the instruction register of the microprocessor. Now the RD’ goes high after this action and thus disables the memory from A/D bus. T4 State: In this state the Opcode which was fetched from the memory is decoded.

9. Memory Read Machine Cycle of 8085 A memory read machine cycle is executed by the  processor  to read a data byte from memory. The processor takes 3T states to perform this cycle. Instructions that have more than one byte word will use machine cycle after machine cycle to load the opcode.

10. Memory Read

11. SIGNAL CLOCK ADD- AD IOfM,SJ S Memory read cycle (3T) T, T, HIGHER ORDER MEMORY ADDRSSS łØ/M - 0. DATA (D - DJ

12. These machine cycles have 3 T- states. T1 state: The higher order address bus (A8- A15) and lower order address and data multiplexed (ADO- AD7) bus. ALE goes high so that the memory latches the (ADO- AD7) so that complete 16- bit address are available. The mp identifies the memory read machine cycle from the status signals IO/M’=O, S1=0, SO=1. This condition indicates the memory read cycle. T2 state: Selected memory location is placed on the (DO- D7) of the A/D multiplexed bus. WR’ goes LOW T3 State: In the middle of the T3 state WR’ goes high and disables the memory write operation. The data which was obtained from the memory is then decoded.

13. Memory Write Machine Cycle A write-to-memory machine cycle is executed by the processor to write a data byte to memory.
The processor takes 3T states to perform this cycle.
Instructions that have more than one byte word will use machine cycle after machine cycle to load the opcode.

14. A write-to-memory machine cycle is executed by the processor to write a data byte to memory. The processor takes 3T states to perform this cycle. Instructions that have more than one byte word will use machine cycle after machine cycle to load the opcode.

15. These machine cycles have 3 T- states. T1 state: The higher order address bus (A8- A15) and lower order address and data multiplexed (ADO- AD7) bus. ALE goes high so that the memory latches the (ADO- AD7) so that complete 16- bit address are available. The mp identifies the memory read machine cycle from the status signals IO/M’=O, S1=0, SO=1. This condition indicates the memory read cycle. T2 state: Selected memory location is placed on the (DO- D7) of the A/D multiplexed bus. WR’ goes LOW T3 State: In the middle of the T3 state WR’ goes high and disables the memory write operation. The data which was obtained from the memory is then decoded.

16. I/O Read Machine Cycle A reader I/O cycle is performed by the processor to read a data byte from an I/O port or peripheral that is I/O mapped in the system.
The processor needs 3T states to execute this machine cycle.

17. I/O Write Machine Cycle A writer’s I/O cycle is executed by the processor to write a data byte to an I/O port or peripheral that is I/O mapped in the system.
The processor needs 3T states to execute this machine cycle.

18. -AD FF IO/ M.S o .S 0, 1, 1 Memoryread T T '0, 0. I 0,0, I Memory wite 0, 1,0

19. Timing diagram for 43h Fetching the Opcode 06H from the memory 2OOOH. (OF machine cycle) Read (move) the data 43H from memory 2001H. (memory read) MV I B, 43 H $$ H 43 H

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22. ADD M T j TI SO, SI OPCODE T4 TI T2 kl emory Address (H igher) DATA

23. References www.sIideshare.net www.docstoc.com www.sIideworId.com www.nptel.ac.in www.scribd.com htt encourses.emu.edu.tr http://engineeringppt.bIogspot.in/ htt www. tsearcheneine.net www.4shared.com http://8085projects.info/ Books: Microprocessors and microcontrollers by krishnakanth Microprocessors and microcontrollers by Nagoor Kani

24. Staff references 8085 microprocessor by S aii d Akram , researcher/lecturer at c.abduI hakeem college of engineering and technology Timingdiagram by u a00 (sIideshare.net) Microprocessor 8086 by Gopikrishna Madanan , Assistant Professor of Physics at Collegiate Education, Kerala, India