8086_architecture-1 detailed analysis in easy language

8086_architecture-1 detailed analysis in easy language

1. 8086 Microprocessor
1

2. History
Microprocessor journey started with a 4-bit processor called
4004; it was made by Intel Corporation in 1971.
It was 1st single chip processor.Then the idea was extended to
8-bit processors like 8008, 8080 and then 8085 (all are Intel
products).
8085 was a very successful one among the 8-bit processors;
however its application is very limited because of its slower
computing speed and other quality factors.

3. INTRODUCTION
8086isanenhancedversionof8085thathasbeendevelopedby
Intelin1976.
Itisa16bitMicroprocessor.Ithasapowerfulinstructionsetandit
iscapabletoprovidingmultiplicationanddivisionoperationsdirectly.
Ithas20addresslinesand16datalines.Soitcanaccessupto1MB
ofmemory.
It supports two modes of operation: first is maximum mode and
second is minimum mode. Minimum mode is applicable for system
that has a single processor and maximum mode is used for the
multiprocessor system.

4. Features of 8086
1.8086 is a 40 pin IC.
2.It is a 16-bit processor.
3.Its operating voltage is 5 volts.
4.Its operating frequency is 5 MHz
5.Total memory addressing capacity is 1MB (external).
6.It has 16-bit data bus and 20-bit address bus.
7.It has fourteen 16-bit registers.
8.Higher throughput (speed).

5. Block Diagram of Intel 8086
The 8086 CPU is divided into two independent functional
units:
Bus Interface Unit (BIU)
Execution Unit (EU)

6. Architecture of 8086
6

7. Bus Interface Unit (BIU)
The function of BIU is to:
Fetch the instruction or data from memory
Write the data to memory
Write the data to the port
Read data from the port

8. Software Model of the 8086 Microprocessors
8

9. 8086 Registers
9CS
SS
DS
ES
Segment
BP
Index
SP
SI
DI
AH
BH
CH
DH DL
CL
BL
AL
General Purpose
Status and Control
Flags
IP
AX
BX
CX
DX

10. General Purpose Registers
Normally used for storing temporary results
Each of the registers is 16 bits wide (AX, BX, CX, DX)
Can be accessed as either 16 or 8 bits AX, AH, AL
10
AX -the Accumulator
BX -the Base Register
CX -the Count Register
DX -the Data Register

11. General Purpose Registers
•AX
–Accumulator Register
–Preferred register to use in arithmetic, logic and data
transfer instructions because it generates the shortest
Machine Language Code
–Must be used in multiplication and division operations
–Must also be used in I/O operations
•BX
–Base Register
–Also serves as an address register
11

12. General Purpose Registers
•CX
–Count register
–Used as a loop counter
–Used in shift and rotate operations
•DX
–Data register
–Used in multiplication and division
–Also used in I/O operations
12

13. Pointer and Index Registers
•All 16 bits wide, L/H bytes are not accessible
•Used as memory pointers
–Example: MOV AH, [SI]
•Move the byte stored in memory location whose addressis contained
in register SI to register AH
•IP is not under direct control of the programmer
13

14. Flag Register
14
Carry
Parity
Auxiliary Carry
Zero
Overflow
Direction
Interrupt enable
Trap
Sign
6 are status flags
3 are control flag

15. 8086 Programmer’s Model
15
ES
CS
SS
DS
IP
AH
BH
CH
DH
AL
BL
CL
DL
SP
BP
SI
DI
FLAGS
AX
BX
CX
DX
Extra Segment
Code Segment
Stack Segment
Data Segment
Instruction Pointer
Accumulator
Base Register
Count Register
Data Register
Stack Pointer
Base Pointer
Source Index Register
Destination Index Register
BIU registers
(20 bit adder)
EUregisters

16. The Stack
•Thestackisusedfortemporarystorageofinformation
suchasdataoraddresses.
•WhenaCALLisexecuted,the8086automatically
PUSHesthecurrentvalueofCSandIPontothestack.
Otherregisterscanalsobepushed
Beforereturnfromthesubroutine,POPinstructions
canbeusedtopopvaluesbackfromthestackintothe
correspondingregisters.
16

17. The Stack
17

18. INTEL 8086 -Pin Diagram
18

19. INTEL 8086 -Pin Details
19
Ground
Clock
Power Supply
5V 10%
Reset
Registers, seg
regs, flags
CS: FFFFH, IP:
0000H
If high for
minimum 4
clks

20. INTEL 8086 -Pin Details
20
Address/DataBus:
Contains address
bits A
15-A
0 when ALE
is 1 & data bits D
15–
D
0when ALE is 0.
Address Latch Enable:
When high,
multiplexed
address/data bus
contains address
information.

21. INTEL 8086 -Pin Details
21
INTERRUPT
Non -maskable
interrupt
Interrupt request
Interrupt
acknowledge

22. INTEL 8086 -Pin Details
22
Direct
Memory
Access
Hold
acknowledge
Hold

23. INTEL 8086 -Pin Details
23
Address/Status Bus
Address bits A
19–
A
16& Status bits S
6
–S
3

24. INTEL 8086 -Pin Details
24
Bus High Enable/S7
Enables most
significant data bits
D
15–D
8during read
or write operation.
S
7: Always 1.
BHE#, A
0:
0,0:Whole word
(16-bits)
0,1:High byte
to/from odd address
1,0:Low byte
to/from even address
1,1:No selection

25. INTEL 8086 -Pin Details
25
Min/Max mode
Minimum Mode: +5V
Maximum Mode: 0V
Minimum Mode Pins
Maximum Mode
Pins

26. Minimum Mode-Pin Details
26
Read Signal
Write Signal
Memory or
I/0
Data Bus
Enable
Data
Transmit/Receive

27. Maximum Mode -Pin Details
27
Status Signal
Inputs to 8288 to
generate eliminated
signals due to max
mode.
S2 S1 S0
000: INTA’
001: read I/O port
010: write I/O port
011: halt
100: code access
101: read memory
110: write memory
111: none -passive

28. Maximum Mode -Pin Details
28
DMA
Request/Grant
Lock Output
LockOutput
Usedtolockperipherals
ofthesystem
Activatedbyusingthe
LOCK:prefixonany
instruction

29. Maximum Mode -Pin Details
29
Queue Status
Used by numeric
coprocessor (8087)
QS1 QS0
00: Queue is idle
01: First byte of opcode
10: Queue is empty
11: Subsequent byte of
opcode

30. READY
Thisistheacknowledgement fromthe
slowdeviceormemory thattheyhave
completedthedatatransfer.

31. Minimum Mode 8086 System
31

32. ‘Read’ Cycle timing Diagram for Minimum Mode
32

33. ‘Write’ Cycle timing Diagram for Minimum Mode
33

34. Maximum Mode 8086 System
34

35. Maximum Mode 8086 System
Here,eitheranumericcoprocessorofthetype8087oranother
processorisinterfacedwith8086.
TheMemory,AddressBus,DataBusesaresharedresources
betweenthetwoprocessors.
ThecontrolsignalsforMaximummodeofoperationare
generatedbytheBusControllerchip8788.
ThethreestatusoutputsS0*,S1*,S2*fromtheprocessorare
inputto8788.
TheoutputsofthebuscontrolleraretheControlSignals,
namelyDEN,DT/R*,IORC*,IOWTC*,MWTC*,MRDC*,ALE
etc.
35

36. Memory Read timing in Maximum Mode
36

37. Memory Write timing in Maximum Mode
37

39. 1.Data Transfer Instructions
2.Arithmetic Instructions
3.Logical Instructions
4.String manipulation Instructions
5.Process Control Instructions
6.Control Transfer Instructions
Instruction Set
39
8086 supports 6 types of instructions.

40. Data Transfer Instructions
40
8086 Microprocessor
Instructions that are used to transfer data/ address in to registers,
memory locations and I/O ports.
Generally involve two operands: Source operand and Destination
operand of the same size.
Source: Register or a memory location or an immediate data
Destination: Register or a memory location.
The size should be a either a byte or a word.
A 8-bit data can only be moved to 8-bit register/ memory and a 16-bit
data can be moved to 16-bit register/ memory.

41. Data Transfer Instructions
41
Mnemonics:MOV, XCHG, PUSH, POP, IN, OUT …
MOV reg2/ mem, reg1/ mem
MOV reg2, reg1
MOV mem,reg1
MOV reg2, mem
(reg2) (reg1)
(mem)(reg1)
(reg2)(mem)
MOV reg/ mem, data
MOV reg, data
MOV mem, data
(reg) data
(mem)data
XCHG reg2/ mem, reg1
XCHG reg2, reg1
XCHG mem, reg1
(reg2) (reg1)
(mem)(reg1)

42. Data Transfer Instructions
42
Mnemonics: MOV, XCHG, PUSH, POP, IN, OUT …
PUSH reg16/ mem
PUSH reg16
PUSH mem
(SP) (SP) –2
MA
S= (SS) x 16
10+ SP
(MA
S; MA
S+ 1)(reg16)
(SP) (SP) –2
MA
S= (SS) x 16
10+ SP
(MA
S; MA
S+ 1)(mem)
POP reg16/ mem
POP reg16
POP mem
MA
S= (SS) x 16
10+ SP
(reg16) (MA
S; MA
S+ 1)
(SP) (SP) + 2
MA
S= (SS) x 16
10+ SP
(mem) (MA
S; MA
S+ 1)
(SP) (SP) + 2

43. Data Transfer Instructions
43
Mnemonics: MOV, XCHG, PUSH, POP, IN, OUT …
IN A, [DX]
IN AL, [DX]
IN AX, [DX]
PORT
addr= (DX)
(AL) (PORT)
PORT
addr= (DX)
(AX) (PORT)
IN A, addr8
IN AL, addr8
IN AX, addr8
(AL) (addr8)
(AX) (addr8)
OUT [DX], A
OUT [DX], AL
OUT [DX], AX
PORT
addr= (DX)
(PORT) (AL)
PORT
addr= (DX)
(PORT) (AX)
OUT addr8, A
OUT addr8, AL
OUT addr8, AX
(addr8) (AL)
(addr8) (AX)

44. Arithmetic Instructions
44
Mnemonics: ADD, ADC, SUB, SBB, INC, DEC, MUL, DIV, CMP…
ADD reg2/ mem, reg1/mem
ADD reg2, reg1
ADD reg2, mem
ADD mem, reg1
(reg2) (reg1) + (reg2)
(reg2)(reg2) + (mem)
(mem)(mem)+(reg1)
ADD reg/mem, data
ADD reg,data
ADD mem, data
(reg) (reg)+ data
(mem)(mem)+data
ADD A, data
ADDAL, data8
ADD AX, data16
(AL)(AL)+ data8
(AX)(AX) +data16

45. Arithmetic Instructions
45
Mnemonics: ADD, ADC, SUB, SBB, INC, DEC, MUL, DIV, CMP…
ADC reg2/ mem, reg1/mem
ADC reg2, reg1
ADC reg2, mem
ADC mem, reg1
(reg2) (reg1) + (reg2)+CF
(reg2)(reg2) + (mem)+CF
(mem)(mem)+(reg1)+CF
ADC reg/mem, data
ADC reg,data
ADC mem, data
(reg) (reg)+ data+CF
(mem)(mem)+data+CF
ADDC A, data
ADDAL, data8
ADD AX, data16
(AL)(AL)+ data8+CF
(AX)(AX) +data16+CF

46. Arithmetic Instructions
46
Mnemonics: ADD, ADC, SUB, SBB, INC, DEC, MUL, DIV, CMP…
SUB reg2/ mem, reg1/mem
SUB reg2, reg1
SUB reg2, mem
SUB mem, reg1
(reg2) (reg1) -(reg2)
(reg2)(reg2) -(mem)
(mem)(mem) -(reg1)
SUB reg/mem, data
SUB reg,data
SUB mem, data
(reg) (reg)-data
(mem)(mem)-data
SUB A, data
SUBAL, data8
SUB AX, data16
(AL)(AL)-data8
(AX)(AX) -data16

47. Arithmetic Instructions
47
Mnemonics: ADD, ADC, SUB, SBB, INC, DEC, MUL, DIV, CMP…
SBB reg2/ mem, reg1/mem
SBB reg2, reg1
SBB reg2, mem
SBB mem, reg1
(reg2) (reg1) -(reg2)-CF
(reg2)(reg2) -(mem)-CF
(mem)(mem) -(reg1) –CF
SBB reg/mem, data
SBB reg,data
SBB mem, data
(reg) (reg) –data -CF
(mem)(mem) -data -CF
SBB A, data
SBB AL, data8
SBB AX, data16
(AL)(AL)-data8 -CF
(AX)(AX) -data16 -CF

48. Arithmetic Instructions
48
Mnemonics: ADD, ADC, SUB, SBB, INC, DEC, MUL, DIV, CMP…
INC reg/ mem
INC reg8
INC reg16
INCmem
(reg8) (reg8) + 1
(reg16) (reg16) + 1
(mem) (mem) + 1
DEC reg/ mem
DEC reg8
DEC reg16
DEC mem
(reg8) (reg8) -1
(reg16) (reg16) -1
(mem) (mem) -1

49. Arithmetic Instructions
49
Mnemonics: ADD, ADC, SUB, SBB, INC, DEC, MUL, DIV, CMP…
MUL reg/ mem
MUL reg
MUL mem
For byte :(AX) (AL) x (reg8)
Forword: (DX)(AX) (AX) x (reg16)
For byte :(AX) (AL) x (mem8)
Forword: (DX)(AX) (AX) x
(mem16)
IMUL reg/ mem
IMUL reg
IMUL mem
For byte :(AX) (AL) x (reg8)
Forword: (DX)(AX) (AX) x (reg16)
For byte :(AX) (AX) x (mem8)
Forword: (DX)(AX) (AX) x
(mem16)

50. Arithmetic Instructions
50
Mnemonics: ADD, ADC, SUB, SBB, INC, DEC, MUL, DIV, CMP…
DIV reg/ mem
DIV reg
DIV mem
For 16-bit :-8-bit :
(AL) (AX) :-(reg8) Quotient
(AH) (AX) MOD(reg8) Remainder
For 32-bit :-16-bit :
(AX) (DX)(AX) :-(reg16) Quotient
(DX) (DX)(AX) MOD(reg16) Remainder
For 16-bit :-8-bit :
(AL) (AX) :-(mem8) Quotient
(AH) (AX) MOD(mem8) Remainder
For 32-bit :-16-bit :
(AX) (DX)(AX) :-(mem16) Quotient
(DX) (DX)(AX) MOD(mem16) Remainder

51. Arithmetic Instructions
51
Mnemonics: ADD, ADC, SUB, SBB, INC, DEC, MUL, DIV, CMP…
IDIV reg/ mem
IDIV reg
IDIV mem
For 16-bit :-8-bit :
(AL) (AX) :-(reg8) Quotient
(AH) (AX) MOD(reg8) Remainder
For 32-bit :-16-bit :
(AX) (DX)(AX) :-(reg16) Quotient
(DX) (DX)(AX) MOD(reg16) Remainder
For 16-bit :-8-bit :
(AL) (AX) :-(mem8) Quotient
(AH) (AX) MOD(mem8) Remainder
For 32-bit :-16-bit :
(AX) (DX)(AX) :-(mem16) Quotient
(DX) (DX)(AX) MOD(mem16) Remainder

52. Arithmetic Instructions
52
Mnemonics: ADD, ADC, SUB, SBB, INC, DEC, MUL, DIV, CMP…
CMP reg2/mem, reg1/
mem
CMP reg2, reg1
CMP reg2, mem
CMP mem, reg1
Modify flags (reg2) –(reg1)
If (reg2) > (reg1) then CF=0,ZF=0, SF=0
If (reg2) < (reg1) then CF=1,ZF=0, SF=1
If (reg2) = (reg1) then CF=0,ZF=1, SF=0
Modify flags (reg2) –(mem)
If (reg2) > (mem) then CF=0,ZF=0, SF=0
If (reg2) < (mem) then CF=1,ZF=0, SF=1
If (reg2) = (mem) then CF=0,ZF=1, SF=0
Modify flags (mem) –(reg1)
If (mem) > (reg1) then CF=0,ZF=0, SF=0
If (mem) < (reg1) then CF=1,ZF=0, SF=1
If (mem) = (reg1) then CF=0,ZF=1, SF=0

53. Arithmetic Instructions
53
8086 Microprocessor
Mnemonics: ADD, ADC, SUB, SBB, INC, DEC, MUL, DIV, CMP…
CMP reg/mem, data
CMP reg, data
CMP mem, data
Modify flags (reg) –(data)
If (reg) > data then CF=0,ZF=0, SF=0
If (reg) < data then CF=1,ZF=0, SF=1
If (reg) = data then CF=0,ZF=1, SF=0
Modify flags (mem) –(mem)
If (mem) > data then CF=0,ZF=0, SF=0
If (mem) < data then CF=1,ZF=0, SF=1
If (mem) = data then CF=0,ZF=1, SF=0

54. Arithmetic Instructions
54
Mnemonics: ADD, ADC, SUB, SBB, INC, DEC, MUL, DIV, CMP…
CMP A, data
CMP AL, data8
CMP AX, data16
Modify flags (AL) –data8
If (AL) > data8 then CF=0,ZF=0, SF=0
If (AL) < data8 then CF=1,ZF=0, SF=1
If (AL) = data8 then CF=0,ZF=1, SF=0
Modify flags (AX) –data16
If (AX) > data16 then CF=0,ZF=0, SF=0
If (mem) < data16 then CF=1,ZF=0, SF=1
If (mem) = data16 then CF=0,ZF=1, SF=0

55. Logical Instructions
55
Mnemonics: AND, OR, XOR, TEST, SHR, SHL, RCR, RCL …

56. Logical Instructions
56
Mnemonics: AND, OR, XOR, TEST, SHR, SHL, RCR, RCL …

57. String Manipulation Instructions
57
String : Sequence of bytes or words
8086 instruction set includes instruction for string movement, comparison, scan, load and
store.
REP instruction prefix : used to repeat execution of string instructions
String instructions end with Sor SBor SW. Srepresents
string, SBstring byte and SWstring word.
Offset or effective address of the source operand is stored in SIregister and that of the
destination operand is stored in DIregister.
Depending on the status of DF, SIand DIregisters are automatically updated.
DF = 0 SI and DI are incremented by 1 for byte and 2 for word.
DF = 1 SI and DI are decremented by 1 for byte and 2 for word.

58. String Manipulation Instructions
58
Mnemonics: REP, MOVS, CMPS, SCAS, LODS, STOS
REP
REPZ/ REPE
(Repeat CMPS or SCAS
untilZF = 0)
REPNZ/ REPNE
(Repeat CMPS or SCAS
untilZF = 1)
While CX 0 and ZF = 1, repeatexecution
of string instruction and
(CX) (CX) –1
While CX 0 and ZF = 0, repeatexecution
of string instruction and
(CX) (CX) -1

59. String Manipulation Instructions
59
Mnemonics: REP, MOVS, CMPS, SCAS, LODS, STOS
MOVS
MOVSB
MOVSW
MA = (DS) x 16
10+ (SI)
MA
E= (ES) x 16
10+ (DI)
(MA
E) (MA)
If DF = 0, then (DI) (DI)+ 1; (SI)(SI) + 1
If DF = 1, then (DI) (DI)-1; (SI)(SI) -1
MA = (DS) x 16
10+ (SI)
MA
E= (ES) x 16
10+ (DI)
(MA
E; MA
E+ 1) (MA; MA + 1)
If DF = 0, then (DI) (DI)+ 2; (SI)(SI) + 2
If DF = 1, then (DI) (DI)-2; (SI)(SI) -2

60. String Manipulation Instructions
60
Mnemonics: REP, MOVS, CMPS, SCAS, LODS, STOS
CMPS
CMPSB
CMPSW
MA = (DS) x 16
10+ (SI)
MA
E= (ES) x 16
10+ (DI)
Modifyflags (MA) -(MA
E)
If (MA) > (MA
E), then CF = 0; ZF = 0; SF = 0
If (MA) < (MA
E), then CF = 1; ZF = 0; SF = 1
If (MA) = (MA
E), then CF = 0; ZF = 1; SF = 0
For byte operation
If DF = 0, then (DI) (DI)+ 1; (SI)(SI) + 1
If DF = 1, then (DI) (DI)-1; (SI)(SI) -1
For word operation
If DF = 0, then (DI) (DI)+ 2; (SI)(SI) + 2
If DF = 1, then (DI) (DI)-2; (SI)(SI) -2
Compare two string byte or string word

61. String Manipulation Instructions
61
Mnemonics: REP, MOVS, CMPS, SCAS, LODS, STOS
SCAS
SCASB
SCASW
MA
E= (ES) x 16
10+ (DI)
Modifyflags (AL) -(MA
E)
If (AL) > (MA
E), then CF = 0; ZF = 0; SF = 0
If (AL) < (MA
E), then CF = 1; ZF = 0; SF = 1
If (AL) = (MA
E), then CF = 0; ZF = 1; SF = 0
If DF = 0, then (DI) (DI)+ 1
If DF = 1, then (DI) (DI)–1
MA
E= (ES) x 16
10+ (DI)
Modifyflags (AL) -(MA
E)
If (AX) > (MA
E; MA
E+ 1), then CF = 0; ZF = 0; SF = 0
If (AX) < (MA
E; MA
E+ 1), then CF = 1; ZF = 0; SF = 1
If (AX) = (MA
E; MA
E+ 1), then CF = 0; ZF = 1; SF = 0
If DF = 0, then (DI) (DI)+ 2
If DF = 1, then (DI) (DI)–2
Scan (compare) a string byte or word with accumulator

62. String Manipulation Instructions
62
Mnemonics: REP, MOVS, CMPS, SCAS, LODS, STOS
LODS
LODSB
LODSW
MA = (DS) x 16
10+ (SI)
(AL)(MA)
If DF = 0, then (SI) (SI)+ 1
If DF = 1, then (SI) (SI)–1
MA = (DS) x 16
10+ (SI)
(AX)(MA ; MA + 1)
If DF = 0, then (SI) (SI)+ 2
If DF = 1, then (SI) (SI)–2
Load string byte in to AL or string word in to AX

63. String Manipulation Instructions
63
Mnemonics: REP, MOVS, CMPS, SCAS, LODS, STOS
STOS
STOSB
STOSW
MA
E= (ES) x 16
10+ (DI)
(MA
E)(AL)
If DF = 0, then (DI) (DI)+ 1
If DF = 1, then (DI) (DI)–1
MA
E= (ES) x 16
10+ (DI)
(MA
E; MA
E+ 1 )(AX)
If DF = 0, then (DI) (DI)+ 2
If DF = 1, then (DI) (DI)–2
Store byte from AL or word from AX in to string

64. Mnemonics Explanation
STC Set CF 1
CLC Clear CF 0
CMC Complement carry CF CF
/
STD Set direction flag DF 1
CLD Clear direction flag DF 0
STI Set interrupt enable flag IF 1
CLI Clear interrupt enable flag IF 0
NOP No operation
HLT Haltafter interrupt is set
WAIT Wait for TEST pin active
ESC opcode
mem/ reg
Used to pass instruction to a coprocessor which shares the
address and data bus with the 8086
LOCK Lock bus during next instruction
Processor Control Instructions
64

65. Control Transfer Instructions
65
Transfer the control to a specific destination or target instruction
Do not affect flags
Mnemonics Explanation
CALL reg/ mem/ disp16 Call subroutine
RET Return fromsubroutine
JMPreg/ mem/ disp8/
disp16
Unconditionaljump
8086 Unconditional transfers

66. Control Transfer Instructions
66
8086 signed conditional
branch instructions
8086 unsigned conditional branch
instructions
Checks flags
If conditions are true, the program control is transferred to the
new memory location in the same segment by modifying the
content of IP

67. Control Transfer Instructions
67
Name Alternate name
JE disp8
Jump if equal
JZ disp8
Jump if result is 0
JNE disp8
Jump if not equal
JNZ disp8
Jump if not zero
JG disp8
Jump if greater
JNLE disp8
Jump if not less or
equal
JGE disp8
Jump if greater than
or equal
JNL disp8
Jump if not less
JL disp8
Jump if less than
JNGE disp8
Jump if not greater
than or equal
JLE disp8
Jump if less than or
equal
JNGdisp8
Jump if not greater
8086 signed conditional
branch instructions
8086 unsigned conditional branch
instructions
Name Alternate name
JE disp8
Jump if equal
JZ disp8
Jump if result is 0
JNE disp8
Jump if not equal
JNZ disp8
Jump if not zero
JA disp8
Jump if above
JNBE disp8
Jump if not below or
equal
JAE disp8
Jump if above or
equal
JNB disp8
Jump if not below
JB disp8
Jump if below
JNAE disp8
Jump if not above or
equal
JBE disp8
Jump if below or
equal
JNAdisp8
Jump if not above

68. Control Transfer Instructions
68
Mnemonics Explanation
JCdisp8 Jump if CF= 1
JNC disp8 Jump if CF = 0
JP disp8 Jump if PF = 1
JNP disp8 Jump if PF =0
JO disp8 Jump ifOF = 1
JNO disp8 Jump if OF = 0
JS disp8 Jump if SF = 1
JNS disp8 Jump if SF = 0
JZ disp8 Jump if resultis zero, i.e, Z = 1
JNZ disp8 Jump if result is not zero, i.e, Z = 1
8086 conditional branch instructions affecting individual flags

69. Memory mapping vs. I/O mapping
69

70. 8086
70

71. Addressing Modes
71
Everyinstructionofaprogramhastooperateonadata.
Thedifferentwaysinwhichasourceoperandisdenotedinaninstruction
areknownasaddressingmodes.

72. Register Addressing Modes
72
Theinstructionwillspecifythenameoftheregisterwhichholdsthedatato
beoperatedbytheinstruction.
Example:
MOVCL,DH
Thecontentof8-bitregisterDHismovedtoanother8-bitregisterCL
(CL)(DH)

73. Immediate Addressing
73
Inimmediateaddressingmode,an8-bitor16-bitdataisspecifiedaspartofthe
instruction
Example:
MOVDL,08H
The8-bitdata(08
H)givenintheinstructionismovedtoDL
(DL)08
H
MOVAX,0A9FH
The16-bitdata(0A9F
H)givenintheinstructionismovedtoAXregister
(AX)0A9F
H

74. Addressing Modes : Memory Access
75

75. Direct Addressing
77
Here,theeffectiveaddressofthememory locationatwhichthedataoperandis
storedisgivenintheinstruction.
Theeffectiveaddressisjusta16-bitnumber writtendirectlyintheinstruction.
Example:
MOV BX,[1354H]
MOV BL,[0400H]
Thesquarebracketsaroundthe1354
Hdenotesthecontentsofthememorylocation.
Whenexecuted,thisinstructionwillcopythecontentsofthememory locationinto
BXregister.
Thisaddressingmodeiscalleddirectbecausethedisplacementoftheoperandfrom
thesegmentbaseisspecifieddirectlyintheinstruction.

76. Register Indirect Addressing
78
InRegisterindirectaddressing,nameoftheregisterwhichholdstheeffectiveaddress
(EA)willbespecifiedintheinstruction.
RegistersusedtoholdEAareanyofthefollowingregisters:BX,BP,DIandSI.
ContentoftheDSregisterisusedforbaseaddresscalculation.
Example:MOVCX,[BX]
Operations:
EA=(BX)
BA=(DS)x16
10
MA=BA+EA
(CX)(MA)or,
(CL)(MA)
(CH)(MA+1)
Note:Register/memory
enclosedinbracketsreferto
contentofregister/memory

77. Based Addressing
79
InBasedAddressing,BXorBPisusedtoholdthebasevalueforeffectiveaddressandasigned8-bitor
unsigned16-bitdisplacementwillbespecifiedintheinstruction.
Incaseof8-bitdisplacement,itissignextendedto16-bitbeforeaddingtothebasevalue.
WhenBXholdsthebasevalueofEA,20-bitphysicaladdressiscalculatedfromBXandDS.
WhenBPholdsthebasevalueofEA,BPandSSisused.
Example:
MOVAX,[BX+08H]
Operations:
0008
H08
H(Signextended)
EA=(BX)+0008
H
BA=(DS)x16
10
MA=BA+EA
(AX)(MA) or,
(AL)(MA), (AH)(MA+1)

78. Indexed Addressing
80
SIorDIregisterisusedtoholdanindexvalueformemory dataandasigned8-bitorunsigned16-bit
displacementwillbespecifiedintheinstruction.
DisplacementisaddedtotheindexvalueinSIorDIregistertoobtaintheEA.
Incaseof8-bitdisplacement,itissignextendedto16-bitbeforeaddingtothebasevalue.
Example:
MOVCX,[SI+0A2H]
Operations:
FFA2
HA2
H(Signextended)
EA=(SI)+FFA2
H
BA=(DS)x16
10
MA=BA+EA
(CX)(MA)or,
(CL)(MA)
(CH)(MA+1)

79. Based Indexed Addressing
81
InBasedIndexAddressing,theeffectiveaddressiscomputed fromthesumofabase
register(BXorBP),anindexregister(SIorDI)andadisplacement.
Example:
MOVDX,[BX+SI+0AH]
Operations:
000A
H0A
H(Signextended)
EA=(BX)+(SI)+000A
H
BA=(DS)x16
10
MA=BA+EA
(DX)(MA)or,
(DL)(MA),(DH)(MA+1)

80. String Addressing
82
Employedinstringoperationstooperateonstringdata.
Theeffectiveaddress(EA)ofsourcedataisstoredinSIregisterandtheEAofdestinationisstoredin
DIregister.
SegmentregisterforcalculatingbaseaddressofsourcedataisDSandthatofthedestinationdataisES
Example:MOVSBYTE
Operations:
Calculationofsourcememorylocation:
EA=(SI) BA=(DS)x16
10 MA=BA+EA
Calculationofdestinationmemorylocation:
EA
E=(DI) BA
E=(ES)x16
10MA
E=BA
E+EA
E
(MAE)(MA)
IfDF=1,then(SI)(SI)–1and(DI)=(DI)-1
IfDF=0,then(SI)(SI)+1and(DI)=(DI)+1

81. I/O Port Addressing
TheseaddressingmodesareusedtoaccessdatafromstandardI/Omappeddevicesorports.
Indirectportaddressingmode,an8-bitportaddressisdirectlyspecifiedintheinstruction.
Example:INAL,[09H]
Operations:PORT
addr=09
H
(AL)(PORT) Contentofportwithaddress09
HismovedtoALregister
Inindirectportaddressingmode,theinstructionwillspecifythenameoftheregisterwhich
holdstheportaddress.In8086,the16-bitportaddressisstoredintheDXregister.
Example:OUT[DX],AX
Operations:PORT
addr=(DX)
(PORT)(AX)
ContentofAXismovedtoportwhoseaddressisspecifiedbyDXregister.
83

82. Relative Addressing
84
Inthisaddressingmode,theeffectiveaddressofaprograminstructionisspecifiedrelative
toInstructionPointer(IP)byan8-bitsigneddisplacement.
Example:JZ0AH
Operations:
000A
H0A
H (signextend)
IfZF=1,then
EA=(IP)+000A
H
BA=(CS)x16
10
MA=BA+EA
IfZF=1,thentheprogramcontroljumpstonewaddresscalculatedabove.
IfZF=0,thennextinstructionoftheprogramisexecuted.

83. Implied Addressing
85
Instructionsusingthismodehavenooperands.Theinstructionitselfwillspecifythe
datatobeoperatedbytheinstruction.
Example:CLC
Thisclearsthecarryflagtozero.