a verilog presentation for deep concept understa

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1. I-CHIP Verilog HDL

2. Hardware Description Language With the advent of SSI, MSI, LSI and now VLSI, designers could put thousands of gates on a single chip. Due to circuits becoming very complicated, designs could no longer be done by hand, and the need came to automate these design processes. Therefore came the advent of Hardware Description Languages (HDLs, like VHDL, Verilog, System Verilog) and Electronic Design Automation (EDA) tools like Xilinx, which generate corresponding circuits to the written code. It resembles an ordinary computer programming language, such as C, but is specifically oriented to describing hardware structures and the behavior of logic circuits. By describing designs in HDLs, functional verification of the design can be done early in the design cycle. Facilitates prototyping digital hardware before fabrication.

3. Verilog HDL Verification + Logic = Verilog Hardware modeling and verification of digital circuit elements. It has many versions, but Verilog-2001 or Verilog-2005 are most commonly used. Two parts to a creating a digital element in HDL: Design of a digital circuit in HDL Verification of the circuit: to provide it different sets of inputs and make sure it behaves as intended. System Verilog: superset of Verilog, having made enhancements suited for verification purposes.

4. Functional Verification and Logic Design The spec is translated to HDL code by the design team. The verification plan is carried out by setting out test cases to be verified. Done parallelly, hand-in-hand. Chip Design Life Cycle

5. Circuit Design The HDL code is mapped to actual hardware components according to the target hardware (FPGA, ASIC). !! The code for your design must always be synthesizable have hardware corresponding to it. Feasible to practically implement. Timing constraints are verified. Chip Design Life Cycle

6. Verilog HDL HDL is meant to describe the behavior or functionality of hardware. It is not a software language. Error free code is not guaranteed to be synthesizable to the correct hardware. Hardware Parallelism is achieved, whereas software languages execute code sequentially.

7. Verilog HDL: Design and Testbench

8. Verilog Syntax

9. Verilog: Module Black-box, or basic hardware that provides some functionality. The ports of a module are declared as input, output, or inout . Each line is terminated. Verilog is a CASE SENSITIVE LANGUAGE Defining one module within another module is illegal. Nesting of comments is illegal.

10. Verilog: Module module modulename (port list); port list declarations; internal signal declarations; behaviour ; //single line comments /* double line comments */ endmodule

11. Verilog: Variable/Module Names Variable names consist of alphanumeric characters, _ and $. They must begin with an alphabet or _ They should be descriptive No keyword should be used as a variable name. $display 2scomp $decoder and, or, not

12. Verilog: Values Verilog is a 4 valued language Logic 1 Logic 0 X – unknown state Z – high impedance state

13. Verilog: Specifying Numbers <size>’<base><number> size is specified in decimal If unspecified, default value is 32-bits Number is comprised of values from 0-9, a-f, x, or z base – legal values include b or B, h or H, o or O, d or D Default value is decimal

14. Verilog: Specifying Numbers <size>’<base><number> Signed number specification Negative numbers are stored as 2’s complement and the negative sign must be specified before the size. Placing _ in numbers improves readability ? Is equivalent to z

15. Verilog: Data Types (Reg and Net) Net Represent connections between hardware components. Nets must be continuously driven by the devices they are connected to Default: one bit value, default value is z Can be assigned only through continuous assignments. wire, wand, wor , tri, triand , trior , trireg wire varname ; wire [size-1:0] varname ;

16. Verilog: Data Types (Reg and Net) Reg Used to store a value with respect to the Verilog language. Retain a value until a new value is assigned to them. Assigned in only procedural blocks ( procedural assignments ). Default value is x. integer varname ; reg [size-1:0] varname ; 128 34 87 1 32

17. Verilog: Data Types (Reg and Net) Reg integer – used to store a 32-bit value, commonly used in loops. real time – used to store the simulation time

18. Verilog: Vectors By default, reg and net values are 1-bit. reg/wire [size-1:0] varname ; //Little Endian Notation reg [7:0]A; A[6:4] wrong A[4:6] A = 8’10101010 reg/wire [0:size-1] varname ; //Big Endian Notation reg [0:7]B; B[1:3] = 3’b111 B[3:1] xxx wrong 7 6 5 4 3 2 1 1 1 1 1 1 1 1 2 3 4 5 6 7 1 1 1

19. Verilog: Vectors Part Select Part select of vectors must be in the order the vector is declared. 7 6 5 4 3 2 1 1 2 3 4 5 6 7

20. Verilog: Vector Variable Part Select varname [ starting_bit +:width] increment from starting bit varname [ starting_bit -:width] decrement from starting bit

21. Verilog: Vectors reg/wire [N-1:0]x; one N-bit variable Can part select Can directly assign N-bit value in one assignment x = 8’b0110_1010 Reg/wire x[N-1:0]; N 1-bit variable Cannot part select Bits can be accessed or assigned one at a time. x[5] = 1’b0;

22. Verilog: Vectors reg/wire [width-1:0] varname [depth-1:0] integer varname [N-1:0] reg [3:0] A[7:0] A[0] = 4’1111;

23. Verilog: Strings Can be assigned to reg values Each character occupies 8 bits/1 byte

24. Gate Level Modeling Use of primitives and, nand , or, nor, xor , xnor , buf , not bufif0, bufif1, notif0, notif1

25. Gate Level Modeling

26. Gate Level Modeling

27. Gate Level Modeling Use of primitives and, nand , or, nor, xor , xnor , buf , not bufif0, bufif1, notif0, notif1

28. Dataflow Modeling Describes functionality of a device based on the dataflow and the transformations(arithmetic or Boolean expressions) carried out on the data from input side to output side.

29. Verilog: Variable Assignments 2 types of assignments Continuous Assignments: for wire/net, infer combinational logic Procedural Assignments: for reg, infer combinational or sequential logic Continuous Assignments: assign varname = < boolean /arithmetic expression>

30. Verilog: Variable Assignments 2 types of assignments Continuous Assignments: for wire/net Procedural Assignments: for reg Procedural Blocks: initial and always initial begin //assignments, behavior end always@ ( negedge clk ) begin //behavior end

31. Verilog: Types of Procedural Assignments Blocking Assignments U sed for implementation of combinational logic in procedural blocks. Blocking assignments are executed sequentially, one after another. They do not block execution of other nonblocking assignments in a parallel block.

32. Verilog: Types of Procedural Assignments 2. Nonblocking Assignments (<=) U sed for implementation of sequential logic in procedural blocks. They are used to simulate the hardware parallelism. First, all of the LHS values are calculated and saved at a temporary location. Then, at the end of the current time-step, they are assigned at once to the RHS.

33. Verilog: Types of Procedural Assignments 2. Nonblocking Assignments

34. Verilog: To print a value

35. Verilog: System Task - To print a value Use system tasks $display and $monitor to print values. $display is written in a procedural block, and executed when encountered only once. $monitor executes and displays values each time one of its arguments changes in value Only one monitor must be used. If more than one monitor are used in a module, the last monitor will be the one that is active. The others will be overwritten. $display (“<format specifiers>”, var1, var2…); $monitor (“<format specifiers>”, var1, var2…);

36. Verilog: Module Instantiations A module can be instantiated within another for use. There are 2 types of instantiations Named/Explicit Instantiations Positional Instantiations module dff (input clk , d, output q); wire a; //working endmodule module shiftregister (); Reg clock, datain ; Dff name(. clk (clock), .d( datain ) endmodule

37. Verilog: Module Instantiations A module can be instantiated within another for use. There are 2 types of instantiations Named/Explicit Instantiations Positional Instantiations

38. Verilog: Module Instantiations Module instantiations create a hierarchy in the design. Signals local to each module cannot be accessed directly from their top module, but instead through a hierarchical referencing dot (.) operator. Use $display(“%m”) to get the location in hierarchy

39. Verilog: Operators

40. Verilog: Arithmetic Operators Result will evaluate to x if either of the operands has an x value in any of its bits.

41. Verilog: Logical Operators Used for logical expressions. A nonzero value is regarded as true, a zero value as false.

42. Verilog: Bitwise Operators

43. Verilog: Reduction Operators Perform the logical operation on all the individual bits to yield a one-bit result. Useful for parity checkers/generators where all bits must be xor / xnor’d Useful for creating multi-input gates.

44. Verilog: Shift Operators Shift the vector Useful for multiplication or division by powers of 2, or shift and add operations.

45. Verilog: Concatenation { var1, var2… } Concatenates the arguments into a single number. Can take only sized arguments.

46. Verilog: Replication {m{n}} Replicates the n argument, m-times.

47. Verilog: Ternary Operator ?: Exp ? True : false; //multiplexer assign out = sel?d1:d0; 4:1 out = sel1? Sel0?d3:d2 : sel0?d1:d0; Out = exp? 4’b1101 : 4’b1011 out=4’b1xx1; If the exp evaluates to x, then both true and false expressions are compared bit by bit. The bit is returned where the bits match X is returned where the bits are different.

48. Verilog: if, else if ( exp ) begin //code end else if (exp) begin //code end else begin //code end Always in a procedural block. Always, initial

49. Verilog: case statement The alternatives are matched with the expression one by one, bit-by-bit, comparing 0, 1, x, and z. The expression that matches is then executed.

50. Verilog: casex and casez statement In casex , the x and z are treated as don’t cares In casez , the z are treated as don’t cares

51. Verilog: While Loop Run continuously until the expression becomes false.

52. Verilog: Repeat Loop Run a fixed number of times The argument cannot be a general expression, it must be a number. Useful for defining clock signals.

53. Verilog: Forever Loop Runs continuously, forever, with no end. Always defined in procedural blocks. They must be terminated by a $finish statement in a parallel block.

54. Verilog: For Loop Consist of An initial condition A loop condition An assignment to change the value of the loop variable Loops unroll into their corresponding set of assignments.

55. Verilog: Latch-based Designs Leaving if..else statements incomplete i.e. not covering all possible scenarios leads to inadvertent synthesis of sequential logic where combinational logic was intended. It leads to synthesis of latch based designs to store the previous value in the scenarios that have been missed, leading to a mismatch from the intended combinational design. To prevent this, ensure that an else(for if/else) or default(case) has been defined. module mux (input sel , d0, d1, output out); always @( sel , d0, d1) begin if ( sel ) out=d1; else out=d0; end endmodule module dlatch (input en , d, output q); always @( en , d) begin if ( en ) q=d; endmodule

56. Verilog: Reset Syntax for Sequential Ckts . 2 types of resets: Synchronous & Asynchronous Synchronous reset is sampled at the clock edge Asynchronous reset does not have any dependency on a synchronizing signal(clock) and it resets the circuit as soon as asserted. Further, we have 2 more types of resets: Active-Low: A logic 0 on the reset line is used to reset the circuit. The line is held high in idle state. Active-High: A logic 1 on the reset line is used to reset the circuit. The line is held low in idle state.

57. Verilog: Reset Syntax always @( posedge clk or negedge rst ) begin if (! rst ) //reset the circuit else //functionality end always @( posedge clk or posedge rst ) begin if ( rst ) //reset the circuit else //functionality end always @( posedge clk ) begin if ( rst ) //reset the circuit else //functionality end always @( posedge clk ) begin if (! rst ) //reset the circuit else //functionality end

58. Verilog: Parameters Constants defined in a module. Enhance Reusability of the code by allowing overwriting of parameters of modules according to requirement. In positional overwriting of parameters, the parameters will be assigned values in the order defined in module. If not overwritten, the default value of the parameter is used. module_name #(parameter1, parameter2…) varname (<port connections) Named overwriting of parameters module_name #(.NAME1(parameter1), .NAME2(parameter2)…) varname (<port connections) Overwriting using defparam

59. Verilog: Local Parameters Constants defined in a module which are local to that module. They cannot be overwritten by instantiation. localparam var1 = < val >, var2 = < val >…; Especially useful for encoding state machines, where we do not want the state to change by overwriting during instantiations.

60. Verilog: Inter & Intra-Assignment Delay Inter-Assignment delay: delay between the various assignments. The statement is evaluated and executed at the time it is scheduled to be. Intra-Assignment delay: delay within an assignment The RHS values are first evaluated and stored at a location. The assignment is made after the delay time has elapsed.

61. Verilog: $monitor, $display, $strobe $display Executes once to print the values. Executes in the active region of event queue, and thus cannot print values after non-blocking assignments in that time-step. $monitor Remains active throughout the lifetime of the program, and prints values each time an update is made to its arguments. Executes in the postponed region of event-queue and therefore can print values updated after non-blocking assignments $strobe Executes once to print the values. Executes in the postponed region of event-queue and therefore can print values updated after non-blocking assignments

62. Thank You