analog cmos vlsi unit 5 ch 2 presentation

analog cmos vlsi design

1. Unit 5 part 2 oscillators

2. Oscillators are integral part of many electronic systems Applications : clock generation, cellular telephones, quartz watches, audio and video systems, radio TV and other communication devices, computers, metal detectors, inverters, ultrasonic etc A simple oscillator produces periodic output,usually in voltage As such, the circuit has no input, but it has sustain output indefenitely

3. General considerations (feedback system and barkhausen criteria) Consider unity gain feedback circuit as shown in fig H(s) is the open loop gain If amplifier  produces high phase shift at high frequency Then overall feedback becomes positive , then oscillation occurs. If then closed loop gain approaches infinity at Under this condition, the circuit amplifies its own noise components at indefinitely.

4. In fig a , the circuit amplifies its own noise components at In fig b , the noise components at produces a total gain of unity & 180 degree phase shift returning to the subtractor as a – ve replica of the input In fig c , the input & feedback signals give a larger difference. Thus circuit continues to “regenerate” allowing the component at to grow.

5. For the oscillation to begin, a loop gain of unity or greater is necessary.

6. It exhibits a frequency- dependent 180 degree phase shift In fig b & c, the open loop amplifier in the stages with proper polarities to provide a total 360 degree phase shift Whereas that in the latter produces no phase shift

7. RING OSCILLATOR Fig 1: one pole feedback system in fig, it is seen that the open-loop circuit contains only one pole, thereby providing a maximum frequency dependent phase shift of 90◦ (at a frequency of infinity). Since the common-source stage exhibits a dc phase shift of 180◦ due to the signal inversion from the gate to the drain, the maximum total phase shift is 270◦. The loop therefore fails to sustain oscillation growth. Oscillation occurs if the circuit contains multiple stages and poles. Ring oscillator consists of number of gain stages in a loop, To arrive at actual implementation , we begin by attempting to make a single stage feedback circuit oscillate.

8. In fig 2: 2 pole feedback system  contain 2 poles appear in signal paths allowing frequency dependent 180 degree phase shift (90+90) fig 2: two pole feedback system unfortunately, It exhibits + ve feedback near 0 frequency ( because of signal inversion through each common source stage) As a result, it “ latches up” rather the oscillate. If VE rises VF falls M1 off Allowing VE to rise further until reaches Vdd VF drops to 0

9. To gain more insight into oscillation condition, Assume an ideal inverting stage inserted in the loop, Providing – ve f/b near 0 frequency & no latchup occurs as in the above fig. Note: contains 2 poles, at E & at F, 180degree phase shift At high frequency  loop gain vanishes Circuit  doesn’t satisfy barkhuasen criteria failing to ocsillate in fig.

10. In fig 3 stage ring oscillate If 3 stages are identical, the total phase shift reaches to - 135 degree This circuit will oscillate & example for ring oscillator To calculate min v/g gain in fig [neglecting the effect of gate – drain overlap capacitance] Denote transfer function of each stage by

11. ------  1 ----- 2 From 1 and 2 Since each stage contributes a frequency dependent phase shift of 60 degree & low frequency inversion The waveform at each node is 240 degree or 120 degree in fig

12. In 3 stage ring oscillator From barkhausen criteria Consider the first model o f the oscillator by a linear f/b system The f/b system is + ve because H(S) is already includes the – ve polarity resulting from three inversion in the s/g path. The closed loop transfer function is

13. The denominator of the above equation can be expanded

14. It illustrates the locations of the poles for different v alues of A0 Revealing that for A0> 2, the 2 complex poles exhibit a + ve part & give rise to a growing sinusoidal Neglecting the effect of S1 The output waveform as

15. LC OSCILLATORS In above fig, an inductor L1  placed in parallel with the capacitor C1 which resonates the frequency At this frequency , the important of inductor are equal & opposite obtaining infinite impedance Ex: the series resistance of metal wire can be modeled in fig b

16. The infinite quality factor Q of the inductor is For this circuit, the equivalent impedance is given by And

17. Consider series combination as shown in fig a In a narrow frequency range, we can convert the circuit, to the parallel configuration fig b

18. The transformation allows the conversion illustrating in fig Cp = C1 Equivalence of course break down  as w departs substantially from the resonance frequency

19. The insight gain from parallel combination is at The tank reduces to simple resistor The phase difference b/w voltage & current of the tank drops to 0 In fig a : plotting the magnitude of tank impedance v/s frequency The behavior In fig b : phase impedance is + ve for - ve for This proves studying of LC OSCILLATOR

20. In fig: consider a tuned gain stage, where LC tank operates as a load At resonance, Voltage gain = The circuit oscillates if the output is connected to i/p as fig b But the frequency dependent phase shift of the tank never reaches 180 degree Therefore circuit doesn’t oscillates.

21. Her the stage is biased at drain at drain current I1 If series resistance Lp  small Vout DC level  close to Vdd Suppose Vout  vary if a small sinusoidal voltage is applied to i/p. Vout will be inverted sinusoidal If avg value of Vout  deviates from Vdd The inductor series resistance  carries great avg current than I1 Peak o/p level exceeds the supply voltage

22. This configuration does not latchup because its low-frequency gain is very low. At resonance, Total phase shift around the loop is 0 Because each stage contributes 0 frequency- dependent phase shift . If

23. Redraw as in fig a, b, c. The drain current of M1 & M2 and the output swings depend on supply voltage Since the waveforms at X & Y are differential , The fig b, suggests that M1 & M2 can be converted to a differential pair as shown in fig c, where the total bias current is defined by Iss the oscillator of fig c, is constructed in fully differential form. The supply sensitivity of the circuit is nonzero even with perfect symmetry Because drain junction capacitances of M1& M2 vary with the supply voltage.

24. LC oscillator is realized w ith only 1 transistor in single path. Consider tuned gate stage, drain v/g cannot be applied to gate (because overall phase shift at resonate equal to 180 degree rather than 360 degree . In fig a: drain v/g is returned to the source rather than gate The circuit oscillates. Coupling of capacitance is done to avoid disturbing the bias point M1 Due to insufficient loop gain, fig a: circuit doesn’t oscillate.

25. To prove this, consider f/b system Applying i/p current in fig b, & neglecting transistor parasitics to obtain the closed loop gain as

26. In fig a: colpitt’s oscillator, approximating M1 by single v/g dependent source Fig b: constructed equivalent circuit since current through the parallel combination of

27. The total current through C1 is And obtaining the current through c2 at the output nodes is Eq 14.40 reduces to ( Lps || Rp ) if C1=0 The circuit oscillates if closed loop transfer function goes to infinity at an imaginary value of s,

28. As a result, both the real & imaginary parts of the denominator drops to 0 at this frequency

29. Oscillators develops based on f/b system. Alternating point  oscillation employs – ve resistance First consider a simple tank that is stimulated by current impulse in fig a Tank responds in a decaying oscillatory behavior Suppose a resistor equal to – Rp is placed parallel with Rp Experiment is repeated as shown in fig b Since the tank oscillates indefinitely. Thus if 1 port circuit exhibiting a – ve resistance is placed parallel with a tank in fig c. The combination may oscillate Such topology is called one port oscillator

30. To provide – ve resistance, consider the f/b multiplier or divider the i/p & o/p impedance of circuit by a factor equal to 1 plus the loop gain. Thus, if the loop gain is sufficiently – ve , a – ve resistance is achieved

31. Fig a  implement the f/b by a common gate stage & add current source b to provide bias current of M2 From fig b

32. METHOD 1: With a – ve resistance available, To construct an oscillator in fig, here Rp denotes the equivalent parallel resistance of the tank, & for oscillator build-up If the small signal presented by M1 &M2 to the tank is less – ve than – Rp The circuit experiences large swings.

33. If drain current M1 flows through a tank, Resulting vg is applied to the gate of M2 The topology of fig b obtained

34. Ignoring bias paths & merging the 2 tank into 1 Gross coupled pair provide a – ve resistance of – Rp b/w x & y to enable oscillation In fig, resistance = -2/g then Thus the circuit can be viewed as either a f/b system or a – ve resistance in parallel with lassy tank. This topology is called

35. Method 2:

36. Another method of creating – ve resistance, Consider topology depicted in fig where none of the nodes is grounded & C. L .M , Body effect and transistors capacitance are neglected. Since drain current of M1 = For s= jw , the impedance consists of – ve resistance In fig c, if inductor is placed b/w gate & drain of M1 the circuit oscillates

37. The 3 nodes in the circuit 1 can be AC grounded Resulting in 3 different topologies in fig In fig a  based on source follower whole input impedance contain – ve real part Fig b colpitts oscillator

38. Voltage controlled oscillator Most applications : oscillations must be ‘tunable’ There o/p frequency be a function of a control i/p v/g An ideal VCO is a circuit whose output is a linear function of its control v/g.

39. IMPORTANT PERFORMANCE PARAMETER OF VCO CENTER FREQUENCY : determined by environment in which VCO is used. Ex: clock generation n/w VCO  used to run at the clock rate as high as 10GHz TUNING RANGE : determined by 2 parameters 1)variation of VCO with temperature 2)center frequency of cmos oscillator may vary (by a factor of 2) also vary with temperature clock frequency vary by 1 or 2 order of magnitude depending on mode of operation. An important concern of VCO’s design is variation of o/p phase & frequency as a result of noise. For the given noise amplitude  noise in o/p frequency is proportional to Kvco

40. Kvco – increases v/g– decreases Oscillator  more noise Tuning linearity: the char of VCO’s exhibit non linearity Gain of Kvco  not constant Therefore we should minimize the variation of Kvco across tuning range. Actual oscillator char exhibit: High gain in middle of range Low gain at extreme

41. OUTPUT AMPLITUDE : to achieve large o/p oscillation amplitude Waveform  less sensitive to noise But amplitude trades with  power dissipation, Supply v/g, tuning range POWER DISSIPATION : like other analog circuits, oscillator suffers from trade offs b/w speed, PD & noise It drains 1 to 10 mW of power SUPPLY & CMR : oscillator are sensitive to noise specially if they are realize in single ended form. O/P SIGNAL PURITY : even if v/g constant The o/p waveform of VCO not perfectly periodic The electronic noise & supply noise in the oscillator leads to noise in o/p phase & frequency These effects are quantized by “jitter” & “phase noise”

42. TUNING IN RING OSCILLATOR: From ring oscillator, the oscillation frequency fosc of an N stage ring equals Td  denotes large signal delay of each stage. Thus to vary frequency, Td can be adjusted. Consider differential pair in fig Vcont  more + ve On resistance of m3 & m4  high Time constant o/p high Focs  low

43. If m3 & m4 remain in deep triode region The delay of circuit proportional to

44. In fig a, m5 operates in deep triode region Amplifier A1 applies – ve f/b to the gate of m5 In fig b: if m3 & m4 are identical to m5 Then Vx & Vy vary from Vdd to Vdd - Vref If process & temperature vary I1 & Iss  low A1 high Vx & Vy = Vref

45. Delay variation by positive feedback To arrive at another tuning technique  cross coupled transistor pair is used It exhibits a – ve resistance of -2/ gm

46. - ve resistance – Rn is placrd parallel with + ve resistance Rp An equivalent value is Which is more + ve if This idea can be applied to each stage of a ring oscillator as in the fig

47. Delay variation by interpolation

48. Another approach to tuning ring oscillator is based on interpolation Each stage consists of fast path and slow paths. Whose outputs are summed and gain are adjusted by Vcont in opposite direction. At one extreme of control v/g-  Only fast path is on, slow path is disabled in fig b- oscillation frequency  maximum In fig c, at other extreme Slow path is on & fast path is disabled oscillation frequency  minimum If Vcont lies b/w 2 extremes, Each path is partially on Total delay  sum of their delays

49. 2. TUNING LC OSCILLATOR

50. The oscillation frequency of LC topologies is equal to Here only inductor & capacitor varied to tune the frequency & other parameters It is difficult to vary the inductor, So change the tank capacitor. v/g dependent capacitors are called “ varactors ” In fig add varactor diodes to cross coupled LC oscillators To avoid forward biasing D1 & D2 Vcont must not exceed Vx or Vy

51. The circuit suffer from a trade offs b/w the output swings & tuning range. This effect appears in most oscillators. varactor diodes in cmos technology

52. In fig a, Anode  ground In fig b, both terminals floating For the circuit in fig 1: only the floating diode can be used. To increase the capacitance of the junction, areas are enlarged

53. Cn represents capacitance b/w the n-well & substrate To decrease the series resistance of structure The p+ region can be surrounded by n+ ring In single minimum p+ area has a small capacitance In fig b: many these units can be placed parallel.

54. VCO definition given by specifies the relationship b/w control voltage & output frequency. The dependence is “ memoryless ” Because change in Vcont  results change in But the output signal of VCO expressed as a function of time

55. Consider waveform The argument of the sinusoid is called “total phase” Ex: phase varies linearly with time. Exhibiting a slope equal to In fig 1: every time cross an integer multiply of In fig 2: consider 2 waveform Where Frequency can be defined as derivative of the phase with respect to time

56. Phase can be computed as This proves essential in the analysis of VCO’s & PLL If a VCO is placed in phase locked loop, Then 2 nd term in the above eq is important The term is called “excess phase” The excess phase is given by

57. Since the o/p frequency of VCO is given by The o/p waveform can be written as

58. The eq can be modified as Vout (t) expressed as a fourier series