The content is related to Analog electronics. The prEsentation contains ADC process, Sampling and holding, Quantizing and encoding, Flash ADC, Pipeline ADC etc.
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Language: en
Added: Jun 26, 2019
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ANALOG To DIGITAL CONVERTER (Analog CMOS Design) Presented by Shruti Shreya A2326418002 M.Tech VLSI Presented to Ms Shikha Bathla
Introduction An electronic integrated circuit which directly converts the continuous form of signal to discrete form. The input (analog) to this system can have any value in a range and are directly measured. But for output (digital) of an N-bit A/D converter, it should have only 2 N discrete values. ADC Provides a link between the analog world of transducers and the digital world of signal processing and data handling. ADC are used virtually everywhere where an analog signal has to be processed, stored, or transported in digital form. Some examples of ADC usage are digital voltmeters, cell phone, thermocouples, and digital oscilloscope.
ADC PROCESS Steps involved in the process of conversion are: Sampling and Holding Quantizing and Encoding Improvement of Accuracy in ADC Two important methods used for improving the accuracy in ADC are: Increasing the resolution By increasing the sampling rate.
ADC PROCESS
The time during which sample and hold circuit generates the sample of the input signal is called sampling time. The time duration of the circuit during which it holds the sampled value is called holding time. It is done to remove variations in input signal which can alter the conversion process and thereby increases the accuracy. Minimum sampling rate should be at least twice the highest data frequency of the analog signal. Sampling and Holding
Quantizing and Encoding Quantizing The process in which the reference signal is partitioned into several discrete quanta and then the input signal is matched with the correct quantum. Encoding Assigning a unique digital code to each quantum and after that the input signal is allocated with this digital code.
TYPES of ADC Successive Approximation ADC This converter compares the input signal with the output of an internal DAC at each successive step. It is the most expensive type . Uses an “code search” strategy. If V d <V A, comparator output goes high, Which is applied to SAR. Advantages Capable of high speed and reliable Medium accuracy compared to other ADC types Capable of outputting the binary number in serial (one bit at a time) format. Disadvantages The circuit is complex Speed limited to ~5Msps
Dual Slope ADC A dual-slope ADC (DS-ADC) integrates an unknown input voltage (VIN) for a fixed amount of time (TINT), then "de-integrates" (TDEINT) using a known reference voltage (VREF) for a variable amount of time. It have high accuracy but very slow in operation. Advantage Conversion result is insensitive to errors in the component values. High Accuracy, Low cost Disadvantage Long conversation time
Flash ADC It is the fastest ADC but very expensive. Typical conversion time is 100ns or less. Fundamental Components (For N bit Flash A/D) 2N-1 Comparators 2N Resistors Control Logic Advantages: Fastest type of ADC because the conversion is performed simultaneously Construction is simple and easier to design. Disadvantages: It is not suitable for higher number of bits Number of comparators required
Pipeline ADC The most popular ADC architecture for sampling rates from a few mega samples per second ( Msps ) up to 100Msps+. Resolutions range from eight bits at the faster sample rates up to 16 bits at the lower rates. These resolutions and sampling rates cover a wide range of applications such as CCD imaging, ultrasonic medical imaging, digital receivers, base stations, digital video (for example, HDTV), xDSL , etc. Pipelined ADCs of various forms have improved greatly in speed, resolution, dynamic performance, and low power in recent years.
The data is transferred in a pipeline fashion: when the data is sent to the second stage, another sampled data is fed to the first stage, The result is a latency delay equal to the number of stages. The analog stage is formed of a 2 bits flash ADC, a 2 bits DAC and a adder/gain stage. The output is called the residue and is sent to the next stage. Each stage is responsible for quantizing Nj -bits, j = 1, 2,..., K ( Nj < N) and generating an amplified residue for further quantization. Each stage’s operation is completed in two phases (one clock cycle): the first for sampling and quantizing, and the second for residue amplification. The amplification of the residue is justified for increasing its dynamic range to the full scale range of the converter, thus facilitating the implementation of subsequent quantizers .
Principal of Operation The input voltage is sampled by the first stage. It is then quantized to generate the MSBs. These bits are used to reconstruct a voltage (using a DAC and reference voltages) that is subtracted from the input voltage generating the residue voltage. This residue is then amplified (and held) to the full scale range of the converter and sampled by the second stage. This process repeats itself between the first and second stages until the LSB is generated. At this point a full digital output is ready, while the converter is sampling the next input sample.