Analog vs digital integrated circuit design

Analog vs digital ic design

1. Integrated Circuit (IC) Design Process Analog IC Design vs. Digital IC Design Processes

2. Outline Background Integrated Circuit CMOS Technology Technology Scaling Design Process & Criteria Analog IC Design Flow Digital IC Design Flow How are microchips made? 2

3. What is an IC? 3 An integrated circuit (IC), also called  microelectronic circuit,  microchip , or  chip , an assembly of electronic components, fabricated as a single unit, in which miniaturized active devices, passive devices and their interconnections are built up on a thin substrate of  semiconductor  material (typically silicon). The individual circuit components are generally microscopic in size (in microns or nm). Source: Britannica

4. Semiconductors – at the heart of the technology wave 4

5. CMOS Technology 5 Manufacturing an integrated circuit is based on CMOS technology. CMOS stands for “ Complementary Metal Oxide Semiconductor ”.  Source: PIIC

6. Technology Scaling 6 Source: EE Times Decreasing transistor’s gate length (L), allows more transistors to fit into the chip.

7. Design Criteria 7 Performance Power Area Denser integration Longer battery life Higher clock Frequencies Source: Cadence

8. Design Process 8 Design: specify design parameters, target values, etc Implementation: refine the design through all phases Verification: verify the correctness of design and implementation

9. Analog IC Design Flow (Full-Custom) 9 Design Specifications Circuit Level Design Circuit Architecture Layout Fabrication SPICE Simulation Design Rule Check, Layout vs. Schematic Pre-layout Simulation Post-layout Simulation

10. Full custom design of a two-stage op amp 10

11. 1. Design Specifications 11 Phase Margin > 60 ° Gain 45dB Slew Rate > 10uV/s CMRR 45dB

12. 2. Circuit Architecture 12 Current Reference Differential Amplifier Common-Source Amplifier

13. 3. Circuit Level Design 13

14. 4. Pre-layout Simulation 14 Target Specs Pre-Sim Results Phase Margin > 45 ° 55.9 ° Gain 45dB 48.2dB Slew Rate > 10uV/s 12.1uV/s CMRR 45dB 48.2dB

15. 5. Layout 15

16. 6. Post-layout Verification and Simulation 16 DRC LVS LPE

17. 6. Post-layout Verification and Simulation 17 Target Specs Pre-Sim Results Post-Sim Results Phase Margin > 45 ° 55.9 ° 54.3 ° Gain 45dB 48.2dB 47.5dB Slew Rate > 10uV/s 12.1uV/s 11.8uV/s CMRR 45dB 48.2dB 47.3dB Ready for Fabrication!!!

18. Digital IC Design Flow (Cell-based) 18 Design Specifications Logic Synthesis Front End Physical Design Back End RTL Coding & Functional Verification Logic Verification Physical Verification & Signoff Fabrication always @( A , B or C ) begin S = A ^ B ^ C ; CO = ( A & B )|( A & C )|( B & C ) end

19. Design Specs and RTL Coding 19 Architecture: Key Algorithms (filtering, for example) Amount of on-chip Memories, sizes, clock frequency, etc RTL: Register Transfer Level Verilog, VHDL, SystemVerilog : an executable spec for the chip, amounting to over a million lines of code Lots of simulations to verify the spec (literally billions of cycles) Timing constraints, clock definitions, etc

20. Logic Synthesis 20 Logic Synthesis: converts the RTL to logic gates (NAND-NORs, NOTs, Registers) Many discrete optimization techniques used here: boolean minimization, static timing analysis, state equivalence, etc , Key technique: how do you prove that two logic equations are equivalent? process begin wait until not CLOCK'stable and CLOCK=1; if(ENABLE='1') then TOGGLE<= not TOGGLE; end if; end process;

21. Functional Verification 21 Verify that the logic gates will do what you want, when you want them to (Simulation, Timing Analysis, Testbench Generation) 1 1 1

22. Physical Design (Layout) 22 Floorplanning , Placement, and Routing Floorplan Placement Routing

23. Verification 23 Make sure "what you see is what you get" Compare what you designed to what's in your layout Layout versus Schematic (LVS) Make sure that minimum spacing, sizes, etc are met (Design Rule Check) Make sure that it meets timing requirements( Static Timing Analysis, etc.) process begin wait until not CLOCK'stable and CLOCK=1; if(ENABLE='1') then TOGGLE<= not TOGGLE; end if; end process; ? ?

24. Design Goes to Fabrication 24

25. 25

26. References 26 D. G. Bailey, “The advantages and limitations of high level synthesis for fpga -based image processing ,” Proceedings of the 9th International Conference on Distributed Smart Cameras , 2015. Genus Synthesis Solution . Cadence Design Systems, Inc., 2021. Genus Physical Guide . Cadence Design Systems, Inc., 2021. PPA Push: Tips & Tricks ( Innovus 17.1x). Cadence Design Systems, Inc.,2018. A. B. Kahng , J. Lienig , I. Markov, and J. Hu, VLSI Physical Design: From Graph Partitioning to Timing Closure . New York City, NY: Springer, 2011 Genus iSpatial - Rapid Adoption Kit . 2655 Seely Ave., San Jose, CA 95134,USA: Cadence Design Systems, Inc, 2021. Innovus User Guide . 2655 Seely Ave., San Jose, CA 95134, USA: Cadence Design Systems, Inc, 2021. Best Full-Flow PPA . Cadence Design Systems, Inc., 2020.

27. Thank you for listening! Any Questions??? 27 [email protected]