Analysis and design of digital circuits PIPO PISO.pptx

Parallel input and parallel output

1. PIPO, PISO, USR

2. Parallel in serial out

3. module  Shiftregister_PISO ( Clk , din,load , SO); input   Clk,load ; input  [3:0]din; output  reg SO; reg  [3:0] tmp ; always  @(posedge Clk ) begin if (!load ) tmp <=din; else begin SO<= tmp [3]; tmp <={1’b0 , tmp [3:1],}; end end endmodule

4. Parallel in parallel out

5. module pipomod ( clk,clear , pi, po); input clk,clear ; input [3:0] pi; output [3:0] po; wire [3:0] pi; reg [3:0] po; always @(posedge clk ) begin if (clear) po<= 4’b0000; else po <= pi; end endmodule

6. Bi-directional shift register

7. Universal shift register