Antifuse programming technology is a one-time programmable method used in field-programmable gate arrays (FPGAs) and programmable read-only memory (PROM) that creates a permanent conductive path between two electrodes by breaking down a thin insulating di

Antifuse Programmed FPGAs

1. Antifuse Programmed FPGAs – Unit -3 What is an Antifuse ? An antifuse is a two-terminal device that irreversibly changes from high resistance to low resistance when a programming voltage is applied. Advantages of Antifuses : Low “on” resistance (100 to 600 ohms) Small area footprint, comparable to vias Highly scalable – up to a million antifuses in a single FPGA High-performance FPGAs with speeds up to 75 MHz Actel FPGA Families: Act1: 1200–2000 gates Act2: 2500–8000 gates - Act3: 1500–10,000 gates

2. Actel Antifuse FPGA Architecture Antifuse Technology: Uses " antifuse " switches which are nonvolatile (retain programming after power off) and act as permanent metal-to-metal links when programmed. Offers low resistance and low capacitance, minimizing delays and power consumption compared to SRAM-based FPGAs. No need for external configuration memory (PROM), reducing board space, cost, and power.

3. Architecture Highlights " Sea of modules " layout: Programmable logic modules are surrounded by a large interconnect network. Fast , live-at-power-up operation since configuration is permanent. Design security: once programmed, the connections cannot be altered or read back, making reverse engineering very difficult.

4. Architecture Description The simplified block diagram of an Actel FPGA includes: Rows of logic modules Horizontal routing channels with pre-defined wire segments Vertical wiring segments for input/output to/from logic modules Antifuses at the intersections of horizontal and vertical segments Each logic module receives inputs via dedicated vertical wires and produces an output on longer vertical wires. Routing is achieved by programming antifuses to form desired connections. The outer layer contains I/O pads and buffers connected through special logic modules.

5. Programming Technology Requirements for a High-Performance Programmable Switch: Small area Low parasitic resistance and capacitance Manufacturability Reliability Alternative Switch Technologies: Laser-Programmed Switches: Require expensive equipment and packaging Fuses (e.g., polysilicon, PtSi ): Reliability issues like fuse regrowth Transistors (SRAM/EPROM-based): High parasitic RC, large area. Why Antifuse ? Antifuses offer several key advantages: Very low resistance and capacitance (lower RC delay) Compact (size of a via) Programmable only once (non-volatile) Suitable for simple and flexible routing

6. Types of Antifuses Amorphous Silicon Antifuse : High leakage and reversibility issues Resistance: 50–110 ohms @ >10 mA Capacitance: 1.3 fF in 1µm CMOS Leakage: <10 nA at 5.5V Dielectric Antifuse (PUCE - Programmable Low Impedance Circuit Element): Composed of ONO (oxide-nitride-oxide) Resistance: >100 GΩ unprogrammed; 100–600 Ω when programmed Capacitance: 6 fF in 0.8µm CMOS Leakage: ~1 fA (negligible) Programming voltage: 16V, time: 1ms

7. PUCE Structure N+ diffusion and N+ polysilicon Separated by ONO dielectric Electrodes are connected by conductive polycrystalline silicon link post-programming

8. Reliability Unprogrammed State: Lifetime estimated over 40 years at 5.5V and 125°C Modeled using Time Dependent Dielectric Breakdown (TDDB) Programmed State: No resistance drift or self-healing observed Long-term stability proven Radiation Resistance: ONO antifuses withstand up to 1.5 million rads

9. Architecture Overview

10. Principles of Programmable Routing Two Main Criteria: Routability : Ability to connect all required nets in a variety of designs using the programmable interconnect. Only the switches can be programmed , not the physical wires themselves. Too many wires waste area , few limit functionality. Speed: Signal propagation delay through routes should be minimized . Every programmable switch adds resistance and capacitance (RC), increasing delay. Delay increases quadratically with more switches in series . Antifuse switches help keep delay and its variability low . Why Antifuse ? Among programmable connections (EPROM, MOS pass device, antifuse ), antifuse offers the lowest resistance, which reduces both average delay and delay variability for routed signals.

11. Detailed Routing Architectures & Trade-offs To connect the signal paths inside an FPGA, various architectures are possible: a. Conventional Masked Device Channel Each connection is custom-laid during device fabrication. The wiring is highly optimized for every signal, minimizing area and giving reliable delays. Not flexible after manufacture; not applicable to FPGAs. b. Switch at Every Crosspoint For maximum routing freedom, install switches at every point where wiring segments cross. This enables tracks of variable length, giving flexibility for routing. But every switch adds RC delay, making long signal routes much slower.

12. Detailed Routing Architectures & Trade-offs c. Full-Length Continuous Tracks Instead of many short segments, provide enough uninterrupted tracks for all nets. Only two switches per net → predictable and equal delay. However, even short connections must use the full length of track, which unnecessarily increases load (capacitance). The total area required grows  quadratically  as you add more nets — very inefficient. d. Segmented Routing Channels ( Actel’s Approach) Divide tracks into segments of varying lengths. Nets can use just a segment or join adjacent segments by switches ( antifuses ). This design balances area, speed, and flexibility . Single-segment routing is efficient and near-optimal for most cases; using multiple segments is more complex, but routing algorithms (software heuristics) make this feasible. The routing problem for multiple segments is NP-complete, but special cases and practical heuristics work well in real FPGA tools.

13. Actel FPGA Routing Architecture

14. Long Vertical Tracks (LVTs) Shared across modules, allowing flexible routing across the chip

15. Actel Device Architecture The architecture of an Actel FPGA is very similar to that of a conventional gate array. The core of the device consists of simple logic modules used to implement the required logic gates and storage elements. These logic modules are interconnected with an abundance of segmented routing tracks. Unlike gate arrays, the segment lengths are predefined and can be connected with low impedance switching elements to create the precise routing length required of the interconnect signal. Surrounding the logic core is the interface to the I/O pads of the devices. This interface consists of I/O modules that translate and interconnect the logic signals from the core of the device to the FPGA output pads.

16. Actel Device Architecture The major elements of the Actel FPGA architecture are thus the I/O modules, interconnect resources, clocking resources, and logic modules. Each Actel FPGA family has a slightly different mix of these resources, optimized for different cost, performance, and density requirements.

17. Logic Module Descriptions

18. Simple Logic Module The first Actel logic module was the Simple Logic Module used in the ACT 1 family. It is a multiplexer-based logic module. Logic functions are implemented by interconnecting signals from the routing tracks to the data inputs and select lines of the multiplexers. Multiplexing is very efficient, but random logic and sequential logic functions are also efficient. These options provide the designer with an excellent mix of logic capabilities, required for applications demanding a variety of logic functions.

19. Example Latches can be implemented in a single logic module per bit and that registers require two logic modules per bit. The ACT 1 logic module is thus extremely flexible in covering a wide range of combinatorial and sequential logic mixes.

20. Combinatorial Logic Module Some improvements were made to the Simple Logic Module when the second generation ACT 2 family was developed. The Simple Logic Module was replaced with two different logic modules, one for implementing combinatorial logic, (the Combinatorial Logic Module) and one for implementing storage elements (the Sequential Logic Module). The Combinatorial Logic Module, shown in the diagram in Figure 4, is like the Simple Logic Module, but an additional logic gate was placed on the first level multiplexer.

21. The added gate improves the implementation of some combinatorial functions. (Some five-input gates are now available.) Also, the first-level multiplexer lines in the Simple Logic Module were combined in the Combinatorial Logic Module. In the Simple Logic Module, the separate multiplexer select lines were used to implement latches and registers efficiently. This was not required in the Combinatorial Logic Module because of the addition the Sequential Logic Module. Figure 5 shows an example of a logic function implemented with the Combinatorial Logic Module.

22. Sequential Logic Module

23. Enhanced Sequential Logic Module The Enhanced Sequential Logic Module used in the ACT 3 family is a refinement of the Sequential Logic Module and is shown in the diagram in Figure 7. The reset input on the register in the sequential section is not shared with the combinatorial logic function, so the full combinatorial logic is available in the Combinatorial Logic Module to be used in front of the register. This makes all single module combinatorial logic functions usable in front of the storage element, simplifying design via schematics or synthesis inputs, and it can result in speed improvements for wide-input functions.