Apple iMac A1311 K74 051-8337 820-2784 PDF.pdf

3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.
8
1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%.
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
3
B
7
ECNREV
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DRAWING NUMBER
REVISION
SIZE
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PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
DRAWING TITLE
THE POSESSOR AGREES TO THE FOLLOWING:
Apple Inc.
SHEET
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DATE
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A
C
THE INFORMATION CONTAINED HEREIN IS THE
2. ALL CAPACITANCE VALUES ARE IN MICROFARADS.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
C
3456
D
B
87 6 5 4 21
12
APPD
CK
DESCRIPTION OF REVISION
TABLE_TABLEOFCONTENTS_ITEM
DRAWING
DRAWING
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K74 MLB
1 OF 92
0000891242A
051-8337
A.0.0
1 OF 110
PRODUCTION RELEASED 2010-04-13
SCH,K74,MLB
Table of Contents K74_MASTER
1 N/A
1
LAST_MODIFIED=Tue Apr 13 17:17:57 2010
ABBREV=DRAWING
TITLE=K22
LAST_MODIFIED=Tue Apr 13 17:17:57 2010
Page
(.csa)
Contents Sync
Date
49
01/07/2010
DAVE
52
SMBus Connections
Contents SyncPage
(.csa) Date
50
N/A
K74_MASTER
53
CPU/GPU POWER SENSE
51
N/A
K74_MASTER
54
HDD TEMP SENSE
52
11/06/2009
NICK
55
REMOTE TEMP/POWER SENSORS
53
N/A
K74_MASTER
56
HD AND OD FAN
54
N/A
K74_MASTER
57
CPU FAN & AMBIENT SENSE
55
11/30/2009
K23F
61
SPI ROM
56
02/02/2010
BREECE
62
AUDIO: CODEC/REGULATOR
57
02/02/2010
BREECE
63
AUDIO: FILTER/BUFFER
58
02/02/2010
BREECE
64
AUDIO: SPEAKER AMP_1
59
02/02/2010
BREECE
65
AUDIO: SPEAKER AMP
60
02/02/2010
BREECE
66
Audio: MLB to I/O Conn.
61
02/02/2010
BREECE
67
AUDIO: Detects/Grounding
62
02/02/2010
BREECE
68
AUDIO: Mikey
63
N/A
K74_MASTER
69
POWER SEQUENCING ENABLES
64
N/A
K74_MASTER
70
POWER SEQUENCING PGOOD
65
N/A
K74_MASTER
71
VREG: PPVCORE_S0_CPU
66
N/A
K74_MASTER
72
VREG: CPU CORE - PHASES 1-3
67
N/A
K74_MASTER
73
VREG: CPU CORE - CAPS
68
12/08/2009
NICK
74
CPU VTT REGULATOR
69
N/A
K74_MASTER
76
IBEX PEAK CORE
70
12/08/2009
NICK
77
5V_S3 / 3V3_S5 VREGS
71
11/30/2009
K23F
78
1.5V / 1.8V VREGS
72
N/A
K74_MASTER
79
3.42 G3HOT SUPPLY
73
N/A
K74_MASTER
80
S3+S0 FETS
74
11/30/2009
K23F
84
MXM PCIe, DP & Power
75
N/A
K74_MASTER
85
MXM I/O
76
11/30/2009
K23F
86
MXM PCIE CAPS
77
N/A
K74_MASTER
87
Display: Aliases
78
N/A
K74_MASTER
90
Display: Int DP Connector
79
01/07/2010
DAVE
91
DISPLAY: DP REDRIVER
80
01/07/2010
DAVE
92
DISPLAYPORT CONNECTIONS
81
N/A
K74_MASTER
94
Display: Ext DP Connector
82
N/A
K74_MASTER
100
K74/K75 RULE DEFINITIONS
83
N/A
K74_MASTER
101
Memory Constraints
84
N/A
K74_MASTER
102
PCIE/DMI/FDI/SATA CONSTRAINTS
85
N/A
K74_MASTER
103
IBEX PEAK CONSTRAINTS
86
N/A
K74_MASTER
104
ENET/SD/FW/AUD CONSTRAINTS
87
01/07/2010
DAVE
105
GRAPHICS CONSTRAINTS
88
12/09/2009
TEMP
106
SMC Constraints
89
N/A
K74_MASTER
107
POWER CONSTRAINTS
90
N/A
K74_MASTER
109
PM RESETS ENABLES PGOOD CONST
91
N/A
K74_MASTER
110
K74/K75 ICT/FCT
System Block Diagram K74_MASTER
2 N/A
2
Power Block Diagram K74_MASTER
3 N/A
3
BOM Configuration K74_MASTER
4 N/A
4
Power Conn / Alias K74_MASTER
6 N/A
5
Holes K74_MASTER
7 N/A
6
UNUSED SIGNAL ALIAS K74_MASTER
8 N/A
7
Signal Aliases K74_MASTER
9 N/A
8
CPU DMI/PEG/FDI/RSVD K74_MASTER
10 N/A
9
CPU CLOCK/MISC/JTAG K74_MASTER
11 N/A
10
CPU DDR3 INTERFACES K74_MASTER
12 N/A
11
CPU POWER K74_MASTER
13 N/A
12
CPU GROUNDS K74_MASTER
14 N/A
13
14 STRAPS,PULL UPS,PULL DOWNS FOR PCH AND CPU NICK
15 12/08/2009
CPU NON-GFX DECOUPLING NICK
16 12/08/2009
15
CPU/PCH GFX DECOUPLING K74_MASTER
17 N/A
16
PCH SATA/PCIE/CLK/LPC/SPI NICK
18 12/08/2009
17
PCH DMI/FDI/GRAPHICS K74_MASTER
19 N/A
18
PCH PCI/FLASHCACHE/USB NICK
20 12/08/2009
19
PCH MISC K23F
21 11/30/2009
20
PCH POWER K23F
22 11/30/2009
21
PCH GROUNDS K23F
23 11/30/2009
22
PCH DECOUPLING K74_MASTER
24 N/A
23
EXTENDED DEBUG PORT(XDP) NICK
25 12/08/2009
24
CLOCK (CK505) K23F
26 11/30/2009
25
DDR3 RESET MATT
27 01/06/2010
26
CHIPSET SUPPORT K74_MASTER
28 N/A
27
DDR3 Vref Margining MATT
29 01/06/2010
28
MEMORY CAPS K74_MASTER
30 N/A
29
DDR3 SO-DIMMs 0 & 2 K74_MASTER
31 N/A
30
DDR3 SO-DIMM CONNECTOR B K74_MASTER
32 N/A
31
DDR3 ALIAS AND BITSWAPS K74_MASTER
33 N/A
32
PCI-E MiniCard Connector K74_MASTER
34 N/A
33
USB HUB 1 K74_MASTER
35 N/A
34
USB HUB 2 K74_MASTER
36 N/A
35
Caesar II/IV Support MASTER
38 N/A
36
Ethernet PHY (Caesar II/IV) T27
39 11/30/2009
37
Ethernet Connector MASTER
40 N/A
38
FireWire LLC/PHY (XIO2213B) MASTER
41 N/A
39
FW: 1394B MISC MASTER
42 N/A
40
FIREWIRE CONNECTOR MASTER
43 11/17/2009
41
SATA Connectors K74_MASTER
45 N/A
42
EXTERNAL USB CONNECTORS MASTER
46 11/30/2009
43
Internal USB Connections MASTER
47 11/06/2009
44
SD READER CONNECTOR K74_MASTER
48 N/A
45
SMC K74_MASTER
49 N/A
46
SMC Support K74_MASTER
50 N/A
47
LPC+SPI Debug Connector K23F
51 11/30/2009
48
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II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
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REVISION
DRAWING NUMBER SIZE
D
R
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
21
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
87 54 21
HDMI/DVI/DP
PG 39
PG 20
IBEX PEAK
PG 18
TEMP SENSORS
MXM - GPU DIE
CPU HEATSINK
GPU HEATSINK
AMBIENT INTAKE
CPU DIE-PECI
HARD DRIVE
J5600, J5601, J5700
0
U6201
U6400, U6500
FAN CONN AND CONTROL
PG 56,57
LPC+SPI CONN
Port80,serial
MAGNETICS
X1 PCIE GEN1 LANE 2.5GBITPS
(SUPPORTED UPTO 4 REQ/GNT)
X1 PCIE GEN1 LANE 2.5GBITPS
PCI-E GEN2
SMB
SATA CONN
PG 19
Misc
PG 19
FDI INTERFACE
XDP
PG 90
J6600,J6601,J6602,J6603
LINE INPUT
MICROPHONES
INTERNAL/EXTERNAL
HEADPHONES
SPEAKER AMPS
Conns
Audio
Audio
ODD
PG 45
J4520
J4510
SATA CONN
PG 45
HD
CK505
PG 26
SATA 2.0 3GHZ.
SYNTH
SATA-A0
SATA
ANALOG VIDEO OUTPUT
(PORT A)
DIGITAL VIDEO OUTPUT
PG 94
INTERNAL
DISPLAY
J9400
PG 84
CLK
PG 61
Ser
Prt
J5100
2 SO-DIMMS
U1000
HDMI/DVI/DP
PG 41
(PORT C)
DIGITAL VIDEO OUTPUT
J3400
FireWire
Conn
RGB OUT
DIGITAL VIDEO OUTPUT
6 SATA 2.O PORTS
HDA
U4900
PG 49
Mini PCI-E
AirPort
PG 43
GPIOs
PG 34
ADC
SMC
BSBB,0
SPI
J4300
Fan
POWER SUPPLY
PG 10
2 SO-DIMMS
13
X16 PCI-E GEN2
PCI
TEMP, CURRENT SENSE
PG 55
POWER SENSE
PG 53
J3100, J3100
J3200, J3200
PG 31
PG 32
U6100
OPTICAL DRIVE
Boot ROM
SPI
INTEL CPU
U2600
X4 DP
X4 DP
J8400
MXM CONNECTOR
DIMM’s
10
9
8
7
6
5
PG 39 PG 38
U1800
PG 20
PG 19
PG 19
PG 18
PG 18
PG 18
PG 19
HDMI/DVI/DP
PG 18
DMI INTERFACE
INTERFACE
LPC
X1 PCIE GEN1 LANE 2.5GBITPS
PG 18
INTEL
U3800
T3900
E-NET
(PORT D)
(PORT B)
J3900
CONNECTOR
E-NET
PG 51
J2500
PG 25
XDP CONN
SO-DIMMS
SO-DIMMS
X4 DMI
SATA-A1
PORT CONN
LGA1156 - CLARKDALE/LYNNFIELD
USB 96MHZ/PCIE 100MHZ/SATA 100MHZ/BCLK 133MHZ.
SATA 2.0 3GHZ.
U4100
TI 1394B
XIO2211
USB 2.0UP TO 8 LANES3
CONTROLLER
AND PHY
GB E-NET
BCM5764M
34
CAMERA
PG 47
J4700 J4780
PG 47
11
21
USB HUB 1
PG 35
3 4431 2
CTRL
12
PWR
PG 47
Bluetooth
USB HUB 2
PG 36
SD CARD
PG 47
IR
PG 46
EXT
PORT0 PORT2
PG 46
EXT EXT
PG 46PG 46
EXT
PG 18
J4610 J4630J4620 J4640
PORT1 PORT3
J4750
PG 13
DISP
J9000
DDR3 1333 CHA
DDR3 1333 CHB
LCD TEMP
SKIN TEMP
POWER SUPPLY
USX2061 USX2061
J4720
MIKEY
Codec
12
U6806
(UP TO 14 DEVICES)
System Block Diagram
SYNC_MASTER=K74_MASTER SYNC_DATE=N/A
2 OF 110
A.0.0
051-8337
2 OF 92
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G S
D
IN
D1
D3
D4
S3
S2
GATE
S1
D2
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
BRANCH
REVISION
DRAWING NUMBER SIZE
D
R
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
21
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
87 54 21
SMC_PM_G2_ENABLE
1
FET (2.8A)
PAGE 80
Sleep (S3/M-Off)
1
0.75V @ 0.6A
AUDIO
12V S5 FET ( 7A )
FET (10.3A)
PM_SMC_G2_EN
TEMP SENSOR
DCM/FCM
PPLED_PWR
CPU_CORE
PAGE 76
REG
USB
IR
CPU PLL
PAGE 78
FW
PAGE 80
PP3V3_S3
MEM_VTT
PP0V75_S0
PAGE 75
PAGE 75
PAGE 74
13A (S3 & S0)
PP1V2_S3
1.2V @ 0.2A
PAGE 38
ENET
PP1V5_S0
BT
CPU MEM
SW (1A)
SMBUS
CPU UNCORE
CONTROL
PP12V_G3H: AUDIO
LCD PANEL
HARD DRIVE
PM_SLP_S3_OD
PP12V_S0
PP12V_S0:
PP5V_S0
PP12V_G3H
AP
1.05V @ 0.4A
HDD
PP3V3_S0
MXM
BOOT ROM
FIREWIRE
BIDIVI
P3V3S0_EN
PPDDR_S3_REG
ETHERNET
1.05V @ 3A
PP1V05_S0
FANS
PAGE 76
PP1V05_S5
.65-1.5V @ 90A
PPVTT_S0
1.1V @ 30A
PAGE 76
PP1V95_S3
AUDIO
3.3V @ 6.2A
PP3V3_S5_REG
PAGE 80
3.3V @ 2.8A
P5VS0_EN
VCCME, PCH
PAGE 79
P3V3S3_EN
AUDIO
IBEX PEAK
LCD PANEL
OPTICAL
MXM
PP1V8_S0_REG
CARD READER
SMC VREF
REG
PAGE 79
PM_SLP_S3
MAIN MEMORY
1.0V @ 0.08A
PAGE 42
FET (6.9A)
AC/DC POWER SUPPLY
PP12V_S0_HDD
MXM
IBEX PEAK
PAGE 71-72
PPVCORE_CPU
PP12V_S5
IBEX PEAK
WM
PP5V_S3_REG CAMERA
PP3V42_G3H_REG
SMC
12V_S5
PP12V_S5:
PAGE 50
PP3V3_S5_AVREF_SMC
0
1
0
0
PM_SLP_M_L
1
1
0
0
1
1
1
PM_SLP_S4_L
0
0
1
0
0
0
PM_SLP_S3_L
0
1
1
0
1
PM_S4_STATE_L
1
1
0
1
Manageability
N/A
Off
On
N/A
On
State
Soft-Off (S5/M-Off)
Soft-Off (S5/M1)
Sleep (S3/M1)
Run (S0/M0)
Off
Battery Off (G3Hot)
FIREWIRE1.5V @ 4.9A
PAGE 78
IBEX PEAK
1
0
2
1C8040
0.47UF
805
16V
10%
X7R
2
1
R8042
5%
1/16W
MF-LF
402
100K
2
1
R8045
402
MF-LF
10K
1/16W
5%
2
1
R8040
5%
1/16W
10K
MF-LF
402
21
R8041
MF-LF
1/16W
402
5%
10K
2
1
3
Q8041
2N7002
SOT23-HF1
46
3
2
1
4
8
7
6
5
Q8040
CRITICAL
FDS4465_G
SOI-HF
Power Block Diagram
SYNC_MASTER=K74_MASTER SYNC_DATE=N/A
=PP12V_G3H_S5_FET
MAKE_BASE=TRUE
VOLTAGE=12V
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
NET_SPACING_TYPE=POWER
MAX_NECK_LENGTH=3 MM
PP12V_S5_FET
P12V_S5_EN_G
SMC_PM_G2_EN
P12V_S5_EN_D
P12V_S5_EN_R
3 OF 110
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051-8337
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PART NUMBER
ALTERNATE FORPART NUMBER BOM OPTION REF DES COMMENTS:
TABLE_ALT_HEAD
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
CRITICAL BOM OPTION
TABLE_5_HEAD
PART# DESCRIPTIONQTY REFERENCE DESIGNATOR(S)
PART NUMBER
ALTERNATE FORPART NUMBER BOM OPTION REF DES COMMENTS:
TABLE_ALT_HEAD
TABLE_ALT_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_BOMGROUP_ITEM
CRITICAL BOM OPTION
TABLE_5_HEAD
PART# DESCRIPTIONQTY REFERENCE DESIGNATOR(S)
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
BOM OPTIONSBOM NAMEBOM NUMBER
TABLE_BOMGROUP_HEAD
TABLE_BOMGROUP_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
CRITICAL BOM OPTION
TABLE_5_HEAD
PART# DESCRIPTIONQTY REFERENCE DESIGNATOR(S)
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
CRITICAL BOM OPTION
TABLE_5_HEAD
PART# DESCRIPTIONQTY REFERENCE DESIGNATOR(S)
TABLE_5_ITEM
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
BRANCH
REVISION
DRAWING NUMBER SIZE
D
R
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
21
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
87 54 21
BOM OPTIONSBOM NAMEBOM NUMBER
TABLE_BOMGROUP_HEAD
TABLE_BOMGROUP_ITEM
TABLE_ALT_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
PART NUMBER
ALTERNATE FORPART NUMBER BOM OPTION REF DES COMMENTS:
TABLE_ALT_HEAD
TABLE_5_ITEM
TABLE_5_ITEM
CRITICAL BOM OPTION
TABLE_5_HEAD
PART# DESCRIPTIONQTY REFERENCE DESIGNATOR(S)
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
BOM OPTIONSBOM GROUP
TABLE_BOMGROUP_HEAD
TABLE_BOMGROUP_ITEM
ALTERNATES
ALTERNATE SOCKET VENDORS MUST USE MATCHING ILM
BOARD STACK-UP
POWER
K74 PARTS
7
SIGNAL
POWER
3
TOP
2
SIGNAL
BOTTOM
4
5
GROUND
SIGNAL
GROUND
COMMON
BOM GROUPS
CPU SOCKET & ILM SUB-BOMS
6
BOM Variants
SIGNAL
RAW: 335S0663
CPUS
639-0694 K74,2P53GHZ_LFD_CPU,BASIC,LYNNFIELD_82WPCBA,MLB,K74,2.53GHZ,LFD
COMMON,ALTERNATE,XDP,MXM,XDP_CPU_BPM,PCH_VRM,BUF_CLK,HUB_USX2061,FW_TI_INT_VREG,BCM5764M,SD_USB,METAL_IO,PRODUCTIONBASIC
XDP_CONN,LPCPLUS,MOJOMUX,CPU_1V5_SENSE,VREFMRGNDEV_GROUP
K74,3P46GHZ_CKD_CPU,BASIC,CLARKDALE_73W639-0695 PCBA,MLB,K74,3.46GHZ,CKD
CKD,SLBLT,PRQ,3.46,73W,1333,C2,4M,LGA 3P46GHZ_CKD_CPU1 CRITICALCPU337S3900
337S3862 LFD,Q3C6,QS,2.53,82W,1333,B1,8M,LGA CPU CRITICAL1 2P53GHZ_LFD_CPU
337S3911 CKD,SLBUD,PRQ,3.20,73W,1333,K0,4M,LGA CPU CRITICAL1 3P20GHZ_CKD_CPU
337S3912 CKD,SLBTD,PRQ,3.06,73W,1333,K0,4M,LGA 3P06GHZ_CKD_CPUCRITICALCPU1
CKD,Q3GR,QS,2.93,73W,1333,C2,4M,LGA 2P93GHZ_CKD_CPU1 CRITICALCPU337S3837
CKD,SLBTM,PRQ,3.60,73W,1333,K0,4M,LGA337S3910 CPU1 3P60GHZ_CKD_CPUCRITICAL
C2,PRQ,3.06 GHZ CKD337S3912337S3898 3P06GHZ_CKD_CPUCPU
639-0707 PCBA,MLB,K74,3.06GHZ,CKD K74,3P06GHZ_CKD_CPU,BASIC,CLARKDALE_73W
BOM Configuration
SYNC_MASTER=K74_MASTER SYNC_DATE=N/A
IC,BCM5764M,ENET,8X8 CRITICAL343S0493 U39001 BCM5764M
337S3828 IC,IBEX PEAK PRQ,DESKTOP,FCBGA,PCH,P425 CRITICALU18001
1IC,SLG2AP108,CLK GEN,CK505,QFN3 CRITICAL359S0157 BUF_CLKU2600
IC,EFI BOOTROM,K74/K75341T0230 U61001 CRITICAL
MLB LABEL,48.0X4.8 CRITICAL1 X14825-7122
U3900343S0494 1 CRITICAL BCM57765IC,BCM57765A,ENET&SD,8X8
IC,XIO2211ZAY,1394B_PCIE,PHY/LINK U4100 CRITICAL1338S0765
SKT_ILM CRITICAL1607-6694 MOLEX CPU SOCKET AND ILM
PCBA,MLB,DEV,K74 DEVELOPMENT,DEV_GROUP085-1107
PCBA,MLB,K74,2.93GHZ,CKD639-0698 K74,2P93GHZ_CKD_CPU,BASIC,CLARKDALE_73W
ENET 1MBIT FLASH,CIV,K74/K75 CRITICAL BCM57765U39901341T0246
U3990ENET 1MBIT FLASH,CII,K74/K75341T0269 CRITICAL1 BCM5764M
639-0808 K74,3P20GHZ_CKD_CPU,BASIC,CLARKDALE_73WPCBA,MLB,K74,3.20GHZ,CKD
MOLEX_SOCKET1511S0063 CRITICALU1000SOCKET,LGA1156,CPU-LF
K74IC,SMC,K74341T0231 CRITICALU49001
PCBF,MLB,K74 MLB11820-2784
SCH1051-8337 SCH,MLB,K741
SUB ASSY,CPU SOCKET,K74,FOXCONN607-6693 FOXCONN_SOCKET
FOXCONN_SOCKET604-1246 1 ILM CRITICALASSY,PURCHASED,ILM,MOLEX,K74
1 U1000 CRITICAL511S0069 FOXCONN_SOCKETSOCKET,LGA1156,CPU-LF
MOLEX_SOCKET1 CRITICALILM604-1161 ASSY,PURCHASED,ILM,MOLEX,K74
607-6693 FOXCONN ALTERNATESKT_ILM607-6694
MOLEX_SOCKETSUB ASSY,CPU SOCKET,K74,MOLEX607-6694
K74,3P60GHZ_CKD_CPU,BASIC,CLARKDALE_73W639-0991 PCBA,MLB,K74,3.60GHZ,CKD
197S0179197S0339 FIREWIRE OSCILLATORY4190
128S0293128S0298 C1670,C7260,C7444
4 OF 110
A.0.0
051-8337
4 OF 92
www.vinaﬁx.vn

IN
G S
D
G
D
S
G
D
S
IN
IN
IN
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
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PAGE TITLE
C
A
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21
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
87 54 21
"S3" RAILS
"S0" RAILS
EMC: C600,C626,C627,C628,C629,C630,C631
PLACE AT J600.
SILKSCREEN:3
SILKSCREEN:1
SILKSCREEN:4
SILKSCREEN:2
ALWAYS ON WHEN UNIT HAS AC POWER AND IN G3HOT PER SMC
"G3H" RAILS
G3H: ALIASES
UNUSED, GROUNDED ON CSA 24
"S5" RAILS
ALWAYS ON WHEN UNIT HAS AC POWER AND IN S5
GND RAILS
518-0352
ONLY ON IN RUN
ENET RAILS
ON IN RUN AND SLEEP
2
1C627
0.001UF
402
50V
X7R
10%
18 26 36 46 47 63 64 81 91
2
1C624
X5R-CERM
1210
10UF
16V
10%
2
1C626
0.001UF
50V
X7R
10%
402
2
1
3
Q610
SOT23-HF1
2N7002
2
1C600
50V
10%
0.001UF
402
X7R
2
1C623
10UF
805
20%
X5R
10V
2
1C630
0.001UF
X7R
10%
50V
402
2
1C631
0.001UF
402
X7R
50V
10%
9
8
7
6
5
4
3
2
14
13
12
11
10
1
J600
CRITICAL
M-RT-TH
76833-0100
4
5
3
Q602
SOT-363
2N7002DW-X-G
1
2
6
Q602
2N7002DW-X-G
SOT-363
78
2
1C690
47PF
402
50V
5%
CERM
21
R690
0
21
R691
0
2
1C691
47PF
50V
CERM
5%
402
K
A
LED601
2.0X1.25MM-SM
GREEN-3.6MCD
2
1
R601
5%
MF-LF
402
1/16W
1K
2
1
R600
DEVELOPMENT
402
MF-LF
5%
1K
1/16W
K
A
LED605
DEVELOPMENT
GREEN-3.6MCD
2.0X1.25MM-SM
2
1
R603
5%
MF-LF
1/16W
402
1K
K
A
LED603
GREEN-3.6MCD
2.0X1.25MM-SM
2
1
R604
MXM
1K
5%
1/16W
MF-LF
402
K
A
LED604
GREEN-3.6MCD
MXM
2.0X1.25MM-SM
20
2
1
R602
1/16W
5%
MF-LF
1K
402
K
A
LED602
GREEN-3.6MCD
2.0X1.25MM-SM
64 91
SYNC_MASTER=K74_MASTER SYNC_DATE=N/A
Power Conn / Alias
MIN_LINE_WIDTH=0.6MM
NET_SPACING_TYPE=GND
MIN_NECK_WIDTH=0.2MM
VOLTAGE=0V
MAKE_BASE=TRUE
MAX_NECK_LENGTH=4.1 MM
GND
VOLTAGE=3.3V
NET_SPACING_TYPE=POWER
MIN_LINE_WIDTH=0.5 mm
MAKE_BASE=TRUE
MAX_NECK_LENGTH=3 MM
MIN_NECK_WIDTH=0.2 mm
PP3V3_S3
=PP3V3_S3_ENETFET
=PP3V3_S3_VREFMRGN
=PP3V3_S3_SMBUS_SMC_A_S3
=PP3V3_S3_PWRCTL
=PP3V3_S3_USB_HUB
=PP3V3_S3_MEMRESET
=PP3V3_S3_MINI
=PP3V3_S3_BT
PP3V3_S3_FET
=PP3V3_G3H_LPCPLUS
=PP3V3R1V8_S0_PCH_VCCPNAND
=PP3V3_S3_SDCARD
=PPSPD_S0_MEM_B
=PP3V3_S0_VRD
=PP3V3_S0_AUDIO
=PPDDR_S3_S0FET
=PP3V3_S0_PWRCTL
PP3V3_ENET_FET
=PP3V3_ENET_PHY
MAKE_BASE=TRUE
VOLTAGE=3.3V
MIN_LINE_WIDTH=0.4MM
NET_SPACING_TYPE=POWER
MIN_NECK_WIDTH=0.2MM
MAX_NECK_LENGTH=3 MM
PP3V3_ENET
=PP3V3_S0_SATALED
=PP3V3_S0_PCH_VCC3_3_CORE
=PP3V3_FW_FWPHY
=PP3V3_S0_DP
=PP3V3_S0_PCH_VCC3_3_PCI
=PP5V_S0_SATA
PP5V_S0_FET
=PP3V3_S0_CPU_VTT_VREG
=PP5V_S0_AUDIO
=PP5V_S0_MXM
=PP5V_S0_ISENSE
=PP5V_S0_CPU_VTT_VREG
=PP5V_S0_VRD
NET_SPACING_TYPE=POWER
VOLTAGE=5V
MAX_NECK_LENGTH=3 MM
MAKE_BASE=TRUE
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.2 MM
PP5V_S0
=PP5V_S0_DP_AUX_MUX
=PP5V_S0_PCH_CORE_VREG
MIN_NECK_WIDTH=0.2MM
MIN_LINE_WIDTH=0.4MM
VOLTAGE=3.3V
MAKE_BASE=TRUE
NET_SPACING_TYPE=POWER
MAX_NECK_LENGTH=3 MM
PP3V3_S0
=PP3V3_S0_PCH_VCC3_3_SATA
=PP12V_S0_VRD
PP1V5_S3_REG
=PP1V5_S3_MEMRESET
=PP1V5_S0_MINI
=PP1V5_S0_CK505
=PP5V_S0_SATA
SMB_ACDC_SCL_RC
PM_ACDC_PS_ON
=SMB_ACDC_SCL
=PP3V3_S0_PCH_STRAPS
=PP3V3_S0_PCH_GPIO
=PP3V3_S0_ODD
PP12V_G3H
=SMB_ACDC_SDASMB_ACDC_SDA_RC
LCD_BKL_ON
PP12V_S0
LCD_PWM
=PP5V_S5_PCH
MAX_NECK_LENGTH=3 MM
MIN_NECK_WIDTH=0.2MM
VOLTAGE=12V
MAKE_BASE=TRUE
MIN_LINE_WIDTH=0.6MM
NET_SPACING_TYPE=POWER
PP12V_S0
=PP12V_S0_FW
=PP12V_S0_SENSE
MAX_NECK_LENGTH=3 MM
MIN_LINE_WIDTH=0.4 MM
NET_SPACING_TYPE=POWER
VOLTAGE=5V
MAKE_BASE=TRUE
MIN_NECK_WIDTH=0.2 mm
PP5V_S5
=PP12V_S5_DDR_VREG
MAX_NECK_LENGTH=3 MM
NET_SPACING_TYPE=POWER
MIN_NECK_WIDTH=0.2 mm
MIN_LINE_WIDTH=0.6 mm
VOLTAGE=1.5V
MAKE_BASE=TRUE
PP1V5_S3
=PP1V5_S3_MEM_A
=PP1V5_S3_MEM_B
PP3V3_S5_REG
=PP3V3_S5_ROM
=PP3V3_S5_PCH_STRAPS
=PP12V_S5_PWRCTL
=PP12V_S5_P5VS3_VREG
=PP12V_S5_P3V3S5_VREG
PP12V_S5_FET
PP5V_S5_LDO
MAKE_BASE=TRUE
VOLTAGE=12V
MIN_NECK_WIDTH=0.2 mm
NET_SPACING_TYPE=POWER
MAX_NECK_LENGTH=3 MM
MIN_LINE_WIDTH=0.6 mm
PP12V_S5
=PP3V3_S5_LPCPLUS
=PP3V3_S5_XDP
=PP3V3_S5_CPURESET
=PP3V3_S5_S3FET
=PP3V3_S5_S0FET
=PP3V3_S5_PWRCTL
=PP3V3_S5_PCH_VCCSUS3_3_USB
=PP3V3_S5_PCH_GPIO
=PP3V3_S5_PCH
MAX_NECK_LENGTH=3 MM
VOLTAGE=3.3V
MIN_NECK_WIDTH=0.2MM
NET_SPACING_TYPE=POWER
MAKE_BASE=TRUE
MIN_LINE_WIDTH=0.6MM
PP3V3_S5
=PP3V3_S0_MXM
=PP3V3_S0_DPCONN
=PP3V3_S0_SMBUS_SMC_B_S0
=PP3V3R1V5_S0_PCH_VCCSUSHDA
PPVTT_S0_DDR_FET
NET_SPACING_TYPE=POWER
MIN_LINE_WIDTH=0.4MM
MAKE_BASE=TRUE
MIN_NECK_WIDTH=0.2MM
MAX_NECK_LENGTH=3 MM
VOLTAGE=1.5V
PP1V8_S0
=PP3V3_S0_SMBUS
MIN_LINE_WIDTH=0.4 mm
MIN_NECK_WIDTH=0.2 mm
PP0V75_S0
MAKE_BASE=TRUE
VOLTAGE=0.75V
NET_SPACING_TYPE=POWER
MAX_NECK_LENGTH=3 MM
PPVTT_S0_DDR_LDO
NET_SPACING_TYPE=POWER
MIN_LINE_WIDTH=0.4MM
PP1V5_CPU_MEM
MAX_NECK_LENGTH=3 MM
MIN_NECK_WIDTH=0.2MM
MAKE_BASE=TRUE
VOLTAGE=1.5V
=PP3V3_S0_TSENS
=PP1V8R1V5_S0_PCH_VCCVRM
MIN_LINE_WIDTH=0.6MM
MAKE_BASE=TRUE
MAX_NECK_LENGTH=3 MM
NET_SPACING_TYPE=POWER
MIN_NECK_WIDTH=0.2MM
VOLTAGE=3.42V
PP3V42_G3H
=PPVAXG_S0_CPU
MAX_NECK_LENGTH=3 MM
MIN_NECK_WIDTH=0.2 MM
NET_SPACING_TYPE=POWER
VOLTAGE=12V
MIN_LINE_WIDTH=0.6 mm
MAKE_BASE=TRUE
PP12V_G3H
VOLTAGE=1.1V
MIN_NECK_WIDTH=0.3MM
MAX_NECK_LENGTH=3 MM
MIN_LINE_WIDTH=0.6MM
NET_SPACING_TYPE=POWER
MAKE_BASE=TRUE
PPVCORE_S0_CPU
=PP5V_S0_LPCPLUS
=PP5V_S0_P1V8_VREG
=PP12V_G3H_S5_FET
=PP1V05_S0_PCH_VCCIO_DMI
=PP3V3_S0_SMBUS_SMC_0_S0
=PP3V3_S0_SMBUS_SMC_MGMT
=PP5V_S0_PCH
=PP1V05_S0_PCH_VCCIO_SATA
=PP1V05_SM_PCH_VCC_LAN
MAKE_BASE=TRUE
VOLTAGE=1.05V
NET_SPACING_TYPE=POWER
MIN_NECK_WIDTH=0.2 mm
MAX_NECK_LENGTH=3 MM
MIN_LINE_WIDTH=0.6 mm
PP1V05_S0
=PP1V05_S0_PCH_VCCIO_PCIE
=PP1V05_S0_PCH_VCC_CORE
=PP0V75_S0_MEM_VTT_S0FET
=PP3V3_S0_SMC_LS
=PP12V_S0_PCH_CORE_VREG
PPVCORE_S0_CPU_REG
=PP1V05_SM_PCH_VCC_ME
=PP1V05_S0_PCH_VCCADPLL
PP1V05_S0_REG
=PP3V3_G3H_SMCUSBMUX
=PP3V3_G3H_SMC
=PPVIN_S5_SMCVREF
=PPVCORE_S0_CPU
MAKE_BASE=TRUE
VOLTAGE=1.05V
PP1V05_SM_PCH_LAN
=PP12V_S0_FAN
=PP12V_S0_LCD
PP3V42_G3H_REG
=PP3V3_S5_RTC_D
=PP1V05_S0_CK505
=PP1V05_S0_PCH_VCCIO_USB
=PP12V_S0_CPU_VTT_VREG
=PP12V_S0_PWRCTL
NET_SPACING_TYPE=POWER
MIN_NECK_WIDTH=0.2MM
MIN_LINE_WIDTH=0.4MM
MAKE_BASE=TRUE
MAX_NECK_LENGTH=3 MM
VOLTAGE=1.5V
PP1V5_S0
=PP0V75_S0_MEM_VTT_A
=PP0V75_S0_MEM_VTT_B
=PP1V5_S0_AUD_DIG
=PP3V3_S0_SMC
=PP3V3_FWRS0_FWXIO
=PP3V3_S0_CK505
=PP3V3_S0_RSTBUF
=PP3V3_S0_ENETPHY
=PP3V3_S0_PCH_PM
=PP3V3_S0_SMBUS_SMC_BSA
=PP3V3_SM_PCH_VCC_ME
PP3V3_S3
PP3V3_S0
PP3V3_S5_REG
PP3V3_S0
CORE_VOLTAGES_ON_R
CORE_VOLTAGES_ON
LCD_SHOULD_ON_R
ITS_PLUGGED_IN
GPU_PRESENT_R
GPU_PRESENT_DRAIN
VIDEO_ON_L
ALL_SYS_PWRGD_R
MXM_GOOD
PP3V3_S3
ITS_ALIVE
PM_SLP_S3_L
MAX_NECK_LENGTH=3 MM
VOLTAGE=0.75V
MIN_NECK_WIDTH=0.2 mm
NET_SPACING_TYPE=POWER
MIN_LINE_WIDTH=0.4 mm
MAKE_BASE=TRUE
PPVTT_S0_DDR
=PP1V5_CPU_MEM
PP1V5_S0_FET
=PP1V5_FWRS0_FWXIO
PP1V8_S0_REG
=PP1V8_S0_CPU_PLL
PP3V3_S0_FET
=PP3V3_S0_PCH
=PP3V3_S0_FAN
=PP3V3_S0_SDCARD
PPVTT_S0_CPU_REG
=PPVTT_S0_PCH_VCC_DMI
=PPVTT_S0_XDP
=PPVTT_S0_PCH_VCCP_CPU
=PPVTT_S0_CPU
MIN_NECK_WIDTH=0.2 mm
NET_SPACING_TYPE=POWER
MIN_LINE_WIDTH=0.6 mm
MAKE_BASE=TRUE
MAX_NECK_LENGTH=3 MM
VOLTAGE=1.1V
PPVTT_S0
=PPV_S0_MXM_PWR
=PP12V_S0_AUDIO_SPKRAMP
=PP3V3_S3_USB_RESET
NET_SPACING_TYPE=POWER
MAX_NECK_LENGTH=3 MM
MIN_NECK_WIDTH=0.2MM
MIN_LINE_WIDTH=0.6MM
VOLTAGE=5V
MAKE_BASE=TRUE
PP5V_S3 PP5V_S3_REG
=PP5V_S3_USB
=PP5V_S3_S0FET
=PP5V_S3_CAMERA
=PP5V_S3_IR
=PP5V_S3_PWRCTL
=PP5V_S3_DDR_VREG
=PP5V_S3_MEMRESET
=PPSPD_S0_MEM_A
=PP3V3_S0_PCH_VCCADAC
6 OF 110
A.0.0
051-8337
5 OF 92
5 89 92
36
28
49
64 73
34 35
26
33
44
73
48
21 23
44 45
31
65
56 58 59 60 61 62
73
63 64 73
36
36 37 45
17 42
21 23
39 40 41
78 79 80
21 23
5 42
73
68
56
74
50
68
65
89 92
80
69
5 89
21 23
65
71
26
33
25
5 42
49
14
19
42
5 72 89
49
78
5 64 89
80
23
5 64 89
41
51
89
71
89
28 29 30
28 29 31
5 70
48 55
14
64 73
70
70
3
70
89
48
10
73
73
10 63 64
21 23
19
17 18 23
89
64 74 75
81
49
21 23
26
89
49
89 71
50 89
52
23
89
12
5 72 89
89
48
71
3
21 23
49
49
23
17 21 23
21 23
89
17 18 21 23
21 23
26
47 51
69
65 66 67
21 23
16
69
43
46 47
47
12 15
89
53 54
78
72
27
25
21 23
68
64
89
30
31
56
47 50
39
25
27
37
27
49
21 23
5 89 92
5 89
5 70
5 89
5 89 92
89
10 12 15 29
50 73
39
71
12 15 64
73
17 20 23 69
53 54
45
68
21 23
24
21 23
10 12 15 47 65
50 89
50
58 59
34
89 92 70 92
43
73
44
44
63
71
26
30 47
16
www.vinaﬁx.vn

II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
BRANCH
REVISION
DRAWING NUMBER SIZE
D
R
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
21
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
87 54 21
For EMC
EMC Spring (870-1577); Near DIMMs
DIMM CONNECTOR NUTS
4mm Plated Holes (998-0850)
PCH HEATSINK
MOUNTING ANCHORS (511-0057)
Standoffs (860-1255)
Nuts (805-9582)
Rear Cover
Backer Plate
Nuts (835-0269)
CPU Heatsink
1
ZH0700
OMIT
4P75R4
1
ZH0701
4P75R4
OMIT
1
ZH0702
OMIT
4P75R4
1
ZH0703
4P75R4
OMIT
1
SC0702
CRITICAL
CLIP-SM-K2
EMI-SPRING
NOSTUFF
1
SDF0713
CRITICAL
STDOFF-6.8OD15.0H-1.56-TH
1
NUT0700
CRITICAL
NUT-6.5OD1.4H-1.56-3.8-TH
1
NUT0701
CRITICAL
NUT-6.5OD1.4H-1.56-3.8-TH
1
NUT0702
NUT-6.5OD1.4H-1.56-3.8-TH
CRITICAL
1
NUT0753
NUT-4.25OD1.4H-1.40-3.25-TH
CRITICAL
1
NUT0752
NUT-4.25OD1.4H-1.40-3.25-TH
CRITICAL
1
NUT0751
NUT-4.25OD1.4H-1.40-3.25-TH
CRITICAL
1
NUT0750
NUT-4.25OD1.4H-1.40-3.25-TH
CRITICAL
1
SDF0714
CRITICAL
STDOFF-6.8OD15.0H-1.56-TH
1
SDF0715
STDOFF-6.8OD15.0H-1.56-TH
CRITICAL
1
SDF0717
STDOFF-6.8OD15.0H-1.56-TH
CRITICAL
1
SDF0718
STDOFF-6.8OD15.0H-1.56-TH
CRITICAL
2
1
AN0700
HSK-TH
HB9703E-SLH
CRITICAL
2
1
AN0701
CRITICAL
HSK-TH
HB9703E-SLH
Holes
SYNC_MASTER=K74_MASTER SYNC_DATE=N/A
7 OF 110
A.0.0
051-8337
6 OF 92
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II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
BRANCH
REVISION
DRAWING NUMBER SIZE
D
R
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
21
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
87 54 21
NC ON UNUSED NAND ALIASES
NC ON UNUSED PCIE ALIASES NC ON UNUSED DISPLAY ALIASES
NC ON UNUSED MISC ALIASES
NC ON UNUSED USB ALIASES
UNUSED CPU SIGNALS
NC ON UNUSED PCI ALIASES
NC ON UNUSED MEM ALIASES
NC ON UNUSED SATA ALIASES
NC ON UNUSED FDI ALIASES
SYNC_MASTER=K74_MASTER
UNUSED SIGNAL ALIAS
SYNC_DATE=N/A
NO_TEST=TRUE
NC_CPU_FDI_TXP<7..0>
MAKE_BASE=TRUE
NC_DMI_CLK100M_LAP
NO_TEST=TRUEMAKE_BASE=TRUE
PCIE_CLK100M_EXCARD_N NC_PCIE_CLK100M_EXCARDN
NO_TEST=TRUEMAKE_BASE=TRUE
NC_DP_IG_B_HPD
NO_TEST=TRUEMAKE_BASE=TRUE
TP_DP_IG_B_HPD
MAKE_BASE=TRUE
NC_DP_IG_B_MLP<3..0>
NO_TEST=TRUE
NC_DP_IG_C_MLN<3..0>
MAKE_BASE=TRUE NO_TEST=TRUE
NC_DP_IG_C_MLP<3..0>
MAKE_BASE=TRUE NO_TEST=TRUE
NC_PCIE_CLK100M_T28P
NO_TEST=TRUEMAKE_BASE=TRUE
PCIE_EXCARD_R2D_C_P
PCIE_EXCARD_D2R_N
TP_PCIE_CLK100M_T28_P
NC_PCIE_CLK100M_T28N
NO_TEST=TRUEMAKE_BASE=TRUE
TP_PCIE_CLK100M_T28_N
TP_PCIE_T28_R2D_C_P<3..0>
NC_USB_3P
MAKE_BASE=TRUE NO_TEST=TRUE
NO_TEST=TRUEMAKE_BASE=TRUE
NC_DP_IG_C_AUXP
NC_GFX_VSENSEP
NO_TEST=TRUEMAKE_BASE=TRUE
NC_GFX_VSENSEN
NO_TEST=TRUEMAKE_BASE=TRUE
TP_SATA_F_R2D_CP
TP_SATA_D_R2D_CN
TP_SATA_D_R2D_CP
TP_SATA_E_D2RN
NC_SATA_SSD_R2D_CP
MAKE_BASE=TRUE NO_TEST=TRUE
TP_SATA_SSD_D2R_P
TP_SATA_SSD_R2D_C_P
TP_SATA_SSD_R2D_C_N NC_SATA_SSD_R2D_CN
NO_TEST=TRUEMAKE_BASE=TRUE
NC_SATA_SSD_D2RN
MAKE_BASE=TRUE NO_TEST=TRUE
NC_SATA_SSD_D2RP
NO_TEST=TRUEMAKE_BASE=TRUE
TP_SATA_SSD_D2R_N
TP_SATA_D_D2RN
MAKE_BASE=TRUE NO_TEST=TRUE
NC_SATA_D_D2RP
MAKE_BASE=TRUE
NC_SATA_E_D2RN
NO_TEST=TRUE
NO_TEST=TRUEMAKE_BASE=TRUE
NC_DP_IG_D_MLN<3..0>
NO_TEST=TRUEMAKE_BASE=TRUE
NC_DP_IG_D_HPD
NC_SATA_F_R2D_CN
MAKE_BASE=TRUE NO_TEST=TRUE
NO_TEST=TRUEMAKE_BASE=TRUE
NC_SATA_F_R2D_CP
TP_SATA_F_R2D_CN
MAKE_BASE=TRUE NO_TEST=TRUE
NC_SATA_D_D2RN
TP_SATA_E_R2D_CP
NC_DP_IG_D_CTRL_DATA
MAKE_BASE=TRUE NO_TEST=TRUE
MAKE_BASE=TRUE NO_TEST=TRUE
NC_SATA_F_D2RP
NO_TEST=TRUE
NC_NV_WE_CK_L<1..0>
MAKE_BASE=TRUE
TP_NV_WE_CK_L<1..0>
TP_NV_RB_L
TP_NV_CE_L<3..0>
SNS_CPU_THERMD_P
TP_HDA_SDIN2
TP_PCH_PWM2
SNS_CPU_THERMD_N
TP_PCH_SST
TP_HDA_SDIN3
TP_JTAG_XDP_TRST_L
TP_PCI_RESET_L
TP_PCI_C_BE_L<3..0>
TP_PCI_AD<31..0>
TP_PCH_PWM0
TP_MEM_A_DQ_CB<7..0>
TP_MEM_B_DQ_CB<7..0>
TP_MEM_B_CS_L<7..4>
TP_MEM_A_CS_L<7..4>
TP_LPC_DREQ1_L
TP_NV_CLE
TP_NV_ALE
TP_NV_WR_RE_L<1..0>
TP_NV_RCOMP
TP_NV_DQ<15..0>
TP_LPC_DREQ0_L
TP_PCIE_CLK100M_XDPN
TP_PCI_PAR
TP_CPU_RSVD<41..29>
TP_CPU_RSVD<26..1>
TP_HDA_SDIN1
TP_PCH_PWM3
TP_PCH_PWM1
TP_CPU_FC_AG40
TP_CPU_FC_AE38
NC_CPU_RSVD<41..29>
NO_TEST=TRUEMAKE_BASE=TRUE
MAKE_BASE=TRUE NO_TEST=TRUE
NC_CPU_RSVD<26..1>
NO_TEST=TRUE
NC_CPU_FC_AE38
MAKE_BASE=TRUE
NC_PCI_AD<31..0>
MAKE_BASE=TRUE NO_TEST=TRUE
NC_PCI_C_BE_L<3..0>
NO_TEST=TRUEMAKE_BASE=TRUE
NO_TEST=TRUE
NC_PCI_PAR
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_PCIE_CLK100M_XDPP
MAKE_BASE=TRUE
NC_PCIE_CLK100M_XDPN
NO_TEST=TRUEMAKE_BASE=TRUE
TP_DMI_CLK100M_LAN
NC_LPC_DREQ0_L
NO_TEST=TRUEMAKE_BASE=TRUE
NO_TEST=TRUE
NC_NV_DQS<1..0>
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_NV_DQ<15..0>
MAKE_BASE=TRUE
MAKE_BASE=TRUE NO_TEST=TRUE
NC_NV_RB_L
NO_TEST=TRUEMAKE_BASE=TRUE
NC_NV_RCOMP
NO_TEST=TRUE
NC_NV_WR_RE_L<1..0>
MAKE_BASE=TRUE
NO_TEST=TRUEMAKE_BASE=TRUE
NC_NV_ALE
NO_TEST=TRUE
NC_NV_CLE
MAKE_BASE=TRUE
TP_MEM_A_DQS_P<8>
TP_MEM_A_DQS_N<8>
MAKE_BASE=TRUE NO_TEST=TRUE
NC_MEM_A_CS_L<7..4>
NO_TEST=TRUE
NC_MEM_A_DQ_CB<7..0>
MAKE_BASE=TRUE
NC_MEM_A_DQSN<8>
NO_TEST=TRUEMAKE_BASE=TRUE
NC_MEM_A_DQSP<8>
NO_TEST=TRUEMAKE_BASE=TRUE
NO_TEST=TRUE
NC_MEM_B_CS_L<7..4>
MAKE_BASE=TRUE
NO_TEST=TRUEMAKE_BASE=TRUE
NC_MEM_B_DQ_CB<7..0>
TP_MEM_B_DQS_N<8> NC_MEM_B_DQSN<8>
NO_TEST=TRUEMAKE_BASE=TRUE
NC_MEM_B_DQSP<8>
NO_TEST=TRUEMAKE_BASE=TRUE
NO_TEST=TRUE
NC_HDA_SDIN2
MAKE_BASE=TRUE
NO_TEST=TRUEMAKE_BASE=TRUE
NC_HDA_SDIN3
NC_JTAG_XDP_TRST_L
NO_TEST=TRUEMAKE_BASE=TRUE
NO_TEST=TRUEMAKE_BASE=TRUE
NC_PCH_PWM0
NO_TEST=TRUEMAKE_BASE=TRUE
NC_PCH_PWM1
NO_TEST=TRUE
NC_PCH_PWM3
MAKE_BASE=TRUE
NC_SNS_CPU_THERMDP
NO_TEST=TRUEMAKE_BASE=TRUE
NO_TEST=TRUEMAKE_BASE=TRUE
NC_PCH_SST
TP_PCIE_T28_D2R_P<3..0>
NC_PCIE_T28_R2D_CN<3..0>
MAKE_BASE=TRUE NO_TEST=TRUE
NC_DMI_CLK100M_LAN
MAKE_BASE=TRUE NO_TEST=TRUE
TP_CRT_IG_DDC_CLK
TP_CRT_IG_DDC_DATA
TP_CRT_IG_GREEN
TP_CRT_IG_HSYNC
TP_CRT_IG_VSYNC
TP_DP_IG_B_MLP<3..0>
TP_DP_IG_B_AUX_N
TP_DP_IG_B_AUX_P
TP_DP_IG_B_DDC_CLK
TP_DP_IG_B_DDC_DATA
TP_DP_IG_C_MLN<3..0>
TP_DP_IG_C_MLP<3..0>
TP_DP_IG_C_AUX_P
TP_DP_IG_C_HPD
TP_DP_IG_C_CTRL_CLK
TP_DP_IG_C_CTRL_DATA
TP_DP_IG_D_MLN<3..0>
TP_DP_IG_D_MLP<3..0>
TP_DP_IG_D_AUXN
TP_DP_IG_D_AUXP
TP_GFX_VSENSE_P
TP_SDVO_TVCLKINN
TP_SDVO_STALLP
TP_SDVO_STALLN
TP_SDVO_INTN
TP_SDVO_INTP
NC_PCIE_T28_R2D_CP<3..0>
MAKE_BASE=TRUE NO_TEST=TRUE
NC_PCIE_T28_D2RN<3..0>
MAKE_BASE=TRUE NO_TEST=TRUE
NO_TEST=TRUEMAKE_BASE=TRUE
NC_CPU_FC_AG40
TP_PCIE_T28_R2D_C_N<3..0>
TP_PCIE_T28_D2R_N<3..0>
NC_PCIE_EXCARD_D2RP
NO_TEST=TRUEMAKE_BASE=TRUE
PCIE_EXCARD_D2R_P
NC_PCIE_EXCARD_R2D_CN
NO_TEST=TRUEMAKE_BASE=TRUE
NC_PCIE_EXCARD_D2RN
NO_TEST=TRUEMAKE_BASE=TRUE
NC_PCIE_EXCARD_R2D_CP
NO_TEST=TRUEMAKE_BASE=TRUE
NC_PCIE_CLK100M_EXCARDP
MAKE_BASE=TRUE NO_TEST=TRUE
PCIE_CLK100M_EXCARD_P
NC_PCIE_CLK100M_PE5P
NO_TEST=TRUEMAKE_BASE=TRUE
TP_PCIE_CLK100M_PE5P
NO_TEST=TRUEMAKE_BASE=TRUE
NC_PCIE_CLK100M_PE5N
NC_DMI_MIDBUS_CLK100MP
NO_TEST=TRUEMAKE_BASE=TRUE
NC_DMI_MIDBUS_CLK100MN
NO_TEST=TRUEMAKE_BASE=TRUE
PCIE_EXCARD_R2D_C_N
DMI_MIDBUS_CLK100M_N
DMI_MIDBUS_CLK100M_P
TP_PCIE_CLK100M_PE5N
TP_DP_IG_D_CTRL_DATA
TP_DP_IG_D_CTRL_CLK
TP_DP_IG_D_HPD
MAKE_BASE=TRUE NO_TEST=TRUE
NC_USB_2NTP_USB_2N
MAKE_BASE=TRUE
NC_USB_1P
NO_TEST=TRUE
TP_USB_1P
MAKE_BASE=TRUE
NC_USB_1N
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_USB_3N
NO_TEST=TRUE
TP_USB_3N
MAKE_BASE=TRUE
NC_USB_2P
NO_TEST=TRUE
TP_USB_2P
TP_USB_3P
NC_USB_4P
MAKE_BASE=TRUE NO_TEST=TRUE
TP_USB_4P
TP_USB_4N
NC_USB_5N
NO_TEST=TRUEMAKE_BASE=TRUE
TP_USB_5N
MAKE_BASE=TRUE
NC_USB_5P
NO_TEST=TRUE
TP_USB_5P
MAKE_BASE=TRUE NO_TEST=TRUE
NC_USB_6NTP_USB_6N
MAKE_BASE=TRUE NO_TEST=TRUE
NC_USB_7NTP_USB_7N
NO_TEST=TRUE
NC_USB_6P
MAKE_BASE=TRUE
TP_USB_6P
NO_TEST=TRUE
NC_USB_7P
MAKE_BASE=TRUE
TP_USB_7P
MAKE_BASE=TRUE
NC_USB_9N
NO_TEST=TRUE
TP_USB_9N
TP_USB_9P
NC_USB_10N
MAKE_BASE=TRUE NO_TEST=TRUE
TP_USB_10N
NC_USB_10P
MAKE_BASE=TRUE NO_TEST=TRUE
TP_USB_10P
NO_TEST=TRUEMAKE_BASE=TRUE
NC_USB_11PTP_USB_11P
MAKE_BASE=TRUE
NC_USB_11N
NO_TEST=TRUE
TP_USB_11N
TP_USB_12N
NC_USB_12P
MAKE_BASE=TRUE NO_TEST=TRUE
TP_USB_12P
MAKE_BASE=TRUE
NC_USB_13N
NO_TEST=TRUE
TP_USB_13N
MAKE_BASE=TRUE
NC_USB_13P
NO_TEST=TRUE
TP_USB_13P
MAKE_BASE=TRUE
NC_USB_12N
NO_TEST=TRUE
NO_TEST=TRUEMAKE_BASE=TRUE
NC_USB_4N
TP_GFX_VSENSE_N
TP_GFX_VID<0..6>
TP_SDVO_TVCLKINP
MAKE_BASE=TRUE
NC_USB_9P
NO_TEST=TRUE
NO_TEST=TRUE
NC_HDA_SDIN1
MAKE_BASE=TRUE
TP_MEM_B_DQS_P<8>
TP_DP_IG_C_AUX_N
NO_TEST=TRUEMAKE_BASE=TRUE
NC_PCH_PWM2
NC_SNS_CPU_THERMDN
NO_TEST=TRUEMAKE_BASE=TRUE
NC_PCIE_T28_D2RP<3..0>
NO_TEST=TRUEMAKE_BASE=TRUE
TP_DMI_CLK100M_LAP
TP_PCIE_CLK100M_XDPP
TP_NV_DQS<1..0>
MAKE_BASE=TRUE NO_TEST=TRUE
NC_NV_CE_L<3..0>
NO_TEST=TRUE
NC_LPC_DREQ1_L
MAKE_BASE=TRUE
MAKE_BASE=TRUE
NC_PCI_RESET_L
NO_TEST=TRUE
TP_CRT_IG_RED
MAKE_BASE=TRUE
NC_CRT_IG_DDC_CLK
NO_TEST=TRUE
NC_CRT_IG_DDC_DATA
MAKE_BASE=TRUE NO_TEST=TRUE
NC_CRT_IG_RED
MAKE_BASE=TRUE NO_TEST=TRUE
MAKE_BASE=TRUE
NC_CRT_IG_GREEN
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_CRT_IG_BLUE
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_CRT_IG_HSYNC
NO_TEST=TRUE
NC_CRT_IG_VSYNC
NO_TEST=TRUEMAKE_BASE=TRUE
MAKE_BASE=TRUE NO_TEST=TRUE
NC_DP_IG_B_MLN<3..0>
NC_DP_IG_B_AUXN
MAKE_BASE=TRUE NO_TEST=TRUE
NO_TEST=TRUE
NC_DP_IG_B_AUXP
MAKE_BASE=TRUE
NC_DP_IG_B_CTRL_CLK
MAKE_BASE=TRUE NO_TEST=TRUE
NO_TEST=TRUEMAKE_BASE=TRUE
NC_DP_IG_B_CTRL_DATA
NC_DP_IG_C_AUXN
MAKE_BASE=TRUE NO_TEST=TRUE
NC_DP_IG_C_HPD
MAKE_BASE=TRUE NO_TEST=TRUE
NC_DP_IG_C_CTRL_CLK
MAKE_BASE=TRUE NO_TEST=TRUE
NC_DP_IG_C_CTRL_DATA
MAKE_BASE=TRUE NO_TEST=TRUE
NO_TEST=TRUEMAKE_BASE=TRUE
NC_DP_IG_D_MLP<3..0>
NO_TEST=TRUEMAKE_BASE=TRUE
NC_DP_IG_D_AUXN
NO_TEST=TRUEMAKE_BASE=TRUE
NC_DP_IG_D_AUXP
MAKE_BASE=TRUE
NC_DP_IG_D_CTRL_CLK
NO_TEST=TRUE
NC_GFX_VID<0..6>
MAKE_BASE=TRUE NO_TEST=TRUE
NC_SDVO_TVCLKINP
MAKE_BASE=TRUE NO_TEST=TRUE
MAKE_BASE=TRUE
NC_SDVO_TVCLKINN
NO_TEST=TRUE
NC_SDVO_STALLP
MAKE_BASE=TRUE NO_TEST=TRUE
MAKE_BASE=TRUE
NC_SDVO_STALLN
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_SDVO_INTN
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_SDVO_INTP
NO_TEST=TRUE
TP_DP_IG_B_MLN<3..0>
TP_CRT_IG_BLUE
NC_CPU_FDI_TXN<7..0>
MAKE_BASE=TRUE NO_TEST=TRUE
TP_CPU_FDI_TX_N<7..0>
TP_CPU_FDI_TX_P<7..0>
NO_TEST=TRUE
NC_PCH_FDI_RXN<7..0>
MAKE_BASE=TRUE
TP_PCH_FDI_RX_N<7..0>
NC_PCH_FDI_RXP<7..0>
MAKE_BASE=TRUE NO_TEST=TRUE
TP_PCH_FDI_RX_P<7..0>
MAKE_BASE=TRUE
NC_CPU_FDI_FSYNC<1..0>
NO_TEST=TRUE
TP_CPU_FDI_FSYNC<1..0>
NC_CPU_FDI_LSYNC<1..0>
MAKE_BASE=TRUE NO_TEST=TRUE
TP_CPU_FDI_LSYNC<1..0>
NO_TEST=TRUE
NC_PCH_FDI_FSYNC<1..0>
MAKE_BASE=TRUE
TP_PCH_FDI_FSYNC<1..0>
NO_TEST=TRUE
NC_CPU_FDI_INT
MAKE_BASE=TRUE
TP_CPU_FDI_INT
NO_TEST=TRUE
NC_PCH_FDI_LSYNC<1..0>
MAKE_BASE=TRUE
TP_PCH_FDI_LSYNC<1..0>
NC_PCH_FDI_INT
MAKE_BASE=TRUE NO_TEST=TRUE
TP_PCH_FDI_INT
NO_TEST=TRUE
NC_SATA_D_R2D_CN
MAKE_BASE=TRUE
TP_SATA_D_D2RP
NC_SATA_D_R2D_CP
NO_TEST=TRUEMAKE_BASE=TRUE
NC_SATA_E_D2RP
MAKE_BASE=TRUE NO_TEST=TRUE
TP_SATA_E_D2RP
NC_SATA_E_R2D_CN
NO_TEST=TRUEMAKE_BASE=TRUE
TP_SATA_E_R2D_CN
NO_TEST=TRUEMAKE_BASE=TRUE
NC_SATA_E_R2D_CP
TP_SATA_F_D2RP
NO_TEST=TRUEMAKE_BASE=TRUE
NC_SATA_F_D2RNTP_SATA_F_D2RN
TP_USB_1N
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II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
BRANCH
REVISION
DRAWING NUMBER SIZE
D
R
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
21
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
87 54 21
PEG Slot Support
THIS SIGNAL NAME IS CONNECTED TO MXM
76 84
76 84 9
9
76 84
76 84
9
9
17
17
18 85 91
21
R929
402
22
MF-LF
5%
1/16W
PLACEMENT_NOTE=PLACE CLOSE TO U1800
46 85 91
74 17
74
74
Signal Aliases
SYNC_MASTER=K74_MASTER SYNC_DATE=N/A
MAKE_BASE=TRUE
PEG_RESET_LMXM_RESET_L
CLK_100M_MXM_P
CLK_100M_MXM_N
MAKE_BASE=TRUE
PEG_R2D_C_N<0..15>
PEG_R2D_C_P<0..15>
MAKE_BASE=TRUE
GPU_CLK100M_PCIE_N
MAKE_BASE=TRUE
GPU_CLK100M_PCIE_P
MAKE_BASE=TRUE
=PEG_R2D_C_P<0..15>
PEG_CLKREQ_L MXM_CLKREQ_L
MAKE_BASE=TRUE
=PEG_D2R_N<0..15>
=PEG_R2D_C_N<0..15>
MAKE_BASE=TRUE
PEG_D2R_P<0..15>
PEG_CLK100M_P
PEG_CLK100M_N
MAKE_BASE=TRUE
PEG_D2R_N<0..15>
=PEG_D2R_P<0..15>
PM_CLK32K_SUSCLKPM_CLK32K_SUSCLK_R
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PEG_TX_2*
PEG_TX_15
PEG_TX_14
PEG_TX_10
PEG_TX_1
PEG_TX_2
PEG_TX_3
PEG_TX_4
PEG_TX_5
PEG_TX_6
PEG_TX_7
PEG_TX_8
PEG_TX_9
PEG_TX_11
PEG_TX_13
PEG_TX_12
PEG_TX_0
PEG_RCOMPO
PEG_ICOMPO
PEG_ICOMPI
PEG_RBIAS
PEG_RX_11
PEG_RX_12
PEG_RX_13
PEG_RX_14
PEG_RX_15
PEG_RX_14*
PEG_RX_15*
PEG_RX_13*
PEG_RX_12*
PEG_RX_10*
PEG_RX_11*
PEG_RX_9*
PEG_RX_8*
PEG_RX_7*
PEG_RX_6*
PEG_RX_5*
PEG_RX_4*
PEG_RX_3*
PEG_RX_2*
PEG_RX_1*
PEG_RX_0*
PEG_TX_0*
PEG_TX_1*
PEG_TX_3*
PEG_TX_4*
PEG_TX_7*
PEG_TX_8*
PEG_TX_9*
PEG_TX_10*
PEG_TX_11*
PEG_TX_12*
PEG_TX_13*
PEG_TX_15*
PEG_TX_6*
PEG_TX_14*
DMI_RX_1*
DMI_RX_2*
DMI_RX_3*
DMI_RX_1
DMI_RX_0
DMI_RX_2
DMI_RX_3
DMI_TX_2
DMI_TX_1
DMI_TX_0
DMI_TX_1*
DMI_TX_0*
FDI_TX_2*
FDI_TX_3*
FDI_TX_4*
FDI_TX_6*
FDI_TX_5*
FDI_TX_7*
FDI_TX_0
FDI_TX_1
FDI_TX_2
FDI_TX_4
FDI_TX_6
FDI_TX_5
FDI_FSYNC_0
FDI_TX_7
FDI_INT
FDI_FSYNC_1
FDI_LSYNC_0
FDI_LSYNC_1
PEG_TX_5*
DMI_TX_3*
DMI_TX_2*
FDI_TX_1*
FDI_TX_0*
DMI_TX_3
PEG_RX_0
PEG_RX_1
PEG_RX_2
PEG_RX_3
PEG_RX_4
PEG_RX_5
PEG_RX_6
PEG_RX_7
PEG_RX_8
PEG_RX_9
PEG_RX_10
FDI_TX_3
DMI_RX_0*
FLEXIBLE DISPLAY INTERFACE
PCI EXPRESS -- GRAPHICS
DMI
(1 OF 10)
RSVD_AM28
RSVD_AM27
RSVD_AK18
RSVD_AM21
RSVD_AH40
RSVD_AE2
RSVD_AJ39
RSVD_AK12
RSVD_AK13
RSVD_AK15
RSVD_AK16
RSVD_AK25
RSVD_AK28
RSVD_AK27
RSVD_AK26
RSVD_AK14
RSVD_AD2
RSVD_AM26
RSVD_TP_AN11
RSVD_AL17
RSVD_AM13
RSVD_A12
CFG_1
RSVD_AL26
RSVD_NCTF_AY37
RSVD_NCTF_AY3
RSVD_NCTF_AW38
RSVD_NCTF_B3
RSVD_NCTF_C2
RSVD_NCTF_D1
RSVD_AM30
RSVD_AM29
RSVD_AM25
RSVD_AM20
RSVD_AM18
RSVD_AM17
RSVD_AM16
RSVD_AM15
RSVD_AM14
RSVD_L12
RSVD_M12
RSVD_AL15
RSVD_AL14
CFG_0
CFG_5
CFG_4
CFG_3
CFG_2
RSVD_AL29
RSVD_AL27
RSVD_AL18
CFG_10
CFG_8
CFG_9
CFG_7
CFG_6
CFG_15
CFG_12
CFG_13
CFG_14
CFG_11
CFG_17
CFG_16
RSVD_NCTF_A4
RSVD_NCTF_AU40
RSVD_NCTF_AV1
RSVD_NCTF_AV39
RSVD_NCTF_AW2
RSVD_AM19
RSVD_AK29
RSVD_AL12
(5 OF 10)
RESERVED
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
BRANCH
REVISION
DRAWING NUMBER SIZE
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IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
21
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
87 54 21
INTEL SUGGESTS TO KEEP THESE TPS
CFG3 :PCIE LANE REVERSAL 1 = NORMAL OPERATION 0 = LANES REVERSED
FOR LYNNFIELD PROCESSOR
CFG4 :NOT USED ON DESKTOP
PLACE R1010 AND R1012 CLOSE TO CPU BALLS
FOR CLARKDALE PROCESSOR
CFG [1:0] :PCIE CONFIGURATION SELECT 11 = 1 X16 PCI EXPRESS 10 = 2 X8 PCI EXPRESS
18 84
18 84
18 84
18 84
18 84
18 84
18 84
18 84
18 84
18 84
18 84
18 84
18 84
18 84
18 84
18 84
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
2
1
R1012
750
1/16W
402
MF-LF
1%
2
1
R1010
402
MF-LF
49.9
1%
1/16W
24 84
24 84
24 84
24 84
24 84
24 84
24 84
24 84
24 84
24 84
24 84
24 84
24 84
24 84
14 24 84
24 84
24 84
24 84
U1000
OMIT
LYNNFIELD
LGA1156-SKT
AN11
D1
C2
B3
AY37
AY3
AW38
AW2
AV39
AV1
AU40
A4
M12
L12
AM30
AM29
AM28
AM27
AM26
AM25
AM21
AM20
AM19
AM18
AM17
AM16
AM15
AM14
AM13
AL29
AL27
AL26
AL18
AL17
AL15
AL14
AL12
AK29
AK28
AK27
AK26
AK25
AK18
AK16
AK15
AK14
AK13
AK12
AJ39
AH40
AE2
AD2
A12
H12
G12
F9
E9
H9
H10
F10
E10
L11
H7
K12
K9
L8
J12
K8
K10
G8
E8
U1000
LYNNFIELD
OMIT
LGA1156-SKT
CPU DMI/PEG/FDI/RSVD
SYNC_MASTER=K74_MASTER SYNC_DATE=N/A
TP_CPU_FDI_TX_P<5>
TP_CPU_FDI_FSYNC<0>
TP_CPU_FDI_LSYNC<0>
TP_CPU_FDI_INT
TP_CPU_FDI_LSYNC<1>
TP_CPU_FDI_TX_P<4>
=PEG_D2R_P<8>
=PEG_R2D_C_N<1>
=PEG_D2R_P<15>
TP_CPU_FDI_FSYNC<1>
TP_CPU_FDI_TX_P<7>
=PEG_R2D_C_N<2>
DMI_N2S_P<1>
DMI_N2S_P<0>
DMI_N2S_N<3>
DMI_N2S_N<2>
DMI_N2S_N<1>
DMI_N2S_N<0>
DMI_S2N_N<2>
=PEG_D2R_N<9>
DMI_S2N_P<3>
=PEG_R2D_C_N<14>
=PEG_R2D_C_P<0>
=PEG_R2D_C_P<1>
=PEG_R2D_C_P<2>
=PEG_D2R_N<8>
=PEG_D2R_N<11>
=PEG_D2R_P<7>
=PEG_D2R_P<11>
CPU_CFG<13>
CPU_CFG<15>
CPU_CFG<17>
CPU_CFG<1>
CPU_CFG<2>
CPU_CFG<10>
CPU_CFG<6>
CPU_CFG<9>
CPU_CFG<5>
CPU_CFG<0>
CPU_CFG<4>
CPU_CFG<12>
CPU_CFG<8>
TP_CPU_RSVD<32>
SNS_CPU_THERMD_N
TP_CPU_RSVD<22>
TP_CPU_RSVD<24>
=PEG_D2R_P<0>
CPU_CFG<14>
CPU_PEG_COMP
=PEG_D2R_N<0>
CPU_PEG_RBIAS
=PEG_D2R_P<4>
=PEG_R2D_C_N<4>
=PEG_R2D_C_P<3>
=PEG_D2R_P<2>
=PEG_D2R_N<15>
=PEG_D2R_N<10>
=PEG_D2R_N<7>
=PEG_D2R_N<6>
=PEG_D2R_N<5>
=PEG_D2R_N<4>
=PEG_D2R_N<3>
=PEG_R2D_C_N<5>
TP_CPU_FDI_TX_N<1>
TP_CPU_FDI_TX_N<2>
TP_CPU_FDI_TX_N<3>
=PEG_D2R_N<14>
TP_CPU_RSVD<21>
TP_CPU_RSVD<25>
TP_CPU_RSVD<26>
SNS_CPU_THERMD_P
TP_CPU_RSVD<39>
TP_CPU_RSVD<41>
TP_CPU_RSVD_NCTF<1>
TP_CPU_RSVD_NCTF<2>
TP_CPU_RSVD_NCTF<4>
TP_CPU_RSVD<7>
TP_CPU_RSVD<6>
DMI_S2N_N<0>
DMI_S2N_N<1>
TP_CPU_RSVD<11>
TP_CPU_RSVD<33>
TP_CPU_RSVD<4>
TP_CPU_RSVD<3>
TP_CPU_RSVD<5>
TP_CPU_RSVD<9>
TP_CPU_RSVD<12>
TP_CPU_RSVD<15>
TP_CPU_RSVD<14>
TP_CPU_RSVD<13>
TP_CPU_RSVD<8>
TP_CPU_RSVD<2>
TP_CPU_RSVD_TP<1>
TP_CPU_RSVD<20>
TP_CPU_RSVD_NCTF<7>
TP_CPU_RSVD_NCTF<6>
TP_CPU_RSVD_NCTF<10>
TP_CPU_RSVD_NCTF<11>
TP_CPU_RSVD<34>
TP_CPU_RSVD<29>
TP_CPU_RSVD<40>
TP_CPU_RSVD<19>
TP_CPU_RSVD<18>
CPU_CFG<3>
TP_CPU_RSVD<23>
CPU_CFG<11>
CPU_CFG<16>
TP_CPU_RSVD_NCTF<3>
TP_CPU_RSVD_NCTF<5>
TP_CPU_RSVD<31>
TP_CPU_RSVD<16>
TP_CPU_RSVD<17>
=PEG_R2D_C_P<15>
=PEG_R2D_C_P<14>
=PEG_R2D_C_P<10>
=PEG_R2D_C_P<4>
=PEG_R2D_C_P<5>
=PEG_R2D_C_P<6>
=PEG_R2D_C_P<7>
=PEG_R2D_C_P<8>
=PEG_R2D_C_P<9>
=PEG_R2D_C_P<11>
=PEG_R2D_C_P<13>
=PEG_R2D_C_P<12>
=PEG_D2R_P<12>
=PEG_D2R_P<14>
=PEG_D2R_N<12>
=PEG_D2R_N<1>
=PEG_R2D_C_N<3>
=PEG_R2D_C_N<7>
=PEG_R2D_C_N<9>
=PEG_R2D_C_N<11>
=PEG_R2D_C_N<12>
=PEG_R2D_C_N<13>
=PEG_R2D_C_N<6>
DMI_S2N_N<3>
TP_CPU_FDI_TX_N<6>
TP_CPU_FDI_TX_N<7>
TP_CPU_FDI_TX_P<1>
=PEG_D2R_P<1>
=PEG_D2R_P<9>
=PEG_D2R_P<10>
=PEG_R2D_C_N<8>
=PEG_R2D_C_N<10>
TP_CPU_RSVD<30>
TP_CPU_RSVD<35>
TP_CPU_RSVD<36>
TP_CPU_RSVD<37>
TP_CPU_RSVD<38>
TP_CPU_RSVD_NCTF<9>
TP_CPU_RSVD_NCTF<8>
TP_CPU_RSVD<10>
CPU_CFG<7>
=PEG_R2D_C_N<15>
TP_CPU_FDI_TX_P<0>
TP_CPU_RSVD<1>
=PEG_D2R_N<2>
=PEG_R2D_C_N<0>
=PEG_D2R_P<13>
=PEG_D2R_P<3>
=PEG_D2R_P<5>
=PEG_D2R_P<6>
TP_CPU_FDI_TX_N<5>
TP_CPU_FDI_TX_P<2>
TP_CPU_FDI_TX_P<3>
TP_CPU_FDI_TX_P<6>
TP_CPU_FDI_TX_N<4>
DMI_N2S_P<2>
TP_CPU_FDI_TX_N<0>
DMI_N2S_P<3>
DMI_S2N_P<2>
=PEG_D2R_N<13>
DMI_S2N_P<1>
DMI_S2N_P<0>
10 OF 110
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051-8337
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IN
IN
RSTIN*
TAPPWRGOOD
VTTPWRGOOD
SM_DRAMPWROK
VCCPWRGOOD_0
VCCPWRGOOD_1
PM_SYNC
RESET_OBS*
THERMTRIP*
TDO
COMP3
BPM_7*
BPM_4*
BPM_6*
BPM_5*
BPM_2*
BPM_3*
BPM_0*
BPM_1*
DBR*
TDO_M
TDI_M
TDI
TRST*
TMS
PREQ*
TCK
PM_EXT_TS_1*
PM_EXT_TS_0*
PRDY*
SM_RCOMP_0
SM_RCOMP_1
SM_RCOMP_2
SM_DRAMRST*
PEG_CLK*
PEG_CLK
BCLK_ITP*
BCLK_ITP
BCLK_1*
BCLK_1
BCLK_0*
BCLK_0
SKTOCC*
COMP0
PROCHOT*
PECI
COMP2
CATERR*
COMP1
DDR3 MISC
JTAG & MBP
(2 OF 10)
CLOCKS
THERMAL
MISC
PWR MANAGEMENT
IN
IN
IN
OUT
IN
OUT
IN
IN
IN
G
D
S
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
BRANCH
REVISION
DRAWING NUMBER SIZE
D
R
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
21
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
87 54 21
BACKUP SOLUTION (FOR CLEANER EDGE): PULL TO 1.5V (DIVIDED) AND DELAY PGOOD. NO-STUFF R1122, STUFF CIRCUIT BELOW
C1180 CAN BE TUNED FOR SPECIFIC DELAY
COMES FROM VTT VR
(GND)
CPU RESET LEVEL SHIFTER
PRIMARY SOLUTION: PULL PM_MEM_PWRGD TO CPU VTT, WHICH RISES SEVERAL MS AFTER 1.5V. STUFF R1122
R1180-R1182 PROVIDE OPTIONS TO TRIGGER FROM RISE OF 1.5V, OR FROM PGOOD
PM_MEM_PWRGD MUST ASSERT MIN. 100 NS AFTER =PP1V5_CPU_MEM IS STABLE
26 91
21
R1180
1/16W
NOSTUFF
0
5%
MF-LF
402
73 91
10 18 91
63 64 68 91
24 91
24 91
20
47
20 47 91
2
1
R1101
402
1/16W
MF-LF
5%
51
2
1
R1100
1/16W
5%
51
MF-LF
402
2
1
R1112
49.9
PLACE R1112 CLOSE TO AF2
402
MF-LF
1/16W
1%
2
1
R1113
PLACE R1113 CLOSE TO AF36
MF-LF
1%
1/16W
49.9
402
2
1
R1110
1/16W
402
1%
MF-LF
20
PLACE R1110 CLOSE TO C11
2
1
R1111
MF-LF
PLACE R1111 CLOSE TO B11
402
20
1/16W
1%
24
24
24
24
24
24
24 84
24 27 91
24
24 84
24 84
24 84
24 84
24 84
24 84
24 84
2
1
R1162
402
1/16W
MF-LF
100
1%
PLACE R1162 CLOSE TO AG1
2
1
R1160
130
402
1/16W
MF-LF
1%
PLACE R1160 CLOSE TO AE1
2
1
R1161
1/16W
MF-LF
402
1%
24.9
PLACE R1161 CLOSE TO AD1
20 84
2
1
R1170
MF-LF
51
5%
1/16W
402
20 24 91
2
1
R1122
1.1K
1%
1/16W
402
MF-LF
2
1
R1103
1K
MF-LF
402
1/16W
5%
AG37
AH36
AH35
AM39
AN40
AF35
AF38
AM38
AF37
AM37
AN37
AK34
AE1
AD1
AG1
AV8
AH37
AK38
AF34
AL39
AH34
AK37
AJ38
AH39
AB4
AB5
AA4
AA3
AG35
AL40
C11
B11
AF2
AF36
AG39
AK31
AK30
AL30
AM31
AK32
AK33
AL32
AL33
AK40
AK39
Y8
AA8
AA6
AA7U1000
LGA1156-SKT
OMIT
LYNNFIELD
20 84
17 84
17 84
24 84
17 84
24 84
17 84
18 91
2
1
C1100
NOSTUFF
402
16V
10%
0.1UF
X7R-CERM
2
1
R1104
1/16W
5%
MF-LF
51
402
1
6
2
Q1177
SOT-363-LF
MMDT3904-X-G
4
3
5
Q1177
SOT-363-LF
MMDT3904-X-G
2
1
R1127
1%
MF-LF
1/16W
402
150
2
1
R1126
MF-LF
1%
1/16W
10K
402
21
R1125
10K
1/16W
MF-LF
1%
402
27 91
1
2
6
Q1180
SOT-563
NOSTUFF
DMB53D0UV
2
1
R1183
10K
1/16W
5%
MF-LF
402
NOSTUFF
2
1
R1181
NOSTUFF
27.4K
1%
402
1/16W
MF-LF
4
3
5 Q1180
NOSTUFF
SOT-563
DMB53D0UV
2
1
C1180
CERM
50V
402
5%
100PF
NOSTUFF
2
1
R1182
1/16W
MF-LF
402
33.2K
NOSTUFF
1%
2
1
R1120
NOSTUFF
402
1/16W
MF-LF
1%
1.1K
2
1
R1121
NOSTUFF
1/16W
MF-LF
1%
402
3.01K
SYNC_DATE=N/ASYNC_MASTER=K74_MASTER
CPU CLOCK/MISC/JTAG
PGOOD_P1V5_S0_DLY
PM_MEM_PWRGD
=PP1V5_CPU_MEM
CPU_PWRGD
=PP3V3_S5_PWRCTL
PGOOD_P1V5_S0
FSB_CPURSTOUT_L
PM_THRMTRIP_L
PLT_RESET_LS1V1_L
CPU_COMP2
XDP_CPUPWRGD
PM_MEM_PWRGD
CPU_PROCHOT_L
PM_MEM_PWRGD_L
=PP1V5_CPU_MEM
CPU_COMP0
=PPVTT_S0_CPU
CPU_COMP3
PM_SYNC
PLT_RESET_LS3V3
=PPVTT_S0_CPU
CPU_COMP1
CPUVTT_REG_PGOOD
CPU_RESET_L CPU_RESET_L_R
PLT_RESET_LS1V1_L
=PP3V3_S5_CPURESET =PPVTT_S0_CPU
PCIE_CLK100M_CPU_P
PCIE_CLK100M_CPU_N
XDP_BPM_L<4>
GFX_CLK120M_DPLLSS_N
FSB_CLK133M_CPU_P
XDP_BPM_L<5>
XDP_TDI
XDP_TDO
XDP_DBRESET_L
XDP_BPM_L<1>
XDP_BPM_L<2>
XDP_BPM_L<6>
XDP_TRST_L
XDP_BPM_L<7>
FSB_CLK133M_CPU_N
XDP_PREQ_L
XDP_TCK
XDP_TMS
CPU_TDO_M_TDI_M
CPU_PECI
FSB_CLK133M_ITP_N
FSB_CLK133M_ITP_P
GFX_CLK120M_DPLLSS_P
CPU_CATERR_L
XDP_BPM_L<0>
XDP_BPM_L<3>
CPU_SM_RCOMP0
CPU_SM_RCOMP1
CPU_MEM_RESET_L
XDP_PRDY_L
CPU_SKTOCC_L
=PPVTT_S0_CPU
CPU_SM_RCOMP2
11 OF 110
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84
5 10 12 15 47 65
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5 10 12 15 47 65
84
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5 5 10 12 15 47 65
83
83
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OUT
SA_ECC_CB_7
SA_ECC_CB_6
SA_ECC_CB_5
SA_ECC_CB_3
SA_ECC_CB_4
SA_ECC_CB_2
SA_ECC_CB_1
SA_ECC_CB_0
SA_MA_15
SA_MA_14
SA_MA_13
SA_MA_12
SA_MA_11
SA_MA_9
SA_MA_10
SA_MA_7
SA_MA_6
SA_MA_8
SA_MA_4
SA_MA_5
SA_MA_1
SA_MA_2
SA_MA_3
SA_MA_0
SA_DQS_8
SA_DQS_6
SA_DQS_7
SA_DQS_5
SA_DQS_4
SA_DQS_3
SA_DQS_2
SA_DQS_1
SA_DQS_0
SA_DQS_8*
SA_DQS_7*
SA_DQS_5*
SA_DQS_6*
SA_DQS_4*
SA_DQS_3*
SA_DQS_2*
SA_DQS_1*
SA_DQS_0*
SA_CS_3*
SA_CS_2*
SA_CS_1*
SA_CS_0*
SA_CS_4*
SA_CS_7*
SA_CS_6*
SA_CS_5*
SA_CK_2*
SA_CK_1*
SA_CK_0*
SA_DIMM_VREFDQ
SA_WE*
SA_RAS*
SA_CAS*
SA_DQ_6
SA_DQ_5
SA_DQ_13
SA_DQ_18
SA_DQ_17
SA_CKE_0
SA_DQ_7
SA_DQ_62
SA_DQ_61
SA_DQ_63
SA_BS_1
SA_BS_2
SA_BS_0
SA_DQ_52
SA_DQ_54
SA_DQ_53
SA_DQ_56
SA_DQ_57
SA_DQ_55
SA_DQ_58
SA_DQ_59
SA_DQ_60
SA_DQ_51
SA_DQ_42
SA_DQ_41
SA_DQ_43
SA_DQ_46
SA_DQ_47
SA_DQ_49
SA_DQ_48
SA_DQ_50
SA_DQ_45
SA_DQ_44
SA_DQ_40
SA_DQ_34
SA_DQ_36
SA_DQ_38
SA_DQ_39
SA_DQ_33
SA_DQ_35
SA_DQ_37
SA_DQ_20
SA_DQ_21
SA_DQ_23
SA_DQ_22
SA_DQ_24
SA_DQ_25
SA_DQ_26
SA_DQ_27
SA_DQ_28
SA_DQ_11
SA_DQ_12
SA_DQ_16
SA_DQ_15
SA_DQ_19
SA_DQ_10
SA_DQ_14
SA_DQ_9
SA_DQ_8
SA_DQ_0
SA_DQ_1
SA_DQ_4
SA_DQ_2
SA_DQ_3
SA_CK_0
SA_DQ_29
SA_DQ_30
SA_DQ_31
SA_DQ_32
SA_CK_1
SA_CKE_1
SA_CK_2
SA_CKE_2
SA_CK_3
SA_CKE_3
SA_ODT_0
SA_ODT_2
SA_ODT_1
SA_ODT_3
SA_DM_0
SA_DM_2
SA_DM_1
SA_DM_3
SA_DM_4
SA_DM_5
SA_DM_6
SA_DM_7
SA_CK_3*
(3 OF 10)
DDR SYSTEM MEMORY A
SB_DQS_2*
SB_DQS_0*
SB_DQS_1*
SB_DQS_5*
SB_DQS_6*
SB_DQS_7*
SB_DQS_8*
SB_DQS_3*
SB_DQS_4*
SB_CS_0*
SB_CS_2*
SB_CS_3*
SB_CS_1*
SB_CS_7*
SB_CS_6*
SB_CS_5*
SB_CS_4*
SB_CK_2*
SB_DQ_16
SB_DQ_1
SB_DQ_0
SB_DQ_8
SB_DQ_9
SB_DQ_52
SB_DQ_51
SB_DQ_38
SB_DQ_39
SB_DQ_63
SB_DQ_62
SB_DQ_61
SB_BS_2
SB_BS_0
SB_BS_1
SB_DQ_60
SB_DQ_59
SB_DQ_58
SB_DQ_57
SB_DQ_56
SB_DQ_55
SB_DQ_54
SB_DQ_53
SB_DQ_49
SB_DQ_47
SB_DQ_48
SB_DQ_46
SB_DQ_44
SB_DQ_45
SB_DQ_42
SB_DQ_41
SB_DQ_43
SB_DQ_50
SB_DQ_40
SB_DQ_33
SB_DQ_37
SB_DQ_35
SB_DQ_34
SB_DQ_36
SB_DQ_32
SB_DQ_31
SB_DQ_27
SB_DQ_26
SB_DQ_25
SB_DQ_24
SB_DQ_23
SB_DQ_22
SB_DQ_21
SB_DQ_20
SB_DQ_19
SB_DQ_18
SB_DQ_17
SB_DQ_15
SB_DQ_14
SB_DQ_13
SB_DQ_12
SB_DQ_11
SB_DQ_7
SB_DQ_6
SB_DQ_5
SB_DQ_4
SB_DQ_2
SB_DQ_3
SB_DIMM_VREFDQ SB_MA_15
SB_MA_10
SB_MA_12
SB_MA_11
SB_MA_13
SB_MA_14
SB_MA_8
SB_MA_9
SB_MA_7
SB_MA_6
SB_MA_5
SB_MA_4
SB_MA_2
SB_MA_1
SB_MA_0
SB_MA_3
SB_DQS_8
SB_DQS_6
SB_DQS_5
SB_DQS_4
SB_DQS_3
SB_DQS_1
SB_DQS_2
SB_DQS_0
SB_ECC_CB_0
SB_ECC_CB_1
SB_ECC_CB_2
SB_ECC_CB_3
SB_ECC_CB_5
SB_ECC_CB_4
SB_ECC_CB_6
SB_ECC_CB_7
SB_DM_7
SB_DM_6
SB_DM_5
SB_DM_4
SB_DM_2
SB_DM_0
SB_ODT_3
SB_ODT_2
SB_ODT_1
SB_ODT_0
SB_CKE_3
SB_CK_3
SB_CKE_2
SB_CKE_1
SB_CK_2
SB_CK_1
SB_CKE_0
SB_CK_0
SB_DQS_7
SB_DM_3
SB_DM_1
SB_DQ_10
SB_DQ_28
SB_DQ_29
SB_DQ_30
SB_WE*
SB_CK_3*
SB_CK_1*
SB_CAS*
SB_CK_0*
SB_RAS*
(4 OF 10)
DDR SYSTEM MEMORY B
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OUTOUT OUT
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
BRANCH
REVISION
DRAWING NUMBER SIZE
D
R
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
21
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
87 54 21
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31 83
31 83
AT22
AT20
AY24
AW23
AV24
AV23
AW12
AU14
AW13
AV14
AY13
AW14
AU15
AV15
AR10
AT11
AU24
AW11
AU13
AT19
AY15
AW18
AM11
AK11
AL9
AK9
AP11
AR11
AN10
AP10
AM10
AL10
AR38
AR39
AV35
AW36
AW32
AV32
AT29
AR28
AW6
AY6
AU3
AU4
AP3
AP2
AJ3
AK3
AN2
AN3
AK2
AP40
AP39
AU39
AU38
AK1
AN39
AN38
AT40
AT39
AW37
AV36
AW34
AY34
AU37
AV37
AH2
AY35
AW35
AW33
AU33
AW30
AV30
AU34
AV33
AU31
AU30
AG2
AN30
AR29
AR27
AN26
AP30
AP28
AT28
AN27
AW7
AV7
AL1
AV5
AU5
AY8
AU8
AY5
AW5
AV4
AV2
AT1
AT3
AL2
AW4
AW3
AU2
AT4
AR4
AP1
AM2
AM3
AR2
AR3
AJ4
AH1
AT38
AU35
AW31
AN29
AV6
AU1
AN1
AJ2
AF3
AK23
AL23
AM22
AK22
AU23
AU21
AW24
AV21
AY10
AV10
AW10
AU10
AN19
AP19
AP21
AN21
AN18
AP18
AR21
AR22
AU22
AU12
AU19
AV20
U1000
OMIT
LGA1156-SKT
LYNNFIELD
AU26
AW26
AU28
AV27
AU29
AU27
AY16
AT17
AU16
AW17
AV17
AY18
AU17
AV18
AV11
AY12
AW28
AW15
AW16
AY25
AU18
AU20
AP13
AN14
AN12
AM12
AP14
AN15
AT13
AR12
AR13
AR14
AM36
AL37
AR37
AR36
AR32
AP32
AR24
AT25
AP8
AR8
AM6
AN6
AJ5
AH6
AE5
AF4
AH7
AG5
AE6
AL36
AJ35
AM34
AN35
AF5
AJ37
AJ36
AM35
AL35
AP37
AN34
AT35
AP34
AP36
AN33
AC6
AT36
AR35
AT33
AR34
AR31
AT31
AM32
AR33
AP31
AT32
AC7
AT26
AP25
AP22
AT23
AR26
AR25
AP23
AN23
AT9
AL8
AJ8
AR6
AN8
AM8
AR9
AR7
AT6
AP5
AN7
AM4
AL5
AH8
AR5
AP6
AN5
AL6
AK7
AJ7
AG4
AG6
AL4
AK6
AD6
AD7
AK35
AM33
AN32
AN24
AT7
AM7
AH4
AE4
AG3
AK24
AL24
AM24
AM23
AV29
AV26
AW29
AY27
AV9
AU9
AY9
AW8
AR18
AR19
AN16
AN17
AR15
AT15
AR16
AR17
AW27
AV12
AW25
AU25
U1000
OMIT
LGA1156-SKT
LYNNFIELD
28 83
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30 83
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28 83 30 83 31 83
CPU DDR3 INTERFACES
SYNC_MASTER=K74_MASTER SYNC_DATE=N/A
MEM_A_CLK_P<0>
MEM_A_CLK_P<1>
MEM_A_CLK_N<2>
MEM_A_CLK_N<3>
MEM_A_CLK_N<0>
MEM_A_CKE<0>
MEM_A_CLK_N<1>
MEM_A_CKE<2>
MEM_A_CLK_P<3>
TP_MEM_A_CS_L<5>
TP_MEM_A_CS_L<6>
TP_MEM_A_CS_L<7>
MEM_A_ODT<0>
MEM_A_ODT<1>
MEM_A_DM<2>
MEM_A_DM<3>
MEM_A_DM<4>
MEM_A_DM<5>
MEM_A_DM<6>
MEM_A_DM<7>
MEM_A_DM<1>
MEM_A_DM<0>
MEM_A_ODT<3>
MEM_A_ODT<2>
MEM_A_CKE<3>
MEM_A_CLK_P<2>
MEM_A_CKE<1>
MEM_A_DQ<32>
MEM_A_DQ<31>
MEM_A_DQ<30>
MEM_A_DQ<29>
MEM_A_DQ<3>
MEM_A_DQ<2>
MEM_A_DQ<4>
MEM_A_DQ<0>
MEM_A_DQ<8>
MEM_A_DQ<9>
MEM_A_DQ<14>
MEM_A_DQ<10>
MEM_A_DQ<19>
MEM_A_DQ<15>
MEM_A_DQ<16>
MEM_A_DQ<12>
MEM_A_DQ<11>
MEM_A_DQ<28>
MEM_A_DQ<27>
MEM_A_DQ<26>
MEM_A_DQ<25>
MEM_A_DQ<24>
MEM_A_DQ<22>
MEM_A_DQ<23>
MEM_A_DQ<21>
MEM_A_DQ<20>
MEM_A_DQ<37>
MEM_A_DQ<35>
MEM_A_DQ<33>
MEM_A_DQ<39>
MEM_A_DQ<38>
MEM_A_DQ<36>
MEM_A_DQ<34>
MEM_A_DQ<40>
MEM_A_DQ<44>
MEM_A_DQ<45>
MEM_A_DQ<50>
MEM_A_DQ<48>
MEM_A_DQ<49>
MEM_A_DQ<47>
MEM_A_DQ<46>
MEM_A_DQ<43>
MEM_A_DQ<41>
MEM_A_DQ<42>
MEM_A_DQ<51>
MEM_A_DQ<60>
MEM_A_DQ<59>
MEM_A_DQ<58>
MEM_A_DQ<55>
MEM_A_DQ<57>
MEM_A_DQ<56>
MEM_A_DQ<53>
MEM_A_DQ<54>
MEM_A_DQ<52>
MEM_A_BA<0>
MEM_A_BA<2>
MEM_A_BA<1>
MEM_A_DQ<63>
MEM_A_DQ<61>
MEM_A_DQ<62>
MEM_A_DQ<7>
MEM_A_DQ<17>
MEM_A_DQ<18>
MEM_A_DQ<13>
MEM_A_DQ<5>
MEM_A_DQ<6>
MEM_A_CAS_L
MEM_A_RAS_L
MEM_A_WE_L
CPU_DIMM_VREF_A
TP_MEM_A_CS_L<4>
MEM_A_CS_L<2>
MEM_A_CS_L<3>
MEM_A_DQS_N<0>
MEM_A_DQS_N<1>
MEM_A_DQS_N<2>
MEM_A_DQS_N<3>
MEM_A_DQS_N<4>
MEM_A_DQS_N<6>
MEM_A_DQS_N<5>
MEM_A_DQS_N<7>
TP_MEM_A_DQS_N<8>
MEM_A_DQS_P<0>
MEM_A_DQS_P<1>
MEM_A_DQS_P<2>
MEM_A_DQS_P<3>
MEM_A_DQS_P<4>
MEM_A_DQS_P<5>
MEM_A_DQS_P<7>
MEM_A_DQS_P<6>
TP_MEM_A_DQS_P<8>
MEM_A_A<0>
MEM_A_A<3>
MEM_A_A<2>
MEM_A_A<1>
MEM_A_A<5>
MEM_A_A<4>
MEM_A_A<8>
MEM_A_A<6>
MEM_A_A<7>
MEM_A_A<10>
MEM_A_A<9>
MEM_A_A<11>
MEM_A_A<12>
MEM_A_A<13>
MEM_A_A<14>
MEM_A_A<15>
TP_MEM_A_DQ_CB<0>
TP_MEM_A_DQ_CB<1>
TP_MEM_A_DQ_CB<2>
TP_MEM_A_DQ_CB<4>
TP_MEM_A_DQ_CB<3>
TP_MEM_A_DQ_CB<5>
TP_MEM_A_DQ_CB<6>
TP_MEM_A_DQ_CB<7>
MEM_B_RAS_L
MEM_B_CLK_N<0>
MEM_B_CAS_L
MEM_B_CLK_N<1>
MEM_B_CLK_N<3>
MEM_B_WE_L
MEM_B_DQ<30>
MEM_B_DQ<29>
MEM_B_DQ<28>
MEM_B_DQ<10>
MEM_B_DM<1>
MEM_B_DM<3>
MEM_B_DQS_P<7>
MEM_B_CLK_P<0>
MEM_B_CKE<0>
MEM_B_CLK_P<1>
MEM_B_CLK_P<2>
MEM_B_CKE<1>
MEM_B_CKE<2>
MEM_B_CLK_P<3>
MEM_B_CKE<3>
MEM_B_ODT<0>
MEM_B_ODT<1>
MEM_B_ODT<2>
MEM_B_ODT<3>
MEM_B_DM<0>
MEM_B_DM<2>
MEM_B_DM<4>
MEM_B_DM<5>
MEM_B_DM<6>
MEM_B_DM<7>
TP_MEM_B_DQ_CB<7>
TP_MEM_B_DQ_CB<6>
TP_MEM_B_DQ_CB<4>
TP_MEM_B_DQ_CB<5>
TP_MEM_B_DQ_CB<3>
TP_MEM_B_DQ_CB<2>
TP_MEM_B_DQ_CB<1>
TP_MEM_B_DQ_CB<0>
MEM_B_DQS_P<0>
MEM_B_DQS_P<2>
MEM_B_DQS_P<1>
MEM_B_DQS_P<3>
MEM_B_DQS_P<4>
MEM_B_DQS_P<5>
MEM_B_DQS_P<6>
TP_MEM_B_DQS_P<8>
MEM_B_A<3>
MEM_B_A<0>
MEM_B_A<1>
MEM_B_A<2>
MEM_B_A<4>
MEM_B_A<5>
MEM_B_A<6>
MEM_B_A<7>
MEM_B_A<9>
MEM_B_A<8>
MEM_B_A<14>
MEM_B_A<13>
MEM_B_A<11>
MEM_B_A<12>
MEM_B_A<10>
MEM_B_A<15>CPU_DIMM_VREF_B
MEM_B_DQ<3>
MEM_B_DQ<2>
MEM_B_DQ<4>
MEM_B_DQ<5>
MEM_B_DQ<6>
MEM_B_DQ<7>
MEM_B_DQ<11>
MEM_B_DQ<12>
MEM_B_DQ<13>
MEM_B_DQ<14>
MEM_B_DQ<15>
MEM_B_DQ<17>
MEM_B_DQ<18>
MEM_B_DQ<19>
MEM_B_DQ<20>
MEM_B_DQ<21>
MEM_B_DQ<22>
MEM_B_DQ<23>
MEM_B_DQ<24>
MEM_B_DQ<25>
MEM_B_DQ<26>
MEM_B_DQ<27>
MEM_B_DQ<31>
MEM_B_DQ<32>
MEM_B_DQ<36>
MEM_B_DQ<34>
MEM_B_DQ<35>
MEM_B_DQ<37>
MEM_B_DQ<33>
MEM_B_DQ<40>
MEM_B_DQ<50>
MEM_B_DQ<43>
MEM_B_DQ<41>
MEM_B_DQ<42>
MEM_B_DQ<45>
MEM_B_DQ<44>
MEM_B_DQ<46>
MEM_B_DQ<48>
MEM_B_DQ<47>
MEM_B_DQ<49>
MEM_B_DQ<53>
MEM_B_DQ<54>
MEM_B_DQ<55>
MEM_B_DQ<56>
MEM_B_DQ<57>
MEM_B_DQ<58>
MEM_B_DQ<59>
MEM_B_DQ<60>
MEM_B_BA<1>
MEM_B_BA<0>
MEM_B_BA<2>
MEM_B_DQ<61>
MEM_B_DQ<62>
MEM_B_DQ<63>
MEM_B_DQ<39>
MEM_B_DQ<38>
MEM_B_DQ<51>
MEM_B_DQ<52>
MEM_B_DQ<9>
MEM_B_DQ<8>
MEM_B_DQ<0>
MEM_B_DQ<1>
MEM_B_DQ<16>
MEM_B_CLK_N<2>
TP_MEM_B_CS_L<4>
TP_MEM_B_CS_L<5>
TP_MEM_B_CS_L<6>
TP_MEM_B_CS_L<7>
MEM_B_CS_L<1>
MEM_B_CS_L<3>
MEM_B_CS_L<2>
MEM_B_CS_L<0>
MEM_B_DQS_N<4>
MEM_B_DQS_N<3>
TP_MEM_B_DQS_N<8>
MEM_B_DQS_N<7>
MEM_B_DQS_N<6>
MEM_B_DQS_N<5>
MEM_B_DQS_N<1>
MEM_B_DQS_N<0>
MEM_B_DQS_N<2>
MEM_A_DQ<1>
MEM_A_CS_L<1>
MEM_A_CS_L<0>
12 OF 110
A.0.0
051-8337
11 OF 92
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www.vinaﬁx.vn

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IN
OUT
OUT
PSI*
VID_1/MSID_1
VID_2/MSID_2
VID_3/CSC_0
VID_5/CSC_2
VID_6
ISENSE
VID_7
VID_4/CSC_1
VID_0/MSID_0
VCC_74
VCC_73
VCC_75
VCC_76
VCC_77
VCC_39
VCC_38
VCC_37
VCC_36
VTT_33
VTT_10
VTT_4
VTT_42
VTT_44
VTT_46
VTT_49
VTT_51
VTT_53
VTT_56
VTT_57
VTT_59
VTT_61
VTT_63
VTT_65
VTT_68
VTT_70
VTT_75
VTT_77
VTT_SELECT
VTT_12
VTT_13
VTT_14
VTT_16
VCC_13
VCC_12
VCC_11
VTT_5
VCC_3
VCC_2
VCC_SENSE
VSS_SENSE
VTT_3
VTT_8
VTT_6
VTT_73
VTT_74
VTT_76
VTT_66
VTT_72
VCC_80
VCC_72
VCC_89
VCC_56
VSS_SENSE_VTT
VTT_SENSE
VCC_88
VCC_87
VCC_86
VCC_85
VCC_84
VCC_4
VCC_1
VCC_9
VCC_8
VCC_7
VCC_5
VCC_10
VCC_14
VCC_18
VCC_19
VCC_17
VCC_16
VCC_15
VCC_21
VCC_22
VCC_23
VCC_24
VCC_20
VCC_25
VCC_26
VCC_27
VCC_28
VCC_29
VCC_30
VCC_34
VCC_33
VCC_32
VCC_31
VCC_40
VCC_45
VCC_44
VCC_43
VCC_42
VCC_41
VCC_50
VCC_49
VCC_48
VCC_47
VCC_46
VCC_55
VCC_53
VCC_52
VCC_51
VCC_60
VCC_59
VCC_58
VCC_57
VCC_64
VCC_65
VCC_62
VCC_63
VCC_61
VCC_70
VCC_69
VCC_68
VCC_67
VCC_66
VCC_71
VCC_81
VCC_82
VCC_83
VCC_90
VCC_91
VCC_92
VCC_93
VCC_94
VCC_95
VCC_96
VCC_99
VCC_97
VCC_98
VTT_2
VTT_0
VTT_1
VTT_9
VTT_11
VTT_15
VTT_17
VTT_18
VTT_23
VTT_22
VTT_24
VTT_21
VTT_25
VTT_26
VTT_29
VTT_27
VTT_34
VTT_35
VTT_50
VTT_47
VTT_48
VTT_52
VTT_54
VTT_60
VTT_58
VTT_62
VTT_64
VTT_67
VTT_69
VTT_71
VTT_43
VTT_41
VTT_39
VTT_38
VTT_37
VTT_36
VCC_0
VCC_54
VTT_55
VTT_45
VTT_40
VTT_32
VTT_31
VTT_30
VTT_28
VTT_20
VTT_19
VCC_6
VTT_7
VCC_35
VCC_78
VCC_79
POWER
1.1V RAIL POWER
SENSE LINES
CPU CORE SUPPLY
(6 OF 10)
CPU VIDS
OUT
VAXG_14
VAXG_15
VAXG_16
VAXG_17
VAXG_0
VAXG_2
VAXG_36
VAXG_34
VAXG_SENSE
VSSAXG_SENSE
GFX_VID_0
GFX_VID_1
GFX_VID_2
GFX_VID_3
GFX_VID_4
GFX_VID_5
GFX_VID_6
GFX_VR_EN
GFX_DPRSLPVR
GFX_IMON
VDDQ_2
VDDQ_1
VDDQ_0
VDDQ_4
VDDQ_3
VDDQ_5
VDDQ_6
VDDQ_7
VDDQ_8
VDDQ_9
VDDQ_10
VDDQ_11
VDDQ_12
VDDQ_13
VDDQ_15
VDDQ_14
VDDQ_17
VDDQ_18
VCCPLL_0
VCCPLL_1
VAXG_9
VAXG_8
VAXG_3
VAXG_4
VAXG_7
VAXG_6
VAXG_5
VAXG_18
VAXG_19
VAXG_23
VAXG_24
VAXG_22
VAXG_21
VAXG_20
VAXG_25
VAXG_28
VAXG_29
VAXG_26
VAXG_27
VAXG_33
VAXG_35
VAXG_37
VAXG_38
VAXG_39
VAXG_40
VAXG_41
VAXG_42
VAXG_43
VAXG_44
VAXG_45
VAXG_46
VAXG_47
VAXG_48
VAXG_13
VAXG_12
VAXG_11
VAXG_10
VAXG_32
VAXG_31
VAXG_30
VAXG_1
VCCPLL_2
VDDQ_16
GRAPHICS VIDS
1.8V
DDR3-1.5V RAILS
SENSE LINES
( 7 OF 10 )
POWER
GRAPHICS
VCC_NCTF_0
VCC_NCTF_1
CGC_TP_NCTF
FC_AE38
FC_AG40
VCC_100
VCC_104
VCC_103
VCC_102
VCC_101
VCC_105
VCC_106
VCC_107
VCC_108
VCC_109
VCC_110
VCC_111
VCC_112
VCC_114
VCC_119
VCC_118
VCC_117
VCC_115
VCC_116
VCC_124
VCC_123
VCC_122
VCC_121
VCC_120
VCC_125
VCC_126
VCC_130
VCC_134
VCC_133
VCC_132
VCC_131
VCC_135
VCC_138
VCC_139
VCC_137
VCC_136
VCC_140
VCC_145
VCC_144
VCC_143
VCC_142
VCC_141
VCC_146
VCC_150
VCC_149
VCC_148
VCC_147
VCC_155
VCC_154
VCC_153
VCC_152
VCC_151
VCC_160
VCC_159
VCC_158
VCC_157
VCC_156
VCC_165
VCC_164
VCC_163
VCC_162
VCC_161
VCC_168
VCC_169
VCC_170
VCC_167
VCC_166
VCC_171
VCC_172
VCC_173
VCC_174
VCC_175
VCC_176
VCC_177
VCC_178
VCC_179
VCC_180
VCC_181
VCC_113
VCC_129
VCC_128
VCC_127
(10 OF 10)
VCC
NCTF
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
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PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
87 54 21
THIS SUPPLY IS NEEDED ONLY FOR SYSTEM WITH DALE IG
CONNECTED TO THE IMON OUT FROM CPU REG
15 65 89
15 65 89
15 65 89
15 65 89
15 65 89
15 65 89
15 65 89
65 89
68 89
68 89
65 88
65 89
50 65 89
AE35
AF39
AC35
AC34
Y38
Y37
Y36
Y35
Y34
Y33
W6
W1
AC33
V8
V7
V6
V40
V39
V38
V37
V36
V35
V34
AB7
V33
V2
T8
T7
T6
T2
P8
P7
P6
N7
AA38
M9
M11
M10
L10
AL21
AL20
AK21
AK20
AK19
AJ32
AA37
AJ31
AJ29
AJ27
AJ25
AJ23
AJ21
AJ19
AJ17
AG33
AF33
AA36
AE8
AE40
AE39
AE34
AE33
AD40
AD39
AD38
AD37
AD36
AA35
AD35
AD34
AD33
AC8
AC5
AC40
AC39
AC38
AC37
AC36
AA34
AA33
AE36
T34
U33
U34
U35
U36
U37
U38
U39
U40
T35
J19
J18
H40
H38
H37
H35
H34
H32
H31
H29
B26
H28
H26
H25
H23
H22
H20
H19
G39
G38
G36
B25
G35
G33
G32
G30
G29
G27
G26
G24
G23
G21
B23
G20
F40
F39
F37
F36
F34
F33
F31
F30
F28
A36
F27
F25
F24
F22
F21
E40
E38
E37
E35
E34
A35
E32
E31
E29
E28
E26
E25
E23
E22
D39
D38
A33
D36
D35
D33
D32
D30
D29
D27
D26
D24
D23
A27
C39
C37
C36
C34
C33
C31
C30
C28
C27
C25
A26
C24
C23
B38
B37
B35
B34
B32
B31
B29
B28
A24
A23
AG38
T40
U1000
LGA1156-SKT
LYNNFIELD
OMIT
15 65 89
B13
AV19
AV16
AV13
AU11
AT21
AT18
AT10
AJ15
AY26
AY23
AY17
AY14
AY11
AW9
AV28
AV25
AV22
AJ13
AJ11
AG8
AF8
AF7
A13
C15
C14
B18
B17
B15
M16
M15
M14
L16
L15
L14
K16
K15
K14
B14
J16
J15
J14
H17
H15
H14
G18
G17
G15
G14
A18
F19
F18
F17
F15
F14
E20
E18
E17
E15
E14
A17
D21
D20
D18
D17
D15
D14
C21
C20
C18
C17
A15
A14
F12
J11
G11
C12
E11
E12
B12
G10
F6
J10
U1000
LYNNFIELD
LGA1156-SKT
OMIT
C40
A38
R40
R39
R38
R37
R36
R35
R34
R33
P40
P39
P38
P37
P36
P35
P34
P33
N39
N38
N36
N35
N33
M40
M39
M37
M36
M34
M33
M30
M28
M27
M25
M24
M22
M21
M19
M17
L40
L38
L37
L35
L34
L32
L31
L29
L28
L26
L25
L23
L22
L20
L19
L17
K39
K38
K36
K35
K33
K32
K30
K29
K27
K26
K24
K23
K21
K20
K18
K17
J40
J39
J37
J36
J34
J33
J31
J30
J28
J27
J25
J24
J22
J21
AG40
AE38
B39
U1000
LGA1156-SKT
LYNNFIELD
OMIT
CPU POWER
SYNC_MASTER=K74_MASTER SYNC_DATE=N/A
=PPVTT_S0_CPU=PPVCORE_S0_CPU
CPU_VID<7>
TP_CPU_VTTSELECT
CPU_VCC_PKG_SENSE_P
CPU_VTTSENSE_P
CPU_VID<1>
CPU_VID<4>
CPU_VCC_PKG_SENSE_N
CPU_VTTSENSE_N
=PPVCORE_S0_CPU
TP_GFX_VR_EN
=PPVAXG_S0_CPU
CPU_VID<6>
VR_CPU_IOUT
TP_GFX_VID<0>
TP_GFX_VSENSE_P
TP_GFX_VSENSE_N
TP_GFX_VID<1>
TP_GFX_VID<2>
TP_GFX_VID<3>
TP_GFX_VID<4>
TP_GFX_VID<5>
TP_GFX_VID<6>
TP_GFX_DPRSLPVR
=PP1V5_CPU_MEM
=PP1V8_S0_CPU_PLL
CPU_PSI_L
CPU_VID<2>
CPU_VID<3>
CPU_VID<5>
CPU_VID<0>
=PPVCORE_S0_CPU
TP_CPU_CGC_NCTF
TP_CPU_FC_AE38
TP_CPU_FC_AG40
13 OF 110
A.0.0
051-8337
12 OF 92
5 10 15 47 65 5 12 15
5 12 15
5
7
7
7
7
7
7
7
7
7
5 10 15 29
5 15 64
5 12 15
7
7
www.vinaﬁx.vn

VSS_27
VSS_26
VSS_84
VSS_83
VSS_82
VSS_80
VSS_81
VSS_89
VSS_88
VSS_87
VSS_85
VSS_86
VSS_94
VSS_93
VSS_92
VSS_90
VSS_91
VSS_99
VSS_98
VSS_95
VSS_96
VSS_97
VSS_104
VSS_103
VSS_102
VSS_100
VSS_101
VSS_105
VSS_109
VSS_108
VSS_107
VSS_106
VSS_110
VSS_111
VSS_114
VSS_112
VSS_113
VSS_115
VSS_119
VSS_118
VSS_117
VSS_116
VSS_120
VSS_125
VSS_124
VSS_122
VSS_121
VSS_123
VSS_130
VSS_129
VSS_128
VSS_127
VSS_126
VSS_134
VSS_133
VSS_132
VSS_135
VSS_131
VSS_140
VSS_139
VSS_138
VSS_137
VSS_136
VSS_145
VSS_144
VSS_143
VSS_141
VSS_142
VSS_150
VSS_149
VSS_148
VSS_146
VSS_147
VSS_151
VSS_152
VSS_153
VSS_154
VSS_155
VSS_156
VSS_159
VSS_157
VSS_158
VSS_1
VSS_0
VSS_2
VSS_3
VSS_4
VSS_5
VSS_6
VSS_7
VSS_8
VSS_9
VSS_11
VSS_12
VSS_13
VSS_14
VSS_10
VSS_18
VSS_15
VSS_17
VSS_16
VSS_19
VSS_23
VSS_22
VSS_21
VSS_20
VSS_24
VSS_25
VSS_29
VSS_30
VSS_31
VSS_32
VSS_33
VSS_34
VSS_35
VSS_36
VSS_37
VSS_38
VSS_39
VSS_40
VSS_41
VSS_42
VSS_43
VSS_45
VSS_44
VSS_48
VSS_49
VSS_50
VSS_47
VSS_46
VSS_51
VSS_52
VSS_53
VSS_54
VSS_55
VSS_57
VSS_56
VSS_58
VSS_59
VSS_60
VSS_65
VSS_64
VSS_63
VSS_62
VSS_70
VSS_69
VSS_68
VSS_67
VSS_66
VSS_71
VSS_72
VSS_73
VSS_74
VSS_75
VSS_76
VSS_78
VSS_77
VSS_79
VSS_28
VSS_61
( 8 OF 10 )
VSS
VSS_277
VSS_276
VSS_275
VSS_188
VSS_164
VSS_165
VSS_176
VSS_175
VSS_174
VSS_224
VSS_223
VSS_221
VSS_220
VSS_219
VSS_218
VSS_217
VSS_216
VSS_215
VSS_214
VSS_213
VSS_212
VSS_211
VSS_210
VSS_209
VSS_208
VSS_207
VSS_206
VSS_205
VSS_204
VSS_203
VSS_202
VSS_201
VSS_200
VSS_199
VSS_198
VSS_197
VSS_196
VSS_193
VSS_191
VSS_190
VSS_189
VSS_187
VSS_186
VSS_183
VSS_182
VSS_180
VSS_179
VSS_178
VSS_170
VSS_171
VSS_172
VSS_173
VSS_168
VSS_169
VSS_160
VSS_161
VSS_163
VSS_271
VSS_270
VSS_268
VSS_269
VSS_266
VSS_265
VSS_260
VSS_262
VSS_261
VSS_259
VSS_256
VSS_258
VSS_257
VSS_255
VSS_254
VSS_250
VSS_253
VSS_251
VSS_252
VSS_249
VSS_246
VSS_248
VSS_247
VSS_245
VSS_240
VSS_243
VSS_241
VSS_242
VSS_235
VSS_238
VSS_236
VSS_237
VSS_234
VSS_229
VSS_230
VSS_233
VSS_232
VSS_231
VSS_227
VSS_228
VSS_226
VSS_225
VSS_222
VSS_162
VSS_274
VSS_273
VSS_272
VSS_239
VSS_244VSS_185
VSS_184
VSS_195
VSS_194
VSS_192
VSS_181
VSS_167
VSS_166
VSS_267
VSS_264
VSS_263
VSS_177
(9 OF 10)
VSS
SKT MNT HOLE
II NOT TO REPRODUCE OR COPY IT
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Apple Inc.
PAGE
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A
B
C
345678
D
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87 54 21
AT12
AR40
AR30
AR23
AR20
AR1
AP9
AP7
AP4
AP38
AB35 AP35
AP33
AP29
AP27
AP26
AP24
AP20
AP17
AP16
AP15
AB34
AP12
AN9
AN4
AN36
AN31
AN28
AN25
AN22
AN20
AN13
AB33
AM9
AM5
AM40
AM1
AL7
AL38
AL34
AL31
AL3
AL28
AB3
AL25
AL22
AL19
AL16
AL13
AL11
AK8
AK5
AK4
AK36
AA5
AK17
AK10
AJ9
AJ6
AJ40
AJ34
AJ33
AJ30
AJ28
AJ26
A37
AJ24
AJ22
AJ20
AJ18
AJ16
AJ14
AJ12
AJ1
AH5
AH38
A34
AH33
AH3
AG7
AG36
AG34
AF40
AF1
AE7
AE37
AE3
A28
AD8
AD5
AC1
AB8
E21
E19
E16
E13
D8
D6
D5
D40
D4
D37
AB6
D34
D31
D28
D25
D22
D19
D16
D13
D12
D10
AB40
C5
C38
C35
C32
C29
C26
C22
C19
C16
C13
AB39
B9
B7
B36
B33
B30
B27
B24
B16
AY7
AY4
AB38
AY36
AY33
AV38
AV34
AV31
AV3
AU7
AU6
AU36
AU32
AB37
AT8
AT5
AT37
AT34
AT30
AT27
AT24
AT2
AT16
AT14
AB36
A25
A16
U1000
LGA1156-SKT
LYNNFIELD
OMIT
AF6
Y7
W38
W37
W36
W35
W34
W33
V5
U4
T5
T39
T38
T37
T36
T33
R4
P5
P2
N40
N4
N37
N34
M7
M6
M5
M38
M35
M32
M29
M26
M23
M20
M2
M18
M13
L9
L4
L39
L36
L33
L30
L27
L24
L21
L18
L13
K6
K5
K40
K37
K34
K31
K28
K25
K22
K2
K19
K13
K11
J9
J7
J4
J38
J35
J32
J29
J26
J23
J20
J17
J13
H6
H5
H39
H36
H33
H30
H27
H24
H21
H2
H18
H16
H13
H11
G9
G40
G4
G37
G34
G31
G28
G25
G22
G19
G16
G13
F8
F38
F35
F32
F29
F26
F23
F20
F2
F16
F13
F11
E4
E39
E36
E33
E30
E3
E27
E24
1159
1158
1157
U1000
LGA1156-SKT
LYNNFIELD
OMIT
SYNC_DATE=N/ASYNC_MASTER=K74_MASTER
CPU GROUNDS
14 OF 110
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87 54 21
CPU_CFG<3> IS USED FOR
REVERSAL0
1
CPU_CFG<3> PCIE LANES
NO REVERSAL
PCIE LANE REVERSAL
UNUSED GPIO SIGNALS
UNUSED GPIO SIGNALS
IF LIKE TO HAVE THE PEB CLOCKS ENABLED. STUFF R1535 AND UNSTUFF R1534
BOOT STRAP OPTIONS
UNUSED CLKREQS
2
1
R1500
5%
402
1.5K
1/16W
MF-LF
2
1
R1509
402
10K
5%
MF-LF
1/16W
2
1
R1517
402
1/16W
MF-LF
5%
10K
BUF_CLK
2
1
R1515
402
MF-LF
10K
5%
1/16W
2
1
R1525
5%
1/16W
402
MF-LF
10K
2
1
R1524
MF-LF
402
5%
1/16W
10K
2
1
R1523
5%
1/16W
MF-LF
10K
402
2
1
R1522
5%
1/16W
MF-LF
402
10K
2
1
R1530
10K
5%
402
1/16W
PCH_VRM
MF-LF
2
1
R1527
1/16W
402
MF-LF
10K
5%
2
1
R1528
MF-LF
1/16W
402
10K
5%
2
1
R1526
MF-LF
10K
1/16W
402
5%
2
1
R1533
402
MF-LF
1/16W
5%
10K
2
1
R1501
10K
1/16W
402
MF-LF
5%
2
1
R1532
MF-LF
1/16W
5%
10K
402
2
1
R1535
1/16W
10K
402
MF-LF
5%
2
1
R1536
1/16W
10K
5%
402
MF-LF
2
1
R1537
1/16W
5%
10K
MF-LF
402
NOSTUFF
2
1
R1538
402
MF-LF
10K
5%
1/16W
2
1
R1539
MF-LF
5%
1/16W
402
10K
2
1
R1543
1/16W
402
10K
5%
MF-LF
2
1
R1550
NOSTUFF
402
1/16W
MF-LF
1K
5%
2
1
R1551
402
MF-LF
1/16W
5%
10K
NOSTUFF
2
1
R1552
1/16W
402
5%
10K
NOSTUFF
MF-LF
2
1
R1553
1/16W
402
MF-LF
5%
10K
NOSTUFF
2
1
R1554
10K
5%
MF-LF
402
1/16W
NOSTUFF
2
1
R1503
402
10K
MF-LF
1/16W
5%
2
1
R1504
5%
10K
MF-LF
402
1/16W
2
1
R1570
10K
5%
1/16W
MF-LF
402
2
1
R1571
10K
402
MF-LF
1/16W
5%
2
1
R1572
10K
MF-LF
402
5%
1/16W
2
1
R1573
1/16W
MF-LF
402
5%
10K
2
1
R1574
5%
1/16W
MF-LF
402
10K
2
1
R1575
10K
402
MF-LF
1/16W
5%
2
1
R1506
10K
5%
1/16W
402
MF-LF
2
1
R1507
402
MF-LF
1/16W
5%
10K
2
1
R1508
1/16W
MF-LF
10K
5%
402
2
1
R1510
10K
5%
402
MF-LF
1/16W
2
1
R1511
5%
1/16W
402
MF-LF
10K
2
1
R1555
10K
5%
MF-LF
402
1/16W
2
1
R1529
402
MF-LF
5%
10K
1/16W
2
1
R1590
MF-LF
10K
5%
402
1/16W
2
1
R1591
MF-LF
402
5%
1/16W
10K
2
1
R1512
1/16W
402
MF-LF
5%
10K
STRAPS,PULL UPS,PULL DOWNS FOR PCH AND CPU
SYNC_DATE=12/08/2009SYNC_MASTER=NICK
ENET_ENERGY_DET
ENET_LOW_PWR
PM_LAN_PWRGD
PCH_INIT3V3_L
WOL_EN
ODD_PWR_EN_L
PCH_CLKOUTFLEX3
PCH_CLKOUTFLEX2
=PP3V3_S0_PCH_STRAPS
ENET_CLKREQ_L
FW_CLKREQ_L
FW_PWR_EN
PCH_GPIO34_STP_PCI_L
PCH_GPIO49_SATA5GP
PM_BATLOW_L
PCH_GPIO27_VRMEN
FW_PME_L
SMC_RUNTIME_SCI_L
=PP3V3_S0_PCH_STRAPS
SPI_DESCRIPTOR_OVERRIDE_L
AP_PWR_EN
PCH_GPIO39_SDATAOUT0
PCH_GPIO38_SLOAD
PCH_GPIO6_TACH2
PCH_PCI_GNT3_L
PCH_PCI_GNT2_L
PCH_PCI_GNT1_L
T28_CLKREQ_L
=PP3V3_S5_PCH_STRAPS
PEB_CLKREQ_L
MINI_CLKREQ_L
PCH_GPIO37_SATA3GP
PCH_SPKR
PM_CLKRUN_L
PCH_PCI_GNT0_L
PCH_CLKOUTFLEX1
BRCRYPT_RESET
=PP3V3_S0_PCH_STRAPS
EXCARD_CLKREQ_L
=PP3V3_S0_PCH_STRAPS
PCH_GPIO0_BMBUSY_L
CPU_CFG<3>
=PP3V3_S0_PCH_STRAPS
PCH_GPIO19_SATA1GP
PCH_GPIO21_SATA0GP
PCH_GPIO24
=PP3V3_S5_PCH_STRAPS
PCH_GPIO8_FCIM_EN_L
BRCRYPT_PWR_EN
PCH_GPIO15
15 OF 110
A.0.0
051-8337
14 OF 92
17 37
20 37
18 91
20
20 36
20
17
17
5 14
17 37
17 40
20
20
20
18 46 91
20
20 40
20 46
5 14
17 46
20
20
20
20
19
19
19
17
5 14
17
17 33
20
17
18 46 48 91
19
17
17
5 14
17
5 14
20
9 24 84
5 14
17
17
20
5 14
20
17
20
www.vinaﬁx.vn

OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
BOM OPTIONSBOM GROUP
TABLE_BOMGROUP_HEAD
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
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REVISION
DRAWING NUMBER SIZE
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SHEET
PAGE TITLE
C
A
D
21
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
87 54 21
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
BOM OPTIONSBOM GROUP
TABLE_BOMGROUP_HEAD
NOTE: BOM Configurations should not call out CPUPOCnU/D BOMOPTIONs directly.
Instead call out appropriate BOM GROUP defined in tables above.
PLACEMENT_NOTE (C1660-C1666):
BULK CAPS ON CPU VTT REG PAGE 74
Memory (CPU VCCDDR) DECOUPLING
2x 22uF 0805, 5x 1uF 0402
BULK CAPS ON CPU VREG PAGE 72
PLACEMENT_NOTE (C1650-C1657):
VTT (CPU Uncore) DECOUPLING
INTEL RECOMMENDATION 9X22UF 0805
60A
IMAX @ 900mV
VID[6] = Reserved (0)
VID[5:3] = IMON CONFIG DEFAULT
VID[2:0] = FUNCTION MSI[2:0]
INTEL RECOMMENDATION 17X 22UF 0805
VID[7] = VRD SELECT (0)
110
120A
MSI - MARKET SEGMENT IDENTIFICATION
40A
CPU Gain Setting Equivalent Gain
80A
000
100
Intel recommends all option straps should be provided in layout
CPU Power On Configuration (POC) Straps
PLL (CPU VCCSFR) DECOUPLING
8X 22UF 0805, 7X 10UF 0805
CPU VCORE DECOUPLING
BULK CAPS ON CPU VREG PAGE 74
180A
140A
111
12.857
1x 22uF 0805, 1x 4.7uF 0603, 1x 2.2uF 0402, 2x 1uF 0402
22.5
18
15
10
45001
010
011
30
100A
101
PREVENTS THE PLATFORM BOOTING USING A HIGHER POWERED CPU
2
1
C1693
X5R
10%
1UF
402
10V
2
1
C1692
X5R
10%
2.2UF
402
6.3V
2
1
C1691
6.3V
10%
4.7UF
603
X5R-CERM
2
1
C1690
20%
6.3V
22uF
CERM-X5R
805
2
1
C1681
6.3V
CERM-X5R
805
22uF
20%
2
1
C1685
1UF
X5R
10%
402
10V
2
1
C1684
10V
402
1UF
10%
X5R
2
1
C1686
1UF
10V
402
10%
X5R
2
1
R1600
MF-LF
1/16W
5%
402
1K
CPUMSI0U
2
1
R1602
1K
MF-LF
1/16W
5%
402
CPUMSI2U
2
1
R1601
MF-LF
5%
402
1K
CPUMSI1U
1/16W
2
1
R1603
CPUPOC3U
MF-LF
1/16W
5%
402
1K
2
1
R1604
MF-LF
402
5%
1K
1/16W
CPUPOC4U
2
1
R1605
MF-LF
1/16W
5%
402
1K
CPUPOC5U
2
1
R1616
1/16W
MF-LF
1K
5%
402
2
1
R1615
402
CPUPOC5D
1K
MF-LF
1/16W
5%
2
1
R1614
1/16W
CPUPOC4D
MF-LF
402
5%
1K
2
1
R1612
1/16W
1K
402
5%
MF-LF
CPUMSI2D
2
1
R1613
CPUPOC3D
1K
402
5%
1/16W
MF-LF
2
1
R1610
1/16W
402
MF-LF
1K
5%
CPUMSI0D
2
1
R1611
1K
5%
1/16W
MF-LF
402
CPUMSI1D
12 65 89
12 65 89
12 65 89
12 65 89
12 65 89
12 65 89
12 65 89
2
1
R1617
1K
5%
1/16W
MF-LF
402
12 65 89
2
1
C1609
805-3
22UF
20%
6.3V
CERM-X5R
2
1
C1608
805-3
CERM-X5R
22UF
20%
6.3V
2
1
C1607
805-3
22UF
20%
6.3V
CERM-X5R
2
1
C1619
6.3V
20%
22UF
805-3
NOSTUFF
CERM-X5R
2
1
C1618
6.3V
20%
22UF
CERM-X5R
805-3
NOSTUFF
2
1
C1617
6.3V
20%
CERM-X5R
805-3
NOSTUFF
22UF
2
1
C1616
6.3V
20%
22UF
CERM-X5R
805-3
2
1
C1615
6.3V
20%
22UF
CERM-X5R
805-3
2
1
C1614
6.3V
20%
22UF
CERM-X5R
805-3
2
1
C1613
6.3V
20%
22UF
CERM-X5R
805-3
2
1
C1612
805-3
CERM-X5R
22UF
20%
6.3V
2
1
C1611
22UF
6.3V
20%
CERM-X5R
805-3
2
1
C1610
20%
6.3V
22UF
CERM-X5R
805-3
2
1
C1670
CASE-D2-SM
POLY
2V
20%
330UF-0.0045OHM
2
1
C1671
CASE-D2-SM
POLY
2V
20%
330UF-0.0045OHM
2
1
C1600
20%
22UF
805-3
CERM-X5R
6.3V
2
1
C1601
805-3
22UF
20%
CERM-X5R
6.3V
2
1
C1602
6.3V
20%
22UF
CERM-X5R
805-3
2
1
C1603
CERM-X5R
805-3
22UF
20%
6.3V
2
1
C1604
CERM-X5R
805-3
20%
6.3V
22UF
2
1
C1650
Place under socket cavity on secondary side.
22UF
20%
CERM-X5R
6.3V
805
2
1
C1605
CERM-X5R
805-3
22UF
20%
6.3V
2
1
C1606
CERM-X5R
805-3
22UF
20%
6.3V
2
1
C1651
805
6.3V
20%
22UF
Place under socket cavity on secondary side.
CERM-X5R
2
1
C1652
6.3V
20%
22UF
805
CERM-X5R
Place under socket cavity on secondary side.
2
1
C1653
6.3V
20%
22UF
805
CERM-X5R
Place under socket cavity on secondary side.
2
1
C1654
22UF
CERM-X5R
6.3V
20%
805
Place under socket cavity on secondary side.
2
1
C1655
6.3V
CERM-X5R
20%
22UF
805
Place under socket cavity on secondary side.
2
1
C1656
6.3V
20%
805
Place under socket cavity on secondary side.
22UF
CERM-X5R
2
1
C1657
6.3V
20%
22UF
805
Place under socket cavity on secondary side.
CERM-X5R
2
1
C1666
Place at edge of socket.
10uF
603
20%
6.3V
X5R
2
1
C1665
X5R
603
10uF
20%
6.3V
Place at edge of socket.
2
1
C1664
10uF
603
20%
6.3V
X5R
Place at edge of socket.
2
1
C1663
10uF
20%
6.3V
X5R
603
Place at edge of socket.
2
1
C1662
603
6.3V
X5R
Place at edge of socket.
20%
10uF
2
1
C1661
10uF
6.3V
20%
603
X5R
Place at edge of socket.
2
1
C1660
6.3V
10uF
X5R
20%
Place at edge of socket.
603
2
1
C1680
805
CERM-X5R
22uF
6.3V
20%
2
1
C1682
X5R
10%
1UF
10V
402
2
1
C1683
10V
10%
X5R
402
1UF
2
1
C1694
10V
402
10%
X5R
1UF
CPUPOC_IMAX_DIS CPUPOC5D,CPUPOC4D,CPUPOC3D
CPUPOC_IMAX_140_180 CPUPOC5U,CPUPOC4U,CPUPOC3U
CPUPOC5D,CPUPOC4D,CPUPOC3UCPUPOC_IMAX_0_40
SYNC_MASTER=NICK SYNC_DATE=12/08/2009
CPU NON-GFX DECOUPLING
CPUPOC_IMAX_40_60 CPUPOC5D,CPUPOC4U,CPUPOC3D
CPUPOC_IMAX_60_80 CPUPOC5D,CPUPOC4U,CPUPOC3U
CPUPOC_IMAX_80_100 CPUPOC5U,CPUPOC4D,CPUPOC3D
CPUPOC_IMAX_100_120 CPUPOC5U,CPUPOC4D,CPUPOC3U
CPUPOC_IMAX_120_140 CPUPOC5U,CPUPOC4U,CPUPOC3D
LYNNFIELD_95W LFD,CPUPOC_IMAX_100_120,CPUMSI2U,CPUMSI1U,CPUMSI0D
CLARKDALE_73W CKD,CPUPOC_IMAX_60_80,CPUMSI2U,CPUMSI1D,CPUMSI0U
LYNNFIELD_82W LFD,CPUPOC_IMAX_60_80,CPUMSI2U,CPUMSI1D,CPUMSI0U
=PP1V5_CPU_MEM
=PPVTT_S0_CPU=PPVCORE_S0_CPU
CPU_VID<0>
=PP1V8_S0_CPU_PLL
CPU_VID<1>
CPU_VID<2>
CPU_VID<4>
CPU_VID<5>
CPU_VID<6>
CPU_VID<7>
CPU_VID<3>
=PPVTT_S0_CPU
16 OF 110
A.0.0
051-8337
15 OF 92
5 10 12 29
5 10 12 15 47 65 5 12
5 12 64
5 10 12 15 47 65
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II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
BRANCH
REVISION
DRAWING NUMBER SIZE
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R
IV ALL RIGHTS RESERVED
SHEET
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C
A
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21
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
87 54 21
150 MA
69 mA
75 MA
75 MA
69 mA
21
R1760
MF-LF
402
0
5%
1/16W
21
R1765
MF-LF
402
0
1/16W
5%
21
R1750
0
402
5%
1/16W
MF-LF
CPU/PCH GFX DECOUPLING
SYNC_MASTER=K74_MASTER SYNC_DATE=N/A
=PP3V3_S0_PCH_VCCADAC
=PP1V05_S0_PCH_VCCADPLL
MIN_LINE_WIDTH=0.4 MM
VOLTAGE=1.05V
PP1V05_S0_PCH_VCCADPLLA
MIN_NECK_WIDTH=0.2 MM
MIN_LINE_WIDTH=0.4 MM
VOLTAGE=1.05V
PP1V05_S0_PCH_VCCADPLLB
MIN_NECK_WIDTH=0.2 MM
PP3V3_S0_PCH_VCCA_DAC
MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=3.3V
17 OF 110
A.0.0
051-8337
16 OF 92
5
5 21 89
21 89
21 89
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IN
IN
OUT
OUT
OUT
IN
BI
BI
BI
BI
OUT
BI
IN
IN
OUT
OUT
IN
IN
OUT
OUT
IN
IN
IN
IN
IN
IN
OUT
OUT
OUT
OUT
OUT
OUT
OUT
IN
OUT
OUT
OUT
IN
OUT
OUT
IN
OUT
OUT
OUT
OUT
IN
OUT
OUT
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
OUT
OUT
OUT
BI
OUT
BI
IN
IN
OUT
OUT
OUT
OUT
IN
OUT
OUT
OUT
OUT
SPI
(1 OF 10)
SATA
JTAG IHDA
LPCRTC
TRST*
GPIO33
GPIO13
SRTCRST*
SPKR
SPI_MOSI
SPI_MISO
SPI_CS1*
SPI_CS0*
SPI_CLK
SERIRQ
SATALED*
SATAICOMPO
SATAICOMPI
SATA5TXP
SATA5TXN
SATA5RXP
SATA5RXN
SATA4TXP
SATA4TXN
SATA4RXP
SATA4RXN
SATA3TXP
SATA3TXN
SATA3RXP
SATA3RXN
SATA2TXP
SATA2TXN
SATA2RXP
SATA2RXN
SATA1TXP
SATA1TXN
SATA1RXP
SATA1RXN
SATA1GP/GPIO19
SATA0TXP
SATA0TXN
SATA0RXP
SATA0RXN
SATA0GP/GPIO21
RTCX2
RTCX1
RTCRST*
LDRQ1*/GPIO23
LDRQ0*
JTAG_TMS
JTAG_TDO
JTAG_TDI
JTAG_TCK
INTRUDER*
HDA_SYNC
HDA_SDO
HDA_SDIN3
HDA_SDIN2
HDA_SDIN1
HDA_SDIN0
HDA_BCLK
FWH4/LFRAME*
FWH3/LAD3
FWH2/LAD2
FWH1/LAD1
FWH0/LAD0
INTVRMEN
HDA_RST*
PCI-E*
FLEX
CLOCK
PEG
SMBUS
(2 OF 10)
FROM CLK BUFFER
SML1DATA/GPIO75
SML1CLK/GPIO58
SML1ALERT*/GPIO74
SML0DATA
SML0CLK
SML0ALERT*/GPIO60
SMBDATA
SMBCLK
SMBALERT*/GPIO11
REFCLK14IN
PETP8
PETP7
PETP6
PETP5
PETP4
PETP3
PETP2
PETP1
PETN8
PETN7
PETN6
PETN5
PETN3
PETN2
PETN1
PERP8
PERP7
PERP6
PERP5
PERP4
PERP3
PERP2
PERP1
PERN8
PERN7
PERN6
PERN5
PERN4
PERN3
PERN2
PERN1
PEG_B_CLKRQ*/GPIO56
PEG_A_CLKRQ*/GPIO47
PCIECLKRQ5*/GPIO44
PCIECLKRQ4*/GPIO26
PCIECLKRQ3*/GPIO25
PCIECLKRQ2*/GPIO20
PCIECLKRQ1*/GPIO18
PCIECLKRQ0*/GPIO73
CLKOUTFLEX3/GPIO67
CLKOUTFLEX2/GPIO66
CLKOUTFLEX1/GPIO65
CLKOUTFLEX0/GPIO64
CLKOUT_PEG_B_P
CLKOUT_PEG_B_N
CLKOUT_PEG_A_P
CLKOUT_PEG_A_N
CLKOUT_PCIE5P
CLKOUT_PCIE5N
CLKOUT_PCIE4P
CLKOUT_PCIE4N
CLKOUT_PCIE3P
CLKOUT_PCIE3N
CLKOUT_PCIE2P
CLKOUT_PCIE2N
CLKOUT_PCIE1P
CLKOUT_PCIE1N
CLKOUT_PCIE0P
CLKOUT_PCIE0N
CLKOUT_DMI_P
CLKOUT_DMI_N
CLKIN_SATA_P/CKSSCD_P
CLKIN_SATA_N/CKSSCD_N
CLKIN_PCILOOPBACK
CLKIN_DOT_96P
CLKIN_DOT_96N
CLKIN_DMI_P
CLKIN_BCLK_P
CLKIN_BCLK_N
XTAL25_OUT
XTAL25_IN
XCLK_RCOMP
CLKIN_DMI_N
CLKOUT_DP_N/CLKOUT_BCLK1_N
CLKOUT_DP_P/CLKOUT_BCLK1_P
PETN4
IN
OUT
BI
OUT
OUT
IN
IN
OUT
OUT
IN
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
BRANCH
REVISION
DRAWING NUMBER SIZE
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SHEET
PAGE TITLE
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A
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PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
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87 54 21
TIE THEM TOGETHER VERY CLOSE TO PINS. PLACE THE RESISTOR LESS THAN 200MILS FROM THE PINS
(IPD)
(IPD)
(IPU)
(IPD)
(IPD)
PLACE THIS RESISTOR NEAR THE PCH PIN
(IPU)
(IPU)
(IPU)
(IPD)
(IPU)
(IPD)
(IPU)
(IPU)
DOES THIS NEED LENGTH MATCH???
(IPD)
(IPD)
(IPD)
(IPD)
(IPD)
(IPD)
(IPU)
(IPD)
(IPD)
(IPU)
PLACE THESE 33 OHM RESISTORS CLOSE TO PCH (MIN 500MIL)
27 85
56 85
48 55 85
48 85
48 55 85
48 55 85
46 48 85
46 48 85
46 48 85
46 48 85
46 48 85
46 48
42 84
42 84
42 84
42 84
42 84
42 84
42 84
42 84
37 86
37 86
33 84
33 84
39 84
39 84
37 86
37 86
33 84
33 84
39 84
39 84
37 84
14 37
37 84
33 84
33 84
14 33
39 84
39 84
14 40
10 84
10 84
8
8
8
10 84
10 84
25 84
25 84
25 84
25 84
25 84
25 84
25 84
25 84
25 85
27 85
27 85
27 85
27 85
49 88
49 88
49 88
49 88
7
7
7
7
2
1
R1800
402
1/16W
5%
MF-LF
330K
2
1
R1801
1M
1/16W
5%
MF-LF
402
2
1
R1802
20K
1/16W
402
5%
MF-LF
2
1
R1803
MF-LF
402
5%
1/16W
20K
2
1
C1803
1UF
X5R
10V
402
10%
2
1
C1802
10V
10%
1UF
402
X5R
2
1
R1830
1%
1/16W
37.4
402
MF-LF
2
1
R1820
MF-LF
402
1/16W
5%
10K
7
7
14
2
1
R1890
90.9
1/16W
1%
402
MF-LF
21
R1810
402
1/16W
MF-LF
33
5%
21
R1811
5%
1/16W
33
MF-LF
402
21
R1812
33
402
MF-LF
5%
1/16W
21
R1813
402
1/16W
5%
MF-LF
33
56 85
56 85
56 85
56 85
AL35
AP28
AJ38
T34
V30
T32
V32
V31
AL40
AN39
T41
T39
AD32
AD33
AF34
AF35
AE38
AD38
AE40
AF41
AB38
AB37
AC39
AC41
AB32
AB31
AD35
AD36
AB35
AB36
Y37
Y38
AH38
V38
U38
V40
W41
AJ37
BA30
AW30
AK24
AP14
AL12
AL34
AN34
AL36
AK33
AW31
AN24
AU15
AP16
AN16
AU13
AP18
AV13
AV14
AW14
AT16
AR16
AR14
AM16
AL16
AK16
AT12
U1800
FCBGA
OMIT
IBEX-PEAK-DESKTOP
Y2
Y4
AA3
AR31
AV31
AY32
AT34
AW33
BA33
AM31
AV32
AL31
AF7
J12
D10
H11
G12
L14
G14
G16
D17
K12
D11
G11
H12
K14
H14
H16
D18
B8
B11
C9
B13
D13
C14
A16
C16
C7
A12
D8
C12
D14
B15
B17
D15
AW35
AV39
AW38
AW37
AP33
AP38
AM39
AN35
AL3
AB6
AK1
AD10
V8
V7
Y7
Y6
Y9
Y8
P6
P7
M10
M9
M7
M6
T9
T10
W1
V2
H38
H37
J41
H40
Y35
Y34
AL11
AL22
AM22
G20
H20
Y31
Y32
U1800
FCBGA
OMIT
IBEX-PEAK-DESKTOP
2
1
R1850
MF-LF
402
10K
1/16W
5%
14
2
1
R1856
51
5%
1/16W
MF-LF
402
2
1
R1881
5%
MF-LF
402
1/16W
XDP
200
2
1
R1883
MF-LF
402
XDP
1/16W
5%
200
49 88
49 88
2
1
R1853
1/16W
10K
MF-LF
402
5%
2
1
R1854
10K
MF-LF
1/16W
5%
402
2
1
R1855
10K
402
5%
1/16W
MF-LF
7
7
7
7
7
7
14 46
2
1
R1882
5%
MF-LF
402
1/16W
100
XDP
2
1
R1884
XDP
100
5%
1/16W
402
MF-LF
21R1860
5%1/16W MF-LF 402
33
21R1861 33
402MF-LF1/16W5%
21R1862 33
402MF-LF1/16W5%
21R1863
MF-LF5%1/16W 402
33
21R1864
4021/16W
33
MF-LF5%
21R1822
4021/16W MF-LF
22
5%
21R1823
402
22
5% MF-LF1/16W
2
1
R1885
5%
MF-LF
1/16W
402
XDP
200
2
1
R1886
MF-LF
1/16W
5%
100
402
XDP
SYNC_MASTER=NICK SYNC_DATE=12/08/2009
PCH SATA/PCIE/CLK/LPC/SPI
ENET_ENERGY_DET
JTAG_PCH_TCK
JTAG_PCH_TMS
TP_JTAG_PCH_TRST_L
SPI_CS0_R_L
PP3V3_G3_RTC
PCH_INTRUDER_L
=PP3V3_S5_PCH
TP_SATA_F_R2D_CP
TP_SATA_SSD_R2D_C_P
PCH_SATAICOMP
TP_SATA_E_R2D_CN
TP_SATA_D_D2RP
TP_SATA_D_D2RN
TP_SATA_SSD_R2D_C_N
HDA_RST_LHDA_RST_R_L
HDA_BIT_CLKHDA_BIT_CLK_R
HDA_SDOUTHDA_SDOUT_R
HDA_SYNCHDA_SYNC_R
=PP3V3_S5_PCH
SMC_WAKE_SCI_L
SML_PCH_0_ALERT_L
SML_PCH_1_ALERT_L
PCH_GPIO19_SATA1GP
PCH_SATALED_L
SPI_MOSI_1_R
JTAG_PCH_TDI
JTAG_PCH_TDO
TP_SATA_E_R2D_CP
TP_SATA_E_D2RP
TP_SATA_SSD_D2R_P
PCIE_EXCARD_D2R_P
PCIE_EXCARD_D2R_N
PCIE_EXCARD_R2D_C_N
TP_PCIE_T28_D2R_N<0>
TP_PCIE_T28_D2R_P<1>
TP_PCIE_T28_R2D_C_N<2>
TP_PCIE_T28_D2R_N<3>
TP_PCIE_T28_R2D_C_P<1>
TP_PCIE_T28_R2D_C_N<0>
SPI_MOSI_R
SPI_CLK_1_R
TP_SATA_F_D2RP
TP_SATA_F_R2D_CN
TP_HDA_SDIN2
TP_PCIE_T28_D2R_P<0>
TP_PCIE_T28_D2R_N<1>
TP_SATA_E_D2RN
JTAG_PCH_TCK
PCH_CLK32K_RTCX2
TP_PCIE_CLK100M_T28_N
TP_PCIE_CLK100M_T28_P
T28_CLKREQ_L
TP_PCIE_CLK100M_PE5P
PEB_CLKREQ_L PCH_CLKOUTFLEX3
PCH_CLKOUTFLEX2
PCH_XCLK_RCOMP
PCH_CLK25M_XTALOUT
BRCRYPT_RESET
TP_PCIE_T28_R2D_C_N<3>
DMI_MIDBUS_CLK100M_P
DMI_MIDBUS_CLK100M_N
RTC_RESET_L
PCH_INTVRMEN_L
PCIE_MINI_D2R_N
PCIE_CLK100M_CPU_N
PCH_SPKR
PCH_CLK32K_RTCX1
SPI_DESCRIPTOR_OVERRIDE_L
SATA_ODD_D2R_N
HDA_SYNC_R
TP_SATA_SSD_D2R_N
TP_PCIE_T28_R2D_C_N<1>
PCIE_ENET_D2R_N
PCIE_ENET_D2R_P
PCIE_ENET_R2D_C_N
SML_PCH_1_ALERT_L
SML_PCH_0_ALERT_L
SMBUS_PCH_DATA
SML_PCH_0_DATA
SML_PCH_1_CLK
SML_PCH_0_CLK
PCIE_EXCARD_R2D_C_P
GFX_CLK120M_DPLLSS_P
GFX_CLK120M_DPLLSS_N
PCH_CLK100M_SATA_N
PCH_CLK14P3M_REFCLK
PEG_CLKREQ_L
PEG_CLK100M_P
PEG_CLK100M_N
PCH_CLK33M_PCIIN
PCH_CLK96M_DOT_P
PCH_CLK96M_DOT_N
FSB_CLK133M_PCH_P
PCIE_CLK100M_PCH_N
SATA_ODD_R2D_C_P
FSB_CLK133M_PCH_N
EXCARD_CLKREQ_L
PCH_INTRUDER_L
SMBUS_PCH_CLK
SMC_WAKE_SCI_L
PCIE_ENET_R2D_C_P
PCIE_MINI_D2R_P
PCIE_MINI_R2D_C_N
SML_PCH_1_DATA
PCIE_CLK100M_PCH_P
TP_PCIE_T28_D2R_P<3>
TP_PCIE_T28_R2D_C_P<0>
PCIE_FW_R2D_C_N
SATA_HDD_R2D_C_P
PCIE_CLK100M_ENET_P
PCH_CLK100M_SATA_P
PCH_SRTCRST_L
HDA_BIT_CLK_R
HDA_RST_R_L
PCH_GPIO21_SATA0GP
=PP3V3_S0_SATALED
=PP1V05_S0_PCH_VCCIO_PCIE
HDA_SDOUT_R
TP_HDA_SDIN3
TP_HDA_SDIN1
HDA_SDIN0
BRCRYPT_PWR_EN
TP_PCIE_CLK100M_PE5N
TP_PCIE_T28_D2R_P<2>
PCH_CLKOUTFLEX1
PCH_CLK25M_XTALIN
PCIE_CLK100M_CPU_P
PCIE_FW_R2D_C_P
PCIE_MINI_R2D_C_P
PCIE_FW_D2R_N
PCIE_FW_D2R_P
MINI_CLKREQ_L
PCIE_CLK100M_EXCARD_P
PCIE_CLK100M_FW_P
PCIE_CLK100M_FW_N
PCIE_CLK100M_MINI_N
PCIE_CLK100M_ENET_N
TP_PCIE_T28_R2D_C_P<2>
TP_PCIE_T28_R2D_C_P<3>
ENET_CLKREQ_L
PCIE_CLK100M_MINI_P
FW_CLKREQ_L
PCIE_CLK100M_EXCARD_N
TP_SATA_F_D2RN
SATA_ODD_R2D_C_N
LPC_SERIRQ
LPC_AD<1>
LPC_AD<3>
LPC_FRAME_L
LPC_R_AD<3>
=PP3V3_S0_PCH
=PP1V05_S0_PCH_VCCIO_SATA
LPC_FRAME_R_L
LPC_R_AD<0> LPC_AD<0>
LPC_AD<2>
TP_LPC_DREQ0_L
LPC_R_AD<2>
SPI_CLK_R
TP_LPC_DREQ1_L
SATA_HDD_D2R_N
SATA_HDD_D2R_P
SATA_HDD_R2D_C_N
LPC_R_AD<1>
SATA_ODD_D2R_P
JTAG_PCH_TDI
JTAG_PCH_TDO
TP_PCIE_T28_D2R_N<2>
RTC_RESET_L
JTAG_PCH_TMS
PCH_SATALED_L
TP_SATA_D_R2D_CP
TP_SATA_D_R2D_CN
SPI_MISO
PCH_SRTCRST_L
PCH_INTVRMEN_L
TP_SPI_CS1_L
18 OF 110
A.0.0
051-8337
17 OF 92
14 37
17
17
21 23 27 89
17
5 17 18 23
7
85
7
7
7
17 85
17 85
17 85
17 85
5 17 18 23
17 46
17
17
14
17 42
17
17
7
7
7
7
7
7
7
7
7
7
7
7
7
7
17
7
7
7
14 14
14
85
14
7
17 91
17
14
17 85
7
17
17
17
17 46
7
7
17
17 85
17 85
14
5 42
5 18 21 23
17 85
7
7
14
7
7
14
7
7
7
5 20 23 69
5 21 23
7
7
17
17
7
17 91
17
17 42
7
7
17
17
www.vinaﬁx.vn

IN
IN
BI
OUT
OUT
OUT
OUT
OUT
OUT
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
OUT
OUT
IN
IN
OUT
OUT
IN
IN
OUT
OUT
IN
IN
OUT
OUT
MANAGEMENT
(3 OF 10)
SYSTEM POWER
FDIDMI
TP23
GPIO32
GPIO72
SYS_RESET*
SYS_PWROK
SUSCLK/GPIO62
SUS_STAT*/GPIO61
SUS_PWR_DN_ACK/GPIO30
SLP_S5*/GPIO63
SLP_S4*
SLP_S3*
SLP_M*
SLP_LAN*/GPIO29
RSMRST*
RI*
PWROK
PWRBTN*
PMSYNCH
LAN_RST*
FDI_RXP7
FDI_RXP6
FDI_RXP5
FDI_RXP4
FDI_RXP3
FDI_RXN5
FDI_RXN4
FDI_RXN3
FDI_RXN2
FDI_RXN1
FDI_RXN0
FDI_LSYNC1
FDI_LSYNC0
FDI_FSYNC1
FDI_FSYNC0
DRAMPWROK
DMI3TXP
DMI3TXN
DMI3RXP
DMI2TXP
DMI2TXN
DMI1TXP
DMI1TXN
DMI0TXP
DMI0TXN
DMI0RXN
DMI_ZCOMP
DMI_IRCOMP
ACPRESENT/GPIO31
WAKE*
FDI_RXN6
FDI_RXN7
FDI_RXP2
FDI_INT
FDI_RXP1
FDI_RXP0
DMI1RXN
DMI2RXN
DMI3RXN
DMI0RXP
DMI1RXP
DMI2RXP
MEPWROK
DIGITAL DISPLAY INTERFACE
(4 OF 10)
CRT
SDVO_TVCLKINP
SDVO_TVCLKINN
SDVO_STALLP
SDVO_STALLN
SDVO_INTP
SDVO_INTN
SDVO_CTRLDATA
SDVO_CTRLCLK
DDPD_HPD
DDPD_CTRLDATA
DDPD_CTRLCLK
DDPD_AUXP
DDPD_AUXN
DDPD_3P
DDPD_3N
DDPD_2P
DDPD_2N
DDPD_1P
DDPD_1N
DDPD_0P
DDPD_0N
DDPC_3P
DDPC_3N
DDPC_2P
DDPC_1P
DDPC_1N
DDPC_0P
DDPB_HPD
DDPB_AUXP
DDPB_AUXN
DDPB_3N
DDPB_2P
DDPB_2N
DDPB_1P
DDPB_1N
DDPB_0P
DDPB_0N
DAC_IREF
CRT_VSYNC
CRT_RED
CRT_IRTN
CRT_HSYNC
CRT_GREEN
CRT_DDC_DATA
CRT_DDC_CLK
DDPB_3P
DDPC_CTRLCLK
DDPC_CTRLDATA
DDPC_AUXN
DDPC_AUXP
DDPC_HPD
DDPC_0N
DDPC_2N
CRT_BLUEOUT
OUT
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
BRANCH
REVISION
DRAWING NUMBER SIZE
D
R
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
21
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
87 54 21
(IPU)
(IPU)
INTERNAL DP
KEEPING TP, IF NEED TO USE IT LATER
(IPU)
(IPD)
(IPD)
(IPD)
(IPD)
EXTERNAL DP
PLACE CLOSE TO U1800 PIN
SHORT THESE TWO PINS VERY NEAR THE PINS
To U6900
TO SMC
PLACE THE RESISTOR VERY CLOSE TO COMMON POINT
9 84
2
1
R1900
1%
1/16W
49.9
MF-LF
402
18 33 36
14 46 48 91
8 85 91
47 91
18 47 91
5 26 36 46 47 63 64 81 91
63 91
10 91
63 91
24 46 91
18
14 46 91
14 91
64 91
64 91
64 91
27 46 91
9 84
9 84
9 84
9 84
9 84
9 84
9 84
9 84
9 84
9 84
9 84
9 84
9 84
9 84
9 84
2
1
R1905
402
MF-LF
1/16W
1%
10K
AR33
AH35
AL38
AT38
AH31
AK31
AT37
AU36
AP35
AV35
AT36
BA35
AL24
AT33
AM24
AK36
C37
AL33
AY31
AY34
AJ40
B34
B32
B31
J31
G31
D32
G30
J30
C33
A33
C30
K31
F31
D31
H30
K30
D35
C35
B36
E36
E34
AW32
C21
D21
K24
L24
H18
G18
G24
H24
D20
E20
F22
G22
C19
B20
H22
J22
B18
A19
AP40
U1800
IBEX-PEAK-DESKTOP
FCBGA
OMIT
L6
L7
N2
P3
M3
N4
AB12
AB13
H2
AB9
AB7
K4
L4
F9
G9
F8
G8
D6
D7
C5
B6
J3
AB11
AB10
L9
L10
D3
D2
B4
C4
F2
G3
E3
F4
J1
M1
L2
G4
H4
H6
F6
K11
J11
K10
J8
AE2
AD3
AC1
AB4
AD4
AC3
AG4
AG2
AB2
U1800
IBEX-PEAK-DESKTOP
FCBGA
OMIT
2
1
R1915
402
MF-LF
1%
1/16W
100K
10 91
46 48
2
1
R1925
MF-LF
1K
1%
1/16W
402
2
1
R1951
1K
5%
1/16W
MF-LF
402
21
R1960
MF-LF
NOSTUFF
5%
0
402
1/16W
2
1
R1961
MF-LF
1%
1/16W
402
10K
21
R1966
5%
MF-LF
1/16W
33
402
2
1
R1909
1%
402
MF-LF
1/16W
10K
SYNC_MASTER=K74_MASTER SYNC_DATE=N/A
PCH DMI/FDI/GRAPHICS
DMI_N2S_N<0>
DMI_N2S_N<1>
DMI_N2S_N<2>
DMI_N2S_N<3>
TP_PCH_FDI_RX_P<6>
TP_PCH_FDI_FSYNC<0>
PM_ME_PWRGD
TP_PCH_FDI_LSYNC<1>
TP_PCH_FDI_FSYNC<1>
TP_PCH_FDI_LSYNC<0>
TP_PCH_FDI_INT
TP_PCH_FDI_RX_P<5>
TP_PCH_FDI_RX_N<0>
DMI_N2S_P<1>
DMI_S2N_N<0>
DMI_S2N_N<1>
DMI_S2N_N<2>
DMI_S2N_N<3>
DMI_S2N_P<0>
DMI_N2S_P<0>
PM_SLP_S4_L PM_SLP_S4_1_L
TP_DP_IG_D_HPD
PM_SUS_PWR_ACK
PCH_DMI_COMP
PM_LAN_PWRGD
PM_SYS_PWRGD
DMI_N2S_P<3>
DMI_N2S_P<2>
PCH_ACPRESENT_GPIO31
PM_SLP_S4_L
TP_DP_IG_C_MLN<3>
TP_DP_IG_D_CTRL_CLK
TP_DP_IG_D_AUXP
TP_DP_IG_D_MLN<0>
TP_DP_IG_C_MLP<2>
TP_DP_IG_C_MLP<1>
TP_DP_IG_C_MLN<1>
TP_DP_IG_C_MLP<0>
TP_DP_IG_C_MLN<0>
TP_DP_IG_C_AUX_P
TP_DP_IG_C_AUX_N
TP_DP_IG_C_CTRL_DATA
TP_DP_IG_C_CTRL_CLK
TP_DP_IG_B_MLP<3>
TP_DP_IG_B_MLN<3>
TP_DP_IG_B_MLN<2>
TP_DP_IG_C_HPD
TP_DP_IG_C_MLN<2>
TP_DP_IG_D_CTRL_DATA
TP_CRT_IG_DDC_DATA
TP_CRT_IG_DDC_CLK
TP_PCH_FDI_RX_N<2>
TP_PCH_FDI_RX_N<3>
TP_PCH_FDI_RX_N<4>
TP_PCH_FDI_RX_N<5>
TP_PCH_FDI_RX_N<6>
=PP3V3_S5_PCH
TP_CRT_IG_VSYNC
PM_SLP_S5_L
PM_PWRBTN_L
TP_DP_IG_D_MLP<0>
TP_DP_IG_D_MLN<1>
TP_DP_IG_D_MLP<1>
TP_DP_IG_D_MLP<2>
TP_DP_IG_D_MLP<3>
PM_CLK32K_SUSCLK_R
TP_DP_IG_D_AUXN
PCIE_WAKE_L
TP_PCH_FDI_RX_N<1>
PM_SYNC
TP_DP_IG_C_MLP<3>
TP_PM_SLP_DSW_L
TP_DP_IG_B_AUX_N
TP_DP_IG_B_AUX_P
TP_DP_IG_B_DDC_CLK
TP_DP_IG_B_DDC_DATA
TP_SDVO_TVCLKINN
TP_SDVO_TVCLKINP
TP_SDVO_STALLN
TP_SDVO_STALLP
TP_SDVO_INTN
TP_SDVO_INTP
LPC_PWRDWN_L
DMI_S2N_P<1>
DMI_S2N_P<2>
DMI_S2N_P<3>
TP_CRT_IG_HSYNC
TP_CRT_IG_GREEN
TP_DP_IG_B_MLP<0>
TP_DP_IG_B_MLN<1>
TP_DP_IG_B_MLP<1>
TP_DP_IG_B_MLP<2>
PM_MEM_PWRGD
PCH_DAC_IREF
TP_DP_IG_B_MLN<0>
TP_DP_IG_B_HPD
=PP1V05_S0_PCH_VCCIO_PCIE
=PP3V3_S5_PCH
TP_CRT_IG_BLUE
PM_PCH_PWRGD
TP_SLP_LAN_L
PM_SLP_M_L
=PP3V3_S5_PCH
TP_PCH_FDI_RX_P<7>
SMC_ADAPTER_EN
TP_DP_IG_D_MLN<2>
TP_DP_IG_D_MLN<3>
TP_CRT_IG_RED
PCH_RI_L
PM_SLP_S3_L
PCH_ACPRESENT_GPIO31
PM_BATLOW_L
PM_RSMRST_PCH_L
PM_CLKRUN_L
TP_PCH_FDI_RX_N<7>
TP_PCH_FDI_RX_P<0>
TP_PCH_FDI_RX_P<1>
TP_PCH_FDI_RX_P<2>
TP_PCH_FDI_RX_P<3>
TP_PCH_FDI_RX_P<4>
PCIE_WAKE_LPM_SYSRST_L
19 OF 110
A.0.0
051-8337
18 OF 92
7
7
7
7
7
7
7
7
18 47 91 63 91
7
91
85
18
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
5 17 18 23
7
7
7
7
7
7
7
18 33 36
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
5 17 21 23
5 17 18 23
7
5 17 18 23
7
46 47
7
7
7
7
7
7
7
7
7
www.vinaﬁx.vn

BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
PCI
NVRAM
USB
(5 OF 10)
TRDY*
USBRBIAS*
USBRBIAS
USBP9P
USBP9N
USBP8P
USBP8N
USBP7P
USBP7N
USBP6P
USBP6N
USBP5P
USBP5N
USBP4P
USBP4N
USBP3P
USBP3N
USBP2P
USBP2N
USBP1P
USBP1N
USBP13P
USBP13N
USBP12P
USBP12N
USBP11P
USBP11N
USBP10P
USBP10N
USBP0P
USBP0N
STOP*
SERR*
REQ3*/GPIO54
REQ2*/GPIO52
REQ1*/GPIO50
REQ0*
PME*
PLTRST*
PLOCK*
PIRQH*/GPIO5
PIRQG*/GPIO4
PIRQF*/GPIO3
PIRQE*/GPIO2
PIRQD*
PIRQC*
PIRQB*
PIRQA*
PERR*
PCIRST*
PAR
OC7*/GPIO14
OC6*/GPIO10
OC5*/GPIO9
OC4*/GPIO43
OC3*/GPIO42
OC2*/GPIO41
OC1*/GPIO40
OC0*/GPIO59
NV_WR1_RE*
NV_WR0_RE*
NV_WE_CK1*
NV_WE_CK0*
NV_RCOMP
NV_RB*
NV_DQS1
NV_DQS0
NV_DQ9/NV_IO9
NV_DQ8/NV_IO8
NV_DQ7/NV_IO7
NV_DQ6/NV_IO6
NV_DQ5/NV_IO5
NV_DQ4/NV_IO4
NV_DQ3/NV_IO3
NV_DQ2/NV_IO2
NV_DQ15/NV_IO15
NV_DQ14/NV_IO14
NV_DQ13/NV_IO13
NV_DQ12/NV_IO12
NV_DQ11/NV_IO11
NV_DQ10/NV_IO10
NV_DQ1/NV_IO1
NV_DQ0/NV_IO0
NV_CE2*
NV_CE1*
NV_CE0*
NV_ALE
IRDY*
GNT3*/GPIO55
GNT2*/GPIO53
GNT1*/GPIO51
GNT0*
FRAME*
DEVSEL*
CLKOUT_PCI4
CLKOUT_PCI3
CLKOUT_PCI2
CLKOUT_PCI1
CLKOUT_PCI0
C/BE3*
C/BE2*
C/BE1*
C/BE0*
AD9
AD8
AD7
AD6
AD5
AD4
AD31
AD30
AD3
AD29
AD28
AD27
AD26
AD25
AD24
AD23
AD22
AD21
AD20
AD2
AD19
AD18
AD17
AD16
AD15
AD14
AD13
AD12
AD11
AD10
AD0
NV_CLE
NV_CE3*
AD1
OUT
OUT
OUT
OUT
BI
BI
BI
BI
BI
BI
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
BRANCH
REVISION
DRAWING NUMBER SIZE
D
R
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
21
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
87 54 21
(IPD)
Unused
Unused
Unused
Unused
Unused
(DPD)
(IPU)
(IPU)
EHCI2
(IPD)
(IPU)
USB HUB 2
Unused
(DPD)
NOTE: Internal pull-downs on all USB pins
PLACE THE RESISTOR CLOSE TO COMMON POINT
EHCI1
Unused
Unused
Unused
Unused
Unused
Unused
TIE TRACES TOGETHER CLOSE TO PINS
USB HUB 1
34 85
34 85
7
7
7
7
7
7
7
7
7
7
7
7
35 85
35 85
7
7
2
1
R2066
10K
1/16W
MF-LF
5%
402
2
1
R2065
MF-LF
1/16W
402
5%
10K
2
1
R2064
10K
402
1/16W
5%
MF-LF
2
1
R2067
5%
MF-LF
1/16W
10K
402
2
1
R2062
10K
402
MF-LF
5%
1/16W
2
1
R2061
5%
1/16W
10K
MF-LF
402
NO STUFF
2
1
R2060
1/16W
402
MF-LF
5%
10K
7
7
7
7
2
1
R2070
402
1/16W
MF-LF
1%
22.6
AY15
AV15
AN20
AM20
AY18
BA19
AW19
AV20
AL20
AK20
AW21
AY20
AV22
AV21
AP22
AR22
AY22
AW23
AY24
BA23
BA16
AY17
AL18
AK18
AT20
AR20
AV18
AV17
AY25
AW25
AL6
AN8
AV6
AH8
AY4
AW5
AP4
AH11
AV34
AK12
AW4
AP12
AH7
AU8
BA5
AT11
AR4
AT8
AT4
AH10
AP6
AM30
AL30
AL28
AP31
AP30
AK28
AT30
AT31
J35
J36
F38
M31
L36
M32
F40
P36
F36
M30
M34
M36
L33
M35
P33
T31
P35
F33
D40
G33
E39
F37
H33
T33
L35
E41
P32
H35
H36
J34
AP7
AM3
BA9
AK6
AK11
AL7
AT6
AD12
AD9
AF9
AD7
AF6
AW10
AP5
AY6
AV3
AR3
AW9
AV7
AR9
AV8
AP9
AN11
AH12
AY10
AN6
AK7
AN7
AL9
AV10
AL4
AT2
AL2
AT5
AL10
AU6
AY8
AM4
AM11
AM2
AN3
AU1
AP2
AU3
AR8
AW7
AP11
AT9
U1800
IBEX-PEAK-DESKTOP
OMIT
FCBGA
21R2010 10K
4025% 1/16W MF-LF
21R2011
402
10K
5% 1/16W MF-LF
21R2012
402
10K
5% 1/16W MF-LF
21R2013
1/16W
10K
4025% MF-LF
21R2015
5%
10K
MF-LF 4021/16W
21R2016
1/16W MF-LF 402
10K
5%
21R2017
5%
10K
402MF-LF1/16W
21R2018
5%
10K
402MF-LF1/16W
21R2020
1/16W MF-LF 4025%
10K
21R2021
1/16W 402MF-LF5%
10K
21R2022
MF-LF 4025% 1/16W
10K
27 91
27 85
27 85
27 85
21R2023
4021/16W MF-LF5%
10K
21R2024
4021/16W MF-LF
10K
5%
21R2026
MF-LF1/16W5% 402
10K
21R2025 10K
MF-LF5% 4021/16W
21R2027 10K
MF-LF5% 4021/16W
7
7
7
7
21R2030
4025%
10K
MF-LF1/16W
21R2031
MF-LF 402
10K
5% 1/16W 7
7
2
1
R2068
402
MF-LF
1/16W
5%
10K
SYNC_MASTER=NICK SYNC_DATE=12/08/2009
PCH PCI/FLASHCACHE/USB
PCI_INTD_L
PCH_PCI_GNT1_L
PCI_INTG_L
TP_PCI_CLK33M_OUT3
LPC_CLK33M_LPCPLUS_R
LPC_CLK33M_SMC_R
PLT_RESET_L
PCH_USB_RBIAS
USB_HUB_SOFT_RESET_L
PCH_GPIO41_OC2_L
PCH_GPIO42_OC3_L
PCH_GPIO43_OC4_L
PCH_GPIO9_OC5_L
PCH_GPIO10_OC6_L
PCH_GPIO59_OC0_L
TP_PCI_AD<26>
PCH_GPIO14_OC7_L
=PP3V3_S5_PCH_GPIO
TP_USB_5N
TP_USB_4P
TP_NV_WR_RE_L<0>
TP_NV_WR_RE_L<1>
TP_NV_WE_CK_L<0>
TP_USB_12N
TP_USB_12P
TP_USB_9P
TP_USB_11N
TP_PCI_AD<12>
TP_PCI_AD<4>
TP_USB_11P
TP_USB_10N
TP_USB_9N
TP_USB_10P
USB_HUB1_UP_N
USB_HUB1_UP_P
TP_PCI_AD<24>
USB_HUB2_UP_P
TP_USB_7P
PCI_REQ0_L
PCH_PCI_GNT2_L
TP_NV_DQ<8>
TP_NV_DQ<9>
TP_NV_DQ<10>
TP_NV_DQ<11>
TP_PCI_AD<2>
TP_NV_CE_L<1>
TP_NV_DQS<0>
TP_NV_DQ<0>
TP_PCI_AD<11>
TP_PCI_AD<9>
TP_PCI_AD<14>
TP_PCI_AD<17>
TP_NV_DQS<1>
TP_NV_CE_L<2>
TP_NV_CE_L<0>
TP_NV_ALE
PCI_DEVSEL_L
TP_PCI_AD<15>
TP_PCI_AD<21>
TP_PCI_AD<29>
TP_NV_DQ<1>
TP_PCI_AD<20>
TP_PCI_AD<19>
PCI_FRAME_L
PCI_PERR_L
PCI_IRDY_L
PCI_STOP_L
TP_PCI_AD<22>
TP_PCI_AD<23>
TP_PCI_AD<25>
TP_PCI_AD<27>
TP_PCI_AD<28>
TP_PCI_AD<5>
TP_PCI_C_BE_L<1>
TP_PCI_AD<18>
TP_PCI_AD<6>
TP_PCI_CLK33M_OUT2
PCH_CLK33M_PCIOUT
TP_PCI_AD<0>
TP_PCI_PME_L
PCI_TRDY_L
TP_PCI_PAR
PCH_PCI_GNT3_L
TP_PCI_AD<31>
PCI_INTA_L
PCI_INTC_L
PCI_INTB_L
TP_PCI_C_BE_L<2>
PCI_REQ1_L
PCI_REQ3_L
PCI_REQ2_L
=PP3V3_S0_PCH_GPIO
AUD_IP_PERIPHERAL_DET
PCI_INTE_L
TP_PCI_RESET_L
TP_NV_CE_L<3>
TP_NV_DQ<3>
TP_NV_DQ<7>
AUD_I2C_INT_L
PCH_PCI_GNT0_L
TP_PCI_AD<7>
TP_PCI_AD<10>
TP_USB_3P
TP_USB_4N
TP_USB_7N
USB_HUB2_UP_N
TP_USB_13N
TP_USB_6P
TP_USB_13P
TP_PCI_AD<16>
TP_NV_WE_CK_L<1>
TP_USB_1N
PCI_PLOCK_L
TP_PCI_AD<1>
TP_PCI_AD<8>
TP_NV_DQ<2>
TP_USB_6N
TP_USB_5P
TP_USB_3N
TP_USB_2P
TP_USB_2N
TP_PCI_AD<30>
PCI_SERR_L
TP_PCI_C_BE_L<0>
TP_PCI_C_BE_L<3>
TP_USB_1P
TP_PCI_AD<3>
TP_NV_DQ<6>
TP_NV_DQ<5>
TP_NV_DQ<4>
TP_NV_DQ<12>
TP_NV_DQ<13>
TP_NV_DQ<14>
TP_NV_DQ<15>
TP_NV_CLE
TP_NV_RCOMP
TP_NV_RB_L
TP_PCI_AD<13>
20 OF 110
A.0.0
051-8337
19 OF 92
14
85
34
7
5
7
7
7
7
7
7
85
14
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
14
7
7
85
5
61
7
7
7
7
62
14
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
www.vinaﬁx.vn

IN
OUT
OUT
BI
OUT
IN
CPU
NCTF
(6 OF 10)
RSVD
GPIO
MISCGPIO8
VSS_NCTF0
VSS_NCTF1
VSS_NCTF2
VSS_NCTF3
VSS_NCTF4
VSS_NCTF5
VSS_NCTF6
VSS_NCTF7
VSS_NCTF8
VSS_NCTF9
VSS_NCTF10
VSS_NCTF11
VSS_NCTF12
A20GATE
CLKOUT_BCLK0_N/CLKOUT_PCIE8N
CLKOUT_BCLK0_P/CLKOUT_PCIE8P
CLKOUT_PCIE6N
CLKOUT_PCIE6P
CLKOUT_PCIE7N
CLKOUT_PCIE7P
GPIO15
GPIO24
GPIO27
GPIO28
GPIO35
GPIO57
INIT3_3V*
LAN_PHY_PWR_CTRL/GPIO12
NC0
NC1
NC2
NC3
NC4
PCIECLKRQ6*/GPIO45
PCIECLKRQ7*/GPIO46
PECI
PROCPWRGD
PWM0
PWM1
PWM2
RCIN*
SATA2GP/GPIO36
SATA3GP/GPIO37
SATA4GP/GPIO16
SATA5GP/GPIO49
SCLOCK/GPIO22
SDATAOUT0/GPIO39
SDATAOUT1/GPIO48
SLOAD/GPIO38
SST
STP_PCI*/GPIO34
TACH0/GPIO17
TACH1/GPIO1
THRMTRIP*
TP1
TP10
TP11
TP12
TP13
TP18
TP19
TP2
TP20
TP21
TP22_NCTF0
TP22_NCTF1
TP22_NCTF2
TP22_NCTF3
TP3
TP4
TP5
TP6
TP7
TP8
TP9
TACH3/GPIO7
TACH2/GPIO6
BMBUSY*/GPIO0
PWM3
IN
OUT
OUT
IN
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
BRANCH
REVISION
DRAWING NUMBER SIZE
D
R
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
21
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
87 54 21
IPU* = Only on TACH function.
(IPU*)
(IPU*)
(IPD)
(IPU*)
THIS SIGNAL IS INTEDED FOR FIRMWARE HUB AND WE ARE NOT USING IT.
(IPD)
(IPU)
(IPU*)14 46
10 84
10 84
10
10 24 91
10 47 91
2
1
R2155
MF-LF
1/16W
5%
402
10K
2
1
R2150
402
1/16W
5%
10K
MF-LF
BA2
BA1
B41
B40
B2
AY41
AY2
AW41
E1
C41
C1
A5
A40
AT24
V34
T12
T13
P13
P12
J20
BA41
AY1
A41
A3
AH30
AU39
K18
AN36
AK35
P9
P10
V20
AR24
L18
C38
AY11
AV11
AL14
AW11
AT40
AN31
AM38
AG38
AL39
AN41
AG40
AH39
AR38
AK39
AM40
AY13
AW12
AR12
BA12
B38
D36
AP36
AV36
Y12
Y11
V11
V10
AF15
AU34
AR39
AK30
AL32
AR41
AV40
AP37
AR34
AY36
T6
T7
V4
U4
K38
L38
AK41
AG37
U1800
OMIT
FCBGA
IBEX-PEAK-DESKTOP
14
14
26
2
1
R2190
MF-LF
1/16W
402
5%
47K
48
SYNC_MASTER=K23F SYNC_DATE=11/30/2009
PCH MISC
=PP3V3_S0_PCH
=PP3V3_S0_PCH
SDCARD_RESET
LPCPLUS_GPIO
PCH_GPIO27_VRMEN
PCH_GPIO34_STP_PCI_L
MXM_GOOD
PCH_GPIO37_SATA3GP
PCH_GPIO38_SLOAD
PCH_A20GATEPCH_GPIO8_FCIM_EN_L
PCH_GPIO24
ISOLATE_CPU_MEM_L
ODD_PWR_EN_L
TP_PCIE_CLK100M_XDPN
PCH_GPIO39_SDATAOUT0
WOL_EN
PCH_GPIO6_TACH2
AUD_IPHS_SWITCH_EN
PCH_GPIO15
ENET_LOW_PWR
SMC_RUNTIME_SCI_L
TP_PCIE_CLK100M_XDPP
FSB_CLK133M_CPU_N
FSB_CLK133M_CPU_P
PM_THRMTRIP_L
TP_PCH_TP7
TP_PCH_TP10
PCH_RCIN_L
TP_PCH_TP8
TP_PCH_TP9
PCH_INIT3V3_L
TP_DMI_CLK100M_LAN
TP_PCH_TP4
TP_DMI_CLK100M_LAP
TP_PCH_TP3
TP_PCH_TP1
TP_PCH_PWM2
TP_PCH_SST
TP_PCH_TP18
TP_PCH_PWM0
TP_PCH_PWM3
TP_PCH_TP19
SPIROM_USE_MLB
CPU_PWRGD
TP_PCH_TP6
TP_PCH_TP13
TP_PCH_TP20
TP_PCH_TP2
TP_PCH_TP21
TP_PCH_TP12
FW_PWR_EN
PCH_GPIO49_SATA5GP
AP_PWR_EN
TP_PCH_PWM1
TP_PCH_TP11
TP_PCH_TP5
CPU_PECI
FW_PME_L
PCH_GPIO0_BMBUSY_L
21 OF 110
A.0.0
051-8337
20 OF 92
5 17 20 23 69
5 17 20 23 69
44 91 92
14
14
5
14
14
14
14
7
14
14 36
62
14
14 37
7
14
7
7
7
7
7
7
48 85
14
14
14
7
14 40
14
www.vinaﬁx.vn

VCCIO54
VCCFDIPLL
VCCVRM0
VCCIO48
VCCIO49
VCCIO50
VCCIO51
VCCIO52
VCC3_3_2
VCC3_3_3
VCCCORE22
VCCCORE21
VCCCORE20
VCCCORE19
VCCCORE5
VCCIO23
VCCVRM1
VCCPNAND2
VCCPNAND1
VCCPNAND0
VCCME3_3_1
VCCME3_3_0
VCCIO53
VCCIO47
VCCIO46
VCCIO45
VCCIO44
VCCIO43
VCCIO42
VCCIO41
VCCIO40
VCCIO39
VCCIO36
VCCIO31
VCCIO30
VCCIO29
VCCIO28
VCCIO27
VCCIO26
VCCIO25
VCCIO24
VCCIO0
VCCDMI
VCCCORE57
VCCCORE56
VCCCORE55
VCCCORE54
VCCCORE53
VCCCORE52
VCCCORE51
VCCCORE50
VCCCORE49
VCCCORE48
VCCCORE47
VCCCORE46
VCCCORE45
VCCCORE44
VCCCORE43
VCCCORE42
VCCCORE41
VCCCORE40
VCCCORE39
VCCCORE38
VCCCORE37
VCCCORE36
VCCCORE35
VCCCORE34
VCCCORE33
VCCCORE32
VCCCORE31
VCCCORE27
VCCCORE26
VCCCORE25
VCCCORE24
VCCCORE23
VCCCORE18
VCCCORE17
VCCCORE16
VCCCORE15
VCCCORE14
VCCCORE13
VCCCORE12
VCCCORE11
VCCCORE10
VCCCORE9
VCCCORE8
VCCCORE6
VCCCORE4
VCCCORE3
VCCCORE2
VCCCORE1
VCCCORE0
VCCAPLLEXP
VCC3_3_1
VCC3_3_0
VCCCORE30
VCCCORE29
VCCCORE28
VCCADAC
VCCCORE7
VCCIO34
VCCIO32
VCCIO38
VCCIO37
VCCIO35
VCCIO33
VCCIO
VCC CORE
NAND / SPI
CRT
(7 OF 10)
FDI
DMI
HVCMOS
CPU
PCI/GPIO/LPC
USB
CLOCK AND MISCELLANEOUS
PCI/GPIO/LPC
SATA
HDARTC
(10 OF 10)
VCCVRM3
VCCVRM2
V5REF_SUS
V5REF
V_CPU_IO_NCTF
V_CPU_IO
DCPSUSBYP
DCPSUS
DCPSST
DCPRTC
VCCSUSHDA
VCCSUS3_3_NCTF1
VCCSUS3_3_NCTF0
VCCSUS3_3_16
VCCSUS3_3_15
VCCSUS3_3_14
VCCSUS3_3_13
VCCSUS3_3_12
VCCSUS3_3_11
VCCSUS3_3_10
VCCSUS3_3_9
VCCSUS3_3_8
VCCSUS3_3_7
VCCSUS3_3_6
VCCSUS3_3_5
VCCSUS3_3_4
VCCSUS3_3_3
VCCSUS3_3_2
VCCSUS3_3_1
VCCSUS3_3_0
VCCSATAPLL
VCCRTC_NCTF
VCCRTC
VCCME26
VCCME25
VCCME24
VCCME23
VCCME22
VCCME21
VCCME20
VCCME19
VCCME18
VCCME17
VCCME16
VCCME15
VCCME14
VCCME13
VCCME12
VCCME11
VCCME10
VCCME9
VCCME8
VCCME7
VCCME6
VCCME5
VCCME4
VCCME3
VCCME2
VCCME1
VCCME0
VCCLAN1
VCCLAN0
VCCIO22
VCCIO21
VCCIO20
VCCIO19
VCCIO18
VCCIO17
VCCIO16
VCCIO15
VCCIO14
VCCIO13
VCCIO12
VCCIO11
VCCIO10
VCCIO9
VCCIO8
VCCIO7
VCCIO6
VCCIO5
VCCIO4
VCCIO3
VCCIO2
VCCIO1
VCCADPLLB
VCCADPLLA
VCCACLK
VCC3_3_NCTF1
VCC3_3_NCTF0
VCC3_3_10
VCC3_3_9
VCC3_3_8
VCC3_3_7
VCC3_3_6
VCC3_3_5
VCC3_3_4
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
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345678
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87 54 21
(VCCSUS3_3 - 17 TOTAL)
(VCCIO[1-56] total)
(VCCIO[1-56] total)
40 mA (if GPIO27 is low)
196 MA (VCCVRM[0-3] TOTAL)
75 MA
(VCCIO[1-56] total)
5 mA (if GPIO27 is low)
0 1 1.5V 1.05V
0 0 1.8V 1.05V
357 mA
(VCCME[1-16] total)
1 (IPU) 0 (IPD) 1.8V Float
PLLs = VccAClk, VccSATAPLL, VccAPLLEXP & VccFDIPLL
Note: 1.5V option consumes more current than 1.8V
75 MA
357 mA
< 1 mA
196 MA (VCCVRM[0-3] TOTAL)
(VCC3_3 - 9 TOTAL PINS)
2.222 A S0, 800 MA M-ON
< 1 mA S0-S5
196 MA ( TOTAL 4 PINS)
163 mA S0, 65 mA S3-S5
3.251 A
3.251 A
(VCCIO[1-56] total)
3.251 A
196 MA (VCCVRM[0-3] TOTAL)
3.251 A
3.251 A
85 mA S0, 22 mA M-on
156 MA (1.8V)
65 MA
69 MA 1.629 A
357 mA (VCC3_3[1-14] total)
357 mA (VCC3_3[1-14] total)
(VCCIO[1-56] total)
6 MA S0
(VCC3_3[1-14] total)
GPIO27 HDA_SYNC VCCVRM PLL POWERS
1 (IPU) 1 1.5V Float
< 1 mA
3.251 A
2 mA S0-S5, ~6 uA G3
PCH output, for decoupling only
372 MA S0, 78 MA M-ON
PCH output, for decoupling only
2.222A S0, 800 MA M-ON
(VCCME[1-16] total)
(VCCIO[1-56] total)
31 mA (if GPIO27 is low)
PCH output, for decoupling only
PCH output, for decoupling only
2
1
C2200
CERM
402
10V
20%
0.1UF
2
1
C2210
0.1UF
10V
402
CERM
20%
2
1
C2220
20%
10V
402
CERM
0.1UF
2
1
C2230
20%
402
0.1UF
CERM
10V
C3
C2
P30
M41
M39
N40
N38
Y36
Y29
Y26
V36
V29
V15
U19
U15
T37
T36
T30
T29
T19
T15
R40
R38
R37
P39
P38
P24
P19
P18
P16
P15
N26
N24
N22
N20
N18
N16
M26
M24
AA26
A37
A23
AD26
AD23
AD20
AD18
Y24
Y23
V26
V24
V23
U26
U23
U22
AB26
U20
T27
T26
T24
T23
T22
T20
P29
P27
P26
AB24
N28
M28
L28
K28
J28
H28
G28
F28
E29
E27
AA24
E26
D29
D28
D27
C28
C26
B29
B27
AF24
AF23
AA23
AF22
AF20
AF19
AE26
AE24
AE23
AE22
AE20
AE19
AE18
A28
A26
A21
AF1
AH16
AE27
AD27
A9
U1800
OMIT
FCBGA
IBEX-PEAK-DESKTOP
L40
L39
AJ18
BA40
AY40
AV25
AU27
AU26
AT26
AR26
AP26
AN26
AM26
BA26
AY27
AW40
AW39
AW26
AV29
AV27
AL26
AK26
P41
BA39
AY29
AE16
AE15
AD16
AD15
AD13
AB16
AB15
Y19
Y18
Y16
Y15
AJ5
AJ4
AJ2
AA18
AH6
AH4
AH3
AH13
AH1
AG5
AF8
AF16
AF13
AF10
AA16
AA15
Y22
Y20
C24
B25
B24
AT28
AJ22
AH23
AH22
M22
M20
M18
AH20
M16
L26
K26
J26
H26
G26
F26
D25
D24
C25
AA27
T1
R2
AA1
BA3
AW1
AY3
AV2
AK14
AJ16
AJ14
AH18
U40
A39
B39
AW16
AN1
AF27
AF30
AH33
AY38
U1800
IBEX-PEAK-DESKTOP
OMIT
FCBGA
2
1
C2250
CERM
10V
20%
402
0.1UF
2
1
C2260
CERM
402
20%
0.1UF
PLACE C2260 ON THE BACK SIDE NEAR AF27
10V
NOSTUFF
PCH POWER
=PP1V05_SM_PCH_VCC_ME
PPVOUT_S0_PCH_DCPSST
MIN_LINE_WIDTH=0.2 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=3.3V
PPVOUT_S0_PCH_VCCRTC_NCTF
MIN_LINE_WIDTH=0.2 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=3.3V
=PP3V3_S0_PCH_VCC3_3_PCI
VOLTAGE=3.3VMIN_NECK_WIDTH=0.2 mmMIN_LINE_WIDTH=0.2 mm
PPVOUT_S5_PCH_DCPSUSBYP
=PP1V05_SM_PCH_VCC_LAN
PP1V05_S0_PCH_VCCADPLLA
PP1V8R1V5_S0_PCH_VCCVRM
VOLTAGE=3.3V
PPVOUT_G3_PCH_DCPRTC
MIN_LINE_WIDTH=0.2 mm MIN_NECK_WIDTH=0.2 mm
PP3V3_G3_RTC
=PP1V05_S0_PCH_VCCIO_DMI
PP1V8R1V5_S0_PCH_VCCVRM
PP5V_S5_PCH_V5REFSUS
PP5V_S0_PCH_V5REF
=PPVTT_S0_PCH_VCCP_CPU
VOLTAGE=3.3V
MIN_NECK_WIDTH=0.2 mm
MIN_LINE_WIDTH=0.2 mm
PPVOUT_S5_PCH_DCPSUS
=PP3V3R1V5_S0_PCH_VCCSUSHDA
PP1V05_S0_PCH_VCCAPLL_SATA
=PP1V05_SM_PCH_VCC_ME
=PP1V05_S0_PCH_VCCIO_DMI
=PP1V05_S0_PCH_VCCIO_USBPP1V05_S0_PCH_VCCA_CLK
=PP3V3_S0_PCH_VCC3_3_SATA
=PP3V3_S0_PCH_VCC3_3_CORE
=PP3V3_SM_PCH_VCC_ME
PP1V8R1V5_S0_PCH_VCCVRM
=PPVTT_S0_PCH_VCC_DMI
=PP1V05_S0_PCH_VCCIO_SATA
PP1V8R1V5_S0_PCH_VCCVRM
PP1V05_S0_PCH_VCCAPLL_FDI
=PP3V3_S0_PCH_VCC3_3_PCI
=PP3V3_S0_PCH_VCC3_3_SATA
=PP1V05_S0_PCH_VCCIO_SATA
PP3V3_S0_PCH_VCCA_DAC =PP1V05_S0_PCH_VCC_CORE
=PP3V3R1V8_S0_PCH_VCCPNAND
PP1V05_S0_PCH_VCCAPLL_EXP
=PP1V05_S0_PCH_VCCIO_PCIE
=PP1V05_S0_PCH_VCCIO_DMI
=PP3V3_S5_PCH_VCCSUS3_3_USB
PP1V05_S0_PCH_VCCADPLLB
22 OF 110
A.0.0
051-8337
21 OF 92
5 21 23
89
5 21 23
89
5 23
16 89
21 23 89
89
17 23 27 89
5 21 23
21 23 89
23 89
23 89
5 23
89
5 23
23 89
5 21 23
5 21 23
5 23 23 89
5 21 23
5 23
5 23
21 23 89
5 23
5 17 21 23
21 23 89
23 89
5 21 23
5 21 23
5 17 21 23
16 89 5 23
5 23
23 89
5 17 18 23
5 21 23
5 23
16 89
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(9 OF 10)
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(8 OF 10)
VSSVSS
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345678
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87 54 21
Y5
Y40
Y33
Y30
Y27
Y13
Y10
W5
W39
W37
W3
V9
V6
V39
V35
V33
V3
V27
V22
V19
V18
V16
V13
V12
U39
U3
U27
U24
U2
U18
U16
T8
T5
T35
T3
T18
T16
T11
R5
R4
P8
P4
P34
P31
P23
P22
P20
P11
P1
N5
N37
N14
M8
M5
M37
M33
M14
M12
M11
L8
L34
L32
L31
L30
L3
L22
L20
L16
L12
L11
K40
K39
K32
K3
K22
K20
K2
K16
J7
J6
J5
J39
J37
J24
J18
J16
J14
H9
H7
H5
H31
G41
G39
G38
G34
G1
F5
F34
F30
F24
F20
F18
F16
F14
F12
F11
E9
E8
E6
E5
E4
E37
E33
E30
E23
E22
E19
E16
E15
E13
E12
D39
D37
D34
D22
C39
C32
C31
C23
C18
C17
C11
U1800
FCBGA
IBEX-PEAK-DESKTOP
OMIT
AR28
AR18
AR11
AR1
AP24
AP20
AN5
AN37
AN30
AN28
AA4
AN22
AN18
AN14
AN12
AM32
AM28
AM18
AM14
AM12
AM10
AA39
AL8
AK9
AK8
AK5
AK37
AK34
AK32
AK3
AK22
AK10
AA38
AJ28
AJ26
AJ24
AJ20
AH9
AH41
AH36
AH34
AH32
AH29
AA22
AH27
AH26
AH24
AH19
AH15
AF5
AF39
AF37
AF36
AF33
AA20
AF32
AF31
AF3
AF29
AF26
AF18
AF12
AF11
AE4
AE39
AA19
AE3
AD8
AD6
AD40
AD39
AD34
AD31
AD30
AD29
AD24
A7
AD22
AD2
AD19
AD11
AC5
AC37
AB8
AB5
AB40
AB34
A35
AB33
AB30
AB29
AB27
AB23
AB22
C10
BA7
BA37
BA28
AB20
BA21
BA14
B22
B10
AW3
AW28
AW24
AW18
AW17
AV5
AB19
AV28
AV24
AU9
AU5
AU41
AU38
AU37
AU33
AU30
AU29
AB18
AU23
AU22
AU20
AU19
AU16
AU12
AT22
AT18
AT14
AR30
AA41
A30
A14
U1800
IBEX-PEAK-DESKTOP
OMIT
FCBGA
SYNC_MASTER=K23F SYNC_DATE=11/30/2009
PCH GROUNDS
23 OF 110
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051-8337
22 OF 92
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345678
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87 54 21
PLACEMENT_NOTE:
(PCH 1.05V ME Core PWR)
PLACEMENT_NOTE:
(PCH RTC 3.3V PWR)
6 uA G3
PCH VCCSUS3_3 BYPASS
PCH V5REF_SUS Filter & Follower
357 MA S0 /
NOTE: VccVRM input also supports
GPIO27: 1 = enabled, 0 = disabled
PLACEMENT_NOTEs:
(OR 1.5V)
(PCH Reference for 5V Tolerance on USB)1 mA S0-S5
(PCH NAND 1.8V/3.3V PWR)
PCH VCCPNAND BYPASSPCH VCCRTC BYPASS
PLACEMENT_NOTEs (all 3):
PCH V5REF Filter & Follower
(PCH Reference for 5V Tolerance on PCI)
PLACEMENT_NOTE:
PCH VCCME BYPASS
2.22 A
PCH VCC3_3 BYPASS
(PCH SATA 3.3V PWR)
(PCH ME 3.3V PWR)
(PCH SUSPEND USB 3.3V PWR)
PCH VCCCORE BYPASS
1.629 A
(PCH 1.05V CORE PWR)
2 mA S0-S5 /
PLACEMENT_NOTE:
(PCH PCI 3.3V PWR)
PLACEMENT_NOTE:
PLACEMENT_NOTEs:
PLACEMENT_NOTE:
PLACEMENT_NOTE:
(PCH DMI 1.05V PWR)
PCH VCCIO BYPASS
88 MA S3-S5
PLACEMENT_NOTE:
6 MA
372 MA
65 MA
<1 MA S0-S5
196 MA
<1 MA
PLACEMENT_NOTEs:
(PCH PCIE 1.05V PWR)
PCH VCCIO BYPASS
PLACEMENT_NOTE:
PCH VCC3_3 BYPASS
PCH VCCIO BYPASS
PLACEMENT_NOTE:
PCH USB/VCCSUS3_3 BYPASS
(VCCSUS3_3 Total)
1 mA
PCH VCCME3_3 BYPASS
1.5V, but draws more current.
Current numbers from Ibex Peak EDS Spec Update rev 0.71, doc #386904 (Table 8-3). Pre-Silicon Mobile Estimates.
PCH VCCSUSHDA BYPASS
(PCH 1.1V/1.05V CPU I/O PWR)
PLACEMENT_NOTEs:
PLACEMENT_NOTE:
PLACEMENT_NOTE:
(VCCIO TOTAL)
369 MA IDLE
3.251 A S0 /
PCH VCCIO BYPASS
(PCH CLK 1.05V PWR)
PLACEMENT_NOTEs (all 5):
(PCH SATA 1.05V PWR)
PCH VCCIO BYPASS
PLACEMENT_NOTE:
(PCH USB 1.05V PWR)
(PCH SUSPEND USB 3.3V PWR)
(PCH HD Audio 3.3V/1.5V PWR)
PCH V_CPU_IO BYPASS
<1 MA
PLACEMENT_NOTEs (all 3):
(PCH 1.05V LAN Core PWR)
PCH VCCLAN BYPASS
PCH CORE/VCC3_3 BYPASS
(PCH MISC 3.3V PWR)
196 MA
(PCH PCIe PLL PWR)
PCH VCCAPLLEXP Filter
HDA_SYNC: 0 = 1.8V, 1 = 1.5V
PCH VCCFDIPLL Filter
(PCH FDI PLL PWR)
PCH VCCSATAPLL Filter
PLACEMENT_NOTEs:
PLACEMENT_NOTEs:
(PCH SATA PLL PWR)
PLACEMENT_NOTEs:
(PCH Misc PLL PWR)
PCH VCCACLK Filter
PLACEMENT_NOTEs:
2
1
C2401
402
10V
10%
1UF
X5R
PLACE C2401 NEAR BALL AN1
2
1
C2419
6.3V
10%
402
CERM
1UF
PLACE C2419 AT BALL AA1
1
2
R2401
5%
402
100
1/16W
MF-LF
2
1
C2400
20%
402
CERM
0.1UF
10V
PLACE C2400 NEAR BALL AW16
6
1
D2400
SOT-363
BAT54DW-X-G
1
2
R2400
10
1/16W
MF-LF
5%
402
3
4
D2400
BAT54DW-X-G
SOT-363
2
1
C2421
PLACE C2421 NEAR BALL AY29
0.1UF
X5R
16V
402
10%
2
1
C2425
PLACE C2425 NEAR BALL AV25
10%
16V
X5R
402
0.1UF
2
1
C2422
0.1UF
16V
10%
402
X5R
2
1
C2413
PLACE C2413 AT BALL A21
6.3V
402
CERM
10%
1UF
2
1
C2415
PLACE C2415 AT BALL A37
6.3V
10%
402
CERM
1UF
2
1
C2417
402
PLACE C2417 AT BALL P41
1UF
CERM
10%
6.3V
21
R2410
402
0
PCH_VRM
1/16W
5%
MF-LF
2
1
C2427
PLACE C2427 NEAR BALL AJ18
X5R
402
0.1UF
10%
16V
2
1
C2426
PLACE C2426 NEAR BALL AW39
0.1UF
X5R
402
10%
16V
2
1
C2430
PLACE C2430 NEAR BALL N38
402
X5R
16V
10%
0.1UF
2
1
C2435
PLACE C2435 NEAR BALL AE27
0.1UF
402
X5R
10%
16V
2
1
C2436
PLACE C2436 NEAR BALL AV2
0.1UF
16V
10%
402
X5R
2
1
C2440
PLACE C2440 NEAR BALL P30
X5R
0.1UF
402
10%
16V
2
1
C2445
PLACE C2445 NEAR BALL AJ18
1UF
6.3V
402
CERM
10%
2
1
C2452
402
X5R
16V
0.1UF
10%
2
1
C2451
402
16V
10%
X5R
0.1UF
2
1
C2450
20%
4.7UF
603
X5R
6.3V
PLACE C2450 NEAR BALL B39
2
1
C2469
1UF
10%
6.3V
CERM
402
PLACE C2469 NEAR BALL AF10
2
1
C2466
22UF
CERM
20%
6.3V
805
PLACE C2466 NEAR BALL AH4
2
1
C2477
PLACE C2477 NEAR BALL AH22
6.3V
402
CERM
1UF
10%
2
1
C2476
PLACE C2476 NEAR BALL H26
CERM
6.3V
10%
1UF
402
2
1
C2475
6.3V
CERM
PLACE C2475 NEAR BALL D25
402
1UF
10%
2
1
C2480
PLACE C2480 NEAR BALL AJ22
10%
CERM
1UF
6.3V
402
2
1
C2485
PLACE C2485 NEAR BALL Y26
10%
402
CERM
1UF
6.3V
2
1
C2494
PLACE C2465 NEAR BALL P24
10%
402
6.3V
CERM
1UF
2
1
C2493
PLACE C2493 NEAR BALL U15
1UF
10%
6.3V
402
CERM
2
1
C2492
PLACE C2492 NEAR BALL P15
6.3V
10%
402
CERM
1UF
2
1
C2491
PLACE C2491 NEAR BALL P18
6.3V
10%
402
CERM
1UF
2
1
C2455
PLACE C2455 NEAR BALL A23
402
CERM
1UF
6.3V
10%
2
1
C2468
402
PLACE C2468 NEAR BALL AJ4
1UF
CERM
10%
6.3V
2
1
C2465
6.3V
20%
805
CERM
22UF
PLACE C2465 NEAR BALL AB15
2
1
C2471
PLACE C2471 NEAR BALL AE18
1UF
10%
6.3V
CERM
402
2
1
C2470
PLACE C2470 NEAR BALL AE18
20%
10UF
6.3V
X5R
603
2
1
C2420
PLACE C2420 NEAR BALL AY29
1UF
402
10%
CERM
6.3V
2
1
C2446
PLACE C2446 NEAR BALL U40
0.1UF
X5R
402
10%
16V
2
1
C2472
PLACE C2472 NEAR BALL AE18
4.7UF
20%
6.3V
X5R
603
2
1
C2473
PLACE C2473 NEAR BALL AE18
20%
CERM
22UF
6.3V
805
2
1
C2467
20%
10UF
6.3V
X5R
603
PLACE C2467 NEAR BALL AH1
2
1
C2437
16V
10%
0.1UF
PLACE C2437 NEAR BALL AH16
402
X5R
2
1
C2438
PLACE C2438 NEAR BALL AH16
NOSTUFF
X5R
402
10%
16V
0.1UF
2
1
C2439
16V
10%
X5R
402
0.1UF
PLACE C2439 NEAR BALL A9
2
1
C2486
PLACE C2465 NEAR BALL Y29
22UF
CERM
805
20%
6.3V
2
1
C2488
PLACE C2488 NEAR BALL AH23
4.7UF
20%
6.3V
X5R
603
2
1
C2441
PLACE C2441 NEAR BALL P30
16V
10%
402
X5R
0.1UF
NOSTUFF
2
1
C2490
PLACE C2465 NEAR BALL P18
22UF
CERM
805
20%
6.3V
2
1
R2460
402
1/16W
MF-LF
5%
1K
PCH DECOUPLING
SYNC_MASTER=K74_MASTER SYNC_DATE=N/A
VOLTAGE=1.05V
MIN_NECK_WIDTH=0.25MM
MIN_LINE_WIDTH=0.5MM
PP1V05_S0_PCH_VCCA_CLK
PP1V05_S0_PCH_VCCAPLL_SATA
MIN_LINE_WIDTH=0.5MM
MIN_NECK_WIDTH=0.25MM
VOLTAGE=1.05V
MIN_NECK_WIDTH=0.25MM
VOLTAGE=1.05V
MIN_LINE_WIDTH=0.5MM
PP1V05_S0_PCH_VCCAPLL_FDI
MIN_LINE_WIDTH=0.5MM
MIN_NECK_WIDTH=0.25MM
VOLTAGE=1.05V
PP1V05_S0_PCH_VCCAPLL_EXP
=PP1V8R1V5_S0_PCH_VCCVRM
=PP3V3_S0_PCH_VCC3_3_CORE
=PP1V05_SM_PCH_VCC_LAN
=PPVTT_S0_PCH_VCCP_CPU
=PP3V3R1V8_S0_PCH_VCCPNAND
=PP1V05_S0_PCH_VCCIO_PCIE
=PP1V05_S0_PCH_VCCIO_USB
=PP1V05_S0_PCH_VCCIO_SATA
=PP3V3R1V5_S0_PCH_VCCSUSHDA
=PPVTT_S0_PCH_VCC_DMI
=PP5V_S0_PCH
=PP3V3_S0_PCH
PP5V_S0_PCH_V5REF
VOLTAGE=5V
MIN_LINE_WIDTH=0.3MM
MIN_NECK_WIDTH=0.25MM
=PP3V3_SM_PCH_VCC_ME
=PP3V3_S5_PCH_VCCSUS3_3_USB
=PP3V3_S0_PCH_VCC3_3_SATA
=PP3V3_S5_PCH_VCCSUS3_3_USB
=PP1V05_S0_PCH_VCC_CORE
=PP3V3_S0_PCH_VCC3_3_PCI
=PP3V3_S5_PCH
=PP5V_S5_PCH
MIN_NECK_WIDTH=0.25MM
PP5V_S5_PCH_V5REFSUS
MIN_LINE_WIDTH=0.3MM
VOLTAGE=5V
MIN_LINE_WIDTH=0.5MM
PP1V8R1V5_S0_PCH_VCCVRM
VOLTAGE=1.5V
MIN_NECK_WIDTH=0.25MM
MAKE_BASE=TRUE
PP3V3_G3_RTC
=PP1V05_S0_PCH_VCCIO_DMI
=PP1V05_SM_PCH_VCC_ME
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5 21
5 17 21
5 21
5 21
5
5 17 20
69
21 89
5 21
5 21 23
5 21
5 21 23
5 21
5 21
5 17 18
5
21 89
21 89
17 21 27 89
5 21
5 21
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IN
IN
IN
IN
IN
IN
IN
IN
OUT
IN
IN
OUT
OUT
OUT
IN
IN
NC
BI
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
BI
BI
OUT
IN
IN
IN
IN
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
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DRAWING NUMBER SIZE
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PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
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87 54 21
OBSDATA_B2
517S0774
OBSDATA_B1
VCC_OBS_CD
PROCESSOR MINI XDP
OBSFN_C1
OBSDATA_C0
OBSDATA_C1
OBSDATA_C2
OBSDATA_D3
NOTE: XDP_DBRESET_L must be pulled-up to 3.3V.
OBSFN_A0
OBSDATA_D2
DBR#/HOOK7
OBSDATA_D0
PWRGD/HOOK0
HOOK1
VCC_OBS_AB
HOOK2
OBSDATA_A0
OBSFN_A1
OBSDATA_B3
TMS
OBSDATA_D1
TCK1
HOOK3
TDI
ITPCLK/HOOK4
ITPCLK#/HOOK5
RESET#/HOOK6
OBSDATA_A2
OBSFN_B1
OBSFN_D0
OBSFN_C0
TRSTn
TDO
OBSFN_B0
OBSDATA_B0
PLACE IT NEAR THE XDP
OBSDATA_C3
TCK0
OBSDATA_A3
OBSDATA_A1
SCL
OBSFN_D1
XDP_PRESENT#
SDA
9 84
10 91
21
R2511
402
PLACEMENT_NOTE=Place close to CPU to minimize stub.
1K
5%
1/16W
MF-LF
XDP
9 84
9 84
9 84
9 84
10 84
10 84
10 27 91
10
9 84
10
10
10
9 84
2
1
C2501
10%
16V
402
X5R
0.1uF
XDP
9 84
2
1
C2500
0.1uF
402
16V
X5R
10%
XDP
10
10
9 84
9 84
9 84
5
6
7
8
4
3
2
1
RP2500
XDP_CPU_BPM
5%
SM-LF
0
1/16W
5
6
7
8
4
3
2
1
RP2501
PLACEMENT_NOTE=Place R2501 close to R2500 to minimize stubs.
XDP_CPU_CFG
1/16W
5%
SM-LF
0
10 84
10 84
10 84
10 84
9 84
9 84
9 84
9 84
9 14 84
10 84
10 84
10 84
10 84
10 91
49
49
10
21
R2510
1/16W
5%
MF-LF
402
1K
XDP
9 84
10 20 91
9 84
18 46 91
2
1
R2515
1/16W
MF-LF
402
5%
XDP
51
9
87
60
6
59
5857
5655
5453
5251
50
5
49
4847
4645
4443
4241
40
4
39
3837
3635
3433
3231
30
3
29
2827
2625
2423
2221
20
2
19
1817
1615
1413
1211
10
1
J2500
CRITICAL
XDP_CONN
F-ST-SM-HF
DF40C-60DS-0.4V
SYNC_MASTER=NICK SYNC_DATE=12/08/2009
EXTENDED DEBUG PORT(XDP)
CPU_CFG<12>
CPU_CFG<13>
CPU_CFG<14>
XDP_BPM_L<0>
FSB_CPURSTOUT_L
XDP_BPM_L<1>
XDP_BPM_L<3>
XDP_BPM_L<2>
CPU_PWRGD
CPU_CFG<15>
FSB_CLK133M_ITP_N
XDP_CPURST_L
XDP_DBRESET_L
XDP_TDO
XDP_TRST_L
XDP_TMS
XDP_TDI
CPU_CFG<8>
CPU_CFG<9>
CPU_CFG<1>
CPU_CFG<0>
CPU_CFG<3>
CPU_CFG<2>
CPU_CFG<10>
CPU_CFG<11>
CPU_CFG<4>
CPU_CFG<5>
CPU_CFG<6>
CPU_CFG<7>
FSB_CLK133M_ITP_P
XDP_TCK
=SMBUS_XDP_SCL
=SMBUS_XDP_SDA
TP_XDP_HOOK3
XDP_CPUPWRGD
=PPVTT_S0_XDP
PM_PWRBTN_L
XDP_PWRGD
XDP_BPM_L<7>
XDP_BPM_L<6>
XDP_BPM_L<4>
CPU_CFG<17>
CPU_CFG<16>
XDP_OBSDATA_A<2>
XDP_OBSDATA_A<3>
XDP_OBSDATA_A<0>
XDP_OBSDATA_A<1>
XDP_PRDY_L
XDP_PREQ_L
XDP_BPM_L<5>
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REF
CPU
CPU*
SRC_2*
SRC_2
SATA*
SATA
27MHZ
27MHZ_SS
DOT_96*
X2
X1
SCL
SDA
CKPWRGD/PD*
VDD_CORE
VDD_REF
VDD_96_IO
VDD_27
VDD_SATA_IO
VDD_SRC_IO VDD_CPU_IO
VSS_CPU VSS_27 VSS_96
THRM
VSS_SATAVSS_SRC VSS_REF VSS_CORE
DOT_96
27MHZ_EN
PAD
BI
IN
IN
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
BRANCH
REVISION
DRAWING NUMBER SIZE
D
R
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
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PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
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PAGE
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A
B
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345678
D
B
87 54 21
PLACE IT CLOSE TO POWER PINS
PLACE IT CLOSE TO L2650
PLACE IT CLOSE TO POWER PINS
PLACE IT CLOSE TO POWER PINS
PCH BCLK 133MHZ
PCH SATA 100MHZ
PCH DMI/PCIe 100MHz
PCH USB Clock 96MHz
PLACE IT CLOSE TO L2610
PLACE IT CLOSE TO L2600
2
1
C2616
BUF_CLK
X5R
0.1UF
16V
10%
402
2
1
C2615
BUF_CLK
0.1UF
16V
10%
402
X5R
2
1
C2610
6.3V
20%
X5R
603
10UF
BUF_CLK
21
L2610
FERR-120-OHM-1.5A
0402
BUF_CLK
2
1
C2605
BUF_CLK
402
16V
10%
0.1UF
X5R
2
1
C2604
BUF_CLK
402
0.1UF
10%
16V
X5R
2
1
C2603
16V
BUF_CLK
0.1UF
402
10%
X5R
2
1
C2602
BUF_CLK
0.1UF
10%
X5R
402
16V
2
1
C2600
20%
X5R
10UF
6.3V
603
BUF_CLK
21
L2600
0402
FERR-120-OHM-1.5A
BUF_CLK
23
24
12 13 2720 21
5
28
9 16 2517 224831
33
11
10
2
3
15
14
26
7
6
18
19
1
30
32
29
U2600
OMIT
CRITICAL
QFN
SLG2AP108
2
1
C2621
5%
50V
402
18pF
CERM
BUF_CLK
21
Y2620
CRITICAL
5X3.2-SM
BUF_CLK
14.31818
2
1
C2620
50V
5%
402
CERM
18pF
BUF_CLK
49
49
64 65 91
2
1
C2652
BUF_CLK
16V
10%
402
X5R
0.1UF
2
1
C2651
BUF_CLK
0.1UF
X5R
402
10%
16V
2
1
C2650
BUF_CLK
10UF
X5R
603
20%
6.3V
21
L2650
BUF_CLK
FERR-120-OHM-1.5A
0402
17 85
21
R2650
BUF_CLK
402
MF-LF
1/16W
5%
2.2
2
1
R2690
1/16W
MF-LF
402
5%
10K
BUF_CLK
2
1
R2616
402
1/16W
5%
MF-LF
10M
NO STUFF
21
R2699
MF-LF1/16W
33
BUF_CLK
5% 402
PLACE R2699 NEAR PIN 26
2
1
R2600
5%
1/16W
402
MF-LF
10K
BUF_CLK
17 84
17 84
17 84
17 84
17 84
17 84
21
R2615
0
BUF_CLK
5% 1/16W
MF-LF402
17 84
17 84
SYNC_MASTER=K23F SYNC_DATE=11/30/2009
CLOCK (CK505)
PP1V5_S0_CK505_R
=PP3V3_S0_CK505
=PP1V05_S0_CK505
CK505_27MHZ_EN
PCH_CLK96M_DOT_P
PM_PGOOD_PVCORE_CPU
=SMBUS_CK505_SDA
=SMBUS_CK505_SCL
CK505_XTAL_OUT
PCH_CLK96M_DOT_N
TP_CK505_CLK27M_SS
PCH_CLK100M_SATA_P
PCH_CLK100M_SATA_N
PCIE_CLK100M_PCH_P
PCIE_CLK100M_PCH_N
FSB_CLK133M_PCH_N
FSB_CLK133M_PCH_P
PCH_CLK14P3M_REFCLK_R
CK505_CLK27M
PCH_CLK14P3M_REFCLK
=PP1V5_S0_CK505 PP1V5_S0_CK505_F
MIN_NECK_WIDTH=0.2mm
MIN_LINE_WIDTH=0.5mm
VOLTAGE=1.5V
CK505_XTAL_IN
CK505_XTAL_OUT_R
VOLTAGE=1.05V
MIN_NECK_WIDTH=0.2mm
MIN_LINE_WIDTH=0.5mm
PP1V05_S0_CK505_F
VOLTAGE=3.3V
MIN_LINE_WIDTH=0.5mm
MIN_NECK_WIDTH=0.2mm
PP3V3_S0_CK505_F
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DS
G
G
D
S
G
D
S
G
D
S
G S
D
G
D
S
S D
G
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
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REVISION
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87 54 21
LFD CANNOT CONTROL THIS SIGNAL DIRECTLY SINCE IT MUST BE HIGH IN SLEEP AND CPU MEM RAILS ARE NOT POWERED IN SLEEP.
MEM RESET ISOLATION
BUFFER ISOLATE_CPU_MEM_L TO 5V
1.5V 3.3V 1.5V
0 3.3V 0
CPU_RESET_L ISOLATE_L MEM_RESET_L
0 3.3V 0
0 3.3V 0
1.5V 3.3V 1.5V
0 0 1.5V
S5
S0
S5
S0
S3
S0
DDR3 RESET Support
2
1
R2753
1/16W
20K
5%
MF-LF
402
2
1
3
Q2704
SOT23-HF1
2N7002
2
1
R2752
5%
402
20K
1/16W
MF-LF
4
5
3
Q2706
SOT-363
2N7002DW-X-G
2
1
R2751
402
1/16W
MF-LF
20K
5%
1
2
6
Q2706
SOT-363
2N7002DW-X-G
2
1
R2750
20K
MF-LF
402
5%
1/16W
2
1
R2740
100K
1/16W
MF-LF
402
5%
2
1
R2784
MF-LF
402
5%
20K
1/16W
4
5
3
Q2770
SOT-363
2N7002DW-X-G
2
1
R2787
20K
5%
1/16W
402
MF-LF
2
1
R2741
1/16W
10
MF-LF
402
5%
2
1
3
Q2780
2N7002
SOT23-HF1
1
2
6
Q2770
SOT-363
2N7002DW-X-G
2
1
C2753
CERM
50V
10%
0.0022UF
402
3
2
1
4
5
Q2775
CRITICAL
FDMC8298
MLP3.3X3.3
DDR3 RESET
SYNC_DATE=01/06/2010SYNC_MASTER=MATT
=PP5V_S3_MEMRESET
MEM_RESET_L
ISOLATE_CPU_MEM_5V_L
VTT_R
PM_SLP_S3_5V
PM_SLP_S3_5V_L
PM_SLP_S3_L
PM_SLP_S3_5V
=PP5V_S3_MEMRESET
ISOLATE_CPU_MEM_L
ISOLATE_CPU_MEM
=PP3V3_S3_MEMRESET
=PP1V5_S3_MEMRESET
ISOLATE_CPU_MEM_5V_L
=PP0V75_S0_MEM_VTT_S0FET
PM_SLP_S3_5V_L
PPVTT_S0_DDR_FET
CPU_MEM_RESET_L
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26 28
26
26
5 18 36 46 47 63 64 81 91
26
5 26
20
5
5
26 28
5
26
5
10 91
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IN OUT
NCNC
OUT
OUT
OUT
OUT
IN
OUT
IN
IN
NC
NC
NCNC
OUT
OUT
OUT
OUT
IN
OUTIN
OUT
OUT
IN
OUT
OUT
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
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DRAWING NUMBER SIZE
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87 54 21
MAY NEED TO MOVE LONGER TRACE ONES TO BUFFERED
Buffered
511-0054
NOTE: R2800 and D2800 form the double-
Reset Button
fault protection for RTC battery.
Platform Reset Connections
Unbuffered
VTT voltage divider on CPU page
Coin-Cell Holder
UNUSED PCH 25MHZ CRYSTAL
RTC Power Sources
PCH RTC Crystal
10 24 91 18 46 91
12
R2800
5%
1/16W
MF-LF
1K
402
21
C2810
402
50V
5%
12pF
CERM
21
C2811
5%
50V
CERM
402
12pF
3
1
4
2
Y2810
SM-2
32.768K
CRITICAL
21
R2896
XDP
MF-LF
5%
0
1/16W
402
3
6
4
1
D2800
BAT54DW-X-G
SOT-363
21
R2883
33
5%
402
1/16W
MF-LF
21
R2881
5%
402
1/16W
33
MF-LF
21
R2890
1/16W
5%
402
MF-LF
33
48 91
46 91
8 91
33 91
17 85
17 85
19 91
21
R2826
33PLACEMENT_NOTE=Place close to U1800
5%
MF-LF
1/16W
402
21
R2825
33PLACEMENT_NOTE=Place close to U1800
1/16W
MF-LF
5%
402
19 85
39 91
21
R2892
MF-LF
402
33
1/16W
5%
48 85
46 85
10 91
19 85
17 85
21
R2827
PLACEMENT_NOTE=Place close to U1800 33
402
MF-LF
1/16W
5%
19 85
21
R2888
33
5%
402
MF-LF
1/16W
2
1
C2880
0.1UF
CERM
20%
10V
402
2
1
R2880
1/16W
100K
5%
402
MF-LF
37 91
21
R2882
33
402
5%
MF-LF
1/16W
1
2
J2800
BB10201-C1403-7H
SM
2
1
R2897
1/16W
402
MF-LF
5%
4.7K
2
1
R2811
1/16W
MF-LF
5%
402
10M
21
R2891
5%
1/16W
MF-LF
402
33
5
4
1
2
3
U2880
MC74VHC1G08
SOT23-5-HF
5
4
1
2
3
U2890
MC74VHC1G08
SOT23-5-HF
2
1
C2890
402
0.1UF
10V
20%
CERM
2
1
R2893
402
1/16W
5%
100K
MF-LF
21
R2810
MF-LF
0
5%
1/16W
402
21
R2895
33
1/16W
5%
402
MF-LF
44 91
17 85
17 85 21
R2820
402
5%
0
MF-LF
1/16W
2
1
R2898
805
SILK_PART=SYS RESET
0
1/8W
NOSTUFF
5%
MF-LF
21
R2887
1/16W
MF-LF
402
5%
33
28
SYNC_MASTER=K74_MASTER SYNC_DATE=N/A
CHIPSET SUPPORT
=PP3V3_S0_PCH_PM
PM_SYSRST_L
PCH_CLK25M_XTALIN
MAKE_BASE=TRUE
TP_PCH_CLK25M_XTALOUT
PCH_CLK32K_RTCX1
LPC_CLK33M_SMC_R
LPC_CLK33M_LPCPLUS_R
PCH_CLK33M_PCIOUT
PEG_RESET_L
PLT_RST_BUF2_L CPU_RESET_L
=PP3V3_S5_RTC_D
SDCARD_PLT_RST_L
=PP3V3_S0_RSTBUF
XDP_DBRESET_L
LPC_CLK33M_SMC
PCH_CLK33M_PCIIN
LPC_CLK33M_LPCPLUS
SMC_LRESET_L
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=3.3V
PP3V3_G3_RTC
MIN_LINE_WIDTH=0.3 mm
PPVBATT_G3_RTC_R
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=3.3V
MIN_LINE_WIDTH=0.3 mmMIN_LINE_WIDTH=0.3 mm
VOLTAGE=3.3V
PPVBATT_G3_RTC
MIN_NECK_WIDTH=0.2 mm
PCH_CLK32K_RTCX2_RPCH_CLK32K_RTCX2
PCH_CLK25M_XTALOUT
PLT_RST_BUF1_L
=PP3V3_S0_RSTBUF
DEBUG_RESET_L
ENET_RESET_L
FW_RESET_L
MINI_RESET_L
PLT_RESET_L
MAKE_BASE=TRUE
PCA9557D_RESET_L
28 OF 110
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25
5
5
5 27
17 21 23 89
89 89
5 27
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V-
V+
V-
V+
IN
DS
G
DS
G
RESET*
A0
A1
A2
SCL
SDA
P0
P1
P2
P5
P6
P7
P3
P4
THRM
VCC
GNDPAD
NC
NC
IN
BI
VDD
VOUTD
VOUTC
VOUTB
VOUTASCL
SDA
A0
A1
GND
IN
BI
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
BRANCH
REVISION
DRAWING NUMBER SIZE
D
R
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
21
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
87 54 21
MEM B VREF CA
Memory Reset Isolation
BOM options provided by this page:
Power aliases required by this page:
PLACE IT CLOSE TO DIMM CONNECTOR PIN
(OD)
RST* on ’platform reset’ so that system
NOTE: Margining will be disabled across all
soft-resets and sleep/wake cycles.
1.056V - 1.442V (+/- 180mV)
1.51mV / step @ output
+33uA - -33uA (- = sourced) +6.0mA - -5.0mA (- = sourced)
0.000V - 3.300V (0x00 - 0xFF)
1.267V (DAC: 0x8B)
6
D
GPU Frame Buffer (1.8V, 70% VRef)
0.75V (DAC: 0x3A) 1.5V (DAC: 0x3A)
0.000V - 1.501V (0x00 - 0x74)
1.998V - 1.002V (+/- 498mV)
8.59mV / step @ output
5
DDAC Channel:
PCA9557D Pin:
DAC range:
Nominal value
DAC step size:
VRef current:
Margined target:
MEM A VREF DQ
B
21
A
+3.4mA - -3.4mA (- = sourced)
7.69mV / step @ output
C
34
C
Addr=0x98(WR)/0x99(RD)
Addr=0x30(WR)/0x31(RD)
- =I2C_VREFDACS_SCL
- =I2C_PCA9557D_SCL
- =I2C_PCA9557D_SDA
- =I2C_VREFDACS_SDA
Signal aliases required by this page:
VREFMRGN - Stuffs VREF Margining
- =PP3V3_S3_VREFMRGN
Page Notes
Circuitry.
MEM VREG
PLACE IT CLOSE TO DIMM CONNECTOR PIN
PLACE IT CLOSE TO DIMM CONNECTOR PIN
watchdog will disable margining.
0.000V - 1.501V (0x00 - 0x74)
0.300V - 1.200V (+/- 450mV)
MEM B VREF DQ
PLACE IT CLOSE TO DIMM CONNECTOR PIN
MEM A VREF CA
2
1
C2902
VREFMRGN
0.1UF
CERM
402
20%
10V
B4
B1
C4
C1
C2
C3
U2902
VREFMRGN
MAX4253
UCSP
B4
B1
A4
A1
A2
A3
U2902
MAX4253
UCSP
VREFMRGN
27
21
R2904
CKD
332
1/16W
1%
402
MF-LF
21
R2906
CKD
332
1/16W
1%
MF-LF
402
2
1C2950
16V
402
0.1UF
X5R
10%
NOSTUFF
2
1
R2970
1%
1/16W
MF-LF
402
1K
2
1
R2971
1/16W
MF-LF
1%
402
1K
2
1
3
Q2993
LFD
SOT23-HF1
2N7002
2
1C2951
NOSTUFF
10%
0.1UF
402
X5R
16V
2
1
R2975
1/16W
1%
MF-LF
402
1K
2
1
R2976
402
MF-LF
1/16W
1%
1K
2
1
3
Q2991
LFD
2N7002
SOT23-HF1
2
1
R2988
1K
402
1%
MF-LF
1/16W
2
1C2921
NOSTUFF
16V
402
0.1UF
10%
X5R
2
1
R2989
1K
1/16W
MF-LF
1%
402
2
1
R2978
1K
MF-LF
1%
1/16W
402
2
1C2991
0.1UF
10%
402
X5R
16V
NOSTUFF
2
1
R2979
1/16W
MF-LF
1%
402
1K
2
1
R2902
5%
1/16W
MF-LF
402
VREFMRGN
100K
2
1
R2901
MF-LF
1/16W
5%
100K
402
VREFMRGN
16
17
2
1
15
14
13
12
11
10
9
7
6
8
5
4
3
U2901
PCA9557
QFN
VREFMRGN
CRITICAL
49
49
5
4
2
1
8
7
6
3
10
9
U2900
CRITICAL
MSOP
DAC5574
VREFMRGN
49
49
2
1
C2901
10V
20%
402
CERM
0.1UF
VREFMRGN
2
1
C2900
6.3V
20%
402-LF
CERM
2.2UF
VREFMRGN
2
1
C2903
VREFMRGN
402
CERM
20%
10V
0.1UF
SYNC_DATE=01/06/2010SYNC_MASTER=MATT
DDR3 Vref Margining
PP0V75_S3_MEM_VREFDQ_B
CPU_DIMM_VREF_B
PP0V75_S3_MEM_VREFDQ_A
PCA9557D_RESET_L
ISOLATE_CPU_MEM_5V_L ISOLATE_CPU_MEM_5V_L
PP0V75_S3_MEM_VREFCA_A
=PP1V5_S3_MEM_A
PP0V75_S3_MEM_VREFCA_B
=PP1V5_S3_MEM_A
=PP1V5_S3_MEM_B
VREFMRGN_DQ_SODIMMB_EN
PP0V75_S3_MEM_VREFDQ_B
PP0V75_S3_MEM_VREFDQ_A
=I2C_VREFDACS_SDA
=I2C_VREFDACS_SCL VREFMRGN_SODIMMA_DQ
=I2C_PCA9557D_SCL
=I2C_PCA9557D_SDA
VREFMRGN_SODIMMB_DQ
VREFMRGN_DQ_SODIMMA_EN
VREFMRGN_DQ_SODIMMB_BUF
=PP1V5_S3_MEM_A
CPU_DIMM_VREF_A
VREFMRGN_DQ_SODIMMA_BUF
=PP3V3_S3_VREFMRGN
29 OF 110
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26 28 26 28
30 89
5 28 29 30
31 89
5 28 29 30
5 29 31
28 31 89
28 30 89
5 28 29 30
11 83
5
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II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
BRANCH
REVISION
DRAWING NUMBER SIZE
D
R
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
21
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
87 54 21
DIMM B (CLOSER TO CPU)
DECOUPLING CAPS FOR DIMM ON CHANNEL A - AT CONNECTOR
DECOUPLING CAPS FOR DIMM ON CHANNEL B - AT CONNECTOR
EXTRA DECOUPLING CAPS FOR CPU MEM RAIL
CAPS TO COUPLE CPU 1V5_MEMDIMM A (FURTHER FROM CPU)
2
1
C3058
6.3V
1UF
10%
CERM
402
2
1
C3057
6.3V
1UF
10%
CERM
402
2
1
C3056
6.3V
1UF
10%
CERM
402
2
1
C3055
6.3V
1UF
10%
CERM
402
2
1
C3054
6.3V
1UF
10%
CERM
402
2
1
C3053
10%
6.3V
1UF
CERM
402
2
1
C3052
402
10%
CERM
1UF
6.3V
2
1
C3051
603
10UF
6.3V
X5R
20%
2
1
C3050
603
20%
6.3V
X5R
10UF
2
1
C3085
402
CERM
10%
1UF
6.3V
2
1
C3084
402
CERM
10%
1UF
6.3V
2
1
C3083
402
CERM
10%
1UF
6.3V
2
1
C3082
402
CERM
10%
1UF
6.3V
2
1
C3081
6.3V
1UF
10%
CERM
402
2
1
C3080
6.3V
1UF
10%
CERM
402
2
1
C3079
6.3V
1UF
10%
CERM
402
2
1
C3078
6.3V
1UF
10%
CERM
402
2
1
C3077
6.3V
1UF
10%
CERM
402
2
1
C3076
6.3V
1UF
10%
CERM
402
2
1
C3075
6.3V
1UF
10%
CERM
402
2
1
C3074
6.3V
1UF
10%
CERM
402
2
1
C3073
10%
6.3V
1UF
CERM
402
2
1
C3072
402
10%
CERM
1UF
6.3V
2
1
C3071
603
10UF
6.3V
X5R
20%
2
1
C3070
20%
6.3V
X5R
603
10UF
2
1
C3094
402
CERM
10%
1UF
6.3V
2
1
C3093
402
CERM
10%
1UF
6.3V
2
1
C3092
402
CERM
10%
1UF
6.3V
2
1
C3091
402
CERM
10%
1UF
6.3V
2
1
C3090
402
CERM
10%
1UF
6.3V
2
1
C3049
402
CERM
10%
1UF
6.3V
2
1
C3048
402
CERM
10%
1UF
6.3V
2
1
C3047
402
CERM
10%
1UF
6.3V
2
1
C3045
6.3V
1UF
10%
CERM
402
2
1
C3043
402
CERM
1UF
6.3V
10%
2
1
C3040
402
10%
CERM
6.3V
1UF
2
1
C30A4
10%
6.3V
402
CERM
1UF
2
1
C30A3
10%
6.3V
402
CERM
1UF
2
1
C30A2
10%
6.3V
402
CERM
1UF
2
1
C30A1
10%
402
CERM
1UF
6.3V
2
1
C30A0
6.3V
CERM
10%
402
1UF
2
1
C30AE
10%
6.3V
1UF
CERM
402
2
1
C30AD
6.3V
1UF
10%
CERM
402
2
1
C30AC
6.3V
CERM
1UF
10%
402
2
1
C30AB
CERM
6.3V
1UF
10%
402
2
1
C30AA
6.3V
1UF
10%
CERM
402
2
1
C30A9
6.3V
1UF
10%
CERM
402
2
1
C30A8
6.3V
402
1UF
10%
CERM
2
1
C30A7
6.3V
1UF
10%
CERM
402
2
1
C30A6
10%
6.3V
1UF
CERM
402
2
1
C30A5
10%
402
CERM
6.3V
1UF
2
1
C3066
6.3V
1UF
10%
CERM
402
2
1
C3067
402
CERM
10%
1UF
6.3V
2
1
C3068
402
CERM
10%
1UF
6.3V
2
1
C3069
402
CERM
10%
1UF
6.3V
2
1
C3089
6.3V
1UF
10%
CERM
402
2
1
C3088
6.3V
1UF
10%
CERM
402
2
1
C3087
6.3V
1UF
10%
CERM
402
2
1
C3086
6.3V
1UF
10%
CERM
402
2
1C3016
402
CERM
10%
1UF
6.3V
2
1C3017
402
CERM
10%
1UF
6.3V
2
1C3018
CERM
10%
1UF
6.3V
402
2
1C3019
402
CERM
1UF
6.3V
10%
2
1C3010
CERM
10%
1UF
6.3V
402
2
1C3025
402
CERM
10%
1UF
6.3V
2
1C3026
402
CERM
10%
1UF
6.3V
2
1C3027
402
CERM
10%
1UF
6.3V
2
1C3028
402
CERM
10%
1UF
6.3V
2
1C3029
6.3V
1UF
10%
CERM
402
2
1C3020
402
CERM
10%
1UF
6.3V
2
1C3021
402
CERM
10%
1UF
6.3V
2
1C3022
402
CERM
10%
1UF
6.3V
2
1C3023
402
CERM
10%
1UF
6.3V
2
1C3014
402
CERM
10%
1UF
6.3V
2
1C3030
402
CERM
10%
1UF
6.3V
2
1C3031
402
CERM
10%
1UF
6.3V
2
1C3032
402
CERM
10%
1UF
6.3V
2
1C3033
6.3V
1UF
10%
CERM
402
2
1
C3041
402
10%
CERM
6.3V
1UF
2
1
C3042
402
10%
CERM
6.3V
1UF
2
1
C3044
402
10%
CERM
6.3V
1UF
2
1
C3046
1UF
6.3V
CERM
10%
402
2
1
C3065
6.3V
1UF
10%
CERM
402
2
1
C3064
6.3V
1UF
10%
CERM
402
2
1
C3063
1UF
10%
CERM
402
6.3V
2
1
C3062
6.3V
1UF
10%
402
CERM
2
1
C3061
6.3V
1UF
10%
CERM
402
2
1
C3060
6.3V
1UF
10%
CERM
402
2
1
C3059
6.3V
1UF
10%
CERM
402
MEMORY CAPS
SYNC_MASTER=K74_MASTER SYNC_DATE=N/A
=PP1V5_CPU_MEM
=PP1V5_CPU_MEM
=PP1V5_S3_MEM_A
=PP1V5_CPU_MEM
=PP1V5_S3_MEM_B
30 OF 110
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051-8337
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5 10 12 15 29
5 10 12 15 29
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5 10 12 15 29
5 28 31
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S1*
A13
VDD_14
CAS*
VDD_12
BA0
A10_AP
WE*
A3
DQ54
DQ55
VSS_44
VSS_0
VSS_2
VSS_5
DQS0
DQS0*
DQ5
DQ4
DQ6
DQ7
VREFDQ
VSS_1
VSS_3
DQ0
DQ1
DM0
VSS_4
VSS_7
DQ12
DQ20
VSS_13
DQ15
DQ14
VSS_11
RESET*
VSS_9
DQ13
DM1
DQ21
VSS_15
DQ22
VSS_16
VSS_18
DQ23
DQ28
DQS3*
VSS_20
DQ29
DM2
VSS_23
DQS3
DQ30
DQ31
VSS_25
VDD_1
CKE1
A15
A14
VDD_3
VDD_9
VDD_5
VDD_7
A7
A11
A4
A6
A2
A0
CK1
NC_1
ODT1
VDD_15
ODT0
VDD_13
RAS*
VDD_11
CK1*
BA1
S0*
DQ39
DQ38
VSS_30
VSS_29
DQ37
DQ36
VSS_27
VREFCA
VDD_17
DM4
VSS_32
DQ47
DQ44
DQ46
VSS_37
DQS5
DQS5*
VSS_39
VSS_34
DQ45
DQ52
VSS_46
DQ61
DQ60
VSS_42
VSS_41
DQ53
DM6
VTT_1
DQS7*
DQS7
EVENT*
VSS_51
DQ63
DQ62
VSS_49
SDA
SCL
DQ2
DQ3
VSS_6
DQ8
DQ9
VSS_8
DQS1*
DQS1
VSS_10
DQ16
VSS_12
DQ11
DQ10
DQ17
DQ18
DQS2
VSS_17
DQS2*
VSS_14
VSS_21
DQ24
DQ25
DQ19
VSS_19
VSS_24
DQ27
DQ26
DM3
VSS_22
CKE0
A5
VDD_4
CK0
VDD_8
A1
VDD_6
VDD_10
CK0*
DQ33
VSS_26
VDD_16
TEST
DQ32
DQ34
VSS_31
DQS4
DQS4*
VSS_28
DQ35
DQ41
VSS_33
VSS_35
DQ40
DM5
VSS_38
DQ43
DQ42
VSS_36
DQ48
VSS_43
DQS6*
DQS6
VSS_40
DQ49
DQ50
VSS_45
DQ56
DQ57
VSS_47
DM7
DQ58
VSS_48
DQ59
SA0
VSS_50
A8
A9
A12/BC*
VDD_2
BA2
NC_0
VDD_0
DQ51
VTT_0
SA1
VDDSPD
MTG PIN MTG PIN
KEY
(1 OF 2)
DQ3
VSS_10
VSS_19
DQ9
VSS_8
DQS1*
DQS1
VSS_21
DQ26
CKE0
BA2
A9
A8
VDD_6
VDD_8
CK0*
A10_AP
BA0
SA0
VTT_0
SA1
VDDSPD
VSS_50
VSS_47
DM7
DQ58
DQ59
DQ57
DQ56
VSS_45
DQ51
DQ50
DQS6
VSS_43
DQS6*
VSS_40
DQ49
DQ48
VSS_38
DQ43
DQ42
VSS_36
DM5
VSS_35
DQ41
DQ40
DQ35
DQ34
VSS_31
DQS4
DQS4*
VSS_28
VSS_26
DQ32
DQ33
TEST
VDD_16
S1*
A13
CAS*
VDD_14
WE*
VDD_12
VDD_10
CK0
A1
A3
A5
VDD_4
A12/BC*
VDD_2
VDD_0
NC_0
DQ11
DQ16
VSS_12
DQ10
DQ8
DM0
VSS_4
VSS_6
DQ2
VREFDQ
DQ0
VSS_3
DQ1
VSS_1
SCL
SDA
VTT_1
VSS_51
VSS_49
DQ63
DQS7
DQS7*
EVENT*
DQ62
DM6
DQ60
VSS_46
VSS_41
DQ53
DQ55
VSS_44
DQ54
VSS_42
DQ61
DQ52
DQ44
VSS_34
DQS5*
VSS_37
DQ46
DQ47
VSS_39
DQ45
DQS5
VSS_32
DM4
VSS_27
VSS_29
DQ36
VREFCA
VDD_17
DQ37
DQ38
DQ39
VSS_30
BA1
NC_1
VDD_13
VDD_11
VDD_15
ODT0
CK1
A0
A2
A6
A4
A7
A11
VDD_9
VDD_7
VDD_5
VDD_3
A15
A14
CKE1
VDD_1
DM1
DQ15
DQ14
DQ13
VSS_11
VSS_9
RESET*
VSS_13
DQ20
DQ12
DQ7
DQ6
DQ5
DQ4
VSS_7
DQS0*
VSS_2
VSS_0
DQS0
VSS_5
DQ21
VSS_15
DM2
VSS_16
DQ22
VSS_18
DQ23
DQ28
VSS_20
DQ29
DQS3
VSS_23
DQS3*
DQ30
DQ31
VSS_25
VSS_14
DQ17
DQS2*
VSS_17
DQS2
DQ18
DQ19
DQ25
DQ24
DM3
VSS_22
DQ27
VSS_24
CK1*
RAS*
S0*
ODT1
VSS_33
VSS_48
KEY
(2 OF 2)
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
BRANCH
REVISION
DRAWING NUMBER SIZE
D
R
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
21
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
87 54 21
DIMM 0 DIMM 2
DIMM0 SPD ADDR=0XA0(WR)/0XA1(RD)
Signal aliases required by this page:
- =I2C_SODIMMA_SDA
- =PP1V5_S3_MEM_A
- =PP1V5_S0_MEM_A
Page Notes
- =I2C_SODIMMA_SCL
TO FACILITATE BITSWAPS WITH ALIASES
- ALL DQ, DQS, DM SIGNALS;
DIMM2 SPD ADDR=0XA2(WR)/0XA3(RD)
Power aliases required by this page:
- =PPSPD_S0_MEM_A (2.5 - 3.3V)
- =PP0V75_S0_MEM_VTT_A
(NONE)
BOM options provided by this page:
2
1
C3131
CERM
20%
0.1UF
10V
402
2
1
C3130
402-LF
6.3V
20%
2.2UF
CERM
2
1
C3136
CERM
402
0.1UF
20%
10V
2
1
C3135
2.2UF
6.3V
CERM
20%
402-LF
2
1
C3151
20%
2.2UF
6.3V
402-LF
CERM
2
1
C3150
CERM
402-LF
20%
2.2UF
6.3V
2
1
R3141
1/16W
10K
402
5%
MF-LF
2
1
R3140
MF-LF
402
1/16W
10K
5%
2
1
C3140
2.2UF
20%
CERM
6.3V
402-LF
2
1
R3142
MF-LF
1/16W
402
5%
10K
2
1
R3143
MF-LF
1/16W
5%
402
10K
113A
204A203A
26A25A
20A19A
14A
196A195A
13A
190A189A
185A
184A
179A
178A
173A
172A
168A167A
9A
162A161A
156A155A
151A
150A
145A
144A
139A
138A
8A
134A133A
128A127A
72A71A
66A65A
61A
60A
3A
55A
54A
49A
48A
44A43A
38A37A
32A31A
2A1A
126A
199A
100A99A
94A93A
88A87A
82A81A
76A
124A123A
118A117A
112A111A
106A105A
75A
125A
200A
202A201A
197A
121A
114A
30A
110A
120A
116A
122A
77A
410409
198A
186A
188A
169A
171A
152A
154A
135A
137A
62A
64A
45A
47A
27A
29A
10A
12A
23A
21A
18A
16A
194A
192A
182A
180A
6A
193A
191A
183A
181A
176A
174A
166A
164A
177A
175A
4A
165A
163A
160A
158A
148A
146A
159A
157A
149A
147A
17A
142A
140A
132A
130A
143A
141A
131A
129A
70A
68A
15A
58A
56A
69A
67A
59A
57A
52A
50A
42A
40A
7A
53A
51A
41A
39A
36A
34A
24A
22A
35A
33A
5A
187A
170A
153A
136A
63A
46A
28A
11A
74A73A
104A
102A
103A
101A
115A
79A
108A
109A
85A
89A
86A
90A
91A 92A
95A 96A
97A
78A
80A
119A
83A 84A
107A
98A
J3100
CRITICAL
DDR3-SODIMM-DUAL
F-RT-TH
113B
204B203B
26B25B
20B19B
14B
196B195B
13B
190B189B
185B
184B
179B
178B
173B
172B
168B167B
9B
162B161B
156B155B
151B
150B
145B
144B
139B
138B
8B
134B133B
128B127B
72B71B
66B65B
61B
60B
3B
55B
54B
49B
48B
44B43B
38B37B
32B31B
2B1B
126B
199B
100B99B
94B93B
88B87B
82B81B
76B
124B123B
118B117B
112B111B
106B105B
75B
125B
200B
202B201B
197B
121B
114B
30B
110B
120B
116B
122B
77B
198B
186B
188B
169B
171B
152B
154B
135B
137B
62B
64B
45B
47B
27B
29B
10B
12B
23B
21B
18B
16B
194B
192B
182B
180B
6B
193B
191B
183B
181B
176B
174B
166B
164B
177B
175B
4B
165B
163B
160B
158B
148B
146B
159B
157B
149B
147B
17B
142B
140B
132B
130B
143B
141B
131B
129B
70B
68B
15B
58B
56B
69B
67B
59B
57B
52B
50B
42B
40B
7B
53B
51B
41B
39B
36B
34B
24B
22B
35B
33B
5B
187B
170B
153B
136B
63B
46B
28B
11B
74B73B
104B
102B
103B
101B
115B
79B
108B
109B
85B
89B
86B
90B
91B 92B
95B 96B
97B
78B
80B
119B
83B 84B
107B
98B
J3100
CRITICAL
DDR3-SODIMM-DUAL
F-RT-TH
DDR3 SO-DIMMs 0 & 2
SYNC_MASTER=K74_MASTER SYNC_DATE=N/A
=MEM_A_DQ<38>
=MEM_A_DQ<39>
=MEM_A_DQ<8>
=MEM_A_DQ<1>
=MEM_A_DQS_P<6>
=MEM_A_DQ<58>
=PPSPD_S0_MEM_A
MEM_DIMM2_SA<1>
=PP0V75_S0_MEM_VTT_A
=MEM_A_DM<1>
=MEM_A_DQ<14>
=MEM_A_DQ<21>
=MEM_A_DQ<20>
=MEM_A_DQ<13>
=MEM_A_DQ<61>
=MEM_A_DQS_P<7>
=MEM_A_DQ<63>
MEM_EVENT_L
=I2C_SODIMMA_SDA
=I2C_SODIMMA_SCL
=MEM_A_DQ<42>
=PP1V5_S3_MEM_A
=MEM_A_DQ<29>
MEM_A_A<4>
=PPSPD_S0_MEM_A
MEM_A_A<0>
=MEM_A_CLK_P<3>
=MEM_A_DM<6>
=MEM_A_DQ<36>
=MEM_A_DQS_N<6>
=MEM_A_DQ<49>
=MEM_A_DQ<48>
=MEM_A_DQ<43>
=MEM_A_DQ<17>
=MEM_A_DQS_N<2>
MEM_A_CKE<1>
=PP1V5_S3_MEM_A
MEM_A_A<15>
=MEM_A_DQ<0>
=MEM_A_DM<0>
=MEM_A_DQ<2>
=MEM_A_DQ<3>
=MEM_A_DQ<9>
=MEM_A_DM<2>
=MEM_A_DQ<12>
=MEM_A_DQ<5>
=PP1V5_S3_MEM_A
MEM_A_A<6>
MEM_A_A<4>
MEM_A_A<14>
=MEM_A_DQS_P<3>
MEM_A_A<5>
=MEM_A_DQS_P<2>
=MEM_A_DQ<19>
=MEM_A_DQ<18>
=MEM_A_DQS_N<0>
=MEM_A_DQ<4>
PP0V75_S3_MEM_VREFDQ_A
=MEM_A_CLK_P<0>
MEM_A_A<10>
MEM_A_BA<0>
=MEM_A_CLK_N<0>
MEM_A_CKE<0>
=MEM_A_DQ<27>
=MEM_A_DQ<25>
=MEM_A_DQ<16>
=MEM_A_DQS_P<1>
MEM_DIMM0_SA<0>
=PPSPD_S0_MEM_A
=PP0V75_S0_MEM_VTT_A
PP0V75_S3_MEM_VREFDQ_A
PP0V75_S3_MEM_VREFCA_A
MEM_DIMM0_SA<1>
MEM_DIMM2_SA<0>
MEM_DIMM2_SA<1>
=PPSPD_S0_MEM_A
MEM_DIMM0_SA<1>
=PP0V75_S0_MEM_VTT_A
=MEM_A_DQ<51>
MEM_A_BA<2>
MEM_A_A<12>
MEM_DIMM0_SA<0>
=MEM_A_DQ<59>
=MEM_A_DQ<58>
=MEM_A_DM<7>
=MEM_A_DQ<57>
=MEM_A_DQ<56>
=MEM_A_DQ<50>
=MEM_A_DQ<49>
=MEM_A_DQS_P<6>
=MEM_A_DQ<48>
=MEM_A_DQ<43>
=MEM_A_DM<5>
=MEM_A_DQ<40>
=MEM_A_DQ<41>
=MEM_A_DQ<35>
=MEM_A_DQS_N<4>
=MEM_A_DQS_P<4>
=MEM_A_DQ<34>
=MEM_A_DQ<32>
=MEM_A_DQ<33>
=MEM_A_DM<3>
=MEM_A_DQ<26>
=MEM_A_DQ<24>
=MEM_A_DQ<10>
=MEM_A_DQ<11>
=MEM_A_DQS_N<1>
=MEM_A_DQ<62>
=MEM_A_DQS_N<7>
=PP0V75_S0_MEM_VTT_A
=MEM_A_DM<6>
=MEM_A_DQ<53>
=MEM_A_DQ<60>
=MEM_A_DQ<52>
=MEM_A_DQ<45>
=MEM_A_DQS_N<5>
=MEM_A_DQS_P<5>
=MEM_A_DQ<46>
=MEM_A_DQ<44>
=MEM_A_DQ<47>
=MEM_A_DM<4>
PP0V75_S3_MEM_VREFCA_A
=MEM_A_DQ<36>
=MEM_A_DQ<37>
=MEM_A_DQ<38>
=MEM_A_DQ<39>
MEM_A_CS_L<0>
MEM_A_BA<1>
=MEM_A_CLK_N<1>
MEM_A_RAS_L
MEM_A_ODT<0>
MEM_A_ODT<1>
=MEM_A_CLK_P<1>
=MEM_A_DQ<31>
=MEM_A_DQ<30>
=MEM_A_DQS_P<3>
=MEM_A_DQ<29>
=MEM_A_DQS_N<3>
=MEM_A_DQ<28>
=MEM_A_DQ<23>
=MEM_A_DQ<22>
MEM_RESET_L
=MEM_A_DQ<15>
=MEM_A_DQ<7>
=MEM_A_DQ<6>
=MEM_A_DQS_P<0>
=MEM_A_DQ<55>
=MEM_A_DQ<54>
MEM_A_WE_L
MEM_A_CAS_L
MEM_A_A<13>
MEM_A_CS_L<1>
MEM_A_ODT<3>
MEM_A_CS_L<2>
MEM_A_RAS_L
=MEM_A_CLK_N<3>
=MEM_A_DQ<27>
=MEM_A_DM<3>
=MEM_A_DQ<24>
=MEM_A_DQ<25>
=MEM_A_DQ<19>
=MEM_A_DQ<18>
=MEM_A_DQS_P<2>
=MEM_A_DQS_N<2>
=MEM_A_DQ<17>
=MEM_A_DQ<31>
=MEM_A_DQ<30>
=MEM_A_DQS_N<3>
=MEM_A_DQ<28>
=MEM_A_DQ<23>
=MEM_A_DQ<22>
=MEM_A_DM<2>
=MEM_A_DQ<21>
=MEM_A_DQS_P<0>
=MEM_A_DQS_N<0>
=MEM_A_DQ<4>
=MEM_A_DQ<5>
=MEM_A_DQ<6>
=MEM_A_DQ<7>
=MEM_A_DQ<12>
=MEM_A_DQ<20>
MEM_RESET_L
=MEM_A_DQ<13>
=MEM_A_DQ<14>
=MEM_A_DQ<15>
=MEM_A_DM<1>
MEM_A_CKE<3>
MEM_A_A<14>
MEM_A_A<15>
MEM_A_A<11>
MEM_A_A<7>
MEM_A_A<6>
MEM_A_A<2>
MEM_A_ODT<2>
MEM_A_BA<1>
=MEM_A_DQ<37>
PP0V75_S3_MEM_VREFCA_A
=MEM_A_DM<4>
=MEM_A_DQS_P<5>
=MEM_A_DQ<45>
=MEM_A_DQ<47>
=MEM_A_DQ<46>
=MEM_A_DQS_N<5>
=MEM_A_DQ<44>
=MEM_A_DQ<52>
=MEM_A_DQ<61>
=MEM_A_DQ<54>
=MEM_A_DQ<55>
=MEM_A_DQ<53>
=MEM_A_DQ<60>
=MEM_A_DQ<62>
MEM_EVENT_L
=MEM_A_DQS_N<7>
=MEM_A_DQS_P<7>
=MEM_A_DQ<63>
=PP0V75_S0_MEM_VTT_A
=I2C_SODIMMA_SDA
=I2C_SODIMMA_SCL
=MEM_A_DQ<1>
=MEM_A_DQ<0>
PP0V75_S3_MEM_VREFDQ_A
=MEM_A_DQ<2>
=MEM_A_DM<0>
=MEM_A_DQ<8>
=MEM_A_DQ<10>
=MEM_A_DQ<16>
=MEM_A_DQ<11>
MEM_A_A<12>
MEM_A_A<5>
MEM_A_A<3>
MEM_A_A<1>
=MEM_A_CLK_P<2>
MEM_A_WE_L
MEM_A_CAS_L
MEM_A_A<13>
MEM_A_CS_L<3>
=MEM_A_DQ<33>
=MEM_A_DQ<32>
=MEM_A_DQS_N<4>
=MEM_A_DQS_P<4>
=MEM_A_DQ<34>
=MEM_A_DQ<35>
=MEM_A_DQ<40>
=MEM_A_DQ<41>
=MEM_A_DM<5>
=MEM_A_DQ<42>
=MEM_A_DQS_N<6>
=MEM_A_DQ<50>
=MEM_A_DQ<51>
=MEM_A_DQ<56>
=MEM_A_DQ<57>
=MEM_A_DQ<59>
=MEM_A_DM<7>
MEM_DIMM2_SA<0>
MEM_A_BA<0>
MEM_A_A<10>
=MEM_A_CLK_N<2>
=PP1V5_S3_MEM_A
MEM_A_A<8>
MEM_A_A<9>
MEM_A_BA<2>
MEM_A_CKE<2>
=MEM_A_DQ<26>
=MEM_A_DQS_P<1>
=MEM_A_DQS_N<1>
=MEM_A_DQ<9>
=MEM_A_DQ<3>
MEM_A_A<11>
MEM_A_A<7>
MEM_A_A<2>
MEM_A_A<0>MEM_A_A<1>
MEM_A_A<3>
MEM_A_A<8>
MEM_A_A<9>
31 OF 110
A.0.0
051-8337
30 OF 92
30 32
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30
5 30
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30 31 47
30 49
30 49
30 32
5 28 29 30
30 32
11 30 83
5 30 47
11 30 83
32
30 32
30 32
30 32
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30 32
30 32
30 32
30 32
11 83
5 28 29 30
11 30 83
30 32
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30 32
30 32
5 28 29 30
11 30 83
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30 32
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30 32
30 32
30 32
30 32
30 32
28 30 89
32
11 30 83
11 30 83
32
11 83
30 32
30 32
30 32
30 32
30
5 30 47
5 30
28 30 89
28 30 89
30
30
30
5 30 47
30
5 30
30 32
11 30 83
11 30 83
30
30 32
30 32
30 32
30 32
30 32
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30 32
30 32
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30 32
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30 32
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30 32
30 32
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30 32
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30 32
30 32
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30 32
5 30
30 32
30 32
30 32
30 32
30 32
30 32
30 32
30 32
30 32
30 32
30 32
28 30 89
30 32
30 32
30 32
30 32
11 83
11 30 83
32
11 30 83
11 83
11 83
32
30 32
30 32
30 32
30 32
30 32
30 32
30 32
30 32
26 30 31 91
30 32
30 32
30 32
30 32
30 32
30 32
11 30 83
11 30 83
11 30 83
11 83
11 83
11 83
11 30 83
32
30 32
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30 32
30 32
30 32
30 32
30 32
30 32
30 32
30 32
30 32
30 32
30 32
30 32
30 32
30 32
26 30 31 91
30 32
30 32
30 32
30 32
11 83
11 30 83
11 30 83
11 30 83
11 30 83
11 30 83
11 30 83
11 83
11 30 83
30 32
28 30 89
30 32
30 32
30 32
30 32
30 32
30 32
30 32
30 32
30 32
30 32
30 32
30 32
30 32
30 32
30 31 47
30 32
30 32
30 32
5 30
30 49
30 49
30 32
30 32
28 30 89
30 32
30 32
30 32
30 32
30 32
30 32
11 30 83
11 30 83
11 30 83
11 30 83
32
11 30 83
11 30 83
11 30 83
11 83
30 32
30 32
30 32
30 32
30 32
30 32
30 32
30 32
30 32
30 32
30 32
30 32
30 32
30 32
30 32
30 32
30 32
30
11 30 83
11 30 83
32
5 28 29 30
11 30 83
11 30 83
11 30 83
11 83
30 32
30 32
30 32
30 32
30 32
11 30 83
11 30 83
11 30 83
11 30 83 11 30 83
11 30 83
11 30 83
11 30 83
www.vinaﬁx.vn

S1*
A13
VDD_14
CAS*
VDD_12
BA0
A10_AP
WE*
A3
DQ54
DQ55
VSS_44
VSS_0
VSS_2
VSS_5
DQS0
DQS0*
DQ5
DQ4
DQ6
DQ7
VREFDQ
VSS_1
VSS_3
DQ0
DQ1
DM0
VSS_4
VSS_7
DQ12
DQ20
VSS_13
DQ15
DQ14
VSS_11
RESET*
VSS_9
DQ13
DM1
DQ21
VSS_15
DQ22
VSS_16
VSS_18
DQ23
DQ28
DQS3*
VSS_20
DQ29
DM2
VSS_23
DQS3
DQ30
DQ31
VSS_25
VDD_1
CKE1
A15
A14
VDD_3
VDD_9
VDD_5
VDD_7
A7
A11
A4
A6
A2
A0
CK1
NC_1
ODT1
VDD_15
ODT0
VDD_13
RAS*
VDD_11
CK1*
BA1
S0*
DQ39
DQ38
VSS_30
VSS_29
DQ37
DQ36
VSS_27
VREFCA
VDD_17
DM4
VSS_32
DQ47
DQ44
DQ46
VSS_37
DQS5
DQS5*
VSS_39
VSS_34
DQ45
DQ52
VSS_46
DQ61
DQ60
VSS_42
VSS_41
DQ53
DM6
VTT_1
DQS7*
DQS7
EVENT*
VSS_51
DQ63
DQ62
VSS_49
SDA
SCL
DQ2
DQ3
VSS_6
DQ8
DQ9
VSS_8
DQS1*
DQS1
VSS_10
DQ16
VSS_12
DQ11
DQ10
DQ17
DQ18
DQS2
VSS_17
DQS2*
VSS_14
VSS_21
DQ24
DQ25
DQ19
VSS_19
VSS_24
DQ27
DQ26
DM3
VSS_22
CKE0
A5
VDD_4
CK0
VDD_8
A1
VDD_6
VDD_10
CK0*
DQ33
VSS_26
VDD_16
TEST
DQ32
DQ34
VSS_31
DQS4
DQS4*
VSS_28
DQ35
DQ41
VSS_33
VSS_35
DQ40
DM5
VSS_38
DQ43
DQ42
VSS_36
DQ48
VSS_43
DQS6*
DQS6
VSS_40
DQ49
DQ50
VSS_45
DQ56
DQ57
VSS_47
DM7
DQ58
VSS_48
DQ59
SA0
VSS_50
A8
A9
A12/BC*
VDD_2
BA2
NC_0
VDD_0
DQ51
VTT_0
SA1
VDDSPD
MTG PIN MTG PIN
KEY
(1 OF 2)
DQ3
VSS_10
VSS_19
DQ9
VSS_8
DQS1*
DQS1
VSS_21
DQ26
CKE0
BA2
A9
A8
VDD_6
VDD_8
CK0*
A10_AP
BA0
SA0
VTT_0
SA1
VDDSPD
VSS_50
VSS_47
DM7
DQ58
DQ59
DQ57
DQ56
VSS_45
DQ51
DQ50
DQS6
VSS_43
DQS6*
VSS_40
DQ49
DQ48
VSS_38
DQ43
DQ42
VSS_36
DM5
VSS_35
DQ41
DQ40
DQ35
DQ34
VSS_31
DQS4
DQS4*
VSS_28
VSS_26
DQ32
DQ33
TEST
VDD_16
S1*
A13
CAS*
VDD_14
WE*
VDD_12
VDD_10
CK0
A1
A3
A5
VDD_4
A12/BC*
VDD_2
VDD_0
NC_0
DQ11
DQ16
VSS_12
DQ10
DQ8
DM0
VSS_4
VSS_6
DQ2
VREFDQ
DQ0
VSS_3
DQ1
VSS_1
SCL
SDA
VTT_1
VSS_51
VSS_49
DQ63
DQS7
DQS7*
EVENT*
DQ62
DM6
DQ60
VSS_46
VSS_41
DQ53
DQ55
VSS_44
DQ54
VSS_42
DQ61
DQ52
DQ44
VSS_34
DQS5*
VSS_37
DQ46
DQ47
VSS_39
DQ45
DQS5
VSS_32
DM4
VSS_27
VSS_29
DQ36
VREFCA
VDD_17
DQ37
DQ38
DQ39
VSS_30
BA1
NC_1
VDD_13
VDD_11
VDD_15
ODT0
CK1
A0
A2
A6
A4
A7
A11
VDD_9
VDD_7
VDD_5
VDD_3
A15
A14
CKE1
VDD_1
DM1
DQ15
DQ14
DQ13
VSS_11
VSS_9
RESET*
VSS_13
DQ20
DQ12
DQ7
DQ6
DQ5
DQ4
VSS_7
DQS0*
VSS_2
VSS_0
DQS0
VSS_5
DQ21
VSS_15
DM2
VSS_16
DQ22
VSS_18
DQ23
DQ28
VSS_20
DQ29
DQS3
VSS_23
DQS3*
DQ30
DQ31
VSS_25
VSS_14
DQ17
DQS2*
VSS_17
DQS2
DQ18
DQ19
DQ25
DQ24
DM3
VSS_22
DQ27
VSS_24
CK1*
RAS*
S0*
ODT1
VSS_33
VSS_48
KEY
(2 OF 2)
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
BRANCH
REVISION
DRAWING NUMBER SIZE
D
R
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
21
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
87 54 21
- =I2C_SODIMMB_SCL
Signal aliases required by this page:
TO FACILITATE BITSWAPS WITH ALIASES
- ALL DQ, DQS, DM SIGNALS;
(NONE)
Power aliases required by this page:
Page Notes
- =PP1V5_S0_MEM_B
- =PP1V5_S3_MEM_B
- =PP0V75_S0_MEM_VTT_B
- =PPSPD_S0_MEM_B (2.5 - 3.3V)
- =I2C_SODIMMB_SDA
BOM options provided by this page:
DIMM3 SPD ADDR=0XA6(WR)/0XA7(RD)
DIMM 1 DIMM 3
DIMM1 SPD ADDR=0XA4(WR)/0XA5(RD)
2
1
C3231
0.1UF
20%
10V
CERM
402
2
1
C3230
CERM
2.2UF
20%
6.3V
402-LF
2
1
C3236
10V
402
CERM
0.1UF
20%
2
1
C3235
402-LF
20%
CERM
6.3V
2.2UF
2
1
C3251
CERM
402-LF
6.3V
20%
2.2UF
2
1
C3250
6.3V
2.2UF
20%
402-LF
CERM
2
1
R3243
10K
5%
1/16W
MF-LF
402
2
1
R3242
10K
MF-LF
1/16W
5%
402
2
1
C3240
20%
2.2UF
6.3V
402-LF
CERM
2
1
R3240
10K
5%
402
1/16W
MF-LF
2
1
R3241
MF-LF
1/16W
5%
402
10K
113A
204A203A
26A25A
20A19A
14A
196A195A
13A
190A189A
185A
184A
179A
178A
173A
172A
168A167A
9A
162A161A
156A155A
151A
150A
145A
144A
139A
138A
8A
134A133A
128A127A
72A71A
66A65A
61A
60A
3A
55A
54A
49A
48A
44A43A
38A37A
32A31A
2A1A
126A
199A
100A99A
94A93A
88A87A
82A81A
76A
124A123A
118A117A
112A111A
106A105A
75A
125A
200A
202A201A
197A
121A
114A
30A
110A
120A
116A
122A
77A
410409
198A
186A
188A
169A
171A
152A
154A
135A
137A
62A
64A
45A
47A
27A
29A
10A
12A
23A
21A
18A
16A
194A
192A
182A
180A
6A
193A
191A
183A
181A
176A
174A
166A
164A
177A
175A
4A
165A
163A
160A
158A
148A
146A
159A
157A
149A
147A
17A
142A
140A
132A
130A
143A
141A
131A
129A
70A
68A
15A
58A
56A
69A
67A
59A
57A
52A
50A
42A
40A
7A
53A
51A
41A
39A
36A
34A
24A
22A
35A
33A
5A
187A
170A
153A
136A
63A
46A
28A
11A
74A73A
104A
102A
103A
101A
115A
79A
108A
109A
85A
89A
86A
90A
91A 92A
95A 96A
97A
78A
80A
119A
83A 84A
107A
98A
J3200
CRITICAL
F-RT-TH
DDR3-SODIMM-DUAL
113B
204B203B
26B25B
20B19B
14B
196B195B
13B
190B189B
185B
184B
179B
178B
173B
172B
168B167B
9B
162B161B
156B155B
151B
150B
145B
144B
139B
138B
8B
134B133B
128B127B
72B71B
66B65B
61B
60B
3B
55B
54B
49B
48B
44B43B
38B37B
32B31B
2B1B
126B
199B
100B99B
94B93B
88B87B
82B81B
76B
124B123B
118B117B
112B111B
106B105B
75B
125B
200B
202B201B
197B
121B
114B
30B
110B
120B
116B
122B
77B
198B
186B
188B
169B
171B
152B
154B
135B
137B
62B
64B
45B
47B
27B
29B
10B
12B
23B
21B
18B
16B
194B
192B
182B
180B
6B
193B
191B
183B
181B
176B
174B
166B
164B
177B
175B
4B
165B
163B
160B
158B
148B
146B
159B
157B
149B
147B
17B
142B
140B
132B
130B
143B
141B
131B
129B
70B
68B
15B
58B
56B
69B
67B
59B
57B
52B
50B
42B
40B
7B
53B
51B
41B
39B
36B
34B
24B
22B
35B
33B
5B
187B
170B
153B
136B
63B
46B
28B
11B
74B73B
104B
102B
103B
101B
115B
79B
108B
109B
85B
89B
86B
90B
91B 92B
95B 96B
97B
78B
80B
119B
83B 84B
107B
98B
J3200
DDR3-SODIMM-DUAL
CRITICAL
F-RT-TH
DDR3 SO-DIMM CONNECTOR B
SYNC_MASTER=K74_MASTER SYNC_DATE=N/A
=MEM_B_DQ<25>
MEM_B_CAS_L
MEM_B_A<13>
=MEM_B_DQ<61>
=MEM_B_DQ<32>
PP0V75_S3_MEM_VREFCA_B
=MEM_B_DQ<31>
=MEM_B_DQ<13>
MEM_DIMM1_SA<0>
MEM_DIMM1_SA<1>
MEM_B_WE_L
=MEM_B_DQ<27>
MEM_B_CKE<0>
MEM_B_A<9>
MEM_B_A<12>
MEM_B_BA<2>
=MEM_B_DQ<25>
=PPSPD_S0_MEM_B
=PP0V75_S0_MEM_VTT_B
PP0V75_S3_MEM_VREFDQ_B
PP0V75_S3_MEM_VREFCA_B
=PPSPD_S0_MEM_B =PPSPD_S0_MEM_B
MEM_DIMM3_SA<1>
MEM_DIMM3_SA<0>
=PPSPD_S0_MEM_B
MEM_DIMM1_SA<1>
=PP0V75_S0_MEM_VTT_B
=MEM_B_DQ<51>
MEM_DIMM1_SA<0>
=MEM_B_DQ<59>
=MEM_B_DQ<58>
=MEM_B_DM<7>
=MEM_B_DQ<57>
=MEM_B_DQ<56>
=MEM_B_DQ<50>
=MEM_B_DQ<49>
=MEM_B_DQS_P<6>
=MEM_B_DQS_N<6>
=MEM_B_DQ<48>
=MEM_B_DQ<42>
=MEM_B_DQ<43>
=MEM_B_DM<5>
=MEM_B_DQ<40>
=MEM_B_DQ<41>
=MEM_B_DQ<35>
=MEM_B_DQS_N<4>
=MEM_B_DQS_P<4>
=MEM_B_DQ<34>
=MEM_B_DQ<33>
=MEM_B_CLK_P<0>
=MEM_B_DM<3>
=MEM_B_DQ<26>
=MEM_B_DQ<19>
=MEM_B_DQ<24>
=MEM_B_DQS_N<2>
=MEM_B_DQS_P<2>
=MEM_B_DQ<18>
=MEM_B_DQ<17>
=MEM_B_DQ<10>
=MEM_B_DQ<11>
=MEM_B_DQ<16>
=MEM_B_DQS_P<1>
=MEM_B_DQS_N<1>
=MEM_B_DQ<9>
=MEM_B_DQ<8>
=MEM_B_DQ<3>
=MEM_B_DQ<2>
=I2C_SODIMMB_SCL
=I2C_SODIMMB_SDA
=MEM_B_DQ<62>
=MEM_B_DQ<63>
MEM_EVENT_L
=MEM_B_DQS_P<7>
=MEM_B_DQS_N<7>
=PP0V75_S0_MEM_VTT_B
=MEM_B_DM<6>
=MEM_B_DQ<53>
=MEM_B_DQ<60>
=MEM_B_DQ<52>
=MEM_B_DQ<45>
=MEM_B_DQS_N<5>
=MEM_B_DQS_P<5>
=MEM_B_DQ<46>
=MEM_B_DQ<44>
=MEM_B_DQ<47>
=MEM_B_DM<4>
=MEM_B_DQ<36>
=MEM_B_DQ<37>
=MEM_B_DQ<38>
=MEM_B_DQ<39>
MEM_B_CS_L<0>
MEM_B_BA<1>
=MEM_B_CLK_N<1>
MEM_B_RAS_L
MEM_B_ODT<0>
MEM_B_ODT<1>
=MEM_B_CLK_P<1>
MEM_B_A<0>
MEM_B_A<2>
MEM_B_A<11>
MEM_B_CKE<1>
=MEM_B_DQ<30>
=MEM_B_DQS_P<3>
=MEM_B_DM<2>
=MEM_B_DQ<29>
=MEM_B_DQ<28>
=MEM_B_DQ<23>
=MEM_B_DQ<21>
=MEM_B_DM<1>
MEM_RESET_L
=MEM_B_DQ<14>
=MEM_B_DQ<15>
=MEM_B_DQ<20>
=MEM_B_DM<0>
=MEM_B_DQ<1>
=MEM_B_DQ<0>
PP0V75_S3_MEM_VREFDQ_B
=MEM_B_DQ<7>
=MEM_B_DQ<6>
=MEM_B_DQ<4>
=MEM_B_DQ<5>
=MEM_B_DQS_N<0>
=MEM_B_DQS_P<0>
=MEM_B_DQ<55>
=MEM_B_DQ<54>
MEM_B_A<3>
MEM_B_CS_L<1>
=MEM_B_DQ<27>
=MEM_B_DM<3>
=MEM_B_DQ<24>
=MEM_B_DQ<19>
=MEM_B_DQ<18>
=MEM_B_DQS_P<2>
=MEM_B_DQS_N<2>
=MEM_B_DQ<17>
=MEM_B_DQ<31>
=MEM_B_DQ<30>
=MEM_B_DQS_N<3>
=MEM_B_DQS_P<3>
=MEM_B_DQ<29>
=MEM_B_DQ<28>
=MEM_B_DQ<23>
=MEM_B_DQ<22>
=MEM_B_DM<2>
=MEM_B_DQ<21>
=MEM_B_DQS_P<0>
=MEM_B_DQS_N<0>
=MEM_B_DQ<4>
=MEM_B_DQ<5>
=MEM_B_DQ<6>
=MEM_B_DQ<7>
=MEM_B_DQ<12>
=MEM_B_DQ<20>
MEM_RESET_L
=MEM_B_DQ<13>
=MEM_B_DQ<14>
=MEM_B_DQ<15>
=MEM_B_DM<1>
MEM_B_CKE<3>
MEM_B_A<14>
MEM_B_A<15>
MEM_B_A<11>
MEM_B_A<7>
MEM_B_A<4>
MEM_B_A<6>
MEM_B_A<2>
=MEM_B_DQ<39>
=MEM_B_DQ<38>
=MEM_B_DQ<37>
PP0V75_S3_MEM_VREFCA_B
=MEM_B_DQ<36>
=MEM_B_DM<4>
=MEM_B_DQS_P<5>
=MEM_B_DQ<45>
=MEM_B_DQ<47>
=MEM_B_DQ<46>
=MEM_B_DQS_N<5>
=MEM_B_DQ<44>
=MEM_B_DQ<52>
=MEM_B_DQ<61>
=MEM_B_DQ<54>
=MEM_B_DQ<55>
=MEM_B_DQ<53>
=MEM_B_DQ<60>
=MEM_B_DM<6>
=MEM_B_DQ<62>
MEM_EVENT_L
=MEM_B_DQS_N<7>
=MEM_B_DQS_P<7>
=MEM_B_DQ<63>
=PP0V75_S0_MEM_VTT_B
=I2C_SODIMMB_SDA
=I2C_SODIMMB_SCL
=MEM_B_DQ<1>
=MEM_B_DQ<0>
PP0V75_S3_MEM_VREFDQ_B
=MEM_B_DQ<2>
=MEM_B_DM<0>
=MEM_B_DQ<8>
=MEM_B_DQ<10>
=MEM_B_DQ<16>
=MEM_B_DQ<11>
MEM_B_A<12>
MEM_B_A<5>
MEM_B_A<3>
MEM_B_A<1>
=MEM_B_CLK_P<2>
MEM_B_WE_L
MEM_B_CAS_L
MEM_B_A<13>
MEM_B_CS_L<3>
=MEM_B_DQ<33>
=MEM_B_DQ<32>
=MEM_B_DQS_N<4>
=MEM_B_DQS_P<4>
=MEM_B_DQ<34>
=MEM_B_DQ<35>
=MEM_B_DQ<40>
=MEM_B_DQ<41>
=MEM_B_DM<5>
=MEM_B_DQ<42>
=MEM_B_DQ<43>
=MEM_B_DQ<48>
=MEM_B_DQ<49>
=MEM_B_DQS_N<6>
=MEM_B_DQS_P<6>
=MEM_B_DQ<50>
=MEM_B_DQ<51>
=MEM_B_DQ<56>
=MEM_B_DQ<57>
=MEM_B_DQ<59>
=MEM_B_DQ<58>
=MEM_B_DM<7>
=PPSPD_S0_MEM_B
MEM_DIMM3_SA<1>
=PP0V75_S0_MEM_VTT_B
MEM_DIMM3_SA<0>
MEM_B_BA<0>
MEM_B_A<10>
=MEM_B_CLK_N<2>
=PP1V5_S3_MEM_B
MEM_B_A<8>
MEM_B_A<9>
MEM_B_BA<2>
MEM_B_CKE<2>
=MEM_B_DQ<26>
=MEM_B_DQS_P<1>
=MEM_B_DQS_N<1>
=MEM_B_DQ<9>
=MEM_B_DQ<3>
MEM_B_A<0>
=PP1V5_S3_MEM_B
MEM_B_ODT<3>
MEM_B_ODT<2>
MEM_B_CS_L<2>
MEM_B_RAS_L
MEM_B_BA<1>
=MEM_B_CLK_N<3>
=MEM_B_CLK_P<3>
=MEM_B_DQ<12>
=MEM_B_DQ<22>
=MEM_B_DQS_N<3>
=PP1V5_S3_MEM_B
MEM_B_BA<0>
MEM_B_A<10>
=PP1V5_S3_MEM_B
=MEM_B_CLK_N<0>
MEM_B_A<1>
MEM_B_A<5>
MEM_B_A<8>
MEM_B_A<4>
MEM_B_A<6>
MEM_B_A<7>
MEM_B_A<14>
MEM_B_A<15>
32 OF 110
A.0.0
051-8337
31 OF 92
31 32
11 31 83
11 31 83
31 32
31 32
28 31 89
31 32
31 32
31
31
11 31 83
31 32
11 83
11 31 83
11 31 83
11 31 83
31 32
5 31
5 31
28 31 89
28 31 89
5 31 5 31
31
31
5 31
31
5 31
31 32
31
31 32
31 32
31 32
31 32
31 32
31 32
31 32
31 32
31 32
31 32
31 32
31 32
31 32
31 32
31 32
31 32
31 32
31 32
31 32
31 32
32
31 32
31 32
31 32
31 32
31 32
31 32
31 32
31 32
31 32
31 32
31 32
31 32
31 32
31 32
31 32
31 32
31 32
31 49
31 49
31 32
31 32
30 31 47
31 32
31 32
5 31
31 32
31 32
31 32
31 32
31 32
31 32
31 32
31 32
31 32
31 32
31 32
31 32
31 32
31 32
31 32
11 83
11 31 83
32
11 31 83
11 83
11 83
32
11 31 83
11 31 83
11 31 83
11 83
31 32
31 32
31 32
31 32
31 32
31 32
31 32
31 32
26 30 31 91
31 32
31 32
31 32
31 32
31 32
31 32
28 31 89
31 32
31 32
31 32
31 32
31 32
31 32
31 32
31 32
11 31 83
11 83
31 32
31 32
31 32
31 32
31 32
31 32
31 32
31 32
31 32
31 32
31 32
31 32
31 32
31 32
31 32
31 32
31 32
31 32
31 32
31 32
31 32
31 32
31 32
31 32
31 32
31 32
26 30 31 91
31 32
31 32
31 32
31 32
11 83
11 31 83
11 31 83
11 31 83
11 31 83
11 31 83
11 31 83
11 31 83
31 32
31 32
31 32
28 31 89
31 32
31 32
31 32
31 32
31 32
31 32
31 32
31 32
31 32
31 32
31 32
31 32
31 32
31 32
31 32
31 32
30 31 47
31 32
31 32
31 32
5 31
31 49
31 49
31 32
31 32
28 31 89
31 32
31 32
31 32
31 32
31 32
31 32
11 31 83
11 31 83
11 31 83
11 31 83
32
11 31 83
11 31 83
11 31 83
11 83
31 32
31 32
31 32
31 32
31 32
31 32
31 32
31 32
31 32
31 32
31 32
31 32
31 32
31 32
31 32
31 32
31 32
31 32
31 32
31 32
31 32
31 32
5 31
31
5 31
31
11 31 83
11 31 83
32
5 28 29 31
11 31 83
11 31 83
11 31 83
11 83
31 32
31 32
31 32
31 32
31 32
11 31 83
5 28 29 31
11 83
11 83
11 83
11 31 83
11 31 83
32
32
31 32
31 32
31 32
5 28 29 31
11 31 83
11 31 83
5 28 29 31
32
11 31 83
11 31 83
11 31 83
11 31 83
11 31 83
11 31 83
11 31 83
11 31 83
www.vinaﬁx.vn

II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
BRANCH
REVISION
DRAWING NUMBER SIZE
D
R
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
21
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
87 54 21
CPU CHANNEL A DQS 4 -> DIMM A DQS 3
CPU CHANNEL B DQS 5 -> DIMM B DQS 2
CPU CHANNEL A DQS 2 -> DIMM A DQS 5
CPU CHANNEL A DQS 0 -> DIMM A DQS 7
CPU CHANNEL A DQS 1 -> DIMM A DQS 6
CPU CHANNEL B DQS 7 -> DIMM B DQS 0
CPU CHANNEL B DQS 4 -> DIMM B DQS 3
CPU CHANNEL B DQS 3 -> DIMM B DQS 4
CPU CHANNEL A DQS 7 -> DIMM A DQS 0
CPU CHANNEL A DQS 6 -> DIMM A DQS 1
CPU CHANNEL A DQS 3 -> DIMM A DQS 4
CPU CHANNEL B DQS 0 -> DIMM B DQS 7
CPU CHANNEL A DQS 5 -> DIMM A DQS 2
CPU CHANNEL B DQS 1 -> DIMM B DQS 6
CPU CHANNEL B DQS 2 -> DIMM B DQS 5
CPU CHANNEL B DQS 6 -> DIMM B DQS 1
MEMORY CLOCK ALIASING
SYNC_DATE=N/ASYNC_MASTER=K74_MASTER
DDR3 ALIAS AND BITSWAPS
=MEM_B_DQ<17>
MAKE_BASE=TRUE
MEM_B_DQ<41>
MEM_A_DQ<5>
MAKE_BASE=TRUE
=MEM_A_DQ<43>
MAKE_BASE=TRUE
MEM_B_DQ<45>
=MEM_A_DQ<45>
=MEM_A_DQS_P<4>
=MEM_A_DQ<39>
=MEM_A_DQ<7>
=MEM_B_DQ<52>
=MEM_A_DQ<57>
=MEM_A_DQ<51>
=MEM_A_DQ<53>
=MEM_A_DQS_N<1>
=MEM_A_CLK_N<1>
=MEM_B_CLK_P<0>
=MEM_B_CLK_N<0>
=MEM_A_CLK_N<3>
=MEM_A_CLK_N<2>
=MEM_A_CLK_N<0>
=MEM_B_DQ<25>
MEM_B_DQ<49>
MAKE_BASE=TRUE
MEM_B_DQS_N<5>
MAKE_BASE=TRUE
=MEM_B_DQ<28>
=MEM_B_DQ<37>
=MEM_B_DQ<43>
=MEM_B_DQ<46>
=MEM_B_DQ<57>
=MEM_B_DQ<63>
=MEM_B_DQ<59>
=MEM_B_DQS_P<7>
=MEM_B_DQS_N<1>
=MEM_A_DQ<2>
MAKE_BASE=TRUE
MEM_A_DQ<21>
=MEM_B_DQS_N<6>
MEM_B_DQ<5>
MAKE_BASE=TRUE
=MEM_B_DQS_P<3>
=MEM_B_DQ<41>
=MEM_B_DQS_P<6>
MAKE_BASE=TRUE
MEM_B_DQS_P<1>
MAKE_BASE=TRUE
MEM_B_DQ<6>
=MEM_B_DQ<54>
=MEM_B_DQ<51>
MAKE_BASE=TRUE
MEM_B_DQ<0>
MAKE_BASE=TRUE
MEM_A_DQ<46>
=MEM_A_DQ<8>
=MEM_A_DQS_P<0>
MEM_A_DQS_P<0>
MAKE_BASE=TRUE
=MEM_B_DQ<60>
=MEM_B_DQ<32>
=MEM_B_DQS_P<4>
=MEM_B_DQ<42>
=MEM_B_DQS_N<4>
MEM_B_DQ<16>
MAKE_BASE=TRUE
=MEM_A_DQS_N<5>
MAKE_BASE=TRUE
MEM_A_DQ<9>
=MEM_B_DQ<49>
=MEM_A_DQS_P<5>
=MEM_A_DQ<40>
=MEM_A_DQ<54>
MEM_B_DQ<13>
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MEM_B_DQ<11>
MEM_B_DQ<10>
MAKE_BASE=TRUE
=MEM_B_DM<6>
MAKE_BASE=TRUE
MEM_B_DQ<26>
MAKE_BASE=TRUE
MEM_B_DQ<25>
MEM_B_DQ<24>
MAKE_BASE=TRUE
=MEM_B_DQS_N<5>
MEM_A_DQ<63>
MAKE_BASE=TRUE
MEM_A_DQ<62>
MAKE_BASE=TRUE
MEM_A_DQ<61>
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MEM_A_DQ<59>
MEM_A_DQS_N<7>
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MEM_A_DM<1>
MAKE_BASE=TRUE
MEM_A_DQS_P<1>
MEM_B_DQ<29>
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MEM_B_DQ<31>
MEM_B_DQ<9>
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MEM_A_DQ<17>
MAKE_BASE=TRUE
MEM_A_DQ<16>
MAKE_BASE=TRUE
MEM_A_DQ<20>
MEM_A_DQ<22>
MAKE_BASE=TRUE
MEM_B_DQ<34>
MAKE_BASE=TRUE
MEM_A_DQ<32>
MAKE_BASE=TRUE
MEM_A_DQ<24>
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MEM_A_DQ<10>
MEM_A_DQ<23>
MAKE_BASE=TRUE
MEM_A_DQ<26>
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MEM_A_DM<4>
MEM_A_DQ<36>
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MEM_A_DQ<35>
MEM_A_DQ<43>
MAKE_BASE=TRUE
MEM_A_DQ<40>
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MEM_A_DM<6>
MAKE_BASE=TRUE
MEM_A_DQ<37>
MEM_A_DQ<15>
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MEM_A_DM<7>
MAKE_BASE=TRUE
MEM_A_DQS_P<7>
MAKE_BASE=TRUE
MEM_A_DQ<48>
MAKE_BASE=TRUE
MEM_A_DQ<52>
MAKE_BASE=TRUE
MEM_B_DQ<59>
MAKE_BASE=TRUE
MEM_B_DQ<57>
MAKE_BASE=TRUE
MEM_B_DQ<58>
MEM_B_DQ<36>
MAKE_BASE=TRUE
MEM_B_DQ<39>
MAKE_BASE=TRUE
MEM_B_DQ<28>
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MEM_B_DQS_P<2>
MAKE_BASE=TRUE
MEM_A_DQ<8>
MEM_B_DQ<37>
MAKE_BASE=TRUE
MEM_B_DQ<17>
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MEM_B_DQS_P<3>
MAKE_BASE=TRUE
MEM_B_DM<3>
MEM_B_DQS_N<3>
MAKE_BASE=TRUE
MEM_B_DQ<30>
MAKE_BASE=TRUE
MEM_B_DQ<27>
MAKE_BASE=TRUE
MEM_B_DQS_P<4>
MAKE_BASE=TRUE
MEM_B_DQ<38>
MAKE_BASE=TRUE
MEM_B_DQ<35>
MAKE_BASE=TRUE
MEM_B_DQ<56>
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MEM_A_DQ<34>
MAKE_BASE=TRUE
MEM_A_DQ<33>
MAKE_BASE=TRUE
MEM_A_DQS_N<6>
MAKE_BASE=TRUE
MEM_A_DQS_P<6>
MAKE_BASE=TRUE
MEM_A_DQ<55>
MAKE_BASE=TRUE
MEM_A_DQ<53>
MEM_A_DQ<60>
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MEM_A_DQ<58>
MAKE_BASE=TRUE
MEM_A_DQ<57>
MAKE_BASE=TRUE
MEM_A_DQ<56>
MEM_A_DQ<12>
MAKE_BASE=TRUE
MEM_B_DM<4>
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MEM_B_DQS_N<4>
MAKE_BASE=TRUE
MEM_A_DQ<41>
MAKE_BASE=TRUE
MEM_A_DQ<42>
MAKE_BASE=TRUE
MEM_A_DQ<54>
MAKE_BASE=TRUE
MEM_A_DQ<49>
MAKE_BASE=TRUE
MEM_A_DQ<50>
MAKE_BASE=TRUE
MEM_A_DQ<51>
MEM_A_DQ<44>
MAKE_BASE=TRUE
MEM_A_DQ<45>
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MEM_A_DQ<47>
MEM_A_DM<5>
MAKE_BASE=TRUE
MEM_A_DQS_P<5>
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MEM_A_DQS_N<5>
MAKE_BASE=TRUE
MEM_B_DQ<12>
MAKE_BASE=TRUE
MEM_B_DQ<23>
MEM_B_DM<2>
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MEM_B_DQ<33>
MAKE_BASE=TRUE
MEM_B_DQS_N<1>
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=MEM_A_DQ<0>
=MEM_A_DQ<1>
=MEM_A_DQ<4>
=MEM_A_DQ<6>
=MEM_A_DQ<5>
=MEM_A_DQS_N<0>
=MEM_A_DQ<15>
=MEM_A_DQ<9>
=MEM_A_DQ<11>
=MEM_A_DQS_P<1>
=MEM_A_DQ<10>
=MEM_A_DQ<14>
=MEM_A_DQ<50>
=MEM_A_DM<5>
=MEM_A_DQ<46>
=MEM_A_DQ<47>
MEM_B_DQ<21>
MAKE_BASE=TRUE
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=MEM_A_DM<2>
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=MEM_A_DQ<23>
=MEM_A_DQ<21>
=MEM_A_DQ<22>
=MEM_A_DQ<17>
=MEM_A_DQ<26>
=MEM_A_DQ<25>
=MEM_A_DM<3>
=MEM_A_DQS_N<3>
=MEM_A_DQ<29>
=MEM_A_DQ<28>
=MEM_A_DQ<30>
MEM_B_DQ<19>
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MEM_B_DQ<22>
=MEM_A_DM<4>
=MEM_B_DQS_N<7>
=MEM_B_DM<7>
=MEM_B_DQ<6>
=MEM_B_DQ<5>
=MEM_B_DQ<4>
=MEM_B_DQ<0>
=MEM_B_DQ<47>
=MEM_B_DQ<30>
=MEM_B_DQ<31>
=MEM_B_DM<3>
=MEM_B_DQ<33>
=MEM_B_DQ<36>
=MEM_B_DQ<35>
=MEM_B_DQ<38>
=MEM_B_DM<4>
=MEM_B_DQ<34>
MAKE_BASE=TRUE
MEM_A_DQ<39>
MEM_A_DQ<13>
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MEM_A_DQ<14>
MAKE_BASE=TRUE
MEM_A_DQ<1>
MEM_A_DQ<2>
MAKE_BASE=TRUE
MEM_A_DQ<6>
MAKE_BASE=TRUE
MEM_A_DQ<4>
MAKE_BASE=TRUE
=MEM_A_DQ<63>MEM_A_DQ<0>
MAKE_BASE=TRUE
=MEM_A_DQS_N<6>
MEM_B_DM<1>
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MEM_B_DQ<15>
MAKE_BASE=TRUE
MEM_B_DQ<14>
=MEM_B_DQ<55>MEM_B_DQ<8>
MAKE_BASE=TRUE
=MEM_A_DQS_P<7>
MAKE_BASE=TRUE
MEM_A_DQ<18>
MAKE_BASE=TRUE
MEM_A_DQS_N<2>
MAKE_BASE=TRUE
MEM_A_DM<2>
MAKE_BASE=TRUE
MEM_A_DQ<19>
MEM_A_DQS_P<3>
MAKE_BASE=TRUE
MEM_A_DQ<28>
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MEM_A_DQ<29>
MEM_A_DQ<30>
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MEM_A_DQ<31>
=MEM_A_DQS_N<4>
=MEM_A_DQ<37>
=MEM_A_DQ<33>
=MEM_A_DQ<35>
=MEM_A_DQS_P<3>
=MEM_A_DQ<34>
=MEM_A_DQ<36>
=MEM_A_DQ<32>
=MEM_A_DQ<38>
MEM_A_DQS_N<4>
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MEM_A_DQ<27>
MEM_A_DM<3>
MAKE_BASE=TRUE
=MEM_A_DQ<20>
=MEM_A_DQ<18>
=MEM_A_DQ<19>
=MEM_B_DQ<44>
MEM_B_DQ<20>
MAKE_BASE=TRUE
=MEM_A_DQ<55>
=MEM_A_DQ<48>
MEM_A_DQ<3>
MAKE_BASE=TRUE
=MEM_A_DQS_N<7>
=MEM_B_DQ<61>
=MEM_A_DQ<62>
=MEM_A_DQ<59>
MAKE_BASE=TRUE
MEM_A_DQ<7>
=MEM_B_DQ<56>
MEM_B_DQ<50>
MAKE_BASE=TRUE
=MEM_A_DM<1>
=MEM_A_DQ<13>
MEM_B_DQ<55>
MAKE_BASE=TRUE
=MEM_B_DQ<15>
MAKE_BASE=TRUE
MEM_B_DQ<62>
MAKE_BASE=TRUE
MEM_B_DM<7>
MAKE_BASE=TRUE
MEM_B_DQS_P<7>
MEM_B_DQ<48>
MAKE_BASE=TRUE
=MEM_B_DQ<26>
MAKE_BASE=TRUE
MEM_B_DQS_P<6>
MEM_B_DQ<51>
MAKE_BASE=TRUE
MEM_B_DQ<52>
MAKE_BASE=TRUE
MEM_B_DQ<53>
MAKE_BASE=TRUE
MEM_B_DQ<54>
MAKE_BASE=TRUE
MEM_B_DQS_N<6>
MAKE_BASE=TRUE
=MEM_B_DQ<10>
=MEM_B_DQS_P<0>
MAKE_BASE=TRUE
MEM_B_DQ<60>
MAKE_BASE=TRUE
MEM_B_DQ<61>
MAKE_BASE=TRUE
MEM_B_DQ<63>
MEM_B_DQS_N<7>
MAKE_BASE=TRUE
=MEM_B_DQ<9>
=MEM_B_DQ<21>
=MEM_B_DQ<11>
=MEM_B_DQ<7>
=MEM_B_DQ<3>
=MEM_B_DQ<1>
=MEM_B_DQ<2>
=MEM_B_DM<0>
=MEM_B_DQS_N<0>
=MEM_B_DQ<13>
=MEM_B_DQ<12>
=MEM_B_DQ<14>
=MEM_B_DQ<8>
=MEM_B_DM<1>
=MEM_B_DQS_P<1>
MAKE_BASE=TRUE
MEM_B_DQ<42>
=MEM_B_DQ<16>MEM_B_DQ<40>
MAKE_BASE=TRUE
MEM_B_DQ<32>
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MEM_B_DQ<43>
MAKE_BASE=TRUE
MEM_B_DQ<44>
MEM_B_DQ<46>
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MEM_B_DQ<47>
MEM_B_DM<5>
MAKE_BASE=TRUE
MEM_B_DQS_P<5>
MAKE_BASE=TRUE
=MEM_B_DQS_N<2>
=MEM_B_DQS_P<2>
=MEM_B_DM<2>
=MEM_B_DQ<18>
=MEM_B_DQ<20>
=MEM_B_DQ<23>
=MEM_B_DQ<19>
=MEM_B_DQ<22>
=MEM_A_CLK_P<1>
MAKE_BASE=TRUE
MEM_A_CLK_P<1>
MAKE_BASE=TRUE
MEM_A_CLK_N<0>
=MEM_A_CLK_P<0>MEM_A_CLK_P<0>
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MEM_A_CLK_N<1>
=MEM_A_CLK_P<2>
MAKE_BASE=TRUE
MEM_A_CLK_P<2>
=MEM_A_CLK_P<3>
MAKE_BASE=TRUE
MEM_A_CLK_P<3>
MAKE_BASE=TRUE
MEM_A_CLK_N<2>
MEM_B_CLK_P<0>
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MEM_A_CLK_N<3>
MEM_B_CLK_N<0>
MAKE_BASE=TRUE
=MEM_B_CLK_P<1>
MAKE_BASE=TRUE
MEM_B_CLK_P<1>
=MEM_B_CLK_N<2>
MAKE_BASE=TRUE
MEM_B_CLK_N<2>
=MEM_B_CLK_P<2>
MAKE_BASE=TRUE
MEM_B_CLK_P<2>
=MEM_B_CLK_N<1>
MAKE_BASE=TRUE
MEM_B_CLK_N<1>
=MEM_B_CLK_P<3>
MAKE_BASE=TRUE
MEM_B_CLK_P<3>
=MEM_B_CLK_N<3>
MAKE_BASE=TRUE
MEM_B_CLK_N<3>
MEM_B_DQS_N<0>
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MEM_B_DM<6>
=MEM_B_DQ<53>
=MEM_B_DQS_P<5>
=MEM_B_DM<5>
=MEM_B_DQ<45>
=MEM_B_DQ<40>
MAKE_BASE=TRUE
MEM_A_DQ<11>
MAKE_BASE=TRUE
MEM_A_DQS_N<3>
=MEM_A_DQ<52>
=MEM_A_DQ<58>
MAKE_BASE=TRUE
MEM_B_DQ<18>
=MEM_A_DQ<49>
=MEM_A_DM<6>
=MEM_A_DQS_P<6>
MEM_A_DQS_N<1>
MAKE_BASE=TRUE
=MEM_A_DQ<61>
=MEM_A_DQ<3>
=MEM_A_DQ<12>
=MEM_B_DQ<27>
=MEM_B_DQ<29>
=MEM_B_DQ<24>
=MEM_B_DQS_N<3>
=MEM_B_DQ<58>
MAKE_BASE=TRUE
MEM_B_DQ<3>
MAKE_BASE=TRUE
MEM_B_DQ<4>
=MEM_B_DQ<62>
=MEM_B_DQ<39>
=MEM_B_DQ<50>
=MEM_B_DQ<48>
=MEM_A_DQ<60>
=MEM_A_DM<7>MEM_A_DM<0>
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MEM_A_DQS_N<0>
=MEM_A_DQ<56>
MAKE_BASE=TRUE
MEM_B_DQ<1>
MAKE_BASE=TRUE
MEM_B_DQ<2>
MAKE_BASE=TRUE
MEM_B_DQ<7>
MEM_B_DM<0>
MAKE_BASE=TRUE
MEM_B_DQS_P<0>
MAKE_BASE=TRUE
MEM_B_DQS_N<2>
MAKE_BASE=TRUE
=MEM_A_DQ<41>
=MEM_A_DQ<44>
=MEM_A_DQ<42>
MAKE_BASE=TRUE
MEM_A_DQS_P<2>
=MEM_A_DQ<24>
=MEM_A_DQ<31>
=MEM_A_DQ<27>
MAKE_BASE=TRUE
MEM_A_DQ<38>
MAKE_BASE=TRUE
MEM_A_DQS_P<4>
MEM_A_DQ<25>
MAKE_BASE=TRUE
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IN
IN
IN
OUT
OUT
OUT
IN
IN
KEY
OUT
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
BRANCH
REVISION
DRAWING NUMBER SIZE
D
R
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
21
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
87 54 21
NOTE: CURRENT DATA PER JAN 12,2008 PCIE MINI CEM ECN
TARGET CARDS DO NOT USE IT
NC
NC
RESERVED
NC
NC
| MAX PEAK N/U N/U |
| MAX CONT. 1100MA 190MA |
| MAX CONT. N/U N/U |
| |
-----------------------------------------
| 3.3V S3 CURRENT D0-D2,D3HOT D3COLD |
| MAX PEAK 2750MA 2750MA |
-----------------------------------------
| 1.5V CURRENT |
NC
NC
NC
516S0457
NC
NC
NC
NC
NC
NC
NO AVAILALBLE USB ON THIS PLATFORM
NCNC
RESERVED
2
1C3401
6.3V
10uF
603
X5R
20%
2
1C3410
10V
20%
0.1uF
402
CERM
2
1C3420
402
20%
CERM
10V
0.1uF
2
1C3421
X5R
603
6.3V
20%
10uF
21
C3431
PLACEMENT_NOTE=PLACE CLOSE TO U1800.
402
16V
10%
X5R
0.1uF
21
C3430
PLACEMENT_NOTE=PLACE CLOSE TO U1800.
402
16V
10%
0.1uF
X5R
21
R3400
5%
0
1/16W
402
MF-LF
NO STUFF
21
R3401
402
1/16W
NO STUFF
0
MF-LF
5%
17 84
17 84
27 91
17 84
17 84
18 36
2
1C3400
0.1uF
20%
CERM
402
10V
17 84
17 84
9
87
6
5251
50
5
49
4847
4645
4443
4241
40
4
39
3837
3635
3433
3231
30
3
29
2827
2625
2423
2221
20
2
19
1817
1615
1413
1211
10
1
54
53
J3400
F-RT-SM
AS0B226-S40N-7F
CRITICAL
14 17
21
R34900
21
R34910
SYNC_DATE=N/A
PCI-E MiniCard Connector
SYNC_MASTER=K74_MASTER
MINI_CLKREQ_L
PCIE_MINI_R2D_N
PCIE_MINI_R2D_P
TP_USB_MINIP
PCIE_MINI_R2D_C_P
PCIE_MINI_R2D_C_N
PCIE_CLK100M_MINI_N
PCIE_MINI_D2R_P
PCIE_MINI_D2R_N
TP_USB_MININ
RSVD_MINI_BT_ACTIVE
RSVD_MINI_WLAN_ACTIVE
PCIE_WAKE_L
SMB_MINI_SDA =SMB_MINI_SDA
=SMB_MINI_SCL
SMB_MINI_SCL
PCIE_CLK100M_MINI_P
MINI_RESET_L
=PP3V3_S3_MINI
=PP1V5_S0_MINI
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IN
G
D
SG
D
S
SCL
THRM_PAD
E0
E1
E2
VSS
SDA
VCC
WC*
TEST
RESET*
USBDM_DN1/PRT_DIS_M1
USBDP_DN1/PRT_DIS_P1
USBDP_DN2/PRT_DIS_P2
USBDM_DN2/PRT_DIS_M2
USBDM_DN3/PRT_DIS_M3
USBDP_DN3/PRT_DIS_P3
USBDM_DN4/PRT_DIS_M4
USBDP_DN4/PRT_DIS_P4
PRTPWR2/BC_EN2*
PRTPWR1/BC_EN1*
PRTPWR4/BC_EN4*
PRTPWR3/BC_EN3*
OCS2*
OCS1*
OSC3*
OSC4*
RBIAS
USBDP_UP
USBDM_UP
VBUS_DET
THRM_PAD
XTALIN/CLKIN
XTALOUT
SUSP_IND/LOCAL_PWR/NON_REM0
SDA/SMBDATA/NON_REM1
SCL/SMBCLK/CFG_SEL0
HS_IND/CFG_SEL1
CRFILT
PLLFILT
VDD33
CRITICAL BOM OPTION
TABLE_5_HEAD
PART# DESCRIPTIONQTY REFERENCE DESIGNATOR(S)
TABLE_5_ITEM
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
BRANCH
REVISION
DRAWING NUMBER SIZE
D
R
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
21
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
87 54 21
TABLE_5_ITEM
DEFAULT K23F ==>
SEL1 SEL0 DESCRIPTION
DEFAULT K23F ==>
0 0 Internal Default with Self powered Operation
1 1 EEPROM Supported
0 1 SMBUS Slave Config
0 0 All ports are Non removable
0 1 Port1 is non removable
1 0 Port 1 and 2 are non removable
1 1 Port1,2 and 3 are non Removable
USB HUB-1
1 0 Internal Default with Bus powered Operation
NON_REM1 NON_REM0 DESCRIPTION
BOM TABLE
21
Y3500
CRITICAL
5X3.2X1.4-SM
24.000M-60PPM-16PF
2
1
C3520
50V
5%
CERM
402
18PF
21
R3591
5%
1/16W
1M
MF-LF
402
2
1
C3519
18PF
402
5%
CERM
50V
2
1
C3534
402
0.1UF
X5R
16V
10%
2
1
R3599
402
100K
5%
1/16W
MF-LF
NOSTUFF
2
1C3537
402
50V
5%
CERM
100PF
2
1C3543
402
CERM
50V
100PF
5%
2
1
R3597
NOSTUFF
10K
5%
1/16W
MF-LF
402
2
1C3539
16V
402
0.1UF
10%
X7R-CERM
2
1C3545
10%
402
16V
X7R-CERM
0.1UF
2
1C3546
16V
402
X7R-CERM
10%
0.1UF
2
1C3547
0.1UF
10%
16V
X7R-CERM
402
2
1C3525
0.1UF
402
X7R-CERM
10%
16V
2
1C3523
X7R-CERM
0.1UF
16V
402
10%
2
1C3524
X7R-CERM
0.1UF
16V
10%
402
2
1C3528
16V
X7R-CERM
10%
402
0.1UF
2
1C3536
0.01UF
10%
16V
CERM
402
2
1C3542
10%
16V
CERM
402
0.01UF
2
1C3529
0.01UF
10%
402
16V
CERM
2
1C3526
10%
CERM
16V
0.01UF
402
19 85
19 85
34 35
21
R3500
12K
MF
1%
402
1/16W
2
1
R3541
MF-LF
5%
1/16W
402
10K
4
5
3
Q3540
SOT-363
2N7002DW-X-G
2
1
R3540
20K
1/16W
5%
402
MF-LF
1
2
6
Q3540
SOT-363
2N7002DW-X-G
2
1C3541
CERM
100PF
5%
402
50V
NOSTUFF
2
1C3540
CERM-X5R
0.47UF
NOSTUFF
10%
402
6.3V
2
1C3518
20%
603
6.3V
10UF
X5R
21
L3559
0402
FERR-120-OHM-1.5A
2
1
R3598
MF-LF
1/16W
10K
5%
402
2
1
R3592
10K
5%
1/16W
402
MF-LF
2
1
R3594
5%
1/16W
402
MF-LF
10K
NOSTUFF
2
1
R3504
MF-LF
1/16W
10K
5%
402 2
1
R3550
MF-LF
1/16W
5%
10K
402
2
1
R3580
10K
5%
1/16W
MF-LF
402 2
1
R3581
1/16W
5%
10K
MF-LF
402
2
1
R3565
5%
MF-LF
402
1/16W
10K
2
1
R3566
MF-LF
5%
10K
402
1/16W
NOSTUFF
2
1
R3567
1/16W
5%
MF-LF
10K
402
21
R3545
0
402
5%
1/16W
MF-LF
2
1
R3501
5%
402
MF-LF
1/16W
10K
7
4
8
9
5
6
3
2
1
U3514
MLP8
NOSTUFF
CRITICAL
M24C02
2
1C3530
1UF
402
X5R
16V
10%
2
1C3527
402
X5R
1UF
16V
10%
2
1C3538
20%
603
6.3V
X5R
10UF
2
1C3544
603
6.3V
20%
10UF
X5R
21
L3558
0402
FERR-120-OHM-1.5A
32
33
36292315105
27
31
9
7
4
2
30
8
6
3
1
37
11
28
22
24
26
35
20
18
16
12
34
21
19
17
13
25
14
U3500
OMIT
QFN
USB2514-AEZG
SMSC USB2514B338S0824 HUB_USB2514BU3500,U36002
CRITICAL
SYNC_DATE=N/A
USB HUB 1
SYNC_MASTER=K74_MASTER
2 HUB_USX2061338S0721
CRITICAL
U3500,U3600SMSC USX2061-AEZG
USB_HUB1_LOCAL_PWR
USB_HUB1_SMBDATA
MIN_NECK_WIDTH=0.25MM
MIN_LINE_WIDTH=0.5MM
USB_HUB1_VDD1V8
USB_HUB1_RBIAS
USB_EXTC_OC_L
=PP3V3_S3_USB_HUB
USB_HUB1_XTAL1
USB_HUB1_XTAL2
=PP3V3_S3_USB_HUB
USB_HUB1_CFG_SEL1
TP_USB_HUB1_PRTPWR4
MIN_LINE_WIDTH=0.5MM
USB_HUB1_VBUS_DET
MIN_NECK_WIDTH=0.25MM
MIN_NECK_WIDTH=0.25MM
MIN_LINE_WIDTH=0.5MM
USB_HUB1_VDD1V8PLL
MIN_LINE_WIDTH=0.5MM
MIN_NECK_WIDTH=0.25MM
USB_HUB1_VDDPLL3V3
=PP3V3_S3_USB_HUB
USB_HUB_SOFT_RESET_L
PGOOD_P3V3_S3
USB_HUB_RESET
=PP3V3_S3_USB_RESET
USB_HUB_RESET_L
=PP3V3_S3_USB_HUB
USB_HUB_RESET_L
USB_CAMERA_N
TP_USB_HUB1_PRTPWR1
USB_EXTC_P
USB_CAMERA_P
USB_IR_N
USB_EXTA_OC_L
USB_IR_P
USB_EXTA_N
USB_EXTA_P
USB_EXTC_N
TP_USB_HUB1_PRTPWR2
TP_USB_HUB1_PRTPWR3
TP_USB_HUB1_OCS1_L
TP_USB_HUB1_OCS2_L
USB_HUB1_UP_N
USB_HUB1_UP_P
USB_HUB1_TEST
=PP3V3_S3_USB_HUB
MIN_LINE_WIDTH=0.5MM
MIN_NECK_WIDTH=0.25MM USB_HUB1_VDDA3V3
WP_HUB1
USB_HUB1_SMBCLK
35 OF 110
A.0.0
051-8337
34 OF 92
85
43
5 34 35
85
85
5 34 35
5 34 35
19
73 91
5
34 35
5 34 35
44 85
43 85
44 85
44 85
43
44 85
43 85
43 85
43 85
5 34 35
www.vinaﬁx.vn

IN
IN
IN
SCL
THRM_PAD
E0
E1
E2
VSS
SDA
VCC
WC*
TEST
RESET*
USBDM_DN1/PRT_DIS_M1
USBDP_DN1/PRT_DIS_P1
USBDP_DN2/PRT_DIS_P2
USBDM_DN2/PRT_DIS_M2
USBDM_DN3/PRT_DIS_M3
USBDP_DN3/PRT_DIS_P3
USBDM_DN4/PRT_DIS_M4
USBDP_DN4/PRT_DIS_P4
PRTPWR2/BC_EN2*
PRTPWR1/BC_EN1*
PRTPWR4/BC_EN4*
PRTPWR3/BC_EN3*
OCS2*
OCS1*
OSC3*
OSC4*
RBIAS
USBDP_UP
USBDM_UP
VBUS_DET
THRM_PAD
XTALIN/CLKIN
XTALOUT
SUSP_IND/LOCAL_PWR/NON_REM0
SDA/SMBDATA/NON_REM1
SCL/SMBCLK/CFG_SEL0
HS_IND/CFG_SEL1
CRFILT
PLLFILT
VDD33
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
BRANCH
REVISION
DRAWING NUMBER SIZE
D
R
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
21
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
87 54 21
USB HUB-2
21
1
Y3600
5X3.2X1.4-SM
CRITICAL
24.000M-60PPM-16PF
2
1C3620
CERM
50V
5%
402
18PF
21
R3691
MF-LF
5%
1/16W
402
1M
2
1C3619
CERM
50V
18PF
5%
402
2
1C3637
100PF
402
CERM
5%
50V
2
1C3643
50V
5%
100PF
402
CERM
2
1C3639
X7R-CERM
16V
402
10%
0.1UF
2
1C3645
X7R-CERM
16V
10%
0.1UF
402
2
1C3646
402
0.1UF
10%
X7R-CERM
16V
2
1C3647
402
16V
10%
0.1UF
X7R-CERM
2
1C3625
10%
402
0.1UF
X7R-CERM
16V
2
1C3623
16V
10%
0.1UF
402
X7R-CERM
2
1C3624
402
10%
16V
0.1UF
X7R-CERM
2
1C3628
0.1UF
X7R-CERM
10%
402
16V
2
1C3636
CERM
16V
10%
402
0.01UF
2
1C3642
0.01UF
402
CERM
16V
10% 2
1C3629
16V
CERM
402
0.01UF
10%
2
1C3626
10%
16V
CERM
402
0.01UF
19 85
19 85
34
2
1C3618
20%
603
X5R
10UF
6.3V
2
1
R3697
NOSTUFF
MF-LF
402
10K
5%
1/16W
2
1
R3698
1/16W
10K
5%
402
MF-LF
2
1
R3699
5%
402
1/16W
MF-LF
100K
NOSTUFF
21
L3629
0402
FERR-120-OHM-1.5A
2
1
R3692
402
MF-LF
5%
10K
1/16W
2
1
R3694
10K
402
MF-LF
1/16W
5%
NOSTUFF
2
1
R3682
MF-LF
10K
1/16W
402
5%
2
1
R3680
10K
MF-LF
5%
1/16W
402 2
1
R3681
402
1/16W
5%
MF-LF
10K
2
1
R3666
10K
402
5%
MF-LF
1/16W
2
1
R3665
402
10K
MF-LF
1/16W
5%
NOSTUFF
2
1
R3667
1/16W
MF-LF
402
5%
10K
2
1
R3601
MF-LF
402
10K
5%
1/16W
2
1
R3604
1/16W
MF-LF
5%
10K
402
2
1C3634
X5R
402
16V
10%
0.1UF
7
4
8
9
5
6
3
2
1
U3614
M24C02
CRITICAL
NOSTUFF
MLP8
2
1C3630
402
X5R
16V
10%
1UF
2
1C3627
10%
402
16V
X5R
1UF
2
1C3638
603
6.3V
10UF
X5R
20%
2
1C3644
20%
603
X5R
6.3V
10UF
21
L3658
0402
FERR-120-OHM-1.5A
21
R3600
1%
12K
MF
402
1/16W
32
33
36292315105
27
31
9
7
4
2
30
8
6
3
1
37
11
28
22
24
26
35
20
18
16
12
34
21
19
17
13
25
14
U3600
USB2514-AEZG
QFN
OMIT
SYNC_DATE=N/A
USB HUB 2
SYNC_MASTER=K74_MASTER
USB_HUB2_XTAL2
=PP3V3_S3_USB_HUB
USB_HUB2_RBIAS
USB_SDCARD_N
USB_BT_N
USB_BT_P
USB_EXTD_N
USB_HUB2_UP_N
USB_SDCARD_P
USB_EXTB_N
TP_USB_HUB2_PRTPWR2
TP_USB_HUB2_PRTPWR1
USB_EXTB_P
TP_USB_HUB2_OCS1
TP_USB_HUB2_PRTPWR4
TP_USB_HUB2_PRTPWR3
USB_EXTD_P
USB_HUB2_UP_P
=PP3V3_S3_USB_HUB
USB_HUB2_VBUS_DET
USB_HUB2_XTAL1
TP_USB_HUB2_OCS2
USB_EXTB_OC_L
USB_EXTD_OC_L
MIN_LINE_WIDTH=0.5MM
USB_HUB2_VDD1V8PLL
MIN_NECK_WIDTH=0.25MM
USB_HUB2_CFG_SEL1
USB_HUB_RESET_L
USB_HUB2_TEST
=PP3V3_S3_USB_HUB
=PP3V3_S3_USB_HUB USB_HUB2_VDDPLL3V3
MIN_NECK_WIDTH=0.25MM
MIN_LINE_WIDTH=0.5MM
MIN_LINE_WIDTH=0.5MM
MIN_NECK_WIDTH=0.25MM USB_HUB2_VDDA3V3
=PP3V3_S3_USB_HUB
WP_HUB2
USB_HUB2_SMBDATA
USB_HUB2_VDD1V8
MIN_NECK_WIDTH=0.25MM
MIN_LINE_WIDTH=0.5MM
USB_HUB2_SMBCLK
USB_HUB2_LOCAL_PWR
36 OF 110
A.0.0
051-8337
35 OF 92
85
5 34 35
85
44 85
44 85
44 85
43 85
44 85
43 85
43 85
43 85
5 34 35
85
43
43
5 34 35
5 34 35
5 34 35
www.vinaﬁx.vn

D
G
S
D
G
S
G
D
S
G
D
S
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
BRANCH
REVISION
DRAWING NUMBER SIZE
D
R
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
21
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
87 54 21
ENET_PWR_ON = "S0" || (S3 power && WOL_EN)
3.3V ENET FET
CAESAR II/IV 25MHZ XTAL
PLACE THESE CLOSE TO L3800 AND AS CLOSE TO ENET CONTROLLER AS POSSIBLE
197S0286
CAESAR II/IV WAKE# ISOLATION
CAESAR II/IV ACTIVITY LED
SILKSCREEN:ENET ACT
NO INTERNAL PULL UP/DOWN. MUST PULL DOWN TO USE INTERNAL SWITCHER
MAX CURRENT = 396MA
WE WANT THESE FOR EITHER CAESAR CHIP
XTAL CHANGED FROM 197S0167 DUE TO HEIGHT RESTRICTIONS
WE WANT THESE FOR EITHER CAESAR CHIP
CAESAR II/IV 1V2 RAIL SUPPLY
PLACE AS CLOSE TO ENET CONTROLLER AS POSSIBLE
2
1C3826
0.1UF
16V
402
X5R
10%
3
42
1
Q3810
CRITICAL
BCM5764M
SOT223
PBSS5540ZDG
2
1C3825
6.3V
X5R
603-2
20%
10UF
2
1C3818
402
10%
X5R
16V
0.1UF
2
1C3817
603
4.7UF
20%
6.3V
CERM
21
R3802
BCM5764M
1.5
MF-LF
5%
1/4W
1206
K
A
LED3801
DEVELOPMENT
GREEN-3.6MCD
2.0X1.25MM-SM
2
1
R3805
330
DEVELOPMENT
5%
1/16W
MF-LF
402
21
Y3850
8X4.5MM-SM-HF
25.0000M
2
1C3850
27PF
CERM
50V
402
5%
2
1C3851
CERM
50V
27PF
5%
402
21
R3850
1/16W
200
5%
MF-LF
402
2
1
3
Q3870
SSM3K15FV
SOD-VESM-HF
2
1
R3870
MF-LF
402
1/16W
10K
5%
21
R3810
0
5%
BCM57765
402
MF-LF
1/16W
21
R3811
0
1/16W
5%
BCM57765
402
MF-LF
21
R3812
0
MF-LF
5%
1/16W
BCM5764M
402
21
R3813
BCM57765
1/16W
MF-LF
5%
402
0
21
L3800
PCAA031B-SM
BCM57765
4.7UH-0.8A
2
1
R3830
10K
1/16W
5%
MF-LF
402
BCM57765
21
C3881
10%
16V
0.01UF
CERM
402
2
1
3
Q3880
NTR4101P
SOT-23-HF
CRITICAL
2
1C3880
16V
0.1UF
402
X5R
10%
21
R3881
MF-LF
1/16W
402
5%
100K
2
1
R3880
MF-LF
5%
1/16W
402
10K
1
2
6
Q3881
BCM5764M
SOT-363
2N7002DW-X-G4
5
3Q3881
BCM5764M
SOT-363
2N7002DW-X-G
Caesar II/IV Support
SYNC_MASTER=MASTER SYNC_DATE=N/A
PP_ENET_CTRL12
MIN_NECK_WIDTH=0.2MM
VOLTAGE=3.3V
MIN_LINE_WIDTH=0.6MM
MAKE_BASE=TRUE
MIN_LINE_WIDTH=0.6MM
VOLTAGE=1.2V
MIN_NECK_WIDTH=0.2MM
PP1V2_ENET_PHY
=PP1V2_ENET_PHY
MAKE_BASE=TRUE
MIN_NECK_WIDTH=0.2MM
VOLTAGE=1.2V
MIN_LINE_WIDTH=0.25MM
BCM57765_SR_VFB
VOLTAGE=3.3V
MIN_NECK_WIDTH=0.2MM
MIN_LINE_WIDTH=0.25MM
MAKE_BASE=TRUE
BCM57765_SR_VDD
MAKE_BASE=TRUE
VOLTAGE=1.2V
MIN_LINE_WIDTH=0.4MM
BCM57765_SR_LX
MIN_NECK_WIDTH=0.2MM
=PP3V3_ENET_PHY
MAKE_BASE=TRUE
VOLTAGE=3.3V
MIN_LINE_WIDTH=0.25MM
MIN_NECK_WIDTH=0.2MM
TP_BCM57765_SR_VDDP
ENET_CTRL12
TP_BCM5764_TRAFFICLED_L ENET_LED_ACT_L
MAKE_BASE=TRUE
ENET_ACT
=PP3V3_ENET_PHY
PCIE_WAKE_L
MAKE_BASE=TRUE
ENET_WAKE_L =ENET_WAKE_L
=PP3V3_ENET_PHY
BCM5764_CLK25M_XTALO
BCM5764_CLK25M_XTAL
BCM5764_CLK25M_XTALI
PP3V3_ENET_FET
ENET_PWR_L
=PP3V3_S3_ENETFET
WOL_EN_L
PM_SLP_S3_L
WOL_EN
BCM57765_SR_DISABLE
38 OF 110
A.0.0
051-8337
36 OF 92
89
37
37
37
37
5 36 37 45
37
37
5 36 37 45
18 33 37
5 36 37 45
37 86
86
37 86
5
5
5 18 26 46 47 63 64 81 91
14 20
37
www.vinaﬁx.vn

IN
IN
IN
OUT
OUT
IN
IN
OUT
OUT
OUT
IN
IN
BI
BI
BI
BI
BI
BI
BI
BI
NC
BI
BI
BI
BI
BI
BI
BI
BI
OUT
IN
IN
IN
AVDDH
BIASVDDH
VDDC
VDDIO
XTALVDDH
VDDIO
VDDC
AVDDL
SI
SO
CS*
RDAC
VDDC
UART_MODE
SCLK
LOW_PWR
LINKLED*
CLKREQ*
PERST*
PCIE_REFCLK_N
PCIE_REFCLK_P
PCIE_TXD_P
PCIE_RXD_P
VDDCVDDC
VDDIO
PCIE_PLLVDDL
GPHY_PLLVDDL
DC2
DC1
NC
VMAIN_PRSNT
VAUX_PRSNT
ENERGY_DET
DC3
DC4
NC
GPIO_2
TRD1_N
TRD1_P
TRD0_N
SMB_DATA TRD0_P
TRD2_N
TRD2_P
TRD3_P
THRM_PAD
XTALI
XTALO
SPD100LED*
TRAFFICLED*
TRD3_N
DC5
PCIE_TXD_N
SPD1000LED*
DC0
WAKE*
PCIE_VDDL
REGCTL12
VDDIO
PCIE_RXD_N
GPIO_0/SERIAL_DO
GPIO_1/SERIAL_DI
SMB_CLK
VDDC
VERSION 2
OUT
RESET*
CS*
SCK
SO
WP*
SI
GND
VCC
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
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REVISION
DRAWING NUMBER SIZE
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C
A
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21
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
87 54 21
86mA (1000base-T, Caesar II)
Required for proper PHY operation.
ROM contains MAC address, PCIe config
PHY Non-Volatile Memory
info as well as code for Bonjour proxy.
All parts below BOMOPTIONed BCM5764M
NOTE: "IPx" == Programmable pull-up/down
(IPx-BCM57765)
(IPx-BCM57765)
(IPU-BCM57765)
(IPU-BCM57765)
(IPU-BCM57765)
(IPD?-BCM57765)
(IPU-BCM57765)
(IPU)
(IPD)
(IPD-BCM5764M)
(IPD)
(OD)
(OD)
(IPD)
(IPD-BCM57765)
Connect only to U3900 pins 9 and 20.
just decoupling for BCM57765 CR I/Os.
GPIO1_LR_OUT is not for SD Card power,
=ENET_WAKE_L to PCIE_WAKE_L.
If PHY is always powered then alias
N-channel FET isolation suggested.
is powered-down in S3/S5. Standard
Must isolate from PCIe WAKE# if PHY
(Required ROM size TBD)
Atmel AT45DB011D (1Mbit) ROM. If a different
NOTE: Pull-down on SO plus internal pull-ups on
provided on this page).
to 3.3V ENET via 1K resistor (not
TP_). If not used, must be pulled
used, this pin can float (alias to
53-VMAIN_PRSNT
BCM5764M Support
BCM57765 supports both active-levels for WP.
All resistors above BOMOPTIONed BCM57765
If BCM57765 switching regulator is
BCM57765_SR_DISABLE
BCM5764M pin-function
WAKE#
(See note)
(See note)
60-ENERGY_DET
13-WAKE*
14-VDDC
06-VDDC
17-VDDC
55-VDDC
(See note)
with no stubs.
Keep net short,
26-PCIE_VDDL
20-XTALVDDH
59-SMB_CLK
16-VDDIO
54-VAUX_PRSNT
58-SMB_DATA
396mA (1000base-T, Caesar II)
BCM57765 SR pins are internal 1.2V switching regulator. See note for SR_DISABLE below.
If disabled: Okay to float VDD, VDDP & LX pin. VFB must always connect to =PP1V2_ENET_PHY.
If enabled: VDD/VDDP connect to =PP3V3_ENET_PHY (add bypassing), LX connects to inductor.
NOTE: BCM5764M requires SI pull-down instead of SO.
ROM is used then the straps must change.
other 3 SPI pins configures BCM57765 for the
2
1
C3921
0.1UF
X7R-CERM
402
16V
10%
2
1
C3935
6.3V
10UF
805
10%
X5R
2
1
C3925
4.7UF
X5R-CERM
603
10%
6.3V
21
L3925
FERR-600-OHM-0.5A
SM
CRITICAL
2
1
C3920
603
6.3V
10%
X5R-CERM
4.7UF
21
L3920
FERR-600-OHM-0.5A
SM
CRITICAL
21
L3900
CRITICAL
SM
FERR-600-OHM-0.5A
21
L3905
SM
CRITICAL
FERR-600-OHM-0.5A
2
1
R3942
BCM57765
402
MF-LF
5%
1K
1/16W
17 84
17 84
27 91
14 17
36 37
14 20
36 86
36 86
21
C3951
0.1uF
402
X5R
16V
10%
21
C3950
402
0.1uF
X5R
16V
10%
21
C3956
16V
10%
0.1uF
X5R
402
21
C3955
0.1uF
402
X5R
16V
10%
2
1
R3965
1%
1.24K
402
1/16W
MF-LF
17 86
17 86
17 86
17 86
38 86
38 86
38 86
38 86
38 86
38 86
38 86
38 86
2
1
R3941
MF-LF
1/16W
5%
4.7K
402
BCM57765
2
1
R3940
MF-LF
5%
402
1/16W
4.7K
BCM57765
21R3980
BCM5764M
402MF-LF1/16W5%
0
21R3984
402MF-LF1/16W5%
4.7K
BCM5764M
21R3999 0
5% 1/16W MF-LF 402
BCM5764M
21R3978 0
BCM57765
4025% 1/16W MF-LF
45 86
21R3983
402MF-LF1/16W5%
4.7K
BCM5764M
21R3982 1K
5% 1/16W MF-LF 402
BCM5764M
21
L3999
SM
CRITICAL
BCM5764M
PLACE_NEAR=U3900.26:2 mm
FERR-600-OHM-0.5A
2
1
C3998
BCM5764M
6.3V
4.7UF
X5R-CERM
603
10%
PLACE_NEAR=L3999.1:1 mm
2
1
C3999
0.1UF
X7R-CERM
402
10%
16V
BCM5764M
PLACE_NEAR=U3900.26:1 mm
21R3977
5%
BCM57765
0
1/16W MF-LF 402
21R3976
5%
BCM57765
MF-LF1/16W
0
402
21R3975
5%
BCM57765
402MF-LF1/16W
0
45 86
45 86
45 86
45 86
45 86
45 86
45 86
45 86
21R3974
PLACE_NEAR=L3999.1:1 mm
0
BCM57765
5% 1/16W MF-LF 402
21R3973 0
5% 1/16W MF-LF 402
BCM57765
45
21
R3943
5%
MF-LF
1/16W
402
BCM57765
0
21R3981
402MF-LF1/16W5%
0
BCM5764M
21R3986
MF-LF 4021/16W5%
0
BCM5764M
21R3985
5% 1/16W MF-LF 402
1K
BCM5764M
21R3989
402MF-LF1/16W5%
0
BCM5764M
21R3987
402MF-LF1/16W5%
0
BCM5764M
21R3988
402MF-LF1/16W5%
0
BCM5764M
21
R3900
BCM57765
0
402
1/16W
MF-LF
5%
21
R3915
BCM57765
0
402
1/16W
MF-LF
5%
2
1
R3990
MF-LF
1/16W
5%
402
4.7K
NOSTUFF
21R3998
402MF-LF1/16W5%
0
BCM5764M
45 86
45
20
19
18
13
53
6256 167 61
55
3517 14
6
54
10
50
49
46
47
44
43
40
41
67
69
2
68
65
58
59
64
66
15
38
11
26
28
27
33
34
31
30
3229
52
1
4
3
9
8
5
36
60
57
25
24
23
22
21
63
12
37 5145394842
U3900
CRITICAL
OMIT
BCM5764M
QFN-8X8
2
1
C3970
4.7UF
603
X5R-CERM
6.3V
10%
BCM57765
2
1
C3971
0.1UF
X7R-CERM
BCM57765
402
10%
16V
2
1
C3972
BCM57765
X7R-CERM
402
10%
16V
0.1UF
21R3972
402MF-LF1/16W5%
0
BCM57765
14 17 37
2
1
R3910
MF-LF
1/16W
402
4.7K
5%
21
R3920
402
5%
MF-LF
1/16W
0
BCM57765
21
L3910
SM
CRITICAL
FERR-600-OHM-0.5A
2
1
C3910
16V
10%
402
X7R-CERM
0.1UF
2
1
C3911
X7R-CERM
16V
10%
402
0.1UF
2
1
C3990
X7R-CERM
16V
402
0.1UF
10%
2
1
C3900
X7R-CERM
0.1UF
402
10%
16V
2
1
C3905
X7R-CERM
0.1UF
402
10%
16V
2
1
C3930
10%
6.3V
X5R-CERM
603
4.7UF
2
1
C3931
0.1UF
16V
10%
402
X7R-CERM
21
L3930
FERR-600-OHM-0.5A
SM
CRITICAL
2
1
C3915
X5R-CERM
603
6.3V
10%
4.7UF
2
1
C3916
402
10%
X7R-CERM
0.1UF
16V
5
6
8
12
3
7
4
U3990
SOIC-8S1
AT45DB011D
OMIT
2
1
R3997
4.7K
MF-LF
402
5%
1/16W
2
1
C3936
0.1UF
10%
402
16V
X7R-CERM
2
1
C3926
16V
10%
X7R-CERM
0.1UF
402
SYNC_DATE=11/30/2009
Ethernet PHY (Caesar II/IV)
SYNC_MASTER=T27BCM57765_SR_VDD
BCM57765_SMB_CLK
BCM57765_CR_CMD
=PP1V2_ENET_PHY
BCM57765_SR_VFB
VOLTAGE=1.2V
MIN_LINE_WIDTH=0.4 mm
MIN_NECK_WIDTH=0.2 mm
PP1V2_ENET_PHY_AVDDL
MIN_LINE_WIDTH=0.4 mm
PP1V2_ENET_PHY_PCIEPLL
VOLTAGE=1.2V
MIN_NECK_WIDTH=0.2 mm
PP1V2_ENET_PHY_GPHYPLL
MIN_LINE_WIDTH=0.4 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=1.2V
=PP1V2_ENET_PHY
PCIE_ENET_D2R_N
PCIE_ENET_D2R_P
PCIE_ENET_R2D_C_N
PCIE_ENET_R2D_C_P
=ENET_WAKE_L
BCM5764_SCLK
BCM5764_CS_L
=PP3V3_ENET_PHY
BCM57765_SR_VFB =ENET_WAKE_L
=PP3V3_S0_ENETPHY
BCM57765_CR_DATA<6>
PP3V3_ENET_PHY_XTALVDDH
BCM57765_SR_LX
BCM57765_CR_DATA<7>
BCM57765_VDDOCR_PIN20
BCM57765_VMAIN_PRSNT
PP3V3_ENET_PHY_XTALVDDH
VOLTAGE=3.3V
MIN_LINE_WIDTH=0.4 mm
MIN_NECK_WIDTH=0.2 mm
BCM57765_CE_L_MS_INS_L
VOLTAGE=3.3V
MIN_NECK_WIDTH=0.2 mm
MIN_LINE_WIDTH=0.4 mm
BCM57765_XTALVDDH
BCM57765_VDDOCR_PIN20
MIN_LINE_WIDTH=0.4 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=3.3V
BCM57765_SR_VDD
BCM5764_SCLK
PCIE_CLK100M_ENET_N
PCIE_CLK100M_ENET_P
PCIE_ENET_R2D_N
PCIE_ENET_D2R_C_P ENET_MDI_N<1>
BCM57765_VMAIN_PRSNT
ENET_MDI_N<2>
ENET_MDI_P<3>
TP_BCM5764_SPD100LED_L
TP_BCM5764_TRAFFICLED_L
ENET_MDI_N<3>
PCIE_ENET_D2R_C_N
ENET_RESET_L
ENET_CLKREQ_L
BCM57765_CE_L_MS_INS_L
PCIE_ENET_R2D_P
ENET_MDI_P<1>
ENET_MDI_N<0>
BCM57765_MEDIA_SENSE
ENET_ENERGY_DET
ENET_ENERGY_DET
SDCONN_CD_L
SDCONN_CMD
MIN_LINE_WIDTH=0.4 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=3.3V
PP3V3_ENET_PHY_BIASVDDH
PP3V3_ENET_PHY_AVDDH
VOLTAGE=3.3V
MIN_NECK_WIDTH=0.2 mm
MIN_LINE_WIDTH=0.4 mm
TP_BCM57765_SR_VDDP
BCM57765_SMB_DATA
BCM57765_CR_DATA<5>
BCM57765_WAKE_L
ENET_LOW_PWR
BCM5764_CLK25M_XTALO
BCM5764_CLK25M_XTALI
BCM57765_XTALVDDH
BCM5764_RDAC
SDCONN_DATA<7>
SDCONN_DATA<6>
SDCONN_WP
BCM57765_SR_DISABLE
BCM57765_CR_PWREN
BCM57765_CR_DATA<5>
BCM5764_MISO
BCM5764_MOSI
BCM5764_CS_L
BCM57765_SR_LX
PP3V3R1V8_SW_LR_OUT
BCM57765_SMB_CLK
BCM57765_CR_DATA<4>
BCM57765_SD_DETECT_L
BCM57765_CR_PWREN
BCM57765_CR_DATA<7>
BCM57765_CR_DATA<6>
=PP3V3_ENET_PHY
=PP3V3_S0_ENETPHY
=PP3V3_ENET_PHY
BCM5764_MOSI
BCM5764_MISO
ENET_MDI_P<0>
SDCONN_DATA<0>
SDCONN_DATA<2>
SDCONN_DATA<4>
SDCONN_DATA<5>
PP3V3R1V8_SW_LR_OUT
MIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=3.3V
SDCONN_DATA<3>
SDCONN_DATA<1>
BCM57765_CR_CMD
SDCONN_CLK
ENET_MDI_P<2>
37 OF 92
051-8337
A.0.0
39 OF 110
36 37
37
37
36 37
36 37
36 37
37
37
5 36 37 45
36 37 36 37
5 37
37 86
37
36 37
37 86
37
37
37
37
37
37
36 37
37
86
86
37
36
86
37
86
14 17 37
36
37
86
37
86 36
37
37 86
37
37
37
36 37
37
37
86
37
37
86
37
86
5 36 37 45
5 37
5 36 37 45
37
37
37
37
www.vinaﬁx.vn

TD4-
TCT4
TD4+
TD3-
TCT3
TD3+
TD2-
TD2+
TD1-
TCT2
TCT1
TD1+
MX4-
MX4+
MCT4
MX3-
MX3+
MCT3
MX2-
MX2+
MCT2
MX1-
MX1+
MCT1
1CT:1CT
1CT:1CT
1CT:1CT
1CT:1CT
ENET_MDI
TRAN_P0
TRAN_N0
TRAN_P1
TRAN_P2
TRAN_N2
TRAN_N1
TRAN_P3
TRAN_N3
PINS
SHIELD
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
BRANCH
REVISION
DRAWING NUMBER SIZE
D
R
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
21
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
87 54 21
CRITICAL BOM OPTION
TABLE_5_HEAD
PART# DESCRIPTIONQTY REFERENCE DESIGNATOR(S)
TABLE_5_ITEM
TABLE_5_ITEM
NOTE: BOB SMITH TERMINATION FOR EMC.
NOTE: Check with PHY and Magnetics MFR to determine what to do with center taps.
PLACE ONE CAP PER TCT PIN
157S0071
514-0733
2
1
R4000
75
5%
MF-LF
402
1/16W
2
1
R4001
MF-LF
75
402
5%
1/16W
2
1
R4002
75
1/16W
MF-LF
402
5%
2
1
R4003
MF-LF
402
1/16W
5%
75
2
1C4000
1206
1000PF
10%
NOSTUFF
2KV
CERM
2
1C4001
CERM
10V
0.1UF
20%
402
2
1C4002
CERM
10V
0.1UF
20%
402
2
1C4003
10V
CERM
0.1UF
20%
402
2
1C4004
CERM
10V
0.1UF
20%
402
11
12
8
9
5
6
2
3
10
7
4
1
14
13
17
16
20
19
23
22
15
18
21
24
T4000
SOI
CRITICAL
LFE9249APF
7
4
3
1
8
5
6
2
9
10
J4000
OMIT_TABLE
RJ45-K74-K75
CRITICAL
F-ANG-TH
PLASTIC_IOK74/K75 RJ45, PLASTIC, PD/NI514-0733
CRITICAL
1 J4000
METAL_IOJ4000K22/K23 PROD. RJ45514-0654 1
CRITICAL
SYNC_MASTER=MASTER
Ethernet Connector
SYNC_DATE=N/A
ENET_MDI_T_N<2>
ENET_MDI_T_N<2>
ENET_MDI_T_P<3>
ENET_MDI_T_N<3>
ENET_MDI_T_P<2>
ENET_MDI_T_N<1>
ENET_MDI_T_P<1>
ENET_MDI_T_N<0>
ENET_MDI_T_P<0>
ENET_MDI_N<0>
ENET_MCT3
ENET_TCT
ENET_MCT0
ENET_MDI_T_N<1>ENET_MDI_N<1>
ENET_MDI_P<0>
ENET_MDI_T_N<0>
ENET_MDI_T_P<0>
ENET_MDI_T_P<2>
ENET_MCT2
ENET_MDI_P<2>
ENET_MCT1
ENET_MDI_P<1> ENET_MDI_T_P<1>
ENET_MDI_N<2>
ENET_MDI_N<3>
ENET_MDI_P<3>
ENET_MDI_T_N<3>
ENET_MDI_T_P<3>
ENET_MCT_BS
MIN_NECK_WIDTH=0.2 mm
MIN_LINE_WIDTH=0.4 MM
40 OF 110
A.0.0
051-8337
38 OF 92
38 86
38 86
38 86
38 86
38 86
38 86
38 86
38 86
38 86
37 86
38 86 37 86
37 86
38 86
38 86
38 86 37 86
37 86 38 86
37 86
37 86
37 86
38 86
38 86
www.vinaﬁx.vn

OUT TRI-ST/NC
VCC
GND
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
OUT
IN
IN
OUT
IN
OUT
OUT
BI
BI
IN
BI
BI
BI
BI
BI
BI
BI
BI
BI
IN
RSVD_19
LKON_DS2_P
XI
CNA
CPS
PD
R1
R0
D6
D5
D4
D3
D2
D1
D0
CTL0
CTL1
LREQ_P
LREQ_L
LPS_P
LPS_L
PINT_P
PCLK_P
PINT_L
LCLK_P
LCLK_L
LINKON_L
DS1
DS0
PC2
PC0
PC1
PHY_RESET*
TPB2_N
TPB2_P
TPB1_N
TPB1_P
TPB0_N
TPB0_P
TPA2_N
TPA2_P
TPA1_N
TPA1_P
TPA0_N
TPA0_P
TPBIAS2
TPBIAS1
TPBIAS0
SE
TESTW_VREG_PD
SM
TESTM
BMODE
PLLGND
GND
DVDD_3_3
PLLVDD_3_3
VDDA_33 AVDD_3_3 VDD_15 VDDA_15 DVDD_CORE
VDD_15_COMBVDD_33_COM_IOVDD_33_COMB
VDD_33
PLLVDD_CORE
PCLK_L
VSSA_PCIEVSSAVSS
REF0_PCIE
REF1_PCIE
PERST*
RXN
RXP
TXN
TXP
CLKREQ*
REFCLK_P
REFCLK_M
REFCLK_SEL
SCL
SDA
GPIO0
GPIO2
GPIO1
GPIO3
GPIO4
GPIO5
GPIO7
GPIO6
OHCI_PME*
GRST*
RSVD_1
RSVD_0
RSVD_3
RSVD_2
RSVD_4
RSVD_6
RSVD_5
RSVD_9
RSVD_7
RSVD_8
RSVD_10
RSVD_11
RSVD_14
RSVD_12
RSVD_13
RSVD_16
RSVD_17
RSVD_18
RSVD_15
D7
CYCLEOUT
PCI EXPRESS
1394B OHCI & PHY
IN
IN
IN
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
BRANCH
REVISION
DRAWING NUMBER SIZE
D
R
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
21
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
87 54 21
Strap DSx high on unused ports.
page assumes no more than
(JTAG_TCK)
(JTAG_TDI)
(JTAG_TDO)
(JTAG_TMS)
(IPU)
(IPU)
Ground TPBx_P/TPBx_N
PC[0:2] = ’100’
Multiple-ports:
Unused Ports:
TP/NC TPAx_P/TPAx_N
TP/NC TPBIASx
Single-port:
2 FW800 connectors
PC[0:2] = ’000’
as appropriate
(VDD_33_AUX)
Power Aliases:
FWRS0_FWXIO nets are OHCI/PCIe power, and
can be S0.
5K pull-down device detect circuit.
For single-port systems, all FW power should
be tied together and powered by S0 or by the
FW_FWPHY nets are PHY power, and for
multi-port systems must come from bus power.
(IPU)
(JTAG_TRST)
(Snoop Enable, for FireBug)
DS2 hard-strapped to 1,
Layout Pads Overlayed
Alias =FWPHY_PC0
2
1
R4181
FW_TI_EXT_VREG
1/16W
402
5%
1K
MF-LF
2
1
C4125
1UF
10%
402
6.3V
CERM
2
1
C4130
6.3V
10%
CERM
1UF
402
2
1
C4120
CERM
1UF
402
6.3V
10%
2
1
R4125
5%
1/16W
MF-LF
1
402
2
1
R4190
FW_TI_EXT_VREG
5%
402
MF-LF
1/16W
4.7
4
13
2
Y4190
SM
98P3040MHZ
CRITICAL
2
1
C4190
0.22UF
402
CERM-X5R
6.3V
10%
2
1
R4135
1
402
MF-LF
1/16W
5%
2
1
R4160
1/16W
1K
MF-LF
402
5%
2
1
R4153
47K
5%
402
1/16W
MF-LF
NO STUFF
2
1
R4189
FW_TI_INT_VREG
MF-LF
1K
5%
402
1/16W
2
1
R4192
402
1/16W
5%
MF-LF
1
FW_TI_INT_VREG
40
2
1
R4150
MF-LF
1/16W
402
5%
1K
21C4146
0.1uF
X5R 40210% 16V
PLACEMENT_NOTE=Place C4146 next to C4145
21C4145
0.1uF
X5R 40210% 16V
PLACEMENT_NOTE=Place C4145 close to UA200
2
1
R4182
1K
1/16W
MF-LF
5%
402
2
1
R4151
220
MF-LF
402
5%
1/16W
2
1
R4152
220
MF-LF
402
5%
1/16W
21C4141
X5R 40210% 16V
0.1uF
PLACEMENT_NOTE=Place C4141 next to C4140
21C4140
0.1uF
X5R 40210% 16V
PLACEMENT_NOTE=Place C4140 close to U1400
2
1
R4141
232
1%
1/16W
402
MF-LF
2
1
C4117
10%
6.3V
CERM
402
1UF
17 84
17 84
40
2
1
R4180
1K
5%
402
1/16W
MF-LF
27 91
2
1
R4140
402
MF-LF
1/16W
1%
14.3K
2
1
C4118
10%
6.3V
CERM
402
1UF
2
1
C4119
10%
6.3V
CERM
1UF
402
2
1
R4119
402
1/16W
5%
1
MF-LF
2
1
R4117
402
1/16W
MF-LF
5%
1
2
1
R4110
402
1/16W
5%
1
MF-LF
2
1
C4110
6.3V
10%
CERM
402
1UF
2
1
C4111
402
10%
6.3V
CERM
1UF
17 84
2
1
C4112
10%
CERM
402
1UF
6.3V
2
1
C4100
10%
6.3V
CERM
402
1UF
2
1
C4101
10%
6.3V
CERM
402
1UF
2
1
C4102
10%
6.3V
CERM
402
1UF
2
1
C4113
10%
6.3V
402
1UF
CERM
2
1
C4114
6.3V
CERM
402
1UF
10%
2
1
C4106
10%
6.3V
CERM
402
1UF
2
1
C4107
10%
6.3V
CERM
402
1UF
2
1
C4115
1UF
10%
6.3V
CERM
402
2
1
C4108
10%
6.3V
CERM
402
1UF
17 84
2
1
C4103
10%
6.3V
CERM
402
1UF
2
1
C4104
10%
6.3V
CERM
402
1UF
2
1
C4105
10%
6.3V
CERM
402
1UF
40
17 84
40 86
40 86
40 86
40 86
40
40
40
40
40
2
1
C4189
CERM-X5R
402
6.3V
0.22UF
10%
17 84
2
1
R4185
MF-LF
1/16W
402
6.34K
1%
2
1
R4186
390K
402
1/16W
MF-LF
5%
P4
C7C6C5C4B6
C10
F5A7
A14
A10C3 B5B7B9B10 B11 C11B12M5J10H10G10E3 C12B8 P7M6K10H3G3
A9
A8
E13
G13
K13
D14
E14
H14
J14
M14
N14
B14
C14
F14
G14
K14
L14
A6
B2
P14
P13
H12
J13
A4
A3
M12
M11
M8
L13
L12
K12
G12
F13
P3
D13
D12
P11
P10
N13
N12
N11
N10
M13
F12
E12
H13
A1
B1
A12
A13
M1
N1
M7N7
N5
D3
D2
B4
B13
B3
F1
G1
A11
E8
E9
P8
E2
F2
C2
C1
D1
E1
H2
G2
C13
N6
P6
P5
N4
N3
P2
N2
P1
G8G7G6G5F9F8F7 K8K7K6K5F6 J8J7J6J5H9H8H7H6H5G9E7E6
M9F3C9K3J3C8
P9
N9
M3
M2
L3
L2
L1
K1
K2
J2
N8
J1
H1
P12
A2
J12
A5
M4M10K9J9F10E10
U4100
XIO2213B
BGA
OMIT
CRITICAL
2
1
C4137
10%
CERM
6.3V
402
1UF
2
1
C4138
6.3V
10%
1UF
CERM
402
2
1
R4175
402
1/16W
5%
10K
MF-LF
40
21
R4170
1K
1/16W
5%
402
MF-LF
40
40
2
1
C4139
10%
6.3V
CERM
402
1UF
2
1
C4135
10%
6.3V
CERM
402
1UF
21
R4191
22
MF-LF
5%
402
1/16W
2
1
R4171
MF-LF
1/16W
5%
402
470
2
1
C4124
402
CERM
6.3V
10%
1UF
2
1
C4128
CERM
1UF
6.3V
10%
402
2
1
C4127
402
CERM
6.3V
1UF
10%
2
1
C4126
1UF
402
10%
CERM
6.3V
2
1
C4123
10%
1UF
6.3V
402
CERM
2
1
C4122
10%
402
CERM
1UF
6.3V
2
1
C4121
CERM
402
1UF
10%
6.3V
2
1
C4132
6.3V
10%
402
1UF
CERM
2
1
C4131
1UF
10%
6.3V
402
CERM
SYNC_DATE=N/ASYNC_MASTER=MASTER
FireWire LLC/PHY (XIO2213B)
MIN_NECK_WIDTH=0.2 mm
MIN_LINE_WIDTH=0.3 mm
PP3V3_FW_AVDD
VOLTAGE=3.3V
=PP1V5_FWRS0_FWXIO
FWPHY_LKON_DS2
MIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.2 mm
PP3V3_FW_VDDA
VOLTAGE=3.3V
MIN_NECK_WIDTH=0.2 mm
MIN_LINE_WIDTH=0.3 mm
VOLTAGE=1.96V
PP1V96_FW_PLLVDD
PP1V95_FW_FWPHY
FWXIO_VDD15COMB
MIN_LINE_WIDTH=0.3 mm
PP3V3_FW_PLLVDD
VOLTAGE=3.3V
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=1.96V
PP1V96_FW_XTAL
MIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.2 mm
FWPHY_TESTW
=PP3V3_FW_FWPHY
FWPHY_BMODE
FWPHY_TESTM
TP_FWXIO_JTAG_TDI
FWXIO_SNOOP_EN
VOLTAGE=1.5V
MIN_NECK_WIDTH=0.2 mm
PP1V5_FW_VDDA
MIN_LINE_WIDTH=0.3 mm
FWXIO_VDD33COMB
FWXIO_VDD33COMIO
PCIE_FW_R2D_P
PCIE_FW_R2D_N
=PP3V3_FWRS0_FWXIO
TP_FWPHY_CNA
FWPHY_CPS
FWPHY_R0
FWPHY_R1
FWPHY_CLK98M_PCLK
FWOHCI_CLK98M_LCLK
FWPHY_PINT
FWOHCI_LPS
FWOHCI_LINKON_L
=FWPHY_PC0
=PP3V3_FW_FWPHY
CLK98M_FW_XI_R
FWXIO_CYCLEOUT
PCIE_FW_D2R_N
PCIE_FW_D2R_P
PCIE_FW_R2D_C_N
PCIE_FW_R2D_C_P
=FW_PME_L
PCIE_CLK100M_FW_N
PCIE_CLK100M_FW_P
=FW_CLKREQ_L
FW_P1_TPA_N
FW_P0_TPA_N
FW_P0_TPBIAS
FWXIO_REF0_PCIE
=FWPHY_DS0
=FWPHY_DS1
TP_FWOHCI_XO
PCIE_FW_D2R_C_N
PCIE_FW_D2R_C_P
FWXIO_REF_PCIE
FWXIO_REF1_PCIE
FW_P0_TPA_P
=PPVP_FW_PHY_CPS
FW_P1_TPA_P
FW_P2_TPA_P
FW_P2_TPA_N
FW_P2_TPBIAS
FW_P1_TPBIAS
FWXIO_SCL
FWXIO_SDA
FWXIO_REFCLK_SEL
FW_RESET_L
TP_FWXIO_GRST_L
TP_FWXIO_JTAG_TMS
TP_FWXIO_JTAG_TDO
CLK98M_FW_XI
FWOHCI_LREQ
=PP3V3_FW_FWPHY
FWPHY_RESET_L
FW_P0_TPB_N
FW_P0_TPB_P
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OUTIN
NR
NC THRML
EN
GND PAD
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
BRANCH
REVISION
DRAWING NUMBER SIZE
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IV ALL RIGHTS RESERVED
SHEET
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A
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PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
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87 54 21
Peak Current: 100mA
FireWire Aliases For Connectivity
1394 PHY STRAPPING OPTIONS
IT IS IN BILINGUL MODE PULL-UPS ASSERT/ENABLE DATA STROBE ONLY MODE.
2ND & 3RD TPA/TPB PAIR UNUSED
Place close to FireWire PHY
Termination
iMacs are now one port only and have Power Code "000"
THERE ARE THREE FIREWIRE PORTS, BUT ONLY ONE IS USED.NO STUFF MEANS THAT
TI PHY requires 1UF, not 0.33uF spec value.
TI PHY "Peaking Inductors" To improve Data Eye.
1394 PHY 1.95V SUPPLY
2
1
R4255
10K
1/16W
5%
NOSTUFF
MF-LF
402
2
1
R4256
10K
5%
1/16W
MF-LF
402
2
1C4250
CERM
1UF
6.3V
10%
402
2
1
R4251
MF-LF
402
1%
1/16W
56.2
2
1
R4250
1%
MF-LF
402
1/16W
56.2
2
1
R4253
56.2
1%
1/16W
402
MF-LF
2
1
R4252
56.2
1%
MF-LF
402
1/16W
2
1
R4254
MF-LF
1/16W
1%
4.99K
4022
1C4254
402
220PF
CERM
5%
25V
2
1
R4258
10K
402
MF-LF
5%
1/16W
2
1
R4257
10K
402
MF-LF
5%
1/16W
7
1
2
6
3
4
U4200
TPS799195
SON
CRITICAL
FW_TI_EXT_VREG
2
1C4202
X5R
2.2UF
20%
4V
402
FW_TI_EXT_VREG
2
1C4201
10%
16V
402
0.01UF
FW_TI_EXT_VREG
CERM
2
1C4200
6.3V
402
CERM
10%
1UF
FW_TI_EXT_VREG
21
L4252
18NH-250MA
0402
21
L4253
18NH-250MA
0402
21
L4250
0402
18NH-250MA
21
L4251
0402
18NH-250MA
FW: 1394B MISC
SYNC_MASTER=MASTER SYNC_DATE=N/A
NET_SPACING_TYPE=POWER
VOLTAGE=1.96V
PP1V95_FW_FWPHY
MAX_NECK_LENGTH=3 MM
MIN_NECK_WIDTH=0.2 mm
MIN_LINE_WIDTH=0.5 mm
MAKE_BASE=TRUE
NO_TEST=TRUE
VOLTAGE=1.86V
FW_P0_TPA_L_P
NO_TEST=TRUE
VOLTAGE=0V
FW_P0_TPB_L_P
FW_P0_TPA_L_N
NO_TEST=TRUE
VOLTAGE=1.86V
FW_P0_TPB_L_N
NO_TEST=TRUE
VOLTAGE=0V
FW_P0_TPB_N
FW_P0_TPA_N
FW_P0_TPA_P
MIN_LINE_WIDTH=0.1MM
FW_P0_TPBIAS
MIN_NECK_WIDTH=0.08MM
VOLTAGE=1.86V
FW_PORT0_TPA_P
MAKE_BASE=TRUE
=PPVP_FW_PHY_CPS PPVP_FW_PHY_CPS
MAKE_BASE=TRUE
MAKE_BASE=TRUE
FW_PME_L=FW_PME_L
=PP3V3_FW_FWPHY
=FWPHY_DS0
=FWPHY_DS1
MAKE_BASE=TRUE
FW_PHY_PC0=FWPHY_PC0
=PP3V3_FW_FWPHY
=FW_CLKREQ_L
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_FW_PORT1_TPBIASFW_P1_TPBIAS
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_FW_PORT1_TPA_PFW_P1_TPA_P
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_FW_PORT1_TPA_NFW_P1_TPA_N
MAKE_BASE=TRUE
NC_FW_PORT2_TPBIAS
NO_TEST=TRUE
NC_FW_PORT2_TPA_P
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_FW_PORT2_TPA_N
NO_TEST=TRUE
MAKE_BASE=TRUE
FW_P2_TPA_N
P1V95_FW_NR
FW_PHY_DS0
MAKE_BASE=TRUE
FW_PHY_DS1
MAKE_BASE=TRUE
FW_P0_TPA_C
FW_PORT0_TPA_N
MAKE_BASE=TRUE
FW_PORT0_TPB_N
MAKE_BASE=TRUE
FW_P0_TPB_P FW_PORT0_TPB_P
MAKE_BASE=TRUE
FW_CLKREQ_L
MAKE_BASE=TRUE
FW_P2_TPBIAS
FW_P2_TPA_P
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39
39
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39 86
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41 86
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39 41 86
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V+
GND
SYM_VER-1
SYM_VER-1
SHIELD
PINS
VGTPA-
TPA(R)
TPB-TPB(R)
TPB+ VP
TPA+
SC/NC
TABLE_5_ITEM
TABLE_5_ITEM
CRITICAL BOM OPTION
TABLE_5_HEAD
PART# DESCRIPTIONQTY REFERENCE DESIGNATOR(S)
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
BRANCH
REVISION
DRAWING NUMBER SIZE
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R
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
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PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
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87 54 21
IT IS 2.2V INSTEAD OF 2.7V BECAUSE THE SNAPBACK ESD DIODES HAVE A .5V DROP
INRUSH RESETABLE PTC
PLACE CLOSE TO COMPARITOR
5.1V
PORT 0
[ LATE VG NOTES ]
CURRENT THROUGH THE BIAS RESISTOR SHOULD BE 5MA FOR A VOLTAGE DROP TO 2.2V
ESD Rail
PLACE CLOSE TO COMPARATOR
5.1V
1394B
SHOULD BE DONE AS A POWER STRIP(SUBPLANE)
FAST NON-RESETABLE FUSE
IT IS HERE FOR SAFETY ONLY
POUR COPPER TO SINK HEAT
7 WATTS MAX PER PORT
12 VOLTS
NC
THIS FUSE WILL NOT BLOW
"Snapback" & "Late VG" Protection
514-0724
3
5
4
DP4310
SOT-363
BAV99DW-X-G
CRITICAL
3
5
4
DP4311
SOT-363
CRITICAL
BAV99DW-X-G
6
2
1
DP4310
SOT-363
CRITICAL
BAV99DW-X-G
6
2
1
DP4311
SOT-363
BAV99DW-X-G
CRITICAL
3
1
D4390
MMBZ5227BLT1H
SOT23
CRITICAL
21
R4390
1/16W
MF-LF
1%
402
332
2
1C4312
0.01UF
10%
50V
402
X7R
2
1C4313
10%
402
50V
0.01UF
X7R
2
1C4310
X7R
10%
50V
0.01UF
402
2
1C4311
X7R
10%
402
50V
0.01UF
21
L4300
SM
CRITICAL
FERR-250-OHM
2
1C4332
10%
402
0.001UF
CERM
50V
NOSTUFF
2
1C4335
603-1
0.1UF
10%
50V
X7R
2
1
R4335
402
1%
MF-LF
1/16W
1M
2
1C4300
603-1
10%
50V
X7R
0.01UF
3
1
D4301
MMBZ5231BXG
SOT23
21
F4301
0.3AMP-60V
CRITICAL
SMD030F-SM
4
3
6
5
2
1
Q4300
SSOT6
FDC610PZ
CRITICAL
21
R4300
5%
0.33
MF
1W
2512
2 3
1Q4301
SOT23
60V-600MA
MMBT2907AXG
21
R4352
402
51.1K
1/16W
1%
MF-LF
21
D4300
SM
CRITICAL
CRS08-1.5A-30V
2
1
R4303
MF-LF
1/16W
402
5%
20K
2
1
R4302
603
1/10W
5%
MF-LF
15K
2
1
R4307
402
MF-LF
1/16W
5%
20K
2
1C4302
20%
CERM
402
16V
0.01UF
2
1
R4301
5%
1/16W
10K
MF-LF
402
2
3
1
Q4302
SOT23
MMBT2222A7F
31
D4302
BAS40XG
SOT23
2
1C4304
10%
16V
402
0.1UF
X7R-CERM
8
1
7
3
5
2
6
4
U4300
SOI-HF
LM393
21
R4304
402
MF-LF
1/16W
5%
100K
2
1
R4306
200K
1/16W
MF-LF
5%
4022
1C4305
16V
X5R
10%
2.2UF
603
31
D4303
SOT23
MMBZ5231BXG
21
R4305
100K
1/16W
402
MF-LF
5%
21
F4300
3AMP-32V
603
CRITICAL
21
XW4300
SM
PLACEMENT_NOTE=PLACE CLOSE TO F4300
4
32
1
FL4310
12-OHM-100MA
TCM1210-4SM
NOSTUFF
4
32
1
FL4311
TCM1210-4SM
12-OHM-100MA
NOSTUFF
21
R4310
1/16W
5%
0
21
R4311
1/16W
5%
0
21
R4313
1/16W
5%
0
21
R4312
0
5%
1/16W
8
6
9
2
1
5
4
3
7
11
10
J4300
OMIT_TABLE
FWB-PL-K74-K75
CRITICAL
F-ANG-TH
SYNC_MASTER=MASTER SYNC_DATE=11/17/2009
FIREWIRE CONNECTOR
J4300514-0656 K22/K23 PROD. FW1
CRITICAL
METAL_IO
J43001 K74/K75 FW, PLASTIC, PD/NI514-0724
CRITICAL
PLASTIC_IO
FW_PORT0_TPB_F_N
FW_PORT0_TPB_F_P
FW_PORT0_VP
MIN_NECK_WIDTH=0.5MM
VOLTAGE=12V
MIN_LINE_WIDTH=1.7MM
FW_PORT0_TPA_R
FW_PORT0_TPA_F_P
FW_PORT0_TPA_F_N
FW_PORT0_VP_F
MIN_NECK_WIDTH=0.5MM
MIN_LINE_WIDTH=1.7MM
VOLTAGE=12V
FW_FET_LINEAR_LIMIT_OUT
P12V_FW_D
MIN_NECK_WIDTH=0.5MM
MIN_LINE_WIDTH=1.7MM
VOLTAGE=12V
FW_CURRENT_LIMIT
=PP12V_S0_FW
FW_FET_LINEAR_LIMIT_IN
FW_CURRENT_LIMIT_R
PP3V3_FW_ESD
MIN_NECK_WIDTH=0.25 mm
MIN_LINE_WIDTH=0.38 mm
VOLTAGE=3.3V
=PP3V3_FW_FWPHY
FW_FET_LINEAR_LIMIT_FB
FW_CURRENT_LIMIT_RD
FW_FET_LINEAR_LIMIT_IN
FW_FET_LINEAR_LIMIT_OUT
FW_CURRENT_LIMIT_Q
FW_TURN_ON_V
PPVP_FW_PHY_CPS
VOLTAGE=12V
MIN_NECK_WIDTH=0.25MM
MIN_LINE_WIDTH=0.5MM
P12V_FW_CL
MIN_LINE_WIDTH=1.7MM
MIN_NECK_WIDTH=0.5MM
VOLTAGE=12V
PP3V3_FW_ESD
PP3V3_FW_ESD
FW_CURRENT_LIMIT
=PP12V_S0_FW P12V_FW_R
MIN_LINE_WIDTH=1.7MM
VOLTAGE=12V
MIN_NECK_WIDTH=0.5MM
FW_PORT0_TPB_N
FW_PORT0_TPB_P
FW_PORT0_TPA_N
FW_PORT0_TPA_P
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41 89 5 39 40
41
41
40 89
41 89
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41
5 41
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OUT
IN
IN
OUT
OUT
IN
IN
OUT
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
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PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
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87 54 21
518S0792
518S0251
SILKSCREEN:ODD PWR
SILKSCREEN:HDD
SATA Activity LED
SATA PORT A0 FOR HDD
SATA PORT A1 FOR SLIMLINE ODDSILKSCREEN:ODD
17 84
21C4521
0.01UF
16V CERM 40210%
21C4520
0.01UF
10% CERM 40216V
21C4523
0.01UF
10% 16V CERM 402
21C4522
16V CERM 40210%
0.01UF
2
1C4524
6.3V
CERM
10%
402
1UF
2
1C4525
10%
6.3V
CERM
402
1UF
2
1
R4520
1/10W
MF-LF
603
33K
5%
7
6
5
4
3
2
1
J4510
EP00-081-91
M-ST-SM
CRITICAL
7
6
5
4
3
2
1
J4520
EP00-081-91
M-ST-SM
CRITICAL
5
4
3
2
1
J4530
CRITICAL
M-ST-SM
50293-0057N-001
21C4510
16V
0.01UF
10% 402 CERM
21C4511
10% 16V
0.01UF
402CERM
21C4515
10%
0.01UF
16V CERM 402
21C4516
CERM16V 402
0.01UF
10%
17 84
17 84
17 84
17 84
2
1
R4599
1/10W
DEVELOPMENT
5%
330
603
MF-LF
K
A
DS4599
SILK_PART=SATA ACTIVE
2.0X1.25MM-SM
GREEN-3.6MCD
DEVELOPMENT
17 84
17 84
17 84
SATA Connectors
SYNC_MASTER=K74_MASTER SYNC_DATE=N/A
SATA_HDD_D2R_C_P
=PP3V3_S0_ODD
SATA_ODD_R2D_P
SATA_ODD_R2D_N
SATA_ODD_D2R_C_N
SATA_ODD_D2R_C_P
SATALED_R_L
=PP3V3_S0_SATALED
SATA_HDD_R2D_N
SATA_HDD_R2D_P
SATA_HDD_D2R_C_N
MAKE_BASE=TRUE
SATALED_L
SATA_HDD_R2D_C_P
SATA_HDD_D2R_P
SATA_ODD_R2D_C_P
SATA_ODD_R2D_C_N
SATA_ODD_D2R_N
SATA_ODD_D2R_P
SATA_HDD_D2R_N
SATA_HDD_R2D_C_N
PCH_SATALED_L
SMC_ODD_DETECT
=PP5V_S0_SATA
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84
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EN1*
OC1*
IN OUT1
GNDTPAD
OUT2
OC2*
EN2*
G S
D
EN1*
OC1*
IN OUT1
GNDTPAD
OUT2
OC2*
EN2*
IO IONC
GND
VBUS
NC
SYM_VER-1
SYM_VER-1
SYM_VER-1
SYM_VER-1
VCC
GND
SELOE*
D+
D-
Y+
Y-
M+
M-
VBUS
DATA-
GND
DATA+
VBUS
DATA-
GND
DATA+
VBUS
DATA-
GND
DATA+
VBUS
DATA-
GND
DATA+
IO IONC
GND
VBUS
NC
IO IONC
GND
VBUS
NC
IO IONC
GND
VBUS
NC
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
CRITICAL BOM OPTION
TABLE_5_HEAD
PART# DESCRIPTIONQTY REFERENCE DESIGNATOR(S)
TABLE_5_ITEM
CRITICAL BOM OPTION
TABLE_5_HEAD
PART# DESCRIPTIONQTY REFERENCE DESIGNATOR(S)
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
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PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
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PAGE
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345678
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87 54 21
(PUT CAP ON CONNECTOR SIDE)
PORT 0
TOTAL: 3100 MA (STILL 100 MA SPARE EXTRA POWER)
IN S3, SOFTWARE MAY ALLOCATE UP TO 2000 MA TOTAL FOR CHARGING DEVICES
EXAMPLE: WIRED KEYBOARD WITH 2 500 MA PORTS = 1100 MA TOTAL ON ONE PORT
IPHONE ’FAST’ CHARGING AT 1000 MA ON ANOTHER PORT
500 MA STANDARD + 600 MA ’EXTRA’ POWER
2 STANDARD PORTS AT 500 MA EACH
500 MA STANDARD + 500 MA ’EXTRA’ POWER
USB PORT POWER:
EACH PORT IS HARDWARE CAPABLE OF 1.5A
SOFTWARE WILL ALLOW 500 MA PER PORT, PLUS
1200 MA ’EXTRA’ POWER TO BE DISTRIBUTED TO APPROVED
DEVICES ON A FIRST-COME, FIRST-SERVED BASIS
514-0732
514-0732
GND
D+
PORT 2
514-0731
(PUT CAP ON CONNECTOR SIDE)
D+
514-0731
PORT 1
(PUT CAP ON CONNECTOR SIDE)
SEL=1: CHOOSE USB
D-
VDD
GND
GND
D+
D-
VDD
D-
VDD
D-
GND
D+
SEL=0: CHOOSE SMC
USB/SMC DEBUG MUX
(PUT CAP ON CONNECTOR SIDE)
VDD
PORT 3
21
L4620
CRITICAL
SM
FERR-250-OHM
21
L4610
FERR-250-OHM
SM
CRITICAL
2
1C4650
10V
0.1UF
20%
CERM
402
21
R4651
402
0
5%
MF-LF
1/16W
PRODUCTION
21
R4652
402
1/16W
5%
MF-LF
0
PRODUCTION
9
6
7
5
8
2
1
4
3
U4600
CRITICAL
TPS2060
MSOP
2
1
C4602
330UF
CASE-D3L-SM
CRITICAL
20%
6.3V
POLY-TANT
2
1
3
Q4600
2N7002
SOT23-HF1
2
1
R4600
MF-LF
10K
5%
1/16W
402
2
1C4605
20%
CERM
402
10V
0.1UF
2
1C4601
402
CERM
0.1UF
20%
10V
2
1C4603
10V
402
20%
0.1UF
CERM
2
1C4611
0.1UF
10V
20%
CERM
402
9
6
7
5
8
2
1
4
3
U4601
MSOP
CRITICAL
TPS2060
2
1C4631
CERM
402
10V
20%
0.1UF
2
1C4630
0.01uF
20%
16V
402
CERM
6
45
1
D4630
CRITICAL
RCLAMP0502N
SLP1210N6
21
L4630
CRITICAL
FERR-250-OHM
SM
2
1C4621
CERM
10V
402
20%
0.1UF
2
1
C4606
6.3V
POLY-TANT
CASE-D3L-SM
20%
330UF
CRITICAL
2
1C4620
402
CERM
16V
20%
0.01uF
2
1C4610
0.01uF
20%
16V
CERM
402
2
1C4600
20%
0.01uF
16V
402
CERM
43
21
L4601
CRITICAL
120-OHM-90MA
DLP0NS
43
21
L4611
120-OHM-90MA
DLP0NS
CRITICAL
43
21
L4621
120-OHM-90MA
DLP0NS
CRITICAL
43
21
L4631
CRITICAL
DLP0NS
120-OHM-90MA
1
2
9
108
5
4
3
7
6
U4650
TQFN
MOJOMUX
PI3USB102ZLE
CRITICAL
1
6
5
4
3
2
J4610
OMIT_TABLE
F-ANG-TH
CRITICAL
USB-MG6-K74-K75
1
6
5
4
3
2
J4600
OMIT_TABLE
USB-MG6-K74-K75
CRITICAL
F-ANG-TH
1
6
5
4
3
2
J4630
OMIT_TABLE
F-ANG-TH
CRITICAL
USB-MG4-K74-K75
1
6
5
4
3
2
J4620
OMIT_TABLE
USB-MG4-K74-K75
CRITICAL
F-ANG-TH
21
L4600
FERR-250-OHM
CRITICAL
SM
6
45
1
D4620
SLP1210N6
CRITICAL
RCLAMP0502N
6
45
1
D4610
CRITICAL
SLP1210N6
RCLAMP0502N
6
45
1
D4600
CRITICAL
RCLAMP0502N
SLP1210N6
SYNC_MASTER=MASTER
EXTERNAL USB CONNECTORS
SYNC_DATE=11/30/2009
514-0672 K22/K23 PROD. USB2 METAL_IO
CRITICAL
J4600,J4610
514-0659
CRITICAL
METAL_IO2 K22/K23 PROD. USB J4620,J4630
514-0732
CRITICAL
PLASTIC_IO2 K74/K75 USB, PLASTIC, PD/NI J4620,J4630
514-0731 2 J4600,J4610 PLASTIC_IO
CRITICAL
K74/K75 USB, PLASTIC, PD/NI
=PP5V_S3_USB
USB_EXTD_OC_L
USB_EXTC_N
PP5V_USB2_PORT2
VOLTAGE=5V
MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM
VOLTAGE=5V
MIN_NECK_WIDTH=0.2MM
PP5V_USB2_PORT3
MIN_LINE_WIDTH=0.6MM
USB_PWR_ENA_L
SMC_RX_L
SMC_TX_L
USB_DEBUGPRT_EN_L
USB_EXTD_P
USB_EXTA_OC_L
PM_EN_USB_PWR
USB_EXTA_P
USB_EXTA_N
USB_EXTB_P
USB_EXTB_N
MIN_NECK_WIDTH=0.2MM
VOLTAGE=5V
MIN_LINE_WIDTH=0.6MM
PP5V_USB2_PORT0
USB_EXTC_P
=PP3V3_G3H_SMCUSBMUX
USB_D_MUXED_N
USB_D_MUXED_P
USB_EXTC_OC_L
MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM
VOLTAGE=5V
PP5V_USB2_PORT1
USB_EXTD_N
USB_EXTB_OC_L
USB_PORT0_P
USB_PORT0_N
USB_PORT1_P
USB_PORT3_P
USB_PORT3_N
PP5V_USB2_PORT3_F
MIN_NECK_WIDTH=0.2MM
MIN_LINE_WIDTH=0.6MM
VOLTAGE=5V
USB_PORT2_P
USB_PORT2_N
=PP5V_S3_USB
MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM
VOLTAGE=5V
PP5V_USB2_PORT0_F
USB_PORT1_N
VOLTAGE=5V
PP5V_USB2_PORT2_F
MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM
MIN_NECK_WIDTH=0.2MM
VOLTAGE=5V
MIN_LINE_WIDTH=0.6MM
PP5V_USB2_PORT1_F
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89
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46 47 48
46 47
35 85
34
63
34 85
34 85
35 85
35 85
89
34 85
5
85
85
34
89
35 85
35
85
85
85
85
85
89
85
85
5 43
89
85
89
89
www.vinaﬁx.vn

SYM_VER-1
SYM_VER-1
SYM_VER-1
G
D
S
G
D
S
SYM_VER-1
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
BRANCH
REVISION
DRAWING NUMBER SIZE
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SHEET
PAGE TITLE
C
A
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PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
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87 54 21
LAZAURS SD CARD READER BOARD CONNECTOR
518S0751
BACKUP TO CAESAR IV
IR RECEIVER CONNECTOR
518S0667
CAMERA/ALS & BLUETOOTH (K37A) CONNECTOR
2
1
C4781
402
6.3V
CERM
10%
1UF
43
21
L4702
CRITICAL
DLP0NS
120-OHM-90MA
4
3
2
1
6
5
J4780
M-RT-SM
53261-8604
CRITICAL
43
21
L4701
DLP0NS
120-OHM-90MA
CRITICAL
2
1C4701
402
0.1UF
20%
10V
CERM
2
1C4700
805-1
CERM
6.3V
20%
10UF
43
21
L4720
120-OHM-90MA
DLP0NS
CRITICAL
2
1
C4721
20%
CERM
10V
402
0.1UF
2
1
C4720
10UF
20%
CERM
6.3V
805-1
2
1
C4750
10%
1UF
6.3V
CERM
402
SD_USB
1
2
6
Q4710
SOT-363
SD_USB
2N7002DW-X-G
21
R4750
1/16W
1%
10K
MF-LF
402
SD_USB
4
5
3
Q4710
SOT-363
SD_USB
2N7002DW-X-G
43
21
L4750
DLP0NS
120-OHM-90MA
CRITICAL
SD_USB
2
1
R4751
402
10K
1%
1/16W
MF-LF
9
8
7
6
5
4
3
2
13
12
11
10
1
15
14
J4700
M-RT-SM
50224-01311-001
6
5
4
3
2
1
8
7
J4750
SM06B-SRKS-G-TB-HF
F-RT-SM
CRITICAL
SD_USB
21
L4751
CRITICAL
SD_USB
0603
220-OHM-1.4A
21
L4703
0603
220-OHM-1.4A
CRITICAL
21
L4721
0603
220-OHM-1.4A
CRITICAL
21
L4700
CRITICAL
0603
220-OHM-1.4A
SYNC_DATE=11/06/2009
Internal USB Connections
SYNC_MASTER=MASTER
USB_CAMERA_P
USB_CAMERA_L_N
USB_CAMERA_L_P
SNS_T1_DP2_DN3
USB_BT_L_N
USB_BT_L_P
SNS_T1_DN2_DP3
USB_BT_N
=SMB_ALS_SCL
=SMB_ALS_SDA
USB_IR_L_N
USB_IR_L_P
USB_CAMERA_N
USB_BT_P
USB_IR_P
USB_SDCARD_N
SDCARD_PLT_RST_R_L
SDCARD_PLT_RST_L
SDCARD_RESET
USB_SDCARD_P
SDCARD_RESET_L
USB_SDCARD_L_N
USB_SDCARD_L_P
=PP3V3_S3_SDCARD
NET_PHYSICAL_TYPE=POWER VOLTAGE=3.3V
MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM
PP3V3_S3_SDCARD_FLT
VOLTAGE=5V
PP5V_S3_IR_FLT
MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM=PP5V_S3_IR
NET_PHYSICAL_TYPE=POWER
USB_IR_N
PP3V3_S3_BT_FLT
MIN_NECK_WIDTH=0.2MM
MIN_LINE_WIDTH=0.5MM
VOLTAGE=3.3V
=PP3V3_S3_BT
NET_PHYSICAL_TYPE=POWER
NET_PHYSICAL_TYPE=POWER
=PP5V_S3_CAMERA
MIN_LINE_WIDTH=0.6MM
PP5V_S3_CAMERA_FLT
VOLTAGE=5V
MIN_NECK_WIDTH=0.2MM
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52 88
85 92
85 92
52 88
35 85
49 92
49 92
85 92
85 92
34 85
35 85
34 85
35 85
27 91
20 91 92
35 85
85 92
85 92
5 45
89
89 92
5
34 85
89 5
5
89
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OUT
BI
BI
OUT
BI
BI
BI
IN
BI
BI
BI
OUT
GS
D
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
BRANCH
REVISION
DRAWING NUMBER SIZE
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SHEET
PAGE TITLE
C
A
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PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
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87 54 21
CAESAR-IV CARD DETECT IS PROGRAMMABLE, BUT A SILICON BUG
MAKES THE ACTIVE-HIGH CASE UNUSABLE.
IMAC CARD DETECT SWITCH IS NORMALLY-CLOSED TO GND
(CARD INSERTED = OPEN)
37 86
37 86
37 86
2
1
R4800
5%
BCM57765
402
10K
1/16W
MF-LF
2
1
C4800
BCM57765
402
CERM
6.3V
1UF
10%
2
1C4801
BCM57765
10UF
20%
X5R
6.3V
603
21
F4800
1.0AMP-32V
BCM57765
0603
CRITICAL
37
37 86
37 86
37 86
21R4810
47
37 86
37 86
37 86
37 86
37
2
1
3
Q4850
BCM57765
SOT23-HF1
2N7002
2
1
R4850
MF-LF
1/16W
5%
10K
402
NOSTUFF
21
L4800
0603
CRITICAL
BCM57765
FERR-120-OHM-3A
9
8
7
6
5
4
3
26
25
24
23
22
21
20
2
19
18
17
16
15
14
13
12
11
10
1
27
28
J4800
CRITICAL
F-RT-SM
51281-2695
BCM57765
SD READER CONNECTOR
SYNC_DATE=N/ASYNC_MASTER=K74_MASTER
SDCONN_CMD
SDCONN_CLK_R
SDCONN_DATA<1>
SDCONN_DATA<7>
SDCONN_WP
PP3V3_S0_SDCARD_CONN
NET_SPACING_TYPE=POWER
MIN_NECK_WIDTH=0.2MM
MAX_NECK_LENGTH=3 MM
MIN_LINE_WIDTH=0.4MM
VOLTAGE=3.3V
SDCONN_DATA<2>
SDCONN_DATA<4>
=PP3V3_ENET_PHY
SDCONN_CD_L
=PP3V3_S0_SDCARD
VOLTAGE=3.3V
MAX_NECK_LENGTH=3 MM
MIN_NECK_WIDTH=0.2MM
PP3V3_S0_SDCARD_F
MIN_LINE_WIDTH=0.4MM
NET_SPACING_TYPE=POWER
SDCONN_DATA<6>
SDCONN_DATA<0>
SDCONN_CLK
=PP3V3_S3_SDCARD
SDCONN_DETECT
SDCONN_DATA<5>
SDCONN_DATA<3>
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IN
IN
IN
OUT
OUT
OUT
IN
IN
OUT
IN
IN
IN
IN
IN
IN
IN
IN
IN
OUT
IN
BI
IN
IN
OUT
OUT
IN
IN
OUT
IN
OUT
OUT
OUT
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
OUT
IN
BI
BI
BI
BI
BI
BI
OUT
OUT
IN
IN
OUT
IN
IN
BI
OUT
IN
OUT
OUT
OUT
OUT
OUTNC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
IN
OUT
OUT
OUT
OUT
NC
NC
OUT
BI
IN
OUT
ININ
IN
OUT
P13
P14
P15
P16 P66
P10
P11
P12
P17
P20
P21
P22
P23
P24
P25
P26
P27
P30
P31
P32
P33
P34
P36
P37
P40
P41
P42
P43
P44
P45
P46
P47
P50
P51
P52
P60
P61
P62
P63
P64
P65
P67
P70
P71
P72
P73
P74
P75
P76
P77
P80
P81
P84
P85
P86
P90
P91
P92
P93
P94
P95
P96
P97
P35
P83
P82
(1 OF 3)
PA5
PA4
PA0
PA1
PA2
PA3
PA6
PA7
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
PC0
PC1
PC2
PC3
PC4
PC5
PC6
PC7
PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7
PE0
PE1
PE2
PE3
PE4
PF0
PF1
PF2
PF3
PF4
PF5
PF6
PF7
PG0
PG1
PG2
PG3
PG4
PG5
PG6
PG7
PH0
PH1
PH2
PH3
PH4
PH5
(2 OF 3)
RES*
NMI
VSS
VCLVCC
NC
MD2
MD1
ETRST
AVSS
AVREFAVCC
EXTAL
XTAL
(3 OF 3)
NC
NC
OUT
NC
NC
NC
IN
NC
NC
IN
NC
NC
NC
NC
NC
NC
NC
NC
BI
BI
BI
BI
IN
IN
IN
BI
IN
IN
BI
BI
IN
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
BRANCH
REVISION
DRAWING NUMBER SIZE
D
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IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
21
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
87 54 21
(OC)
(OC)
(OC)
(OC)
(OC)
NOTE: Unused pins have "SMC_Pxx" names. Unused
pins designed as outputs can be left floating,
those designated as inputs require pull-ups.
(OC)
(OC)
(OC)
(OC)
(See below)
(OC)
Otherwise, TP/NC okay (was ISENSE_CAL_EN)
SMC_IG_THROTTLE_L for MG systems.
(OC)
If SMS interrupt is not used, pull up to SMC rail.
(OC)
Peak/Ave/Standby= 2mA/1mA/5uA
(OC)
NOTE: SMS Interrupt can be active high or low, rename net accordingly.
Peak/Ave/Standby = 2mA/1mA/5uA
Peak/Ave/Sleep/Standby = 40mA/25mA/20mA/50uA
SMC_PB3:
(OC)
(OC)
(OC)
(OC)
2
1
C4902
805
22UF
CERM
20%
6.3V
18 48
47 48 91
47
2
1
C4907
402
CERM-X5R
0.47UF
6.3V
10%
PLACEMENT_NOTE=Place C4907 close to U4900 pin 13
2
1
C4903
402
CERM
20%
10V
0.1UF
2
1
C4920
10V
402
0.1UF
CERM
20%
PLACEMENT_NOTE=Place C4920 close to U4900 pin 76
21
R4999
1/16W
MF-LF
402
5%
4.7
PLACEMENT_NOTE=Place R4999 close to U4900 pin 76
2
1
C4904
10V
402
0.1UF
CERM
20%
21
XW4900
SM
18 24 91
47
2
1
C4905
10V
402
CERM
20%
0.1UF
63 91
64 91
64 91
47
2
1
C4906
20%
CERM
0.1UF
10V
402
50 88
50 88
47
50
47
47
50
50
47
43 46 47 48
43 46 47 48
49
2
1
R4909
5%
10K
1/16W
MF-LF
402
48
48
2
1
R4901
10K
MF-LF
5%
1/16W
402
2
1
R4902
402
10K
5%
MF-LF
1/16W
2
1
R4903
402
1/16W
5%
MF-LF
0
NOSTUFF
2
1
R4998
10K
1/16W
MF-LF
402
5%
43 47
14 18 91
42 92
51 88
14 20
47
53
53
54
54
53
53
50 88
50
50 88
47
47
47
47
47 48
47
47 48
47 48
47 48
49
49
49
49
49
49
47
47
47
43 46 47 48
43 46 47 48
47
47
17 48
18 27 91
48
17
14 18 48 91
47
47
18 47
47
47
47
47
47
14 17
47
47
47
47 47
47
3
F1
F4
G4
H4
G1
H2
G3
J4
C6
B5
A6
D5
C7
B6
A7
L12
N13
M13
N12
N11
L10
M11
N10
H12
J11
J10
K13
J12
K11
K12
L13
E4
F3
G2
C3
C1
B2
C2
A1
B4
A5
D4
D6
D7
D8
A8
B7
C8
D9
A9
E10
F13
E12
E13
F11
D12
E11
D13
D10
C12
C13
D11
B13
A12
A13
B12
U4900
H8S2117
OMIT
LGA-HF
C4
B3
A4
J2
F2
E2
L6
M7
N6
K6
K7
K8
N7
M8
M4
L4
N4
M5
L5
M6
N5
K5
K4
J1
K2
J3
K1
L7
K9
N8
M9
L8
K10
N9
M10
J13
H11
G12
G10
H13
F12
G13
G11
A11
C11
B10
C10
A10
B9
C9
B8
L2
K3
L1
N2
M2
M3
N1
N3
U4900
H8S2117
LGA-HF
OMIT
A3
C5
B11F10
L3D2
E1H10M1B1
D3
E3
H1
D1
A2
H3
L9
L11M12
U4900
OMIT
H8S2117
LGA-HF
47
47
47
17 48 85
17 48 85
17 48 85
17 48 85
17 48 85
27 91
27 85
49
5 18 26 36 47 63 64 81 91
8 85 91
49
49
47
SMC
SYNC_MASTER=K74_MASTER SYNC_DATE=N/A
BDV_SRC_AUX_TERM_EN
SMC_LRESET_L
SMC_ONOFF_L
SMB_MGMT_CLK
SMC_CPU_VTT_VSENSE
PM_SLP_S3_L
BDV_AUXP_STATE
PM_SLP_S45_L
BDV_DP_VIDEO_ON
SMC_TMS
SMC_LID
BDV_PWM_OR_SINK_TERM
SMB_BSA_DATA
SMB_BSA_CLK
SMB_B_S0_DATA
SMB_B_S0_CLK
MEM_EVENT_B_L
SMC_GFX_THROTTLE_L
SMS_ONOFF_L
SMC_P41
LPC_CLK33M_SMC
LPC_AD<0>
LPC_AD<1>
LPC_AD<2>
LPC_AD<3>
BDV_AV_MUX_SEL_SMC
SMC_EXCARD_PWR_EN
SMC_PROCHOT_3_3_L
SMC_PM_G2_EN
SMC_THRMTRIP
BDV_HPD_STATE
SMC_GFX_OVERTEMP_L
SMC_HDD_OOB_TEMP
SMC_PB3
SMC_ODD_DETECT
SMC_RUNTIME_SCI_L
PM_BATLOW_L
SYS_ONEWIRE
MEM_EVENT_A_L
USB_DEBUGPRT_EN_L
SMB_0_S0_DATA
PM_CLK32K_SUSCLK
SMC_BC_ACOK
SMC_WAKE_SCI_L
LPC_PWRDWN_L
LPC_SERIRQ
PM_CLKRUN_L
BDV_AUXN_STATE
SMC_CPU_VTT_ISENSE
SMC_KBC_MDE
SMC_MD1
=PP3V3_G3H_SMC
PP3V3_G3H_AVREF_SMC
SMC_VCL
MIN_LINE_WIDTH=0.25 MM
MIN_NECK_WIDTH=0.20 MM
PP3V3_G3H_SMC_AVCC
VOLTAGE=3.4V
SMC_RESET_L
SMC_XTAL
SMC_EXTAL
GND_SMC_AVSS
SMC_TRST_L
SMC_TX_L
SMC_RX_L
SMC_BIL_BUTTON_L
SMC_CPU_ISENSE
SMC_CPU_VSENSE
SMC_ANALOG_P72
SMC_GPU_VSENSE
SMC_DCIN_ISENSE
SMC_PBUS_VSENSE
SMC_ANALOG_PD7
SMC_CPU_1V5_VSENSE
SMC_FAN_3_TACH
SMC_FAN_0_TACH
SMC_FAN_3_CTL
SMC_FAN_1_CTL
SMC_FAN_0_CTL
SMC_PROCHOT
PM_SYSRST_L
SMC_SYS_LED
SMC_ANALOG_PD6
SMC_ANALOG_PD5
SMC_FAN_1_TACH
SMC_ANALOG_PD2
SMC_GPU_ISENSE
SMC_ANALOG_PD3
SMC_CPU_1V5_ISENSE
G3_POWERON_L
RSMRST_PWRGD
ALL_SYS_PWRGD_SMC
SMC_RSTGATE_L
SMC_ADAPTER_EN
SMB_A_S3_CLK
SMB_A_S3_DATA
=SMC_SMS_INT
SPI_DESCRIPTOR_OVERRIDE_L
SMB_0_S0_CLK
LPC_FRAME_L SMC_TX_L
SMC_RX_L
PM_PWRBTN_L
PM_RSMRST_L
CPUIMVP_VR_ON
SMC_TCK
SMC_TDI
SMC_TDO
SMB_MGMT_DATA
SMC_NMI
49 OF 110
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G
D
S
IN
BI
OUT
G
D
S
OUT
IN
IN
G
D
S
G
D
S
IN
OUT
REFOUT
MR1*
THRM
GND
RESET*
DELAY
MR2*
VINV+
SN0903048
PAD
OUT
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
BRANCH
REVISION
DRAWING NUMBER SIZE
D
R
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
21
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
87 54 21
UNUSED PORT 7 ANALOG SENSORS
SMC PROCHOT 3.3V LEVEL SHIFTING
MEM_EVENT
MISC. SIGNAL ALIASES
POWER BUTTON
NOTE: Internal pull-ups are to VIN, not V+.
Used on mobiles to support SMC reset via keyboard.
TO CPU
NC
NC
(IPU)
518S0665
TO SMC
FROM SMC
FROM MXM
FROM SMC
PULL-UP ON PAGE 14
SMC & MXM THERMTRIP LEVEL SHIFTING
MR1* and MR2* must both be low to cause manual reset.
TO SMC
TO/FROM SMC
(IPU)
UNUSED PORT D ANALOG (INTERNAL PULLUPS)
TIES OFF AUDIO DETECT CIRCUIT WHEN BIDIVI IS NOT USED
UNUSED TP/NC ALIASES
SMC Reset "Button", Supervisor & AVREF Supply
SMC Crystal Circuit
FROM DIMMS
4
5
3
Q5095
SOT-363
2N7002DW-X-G
21R5032
4025%
10K
1/16W MF-LF
21R5035
1/16W
10K
4025% MF-LF
21R5036
5%
100K
402MF-LF1/16W
21R5037
4025% MF-LF1/16W
2.0K
21R5039 10K
5% 4021/16W MF-LF
21R5040 10K
5% 402MF-LF1/16W
21R5041 10K
5% MF-LF4021/16W
21R5042 10K
4025% 1/16W MF-LF
2
1
Y5020
20.000M
CRITICAL
SM-4
21R5094
1/16W
100K
MF-LF5% 402
46
2
1
C5010
10V
20%
0.1UF
CERM
402
21
R5010
1K
5%
MF-LF
402
1/16W
1
6
2
Q5077
MMDT3904-X-G
SOT-363-LF
21
R5071
MF-LF
1/16W
5%
402
3.3K
4
3
5
Q5077
SOT-363-LF
MMDT3904-X-G
2
1
R5070
1/16W
402
MF-LF
5%
3.3K
2
1
R5078
402
1/16W
MF-LF
5%
470
10
46
21R5091 10K
5% MF-LF4021/16W
21R5090
1/16W MF-LF 4025%
100K
21R5092 10K
5% 1/16W 402MF-LF
21R5047 10K
5% 1/16W 402MF-LF
21R5049 10K
MF-LF1/16W 4025%
21R5098 10K
MF-LF5% 4021/16W
1
2
6
Q5095
2N7002DW-X-G
SOT-363
10 20 91
46
75
21
R5018
1/16W
MF-LF
5%
0
402
MXM
21R5099
5% 1/16W MF-LF
10K
402
1
2
6
Q5096
SOT-363
MXM
2N7002DW-X-G
4
5
3
Q5096
MXM
2N7002DW-X-G
SOT-363
2
1
R5069
MXM
3.3K
5%
402
MF-LF
1/16W
2
1
R5068
402
MF-LF
1/16W
5%
10K
MXM
2
1
4
3
J5010
SILK_PART=PWR BTN
CRITICAL
M-RT-SM
53261-8602
21R5087
402
10K
MF-LF1/16W5%
2
1
R5080
1/16W
402
MF-LF
5%
10K
30 31
21R5086
402
10K
1/16W MF-LF5%
21
R5002
1/16W
10K
402
5%
MF-LF
43
21
S5000
NTC020-CC1J-B260T
SILK_PART=SMC RESET
DEVELOPMENT
SM
43
21
S5010
SILK_PART=SYS POWER
DEVELOPMENT
NTC020-CC1J-B260T
SM
21R5089 100K
1/16W5% MF-LF402
46 48 91
2
1
R5000
402
5%
MF-LF
1/16W
1K
2
1
C5026
0.01UF
402
16V
CERM
10%
2
1
C5025
6.3V
20%
603
X5R
10uF
31
9
5
8
7
6
2
4
U5010
DFN
VREF-3.3V-VDET-3.0V
2
1
C5000
10%
6.3V
402
0.47UF
CERM-X5R
2
1
C5001
0.01UF
CERM
402
16V
10%
2
1
R5085
1/16W
402
MF-LF
5%
10K
21R5063
MF-LF5% 402
100K
1/16W
21R5062
1/16W
100K
4025% MF-LF
21R5061
1/16W
100K
4025% MF-LF
21R5060
MF-LF5% 402
100K
1/16W
21
L5010
FERR-220-OHM
0402
46 47
21
C5020
22PF
50V
5%
402
CERM
21
C5021
50V
CERM
5%
22PF
402
SMC Support
SYNC_MASTER=K74_MASTER SYNC_DATE=N/A
MEM_EVENT_A_L
MAKE_BASE=TRUE
SMC_EXTAL
SMC_XTAL
SMC_ONOFF_R_L
POWER_BUTTON_L
GND_SMC_AVSS
MIN_LINE_WIDTH=0.4 mm
MIN_NECK_WIDTH=0.1 mm
VOLTAGE=0V
SMC_PB3
SMC_P41
MAKE_BASE=TRUE
GND_AUDIO_CODEC
BDV_AV_MUX_SEL
SMC_ANALOG_PD7
BDV_AV_MUX_SEL_SMC
SMC_EXCARD_PWR_EN
SMC_ANALOG_PD5
SMC_ANALOG_PD3
BDV_SRC_AUX_TERM_EN
MAKE_BASE=TRUE
TP_BDV_AV_MUX_SEL_SMC
TP_BDV_SRC_AUX_TERM_EN
MAKE_BASE=TRUE
BDV_PWM_OR_SINK_TERM
SMC_SYS_LED
SMC_RSTGATE_L
MAKE_BASE=TRUE
TP_SMC_PB3
MAKE_BASE=TRUE
TP_SMS_ONOFF_L
SMC_DCIN_ISENSE
MAKE_BASE=TRUE
SMC_DELAYED_PWRGD
=PPSPD_S0_MEM_A =PP3V3_S0_SMC
NC_SMC_ANALOG_PD3
MAKE_BASE=TRUE NO_TEST=TRUE
SMC_ANALOG_PD6
MAKE_BASE=TRUE
SMC_SMS_INT
SMC_ADAPTER_EN
SMC_TDI
SMC_TMS
SMC_TDO
SYS_ONEWIRE
SMC_RX_L
SMC_TX_L
MXM_PWR_LEVEL
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_SMC_ANALOG_PD6
MAKE_BASE=TRUE
NC_SMC_ANALOG_PD7
MAKE_BASE=TRUE NO_TEST=TRUE
TP_SMC_EXCARD_PWR_EN
MAKE_BASE=TRUE
CPU_PROCHOT_L
CPU_PROCHOT_BUF
SMC_THRMTRIP
MXM_OVERT_L
MXM_THRMTRIP
=PP3V3_S0_SMC_LS
PM_THRMTRIP_L
MXM_THRMTRIP_L
SMC_PROCHOT
CPU_PROCHOT_L_R
MIN_LINE_WIDTH=0.4 mm
PP3V3_G3H_AVREF_SMC
MIN_NECK_WIDTH=0.1 mm
VOLTAGE=3.3V
SMC_RESET_L
SMC_GFX_THROTTLE_L
SMC_GFX_OVERTEMP_L
CPUIMVP_VR_ON
SMC_ONOFF_L
SMC_PBUS_VSENSE
SMC_MANUAL_RST_L
=PP3V3_S0_SMC
MEM_EVENT_B_L
=PPVIN_S5_SMCVREF
=PP3V3_G3H_SMC
SMC_ANALOG_P72
MAKE_BASE=TRUE
TP_SMC_RSTGATE_L
MAKE_BASE=TRUE
TP_SMC_P41
MAKE_BASE=TRUE
TP_SMC_SYS_LED
SMC_PROCHOT_3_3_L
=PPVTT_S0_CPU
MAKE_BASE=TRUE NO_TEST=TRUE
NC_SMC_ANALOG_PD5
NC_SMC_ANALOG_PD2
MAKE_BASE=TRUE NO_TEST=TRUE
SMC_ANALOG_PD2
MAKE_BASE=TRUE
SMC_UNUSED_ADC_PORT7
MAKE_BASE=TRUE
MXM_ALERT_L
SMS_ONOFF_L
SMC_BIL_BUTTON_L
SMC_TCK
SMC_LID
SMC_BC_ACOK
=PP3V3_G3H_SMC
PM_SLP_S5_L
MEM_EVENT_L
=PP3V3_S0_SMC_LS
PM_SLP_S45_L
PM_SLP_S4_L
PM_SLP_S3_L
BDV_DP_VIDEO_ON
SMC_GFX_OVERTEMP_L
BDV_AUXP_STATE
=SMC_SMS_INT
G3_POWERON_L
USB_DEBUGPRT_EN_L
BDV_HPD_STATE
BDV_AUXN_STATE
MAKE_BASE=TRUE
TP_BDV_PWM_OR_SINK_TERM
SMC_ONOFF_L
50 OF 110
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56 57 61 62 61
46
46
46
46
46
46
46
46
46
46
64 91
5 30 5 47 50
46
18 46
46 48
46 48
46 48
46
43 46 48
43 46 48
75
5 47 51
46 89
46
46 47
46
46 47
46
5 47 50
46
5
5 46 47
46
5 10 12 15 65
46
75
46
46
46 48
46
46
5 46 47
5 47 51
46
18 91
5 18 26 36 46 63 64 81 91
46
46 47
46
46
46
43 46
46
46
www.vinaﬁx.vn

IN
IN
OUT
OUT
IN
IN
OUT
OUT
OUT
IN
BI
IN
BI
OUT
OUT
OUT
OUT
OUT
OUT
IN
BI
IN
IN
OUT
BI
BI
IN
INOUT
INOUT
OUTIN
OUT
OUT
VER 1
VCC
A
1
0
B1
GND
B0
SEL
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
BRANCH
REVISION
DRAWING NUMBER SIZE
D
R
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
21
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
87 54 21
516S0573
Alternate SPI ROM Support
FRANK CONNECTOR
SPI Bus Series Resistance Option
Pull-up on debug card
LPC+SPI Connector
2
1C5144
0.1UF
10V
20%
402
CERM
21
R5145
PLACEMENT_NOTE=Place near U1400
LPCPLUS
402
5%
MF-LF
0
1/16W
17 85
43 46 47
46
46 47
46
27 91
46 47
14 18 46 91
48 85
17 46 85
17 46 85
48 85
17 46 85
9
87
65
4
3433
3231
30
3
29
2827
2625
2423
2221
20
2
19
1817
1615
1413
1211
10
1
J5100
55909-0374
CRITICAL
LPCPLUS
M-ST-SM
20
43 46 47
46
46 47 91
46 47
46 47
18 46
17 46
48 85
48 85
20 48 85
17 46 85
17 46 85
27 85
17 55 85
21
R5156
LPCPLUS
402
PLACEMENT_NOTE=Place next to R6150 5%
MF-LF
0
1/16W
48 85
17 55 85
21
R5157
PLACEMENT_NOTE=Place next to R6152
402
0
MF-LF
5%
1/16W
LPCPLUS
48 85
17 55 85
21
R5158
PLACEMENT_NOTE=Place next to R6105
402
1/16W
5%
MF-LF
0
LPCPLUS
48 85
2
1
R5140
MF-LF
402
5%
1/16W
100K
48 85
55 85
5
6
2
1
34
U5100
LPCPLUS
PATH=I96
SC70
CRITICAL
NC7SB3157P6XG
2
1
R5144
402
MF-LF
1/16W
5%
20K
21
R5146
PRODUCTION
5%
MF-LF
0
402
1/16W
PLACEMENT_NOTE=PLACE NEXT TO U5100
SYNC_MASTER=K23F SYNC_DATE=11/30/2009
LPC+SPI Debug Connector
SMC_MD1
SPIROM_USE_MLB
MAKE_BASE=TRUE
SPI_CS0_R_L
=PP3V3_S5_LPCPLUS
SMC_RX_L
SMC_TCK
SPI_CLK_R
SPI_ALT_MOSI
SPI_ALT_MISO
=PP3V3_S5_LPCPLUS
SPI_MOSI_R
SPI_MISO
SMC_RESET_L
SMC_NMI
SPI_ALT_MISO
SMC_TMS
DEBUG_RESET_L
SMC_TDO
SPI_ALT_CLK
SMC_TDI
LPC_PWRDWN_L
SPI_ALT_CLK
LPC_AD<3>
LPC_FRAME_L
PM_CLKRUN_L
SPI_ALT_CS_L SPI_CS0_L
=PP3V3_S5_ROM
SPI_MLB_CS_L
LPC_AD<0>
LPC_SERIRQ
SPI_ALT_CS_L
SPIROM_USE_MLB
LPC_AD<2>
LPC_CLK33M_LPCPLUS
LPCPLUS_GPIO
SPI_ALT_MOSI
LPC_AD<1>
SMC_TX_L
SMC_TRST_L
=PP5V_S0_LPCPLUS
=PP3V3_G3H_LPCPLUS
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5 48
85
5 55
5
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II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
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DRAWING NUMBER SIZE
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A
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PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
87 54 21
SMC SLAVE SMBUS "2" CONNECTIONS
USES INTERNAL SMC CONTROLLER CHANNEL 2 ONLY
DISPLAY TCON
DP RX MASTER FOR MCCS
PCH
PCH "SMBUS" CONNECTIONS
MEMORY A DIMMS
(WRITE: 0X98 OR 0X9A, READ: 0X99 OR 0X9B)
3 SENSE POINTS - PRIMARY, SECONDARY, AMB
DP TX REDRIVER
U9180
(WRITE: 0X9C, READ: 0X9D)
OUTPUT VOLTAGE, CURRENT, POWER
SMC SLAVE ADDRESS TBD
SMC "MANAGEMENT" SMBUS (BUS 1)
BUS A CAN USE EITHER INTERNAL SMC CHANNEL 0 OR 1, K74 CHOOSES 1
BUS B CAN USE EITHER INTERNAL SMC CHANNEL 0 OR 1, K74 CHOOSES 0
SMC "B" SMBus Connections
MXM CARD (WRITE: 0X98 READ: 0X99)
MXM TEMP
AC/DC PS POWER
(MASTER)
U4900
SMC
(WRITE: 0X98 READ: 0X99)
XDP
(WRITE: 0XD8 READ: 0XD9)
TMP423: U5550
HEATSINK TEMPS
EMC1414: U5500
(MASTER)
(WRITE: 0X9A READ: 0X9B)
AMB,ODD,SKIN TEMPS
Also reserve 0x56 and 0x32 per spec
(WRITE: 0X80, READ: 0X81))
INA219: ACDC THRU J600
SMC
(WRITE: 0X88 READ: 0X89)
(SLAVE)
PCIE MINI-CARD
X18 WI-FI MODULE
(WRITE: 0X90 READ: 0X91)
EMC1403-[1,2]: ACDC THRU J600
AC/DC PS TEMPS
U4900
(MASTER)
SMC
NV INSIDE (WRITE: 0X9E READ: 0X9F)
GPU ON CARD - J8400
(MASTER)
SMC
U4900
(WRITE: 0X72 READ: 0X73)
SMC "A" SMBus Connections
NOTE: SMC RMT BUS REMAINS POWERED AND MAY BE ACTIVE IN S3 STATE
U1800
PCH
(SLAVE)
CK505
J3200-A/B
(WRITE: 0XD2 READ: 0XD3)
U2600
ALS
U4900
(MASTER)
U1800
SMC
U4900
USES INTERNAL SMC CONTROLLER CHANNEL 1 ONLY
TMP106: J3400
(WRITE: 0X52 READ: 0X53)
USES INTERNAL SMC CONTROLLER CHANNEL 0 ONLY
SMC "0" SMBus Connections
PCH "SML 1" CONNECTIONS
PCH "SML 0" CONNECTIONS
(MASTER)
U1800
PCH
(WRITE: 0XA2 READ: 0XA5)
(Write: 0xA0 Read: 0xA1)
(MASTER)
J2500
J3100-A/B
MIKEY
MEMORY VREF DAC
U2900
U2910
MEMORY B DIMMS
(WRITE: 0X30 READ: 0X31)
MEMORY VREF MARGIN
(WRITE: 0XA6 READ: 0XA7)
(WRITE: 0XA4 READ: 0XA3)
U6806
2
1
R5280
4.7K
402
5%
1/16W
MF-LF
2
1
R5281
4.7K
1/16W
5%
402
MF-LF
2
1
R5291
5%
402
MF-LF
1/16W
4.7K
2
1
R5290
1/16W
MF-LF
402
5%
4.7K
2
1
R5261
5%
1/16W
2.2K
402
MF-LF
2
1
R5260
5%
2.2K
MF-LF
402
1/16W
2
1
R5251
402
5%
1/16W
4.7K
MF-LF
2
1
R5250
4.7K
5%
402
MF-LF
1/16W
2
1
R5203
402
MF-LF
1/16W
5%
8.2K
2
1
R5202
5%
8.2K
1/16W
MF-LF
402
2
1
R5204
8.2K
NOSTUFF
5%
402
1/16W
MF-LF
2
1
R5205
NOSTUFF
8.2K
5%
402
1/16W
MF-LF
21
R5206
5%
MF-LF
0
1/16W
402
21
R5207
1/16W
MF-LF
0
5%
402
2
1
R5270
4.7K
402
5%
1/16W
MF-LF
2
1
R5271
4.7K
5%
402
MF-LF
1/16W
2
1
R5208
MF-LF
1/16W
2.2K
402
5%
2
1
R5209
2.2K
402
5%
1/16W
MF-LF
SYNC_MASTER=DAVE
SMBus Connections
SYNC_DATE=01/07/2010
=I2C_SODIMMB_SCL
=I2C_SODIMMB_SDA
SMBUS_PCH_CLK
MAKE_BASE=TRUE
=I2C_VREFDACS_SDA
=I2C_PCA9557D_SCL
=I2C_PCA9557D_SDA
=I2C_VREFDACS_SCL
=PP3V3_S0_SMBUS_SMC_B_S0
=I2C_SODIMMA_SDA
=SMBUS_XDP_SCL
=I2C_SODIMMA_SCL
=PP3V3_S0_SMBUS
MAKE_BASE=TRUE
SML_PCH_0_CLK
MAKE_BASE=TRUE
SML_PCH_0_DATA
MAKE_BASE=TRUE
SMBUS_SMC_0_S0_SCLSMB_0_S0_CLK
SMB_0_S0_DATA
=PP3V3_S0_SMBUS
MAKE_BASE=TRUE
SMBUS_SMC_0_S0_SDA
=SMBUS_CK505_SDA
SMB_BSA_CLK
=SMBUS_XDP_SDA
=SMBUS_CK505_SCL
=I2C_AUDIO_SCL
SMB_A_S3_CLK
SML_PCH_1_CLK
MAKE_BASE=TRUE
=PP3V3_S3_SMBUS_SMC_A_S3
SMBUS_SMC_A_S3_SCL
MAKE_BASE=TRUE
=SMB_SNS1_SDA
=SMB_MXM_THRM_SCL
=PP3V3_S0_SMBUS_SMC_0_S0
SMB_B_S0_DATA
SMB_B_S0_CLK
SMBUS_SMC_B_S0_SDA
MAKE_BASE=TRUE
SMBUS_SMC_B_S0_SCL
MAKE_BASE=TRUE
=SMB_ACDC_SCL
MAKE_BASE=TRUE
SML_PCH_1_DATA
=SMB_SNS2_SCL
=SMB_SNS2_SDA
=SMB_MINI_SDA
=SMB_MINI_SCL
=PP3V3_S0_SMBUS_SMC_BSA
SMB_BSA_DATA
=SMB_SNS1_SCL
=SMB_MXM_THRM_SDA
=SMB_ACDC_SDA
=I2C_AUDIO_SDA
=SMB_ALS_SCL
=SMB_ALS_SDA
=PP3V3_S0_SMBUS_SMC_MGMT
SMBUS_SMC_A_S3_SDA
MAKE_BASE=TRUE
MAKE_BASE=TRUE
SMBUS_SMC_BSA_SCL
SMBUS_SMC_BSA_SDA
MAKE_BASE=TRUE
=SMB_DP_TCON_SDA
=SMB_DP_TCON_SCL
=I2C_DP_DRV_SCL
=I2C_DP_DRV_SDA
MAKE_BASE=TRUE
SMBUS_SMC_MGMT_SDA
SMBUS_SMC_MGMT_SCL
MAKE_BASE=TRUE
SMB_MGMT_DATA
SMB_MGMT_CLK
=PP3V3_S0_SMBUS
MAKE_BASE=TRUE
SMBUS_PCH_DATA SMB_A_S3_DATA
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31
17 88
28
28
28
28
5
30
24
30
5 49
17 88
17 88
88
46
46
5 49
88
25
46
24
25
62
46
17 88
5
88
52
75
5
46
46
88
88
5
17 88
52
52
33
33
5
46
52
75
5
62
44 92
44 92
5
88
88
88 78
78
79
79 88
88
46
46
5 49
17 88 46
www.vinaﬁx.vn

OUT
IN
V+
REFIN+
IN- OUT
GND
GND
OUT
RS-
RS+
OUT
REFERENCE DESIGNATOR(S) BOM OPTION
TABLE_5_HEAD
QTYDESCRIPTIONPART#
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
BRANCH
REVISION
DRAWING NUMBER SIZE
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R
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
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21
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
87 54 21
MXM PWRSRC CURRENT & VOLTAGE SENSE
IMAX = 4A
IMAX = 6A
CPU 1.5V CURRENT SENSE
CPU VTT CURRENT SENSE
PLACE R CLOSE TO CPU
CPU 1.5V VOLTAGE SENSE
CPU CURRENT SENSE AMP & FILTER
IMAX = 2.79V
IMAX = 30A
IMAX = 0.9V
PCB: PLACE R5364, C5362 WITHIN 1" OF SMC (U4900)
PLACE C CLOSE TO SMC
CPU Voltage Sense / Filter
AMPLIFIED AND FILTERED ISNS TO SMC
353S2073
GAIN = 200V/V
46 88
2
1C5362
402
6.3V
0.22UF
10%
CERM-X5R
21
R5364
5.1K
402
5%
1/16W
MF-LF
21
C5360
0.01UF
CERM
20%
16V
402
21
R5363
1%
402
21K
1/16W
MF-LF
21
R5360
10K
402
MF-LF
1/16W
1%
65 89
5
2
4
1
3
U5360
CRITICAL
OPA348
SC70-5
2
1
R5361
1/16W
1%
MF-LF
402
10K
3
1
6
4
5
2
U5300
SC70
INA210
CPU_1V5_SENSE
2
1C5301
OMIT
0.22UF
20%
6.3V
X5R
402
43
21
R5300
OMIT
1206
MF-LF
1/4W
1%
0.002
2
1C5300
0.22UF
X5R
6.3V
20%
CPU_1V5_SENSE
402
21
R5301
CPU_1V5_SENSE
4.53K
1/16W
402
1%
MF-LF
21
R5302
1%
4.53K
402
MF-LF
1/16W
CPU_1V5_SENSE
2
1C5302
X5R
6.3V
20%
402
0.22UF
OMIT
43
21
R5330
1%
1W
MF
2512
0.015
CRITICAL
2
1C5320
20%
402
6.3V
0.22UF
X5R
21
R5320
MF-LF
1%
4.53K
1/16W
402
2
1C5321
20%
402
6.3V
0.22UF
X5R
21
R5321
MF-LF
1%
4.53K
1/16W
402
2
1
C5330
20%
0.1UF
CERM
10V
402
21
R5331
18.2K
1/16W
MF-LF
1%
402
2
1C5331
X5R
6.3V
20%
402
0.22UF
2
1
R5332
1%
1/16W
MF-LF
402
6.04K
2
1
R5333
MF-LF
5%
100
402
1/16W
21
C5332
0.33UF
10%
6.3V
402
CERM-X5R
A1
A2
B2
B1
U5330
MAX9938
UCSP-2
CRITICAL
46 88
21
R5359
4.53K
1/16W
402
MF-LF
1%
2
1
C5359
402
6.3V
20%
0.22UF
X5R
CPU/GPU POWER SENSE
SYNC_DATE=N/ASYNC_MASTER=K74_MASTER
132S0080 CAP,0.22UF,4022 CPU_1V5_SENSEC5301,C5302
1 RES,2 MILLIOHM,1206 R5300 CPU_1V5_SENSE104S0018
116S0004 RES,0 OHM,4022 PRODUCTIONC5301,C5302
RES,0 OHM,1206,20 MILLIOHM MAX1 R5300101S0414 PRODUCTION
=PPV_S0_MXM_PWRSRC
GND_SMC_AVSS
GND_SMC_AVSS
=PP3V3_S0_SMC
=PP5V_S0_ISENSE
SMC_CPU_ISENSE
GND_SMC_AVSS
SMC_CPU_VSENSE
VR_ISNS_CPU_P
SMC_CPU_1V5_ISENSE_R
SMC_CPU_VTT_ISENSE
CPUVTT_IMON
PPVTT_S0
SMC_CPU_VTT_VSENSE
GND_SMC_AVSS
GND_SMC_AVSS
CPU_VCC_PKG_SENSE_P
VR_CPU_IMON
SNS_PS_CPU_ISNS
VR_ISNS_CPU_N
SMC_CPU_1V5_ISENSE
GND_SMC_AVSS
SMC_CPU_1V5_VSENSE
GND_SMC_AVSS
PP1V5_CPU_MEM
=PPV_S0_MXM_PWR
SMC_GPU_VSENSE
SENSE_MXM_N_R
PPV_S0_MXM_PWRSRC
MAKE_BASE=TRUE
GND_SMC_AVSS
SMC_GPU_ISENSE
SENSE_MXM_N
SENSE_MXM_P
SENSE_CPU_1V5_N
SENSE_CPU_1V5_P
PP1V5_S0_FET
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74
46 47 50 88
46 47 50 88
5 47
5
46 47 50 88
88
88
46 68
5 89 46
46 47 50 88
46 47 50 88
12 65 89
88
88
46 88
46 47 50 88
46 88
46 47 50 88
5 89
5 46
89
46 47 50 88
46
88
88
88
88
5 73
www.vinaﬁx.vn

GND
V+
GND
V+
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
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DRAWING NUMBER SIZE
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Apple Inc.
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NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
87 54 21
Drive active = valid signal protocol
Drive asleep = HDD drives HDD_OOB_TEMP low
Must pull high to 2.5V for compatibility with all drives
HIGH: 2.0V TO 3.6V
SPARE
518S0698
Cannot pull low because some drives use this bit to
determine 1.5 Gbps vs. 3.0 Gbps SATA
Drive disconnected = pulled high
FROM DRIVE:
LOW: -0.3V TO 0.5V
HDD OUT OF BAND TEMPERATURE SENSING LEVEL SHIFTING
2
1
R5405
MF-LF
1/16W
5%
1K
402
2
1
R5402
402
62K
1/16W
5%
MF-LF
2
1
R5404
402
200K
1/16W
5%
MF-LF
21
L5400
FERR-220-OHM
04022
1
4
3
J5400
53780-8602
SILK_PART=HDD TEMP
M-RT-SM
CRITICAL
8
7
5
6
4
U5400
LM393
CRITICAL
SOI-HF
2
1
C5400
603
CERM
16V
20%
0.1UF
8
1
3
2
4
U5400
LM393
SOI-HF
CRITICAL
2
1
R5400
64.9K
1%
402
1/16W
MF-LF
2
1
R5401
1%
10K
1/16W
MF-LF
402
21
R5403
MF-LF
402
5%
1/16W
3.3K
HDD TEMP SENSE
SYNC_MASTER=K74_MASTER SYNC_DATE=N/A
=PP3V3_S0_SMC_LS=PP3V3_S0_SMC_LS
SMC_HDD_OOB_TEMP
=PP12V_S0_SENSE
HDD_OOB_1V60_REF
HDD_OOB_TEMP_RHDD_OOB_TEMP_FILT
=PP3V3_S0_SMC_LS
HDD_OOB_TEMP
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88 88 92
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88
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GND
V+
SCL
SDA
DXP1
DXP2
DXP3
DXN
ALERT*
THERM*/ADDRDP1
SMCLK
SMDATA
VDD
DN1
DP2/DN3
DN2/DP3
GND
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
BRANCH
REVISION
DRAWING NUMBER SIZE
D
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IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
21
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
87 54 21
REMOTE SKIN & ODD THERMAL SENSORS
AMBIENT SENSE CONNECTOR COMBINED WITH CPU FAN
518S0678
518S0678
518S0665
PLACE HSK SENSOR CONN. TOP SIDE NEAR MXM OR CPU
REMOTE HEATSINK SENSORS
PLACE SHORTS CLOSE TO U5550
518S0677
2
1
C5502
50V
CERM
10%
0.0022UF
402
2
1
C5500
402-1
X5R
10V
1UF
10%
21
L5553
FERR-220-OHM
0402
21
L5554
FERR-220-OHM
0402
21
L5522
FERR-220-OHM
0402
21
L5523
0402
FERR-220-OHM
21
L5512
0402
MXM
FERR-220-OHM
21
L5513
MXM
FERR-220-OHM
0402
2
1
4
3
J5510
SILK_PART=CPU HSK
M-ST-SM
53398-8602
CRITICAL
21
L5510
FERR-220-OHM
0402
21
L5511
FERR-220-OHM
0402
2
1
4
3
J5511
MXM
SILK_PART=MXM HSK
M-ST-SM
53398-8602
CRITICAL
21
L5563
FERR-220-OHM
0402
21
L5564
FERR-220-OHM
0402
2
1
4
3
J5560
53261-8602
CRITICAL
M-RT-SM
SILK_PART=SKIN TEMP
2
1
R5504
402
MF-LF
5%
1/16W
15K
2
1
C5501
402
10%
CERM
50V
0.0022UF
2
1
C5550
402-1
X5R
10%
1UF
10V
2
1
C5551
50V
0.001UF
20%
CERM
402
2
1
C5552
CERM
50V
20%
0.001UF
402
2
1
C5553
0.001UF
CERM
20%
402
50V
2
1
R5508
1/16W
402
MF-LF
5%
10K
8
6
7
5
3
2
1
4
U5550
TMP423
SOT23-8
CRITICAL
21
XW5553
SM
21
XW5552
SM
21
XW5551
SM
3
2
1
5
4
J5551
SILK_PART=ODD TEMP
CRITICAL
M-RT-SM
53780-8603
1
7
9
10
6
4
2
5
38
U5500
CRITICAL
MSOP
EMC1414-A
SYNC_DATE=11/06/2009SYNC_MASTER=NICK
REMOTE TEMP/POWER SENSORS
SNS_ODD_N
SNS_T2_DP3
SNS_T2_DP2
=SMB_SNS2_SCL
SNS_T2_DN
=PP3V3_S0_TSENS
SNS_T1_DN2_DP3SNS_T1_DN1
SNS_T1_DP1 SNS_T1_DP2_DN3
SNS_CPU_H_N
SNS_CPU_H_P
SNS_MXM_N
SNS_MXM_P
SNS_T2_DN1
SNS_T2_DP1
SNS_T2_DN2
SNS_T2_DN3
SNS_T2_DP2
SNS_AMB_N
SNS_AMB_P
SNS_SKIN_N
SNS_SKIN_P
SNS_T2_DN1
SNS_T2_DN3
SNS_T2_DN2
SNS_T2_DP1
=SMB_SNS2_SDA
SNS_T1_DN2_DP3
DIFFERENTIAL_PAIR=SNS_T2
DIFFERENTIAL_PAIR=SNS_T1
SNS_T1_DP1
SNS_T1_DP2_DN3
DIFFERENTIAL_PAIR=SNS_T2
=PP3V3_S0_TSENS
SNS1_ADDR
SNS1_ALERT_L
SNS_T1_DN1
DIFFERENTIAL_PAIR=SNS_T1
=SMB_SNS1_SCL
=SMB_SNS1_SDA
SNS_T2_DP3
SNS_ODD_P
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52 88 44 52 88
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88
52 88
52 88
52 88
52 88
52 88
54 88 92
54 88 92
88 92
88 92
52 88
52 88
52 88
52 88
49
44 52 88
52 88
44 52 88
5 52
52 88
49
49
52 88
88 92
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G S
D
G S
D
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
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PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
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PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
87 54 21
518S0730
518S0730
MOTOR CONTROL
GND
TACH
MOTOR CONTROL
GND
FAN 1
NOTE: ADDED TO PROTECT SMC
HD FAN
FAN 0
12V DC
12V DC
ODD FAN
TACH
C5605 IS POLY-TANT BECAUSE IT MUST BE PLACED ON THE BOTTOM
2
1
R5600
402
MF-LF
1/16W
10K
5%
2
1
R5601
MF-LF
5%
10K
1/16W
402
2
1
R5602
1206
MF-LF
1/4W
1.5K
5%
5
4
876321
Q5600
NTHS5443T1H
CRITICAL
1206A-03-HF
2
1
R5603
805
5%
1/8W
MF-LF
1.5K
3
1
D5600
SOT23
MMBD914XG
2
1C5601
0.47UF
805
16V
10%
X7R
21
R5605
3.9K
MF-LF
5%
1/8W
805
2
1
R5606
5%
402
10K
1/16W
MF-LF
5
4
876321
Q5603
NTHS5443T1H
CRITICAL
1206A-03-HF
2
1
R5607
805
MF-LF
5%
1.5K
1/8W
2
1C5603
16V
X7R
805
10%
0.47UF
21
R5609
3.9K
MF-LF
1/8W
5%
805
3
1
D5601
SOT23
MMBD914XG
2
1
R5610
1/4W
1206
5%
MF-LF
1.5K
2
1
R5611
10K
MF-LF
402
5%
1/16W
21
R5699
MF-LF
5%
47K
1/16W
402
21
R5698
47K
5%
1/16W
MF-LF
402
2
1
3
Q5602
2N7002
SOT23-HF1
2
1
3
Q5605
2N7002
SOT23-HF1
2
1
C5602
20%
CRITICAL
16V
ELEC
6.3X5.5-SM1-HF
100UF
4
3
2
1
6
5
J5601
CRITICAL
53780-8604
M-RT-SM
4
3
2
1
6
5
J5600
CRITICAL
M-RT-SM
53780-8604
2
1C5607
402
20%
CERM
16V
0.01UF
2
1C5606
20%
CERM
1206-1
16V
4.7UF
2
1C5609
16V
20%
0.01UF
402
CERM
2
1C5608
X5R
603
10%
16V
2.2UF
21
L5600
0402
CRITICAL
FERR-220-OHM
21
L5601
CRITICAL
0402
FERR-220-OHM
21
L5610
220-OHM-1.4A
CRITICAL
0603
21
L5620
220-OHM-1.4A
0603
CRITICAL
21
L5630
CRITICAL
220-OHM-1.4A
0603
21
L5640
220-OHM-1.4A
0603
CRITICAL
2
1
R5620
MF-LF
1/10W
5%
0
603
PLACEMENT_NOTE=PLACE R5620 CLOSE TO J5600 Pin3
2
1
R5630
0
603
MF-LF
1/10W
5%
PLACEMENT_NOTE=PLACE R5630 CLOSE TO J5601 Pin3
2
1C5628
16V
10%
2.2UF
603
X5R
2
1
C5605
TANT
16V
20%
100UF
D-HF
CRITICAL
HD AND OD FAN
SYNC_MASTER=K74_MASTER SYNC_DATE=N/A
SMC_FAN_0_CTL
MIN_NECK_WIDTH=0.25MM
MIN_LINE_WIDTH=0.5MM
FAN_0_PWR
FAN_TACH1_L
FAN_1_PWR
MIN_LINE_WIDTH=0.5MM
MIN_NECK_WIDTH=0.25MM
FAN_TACH1
FAN_TACH0
=PP12V_S0_FAN
F0_VOLTAGE8R5
FAN_1_PWR_L
MIN_LINE_WIDTH=0.5MM
MIN_NECK_WIDTH=0.25MM
MIN_NECK_WIDTH=0.25MM
MIN_LINE_WIDTH=0.5MM
FAN_0_PWR_L
=PP12V_S0_FAN
F0_GATESLOWDN
=PP3V3_S0_FAN
=PP3V3_S0_FAN
=PP3V3_S0_FAN
F1_VOLTAGE8R5
SMC_FAN_0_TACH
SMC_FAN_1_TACH
=PP3V3_S0_FAN
F1_GATESLOWDN
SMC_FAN_1_CTL
FAN_0_GND
MIN_LINE_WIDTH=0.5MM
MIN_NECK_WIDTH=0.25MM
FAN_1_GND
MIN_LINE_WIDTH=0.5MM
MIN_NECK_WIDTH=0.25MM
VOLTAGE=12V
MIN_LINE_WIDTH=0.5MM
PP12V_S0_FAN0_L
MIN_NECK_WIDTH=0.25MM
PP12V_S0_FAN1_L
MIN_LINE_WIDTH=0.5MM
VOLTAGE=12V
MIN_NECK_WIDTH=0.25MM
FAN_TACH0_L
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92
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92
89
92
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G S
D
IN
IN
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
BRANCH
REVISION
DRAWING NUMBER SIZE
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21
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
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87 54 21
12V DC
MOTOR CONTROL
TACH
GND
CPU FAN
FAN 3
FAN 2 UNUSED
2
1
3
Q5702
SOT23-HF1
2N7002
2
1
C5702
20%
16V
ELEC
CRITICAL
6.3X5.5-SM1-HF
100UF
2
1C5708
1206-1
CERM
16V
20%
4.7UF
2
1C5709
402
CERM
0.01UF
16V
20%
21
L5701
0402
FERR-220-OHM
CRITICAL
21
L5710
0603
220-OHM-1.4A
CRITICAL
21
L5720
CRITICAL
220-OHM-1.4A
0603
2
1
R5720
PLACEMENT_NOTE=PLACE R5720 CLOSE TO J5700 Pin3
603
1/10W
5%
0
MF-LF
52 88 92
52 88 92 6
5
4
3
2
1
8
7
J5700
CRITICAL
M-RT-SM
53780-8606
2
1
R5700
1/16W
MF-LF
402
5%
10K
5
4
876321
Q5700
1206A-03-HF
CRITICAL
NTHS5443T1H
3
1
D5700
SOT23
MMBD914XG
2
1
R5701
MF-LF
1.5K
5%
805
1/8W
2
1C5701
805
X7R
16V
10%
0.47UF
21
R5703
1/8W
5%
3.9K
MF-LF
805
2
1
R5704
5%
1/4W
1.5K
1206
MF-LF
2
1
R5705
MF-LF
10K
402
5%
1/16W
21
R5797
47K
5%
1/16W
MF-LF
402
CPU FAN & AMBIENT SENSE
SYNC_MASTER=K74_MASTER SYNC_DATE=N/A
SMC_FAN_3_TACH
MIN_NECK_WIDTH=0.25MM
FAN_2_PWR_L
MIN_LINE_WIDTH=0.5MM
SNS_AMB_N
SNS_AMB_P
F2_VOLTAGE8R5
FAN_2_GND
MIN_LINE_WIDTH=0.5MM
MIN_NECK_WIDTH=0.25MM
FAN_TACH2
SMC_FAN_3_CTL
FAN_2_PWR
MIN_NECK_WIDTH=0.25MM
MIN_LINE_WIDTH=0.5MM
=PP12V_S0_FAN
F2_GATESLOWDN
VOLTAGE=12V
MIN_NECK_WIDTH=0.25MM
MIN_LINE_WIDTH=0.5MM
PP12V_S0_FAN2_L
=PP3V3_S0_FAN
=PP3V3_S0_FAN
FAN_TACH2_L
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OUT
IN
IN IN
WP*
SI
HOLD*
VSS
SCK
CE*
VDD
SO
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
BRANCH
REVISION
DRAWING NUMBER SIZE
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SHEET
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PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
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87 54 21
2
1
C6100
10V
0.1UF
CERM
20%
4022
1
R6101
1/16W
5%
3.3K
MF-LF
402
2
1
R6100
1/16W
5%
MF-LF
3.3K
402
17 48 85
48 85
17 48 85 17 48 85
21
R6105
402
MF-LF
5%
1/16W
0
21
R6152
MF-LF
5%
1/16W
0
402
PLACEMENT_NOTE=PLACE CLOSE TO U6100
21
R6150
402
0
1/16W
5%
MF-LF
PLACEMENT_NOTE=PLACE CLOSE TO U6100
3
4
8
2
56
7
1
U6100
SOIC
CRITICAL
OMIT
32MBIT
SST25VF032B
SYNC_DATE=11/30/2009
SPI ROM
SYNC_MASTER=K23F
SPI_CLK_R SPI_MOSI_R
SPI_MISO
SPI_CLK
SPI_MISO_R
SPI_WP_L
SPI_MLB_CS_L
SPI_MOSI
=PP3V3_S5_ROM
SPI_HOLD_L
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85
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IN
IN
IN
IN
OUT
IN
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
OUT
IN
IN
OUT
NR/FB
NC
IN
EN
GND
OUT
IN
VL_HD
SENSE_A
GPIO1/DMIC_SDA2
GPIO0/DMIC_SDA1
VHP_FILT+
GPIO2
RESET*
LINEOUT_L1-
VBIAS_DAC
FLYP
VA_REFVD
GPIO3
VHP_FILT-
LINEOUT_R1-
LINEOUT_R1+
LINEOUT_R2-
SPDIF_OUT
LINEIN_C-
FLYC
FLYN
SPDIF_IN
LINEOUT_L1+
THRM_PAD
VA_HP
HPOUT_R
HPREF
VCOM
AGND
VA
LINEIN_R+
LINEIN_L+
MICIN_L+
MICIN_L-
MICBIAS
SYNC
DGND
DMIC_SCL
HPOUT_L
SDI
SDO
VL_IF
BITCLK
MICIN_R-
MICIN_R+
VREF+_ADC
LINEOUT_L2+
LINEOUT_L2-
LINEOUT_R2+
/SPDIF_OUT2
OUT
OUT
OUT
OUT
OUT
OUT
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
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REVISION
DRAWING NUMBER SIZE
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SHEET
PAGE TITLE
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21
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
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87 54 21
4.5V POWER SUPPLY FOR CODEC
DIFF FSINPUT= 2.45VRMS
SE FSINPUT= 1.22VRMS
APPLE P/N 353S2456
DAC1 FSOUTPUT= 1.34VRMS
DAC2/3 FSOUTPUTSE= 1.34VRMS
DAC2/3 FSOUTPUTDIFF= 2.67VRMS
HP OUT ZOBEL NETWORK
NC
NC
VD MUST BE LESS THAN OR EQUAL TO VL_HD
NC
APPLE P/N 353S2592
AUDIO CODEC
NC
NC
PLACE TP FOR ALL HDA SIGNALS NEAR CODEC
NC
NC
21
XW6201
SM
2
1C6206
6.3V
2.2UF
402-LF
20%
CERM
2
1C6208
2.2UF
402-LF
20%
6.3V
CERM
2
1C6203
4.7UF
4V
X5R
402
20%
17 85
17 85
17 85
17 85
17 85
61
58
56 60
56 60
59 86
58 86
59 86
58 86
61
57
57
62
62
61
61
2
1C6213
6.3V
20%
10UF
603
X5R
57
21
L6201
FERR-220-OHM
0402
21
R6201
1/16W
MF-LF
402
1%
2.21K
2
1C6201
402-1
X5R
1UF
10%
10V
2
1C6264
0.47UF
10%
X5R
402
10V
2
1C6258
402
10V
X5R
10%
0.47UF
2
1C6265
402
X5R
0.47UF
10%
10V
2
1
R6255
402
MF-LF
2.67K
1/16W
1%
2
1
R6263
NOSTUFF
MF-LF
0
5%
402
1/16W
2
1
R6267
100K
5%
402
1/16W
MF-LF
NOSTUFF
21
R6254
402
5%
MF-LF
22
1/16W
2
1C6261
X5R
10%
10V
0.47UF
402
2
1
C6263
CASE-B2-SM
10UF
CRITICAL
20%
POLY-TANT
16V
2
1
C6262
CASE-B2-SM
16V
20%
10UF
POLY-TANT
2
1
C6260
16V
10UF
20%
CASE-B2-SM
POLY-TANT
5 56
5 56 58 59 60 61 62
56 89
56 89
60
56 89
5 56 58 59 60 61 62
5 56
2
1C6259
1UF
10%
10V
X5R
402-1
1
3
6
2
4
VR6201
CRITICAL
SON
TPS71745
2
1C6266
16V
X7R-CERM
402
10%
0.1UF
21
R6257
402
22
5%
MF-LF
1/16W
2
1
R6296
1/16W
MF-LF
5%
39
402
2
1
R6297
402
MF-LF
1/16W
5%
39
2
1C6298
0.1UF
X7R-CERM
10%
16V
402
2
1C6297
X7R-CERM
0.1UF
16V
402
10%
60 85
77
2
1
R6295
100K
1%
402
MF-LF
1/16W
2
1C6204
X5R
6.3V
20%
10UF
603
27
1
3
44
41
9
28
29
24 46 25
49
10
48
47
13
5
8
11
19
20
18
17
16
32
33
36
37
31
30
35
34
23
21
22
39
40
38
15
14
12
2
45
42
43
4
7
6
26
U6201
CRITICAL
QFN
CS4206ACNZC
2
1C6205
10UF
X5R
6.3V
20%
603
2
1C6202
10%
1UF
10V
X5R
402-1
2
1C6207
402-1
1UF
X5R
10%
10V
59 86
58 86
59 86
58 86
56 60
56 60
2
1
C6211
1UF
10%
TANT
20V
CRITICAL
CASE-P3-HF
SYNC_MASTER=BREECE
AUDIO: CODEC/REGULATOR
SYNC_DATE=02/02/2010
AUD_SPDIF_OUT
PP4V5_AUDIO_ANALOG
AUD_MIC_INP_L
AUD_MIC_INN_R
CS4206_VREF_ADC
AUD_SPDIF_IN_CODEC
AUD_SENSE_A
TP_AUD_GPIO0
TP_AUD_GPIO_1
AUD_HP_PORT_REFMIN_NECK_WIDTH=0.1MMMIN_LINE_WIDTH=0.2MM
GND_AUDIO_CODEC
AUD_LO2_N_L
AUD_LO2_P_R
AUD_LO2_N_R
AUD_LO1_N_L
AUD_LO1_P_R
AUD_LO1_P_L
AUD_LO1_N_R
AUD_LO2_P_L
AUD_LI_P_L
AUD_MIC_INP_R
TP_AUD_GPIO_2
AUD_GPIO_3
CS4206_FP
TP_AUD_DMIC_CLK
GND_AUDIO_HP_AMP_L
CS4206_VCOM
CS4206_FLYP
HDA_SYNC
AUD_SDI_R
GND_AUDIO_HP_AMP_L
HDA_SDIN0
VBIAS_DAC
CS4206_FLYN
CS4206_FLYC
=PP1V5_S0_AUD_DIG
=PP5V_S0_AUDIO
HDA_BIT_CLK
HDA_SDOUT
HDA_RST_L
AUD_MIC_INN_L
AUD_LI_P_R
AUD_LI_COM
MIN_LINE_WIDTH=0.3MM MIN_NECK_WIDTH=0.2MM AUD_HP_L
GND_AUDIO_CODEC
4V5_REG_EN
PP4V5_AUDIO_ANALOG
VOLTAGE=4.5V
MIN_NECK_WIDTH=0.10MM
MIN_LINE_WIDTH=0.20MM
4V5_NR
VOLTAGE=4.5V
MIN_NECK_WIDTH=0.10MM
MIN_LINE_WIDTH=0.20MM
4V5_REG_IN
GND_AUDIO_HP_AMP_L
VOLTAGE=0V
=PP5V_S0_AUDIO
=PP3V3_S0_AUDIO
AUD_HP_L
MIN_LINE_WIDTH=0.3MM
MIN_NECK_WIDTH=0.2MM
MIN_LINE_WIDTH=0.30MM
MIN_NECK_WIDTH=0.20MM
AUD_Z_L
GND_AUDIO_HP_AMP_L
AUD_HP_R
MIN_LINE_WIDTH=0.3MM
MIN_NECK_WIDTH=0.2MM
MIN_NECK_WIDTH=0.20MM
MIN_LINE_WIDTH=0.30MM
AUD_Z_R
AUD_CODEC_MICBIAS
AUD_SPDIF_CHIP
MIN_NECK_WIDTH=0.2MMMIN_LINE_WIDTH=0.3MM AUD_HP_R
CS4206_FN
VOLTAGE=4.5V
MIN_NECK_WIDTH=0.10MM
MIN_LINE_WIDTH=0.20MM
PP4V5_AUDIO_ANALOG
=PP3V3_S0_AUDIO
MIN_LINE_WIDTH=0.5MM
MIN_NECK_WIDTH=0.2MM
VOLTAGE=0V
GND_AUDIO_CODEC
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85
56 60 61
5
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89
56 60 61
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85
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PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
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C
345678
D
B
87 54 21
CODEC Nom SE RIN = 20K OHMS
FC = 3.62 HZ
VIN = 2VRMS, CODEC VIN = 1.14 VRMS
NET RIN = 18K OHMS
56
56
56
60
60
47 56 61 62
60
21
R6300
1/16W
1%
402
MF-LF
7.87K
2
1
R6301
MF-LF
1%
1/16W
21.5K
402
2
1C6301
402
CERM
NOSTUFF
50V
10%
820PF
2
1
R6303
10
402
MF-LF
1/16W
1%
21
R6306
MF-LF
1/16W
402
7.87K
1%
2
1C6304
CERM
50V
10%
820PF
NOSTUFF
4022
1
R6305
402
21.5K
1%
1/16W
MF-LF
21
C6300
CRITICAL
10%
2.2UF
805
X5R-CERM
25V
21
C6302
CRITICAL
25V
805
10%
2.2UF
X5R-CERM
21
C6303
CRITICAL
10%
25V
X5R-CERM
805
2.2UF
AUDIO: FILTER/BUFFER
SYNC_DATE=02/02/2010SYNC_MASTER=BREECE
AUD_LI_L
MIN_NECK_WIDTH=0.2MM
MIN_LINE_WIDTH=0.3MM
AUD_LI_RF
MIN_LINE_WIDTH=.3MM
MIN_NECK_WIDTH=.2MM
MIN_LINE_WIDTH=0.3MM
MIN_NECK_WIDTH=0.2MM
AUD_LI_GND
GND_AUDIO_CODEC
MIN_NECK_WIDTH=.2MM
AUD_LI_COM
MIN_LINE_WIDTH=.3MM
MIN_NECK_WIDTH=.2MM
MIN_LINE_WIDTH=.3MM
AUD_LI_P_L
AUD_LI_R
MIN_NECK_WIDTH=0.2MM
MIN_LINE_WIDTH=0.3MM
MIN_LINE_WIDTH=.3MM
MIN_NECK_WIDTH=.2MM
AUD_LI_P_R
AUD_LI_LF
MIN_NECK_WIDTH=.2MM
MIN_LINE_WIDTH=.3MM
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IN
G
S
D
G
S
D
IN
IN
IN
OUT
OUT
OUT
OUT
OUT
OUT
NC2
NC3
NC8
NC6
NC7
NC4
NC5
NC1
NC0
SYNC
VCLAMPR
LOUTN2
LOUTN1
LOUTP2
LOUTP1
BSLP
BSRN
ROUTN2
ROUTN1
BSRP
ROSC
VBYP
VREG
GAIN1
GAIN0
MSTR/SLV*
SD*
FAULT
LINP
BSLN
ROUTP2
ROUTP1
LINN
RINN
RINP
VCLAMPL
MUTE*
PVCCL PVCCR
AVCC
THM
PADPGNDRPGNDLAGND
IN
IN
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
BRANCH
REVISION
DRAWING NUMBER SIZE
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21
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
87 54 21
RIGHT CH. SPEAKER AMP
APPLE P/N 353S2768
U6400 IS CLOCK MASTER
R6402=HIGH=MASTER
SPEAKER AMP GAIN = 9DB
FC_HPF = 2.5HZ TO 3.8HZ
SPEAKER AMP RIN = 89.6K TO 134K W/ 9DB
21
L6404
0603
FERR-220-OHM-2.5A
CRITICAL
2
1
R6411
5%
402
1/16W
MF-LF
0
21
R6401
5%
402
MF-LF
1/16W
0
5 59
2
1
C6406
20%
D-HF
TANT
16V
100UF
CRITICAL
2
1
C6408
16V
TANT
D-HF
20%
100UF
CRITICAL
21
R6412
MF-LF
402
0
1/16W
5%
NOSTUFF
21
C6407
10%
25V
X5R
0.068UF
0402
21
C6409
10%
25V
X5R
0402
0.068UF
21
C6411
10%
25V
X5R
0402
0.068UF
21
C6413
0.068UF
25V
X5R
0402
10%
21
C6416
0.22UF
20%
25V
603
X5R
21
C6417
20%
X5R
0.22UF
25V
603
21
C6410
0.22UF
20%
603
X5R
25V
21
C6415
25V
603
20%
X5R
0.22UF
2
1
R6408
100K
5%
402
MF-LF
1/16W
2
1C6401
10%
X5R
25V
0.1UF
402
2
1C6400
25V
10%
X5R
805
10UF
21
L6400
FERR-1000-OHM
0402
2
1C6404
25V
10%
X5R
0.1UF
402
2
1
R6406
NOSTUFF
1/16W
MF-LF
100K
402
5%
2
1
R6404
NOSTUFF
1/16W
100K
MF-LF
402
5%
2
1C6414
NOSTUFF
100PF
5%
402
CERM
50V
2
1
R6402
1/16W
100K
5%
402
MF-LF
2
1C6418
0.01UF
10%
25V
402
X7R
2
1
R6407
402
5%
1/16W
MF-LF
100K
2
1
R6405
402
MF-LF
1/16W
5%
100K
21
L6401
FERR-1000-OHM
0402
21
L6402
0402
FERR-1000-OHM
21
L6403
FERR-1000-OHM
0402
2
1C6402
10%
402
X5R
0.1UF
25V
2
1C6421
10%
402
CERM
0.001UF
50V
2
1
R6400
1/16W
MF-LF
5%
100K
402
2
1C6403
10%
X5R
1UF
25V
603-1
2
1C6423
402
50V
CERM
0.001UF
10%
21
L6405
FERR-220-OHM-2.5A
CRITICAL
0603
21
L6406
CRITICAL
0603
FERR-220-OHM-2.5A
21
L6407
FERR-220-OHM-2.5A
0603
CRITICAL
21
R6410
1/16W
270K
NOSTUFF
5%
402
MF-LF
1
2
6
Q6400
NOSTUFF
SOT-563-HF
NTZD3154NT1H
4
5
3
Q6400
SOT-563-HF
NTZD3154NT1H
NOSTUFF
2
1C6420
402
10%
CERM
0.001UF
50V
2
1C6405
X5R
25V
10%
603-1
1UF
2
1C6424
X5R
10%
25V
1UF
603-1
2
1C6425
603-1
X5R
25V
1UF
10%
56 86
56 86
56
60 85
92
60 85
92
60 85
92
2
1C6422
402
CERM
10%
0.001UF
50V
60 85
92
59
58 59 58 59
2
1C6419
402
1UF
X5R
10%
10V
15
31
30
16
49
11
44
42
41
40
39
14
3
2
35342726
33322928
47
37
36
25
24
13
12
7
1
45
10
20
19
22
21
5
6
9
8
46
43
38
18
23
48
17
4
U6400
QFN
TPA3103D2
CRITICAL
56 86
56 86
SYNC_MASTER=BREECE
AUDIO: SPEAKER AMP_1
SYNC_DATE=02/02/2010
AUDAMPFAULT
=PP3V3_S0_AUDIO
AUDAMPG1
AUDAMPG2
AUDAMPVREG
AUDAMPVBYP
AUDAMPMUTE
AUDAMPMSTR
AUDAMPINBLP
AUDAMPINBLN
AUDAMPINBRN
AUDAMPINBRP AUDAMPINRP
AUDAMPINLN
AUDAMPINLP
AUD_LO2_N_R
AUDAMPINRNAUD_LO1_N_R
AUD_LO1_P_R
=PP12V_S0_AUDIO_SPKRAMP
MIN_LINE_WIDTH=0.5MM
MIN_NECK_WIDTH=0.2MM
AUDAMPOUTBLN
AUD_SPKR_OUTLO2R_POUT
MIN_LINE_WIDTH=0.5MM
MIN_NECK_WIDTH=0.2MM
MIN_LINE_WIDTH=0.5MM
AUD_SPKR_OUTLO2R_NOUT
MIN_NECK_WIDTH=0.2MM
AUD_LO2_P_R
AUDAMPCLAMPL
AUDSPKRAMPSYNC
AUDBAMPBSLN
AUDAMPOUTBRP
MIN_NECK_WIDTH=0.2MM
MIN_LINE_WIDTH=0.5MM
AUDBAMPBSRP
AUDAMPCLAMPR
AUD_SPKR_OUTLO1R_POUT
MIN_NECK_WIDTH=0.2MM
MIN_LINE_WIDTH=0.5MM
=PP3V3_S0_AUDIO
MIN_LINE_WIDTH=0.5MM
MIN_NECK_WIDTH=0.2MM
AUD_SPKR_OUTLO1R_NOUT
AUD_GPIO_3
=PP3V3_S0_AUDIO
AUD_SPKRAMP_MUTE_L
AUD_SPKRAMP_MUTE_L
AUDAMPROSC
MIN_NECK_WIDTH=0.2MM
AUDAMPOUTBRN
MIN_LINE_WIDTH=0.5MM
AUDBAMPBSRN
AUDBAMPBSLP
MIN_NECK_WIDTH=0.2MM
MIN_LINE_WIDTH=0.5MM
AUDAMPOUTBLP
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G
S
D
G
S
D
IN
IN
IN
IN
OUT
OUT
OUT
OUT
NC2
NC3
NC8
NC6
NC7
NC4
NC5
NC1
NC0
SYNC
VCLAMPR
LOUTN2
LOUTN1
LOUTP2
LOUTP1
BSLP
BSRN
ROUTN2
ROUTN1
BSRP
ROSC
VBYP
VREG
GAIN1
GAIN0
MSTR/SLV*
SD*
FAULT
LINP
BSLN
ROUTP2
ROUTP1
LINN
RINN
RINP
VCLAMPL
MUTE*
PVCCL PVCCR
AVCC
THM
PADPGNDRPGNDLAGND
IN
IN
IN
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
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21
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
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345678
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87 54 21
U6500 IS SLAVE
R6503 = LOW = SLAVE
SPEAKER AMP GAIN = 9DB
SPEAKER AMP RIN = 89.6K TO 134K W/ 9DB
FC_HPF = 2.5HZ TO 3.8HZ
APPLE P/N 353S2768
LEFT CH. SPEAKER AMP
2
1
C6506
CRITICAL
16V
TANT
D-HF
100UF
20%
2
1
C6508
CRITICAL
16V
TANT
D-HF
100UF
20%
21
R6512
5%
MF-LF
0
1/16W
402
NOSTUFF
21
C6507
25V
X5R
0402
10%
0.068UF
21
C6509
0.068UF
10%
0402
X5R
25V
21
C6511
10%
0.068UF
0402
X5R
25V
21
C6513
10%
0.068UF
0402
X5R
25V
21
C6516
25V
20%
0.22UF
603
X5R
21
C6517
0.22UF
603
X5R
25V
20%
2
1C6523
402
10%
50V
CERM
0.001UF
2
1C6522
10%
50V
0.001UF
CERM
402
21
C6510
603
25V
X5R
0.22UF
20%
21
C6515
20%
603
X5R
0.22UF
25V
2
1
R6508
1/16W
100K
5%
MF-LF
402
2
1C6501
402
10%
X5R
25V
0.1UF
2
1C6500
X5R
10UF
10%
25V
805
2
1C6504
0.1UF
X5R
402
10%
25V
2
1C6518
10%
X7R
25V
402
0.01UF
2
1
R6506
NOSTUFF
100K
1/16W
402
5%
MF-LF
2
1
R6504
NOSTUFF
100K
402
MF-LF
5%
1/16W
2
1
R6507
5%
1/16W
100K
MF-LF
402
2
1
R6505
5%
402
100K
1/16W
MF-LF
2
1
R6503
MF-LF
5%
402
1/16W
100K
21
L6500
0402
FERR-1000-OHM
21
L6501
0402
FERR-1000-OHM
21
L6502
FERR-1000-OHM
0402
21
L6503
FERR-1000-OHM
0402
2
1C6502
0.1UF
10%
X5R
25V
402
2
1C6521
0.001UF
402
10%
50V
CERM
2
1C6503
603-1
X5R
10%
1UF
25V
21
L6505
0603
CRITICAL
FERR-220-OHM-2.5A
21
L6506
0603
CRITICAL
FERR-220-OHM-2.5A
21
L6507
0603
CRITICAL
FERR-220-OHM-2.5A
2
1C6520
402
0.001UF
10%
50V
CERM
21
R6510
270K
MF-LF
5%
402
NOSTUFF
1/16W
1
2
6
Q6500
NOSTUFF
SOT-563-HF
NTZD3154NT1H
4
5
3
Q6500
NOSTUFF
SOT-563-HF
NTZD3154NT1H
2
1C6505
603-1
1UF
10%
X5R
25V
2
1C6525
X5R
25V
1UF
10%
603-1
2
1C6524
1UF
25V
10%
603-1
X5R
58
58
56 86
56 86
60 85 92
60 85 92
60 85 92
60 85 92
2
1C6519
10%
1UF
X5R
10V
402
15
31
30
16
49
11
44
42
41
40
39
14
3
2
35342726
33322928
47
37
36
25
24
13
12
7
1
45
10
20
19
22
21
5
6
9
8
46
43
38
18
23
48
17
4
U6500
TPA3103D2
QFN
CRITICAL
56 86
21
L6504
FERR-220-OHM-2.5A
0603
CRITICAL
56 86
21
R6511
5%
MF-LF
0
1/16W
402
5 58
AUDIO: SPEAKER AMP
SYNC_MASTER=BREECE SYNC_DATE=02/02/2010
AUD_SPKRAMP_MUTE_L
AUD_AMPMUTE
AUDAMPINCLP
AUDAMPINCRP
AUDAMPINCLN
AUDAMPINCRN
AUD_LO1_N_L
AUD_AMPFAULT
AUD_AMPSLAVE
AUD_LO2_P_L
AUDSPKRAMPSYNC
MIN_LINE_WIDTH=0.5MM
MIN_NECK_WIDTH=0.2MM
AUDAMPOUTCLN
AUDAMPVCLAMPR
AUD_AMPROSC
=PP3V3_S0_AUDIO
MIN_NECK_WIDTH=0.2MM
MIN_LINE_WIDTH=0.5MM
AUD_SPKR_OUTLO2L_POUT
MIN_LINE_WIDTH=0.5MM
MIN_NECK_WIDTH=0.2MM
AUD_SPKR_OUTLO1L_NOUT
MIN_LINE_WIDTH=0.5MM
MIN_NECK_WIDTH=0.2MM
AUD_SPKR_OUTLO1L_POUT
AUDAMPOUTCLP
MIN_NECK_WIDTH=0.2MM
MIN_LINE_WIDTH=0.5MM
MIN_LINE_WIDTH=0.5MM
AUD_SPKR_OUTLO2L_NOUT
MIN_NECK_WIDTH=0.2MM
=PP3V3_S0_AUDIO
=PP3V3_S0_AUDIO
AUDAMPOUTCRN
MIN_NECK_WIDTH=0.2MM
MIN_LINE_WIDTH=0.5MM
AUDAMPVCLAMPL
AUDCAMPBSLP
AUDCAMPBSRN
AUDAMPOUTCRP
MIN_NECK_WIDTH=0.2MM
MIN_LINE_WIDTH=0.5MM
AUDCAMPBSLN
AUDCAMPBSRP
AUD_LO1_P_L
AUD_AMPINLN
AUD_LO2_N_L
AUD_AMPINLP
AUD_AMPVBYP
AUD_AMPG2
AUD_AMPVREG
AUD_AMPG1
AUD_AMPINRN
=PP12V_S0_AUDIO_SPKRAMP
AUD_AMPINRP
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IN
OUT
IN
IN
IN
IN
IN
IN
IN
IN
IN
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
IN
IN
OUT
IN
IN
IN
IN
IN
IN
OUT
OUT
OUT
OUT
OUT
OUT
OUT
IN
IN
OUT
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
BRANCH
REVISION
DRAWING NUMBER SIZE
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R
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
21
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
87 54 21
AUD_HP_GND_JACK
AUD_LI_GND_JACK
TWEETER (FR)
WOOFER (BL)
SPEAKER CABLE CONNECTORS
APPLE P/N 518S0748
APPLE P/N 518S0656
TWEETER (FL)
WOOFER (BR)
PROPERTIES FOR ALL SPKR NETS
APPLE P/N 518S0677
NC
PROPERTIES FOR ALL SPKR NETS
INTERNAL MIC CON
APPLE P/N 518S0791
REMOTE I/O CONNECTOR
PP3V3_AUDIO_SPDIF_JACK
21
L6602
0402
FERR-1000-OHM
21
L6600
FERR-1000-OHM
0402
21
L6603
0402
FERR-1000-OHM
21
L6601
0402
FERR-1000-OHM
21
L6604
FERR-1000-OHM
0402
2
1
DZ6600
402
6.8V-100PF
CRITICAL
2
1
DZ6601
CRITICAL
402
6.8V-100PF
2
1
DZ6613
6.8V-100PF
CRITICAL
402
2
1
DZ6611
6.8V-100PF
402
CRITICAL
2
1
DZ6605
CRITICAL
402
6.8V-100PF
2
1
DZ6609
6.8V-100PF
CRITICAL
402
21
L6614
FERR-1000-OHM
0402
2
1
DZ6604
402
CRITICAL
6.8V-100PF
2
1
DZ6607
CRITICAL
402
6.8V-100PF
56 85
61
5 56 58 59
61 62
58 85 92
58 85 92
58 85 92
58 85 92
59 85 92
59 85 92
59 85 92
59 85 92
61
61
2
1
R6600
5%
MF-LF
1/16W
402
0
2
1C6601
10V
X5R
10%
0.47UF
402
21
L6607
0402
FERR-1000-OHM
57
21
L6608
FERR-1000-OHM
0402
57
21
L6609
0402
FERR-1000-OHM
62
62
56 61
61
2
1
DZ6614
CRITICAL
402
6.8V-100PF
2
1
DZ6612
CRITICAL
402
6.8V-100PF
2
1
DZ6610
6.8V-100PF
402
CRITICAL
2
1
DZ6608
CRITICAL
6.8V-100PF
402
2
1
DZ6615
CRITICAL
402
6.8V-100PF
2
1
DZ6603
402
6.8V-100PF
CRITICAL
2
1C6600
10V
X5R
402-1
1UF
10%
21
L6615
FERR-1000-OHM
0402
3
2
1
5
4
J6601
53780-8603
CRITICAL
M-RT-SM
21
L6605
FERR-1000-OHM
0402
21
R6601
5%
1/16W
402
22
MF-LF
77 85
61
21
L6606
FERR-1000-OHM
0402
21
L6612
0402
FERR-1000-OHM
21
L6613
0402
FERR-1000-OHM
56
61
56
56
57
21
XW6617
SM
21
R6617
MF-LF
603
5%
0
1/10W
21
L6616
220-OHM-0.7A-0.28-OHM
0402
21
L6618
220-OHM-0.7A-0.28-OHM
0402
5
4
3
2
1
J6603
M-RT-SM
78048-0573
CRITICAL
4
3
2
1
J6602
78048-0473
CRITICAL
M-RT-SM
9
87
65
43
22
21
20
2
19
1817
1615
1413
1211
10
1
J6600
CRITICAL
F-ST-SM
50238-02071
60 92
60 92
60 92
60 92
60
92
60 92
60
92
60 92
60 92
60 92
60 92
60 92
60 92
60 92
60 92
60 92
21
L6610
600OHM-0.2A
0402
CRITICAL
2
1
DZ6606
ESDALC5-1BM2
CRITICAL
SOD882
SYNC_MASTER=BREECE SYNC_DATE=02/02/2010
Audio: MLB to I/O Conn.
AUD_SPDIF_OUT
AUD_HP_TIP_DET
MIN_LINE_WIDTH=0.2MM
MIN_NECK_WIDTH=0.1MM
MIN_LINE_WIDTH=0.2MM
MIN_NECK_WIDTH=0.1MM
AUD_IP_PERPH_DET
MIN_LINE_WIDTH=0.2MM
MIN_NECK_WIDTH=0.1MM
AUD_HP_TYPE
AUD_HP_R
VOLTAGE=0V
MIN_LINE_WIDTH=0.3MM
MIN_NECK_WIDTH=0.2MM
AUD_HP_L
MIN_NECK_WIDTH=0.2MM
MIN_LINE_WIDTH=0.3MM
MIN_NECK_WIDTH=0.1MM
MIN_LINE_WIDTH=0.2MM
AUD_HP_PORT_REF
HS_MIC_HI
MIN_NECK_WIDTH=0.1MM
MIN_LINE_WIDTH=0.15MM
AUD_LI_L
MIN_LINE_WIDTH=0.3MM
MIN_NECK_WIDTH=0.2MM
=PP3V3_S0_AUDIO
AUD_SPDIF_IN
AUD_LI_DET_JACK
AUD_SPDIFIN_JACK
AUD_LI_R_JACK
AUD_LI_L_JACK
HS_MIC_HI_JACK
AUD_HP_R_JACK
AUD_HP_L_JACK
AUD_IP_PERPH_JACK
PP3V3_AUDIO_SPDIF_JACK
GND_AUDIO_HP_AMP_L
MIN_NECK_WIDTH=0.1MM
MIN_LINE_WIDTH=0.2MM
GND_AUDIO_MIC1_CONN
AUD_MIC_IN1_P_CONN
AUD_SPKR_OUTLO1R_POUT
MIN_LINE_WIDTH=0.5MM
MIN_NECK_WIDTH=0.2MM
AUD_SPKR_OUTLO1R_NOUT
AUD_MIC_IN1_N_CONN
AUD_MIC1_IN_P
AUD_MIC1_IN_N
NC_J6702_3NO_TEST
MIN_NECK_WIDTH=0.2MM
MIN_LINE_WIDTH=0.5MM
AUD_SPKR_OUTLO2L_POUT
AUD_SPKR_OUTLO2L_NOUT
AUD_SPKR_OUTLO1L_POUT
AUD_SPKR_OUTLO1L_NOUT
AUD_SPKR_OUTLO2R_POUT
AUD_SPKR_OUTLO2R_NOUT
AUD_MIC_IN1_P_EMI
HS_MIC_LO
VOLTAGE=0V
MIN_NECK_WIDTH=0.1MM
MIN_LINE_WIDTH=0.15MM
AUD_MIC_IN1_N_EMI
AUD_LI_TIP_DET
MIN_NECK_WIDTH=0.2MM AUD_HP_GND_JACKMIN_LINE_WIDTH=0.3MM
AUD_HP_R_JACKMIN_NECK_WIDTH=0.2MMMIN_LINE_WIDTH=0.3MM
AUD_IP_PERPH_JACKMIN_LINE_WIDTH=0.2MM MIN_NECK_WIDTH=0.1MM
MIN_LINE_WIDTH=0.2MM MIN_NECK_WIDTH=0.1MM AUD_HP_TIPDET_JACK
AUD_SPDIF_OUT_JACK
HS_MIC_HI_JACKMIN_NECK_WIDTH=0.1MMMIN_LINE_WIDTH=0.2MM
MIN_LINE_WIDTH=0.3MM MIN_NECK_WIDTH=0.2MM HS_MIC_LO_JACK
MIN_LINE_WIDTH=0.2MM MIN_NECK_WIDTH=0.1MM AUD_HP_TYPEDET_JACK
AUD_LI_L_JACKMIN_NECK_WIDTH=0.2MMMIN_LINE_WIDTH=0.3MM
MIN_LINE_WIDTH=0.2MM MIN_NECK_WIDTH=0.1MM VOLTAGE=3.3V PP3V3_AUDIO_SPDIF_JACK
MIN_NECK_WIDTH=0.2MMMIN_LINE_WIDTH=0.3MM
AUD_LI_GND_JACKMIN_NECK_WIDTH=0.2MMMIN_LINE_WIDTH=0.3MM
AUD_SPDIFIN_JACK
AUD_HP_L_JACKMIN_NECK_WIDTH=0.2MMMIN_LINE_WIDTH=0.3MM
AUD_LI_DET_JACK
MIN_LINE_WIDTH=0.2MM MIN_NECK_WIDTH=0.1MM
AUD_LI_R_JACKMIN_LINE_WIDTH=0.3MM MIN_NECK_WIDTH=0.2MM
AUD_LI_R
MIN_NECK_WIDTH=0.2MM
MIN_LINE_WIDTH=0.3MM
AUD_LI_GND
MIN_NECK_WIDTH=0.2MM
MIN_LINE_WIDTH=0.3MM
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G
S
D
G
S
D
G
S
D
OUT
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
OUT
IN
OUT
OUT
G
S
D
IN
IN
G
S
D
G
S
D
IN
G
S
D
G
S
D
IN
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
BRANCH
REVISION
DRAWING NUMBER SIZE
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SHEET
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PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
87 54 21
AUDIO STAR GND AND STUFFING OPTIONS
IPHS HS Detect Debounce CKT
Internal Microphone Impedance Matching
DP Audio Enable
Headphone Out LI Insert DetectDigital Out
NCNC
21
C6795
10%
X5R
16V
402
0.1UF
21
XW6702
SM
21
XW6705
SM
21
R6743
1/16W
MF-LF
402
5%
2.2K
1
2
6
Q6700
SOT-563-HF
NTZD3154NT1H
1
2
6
Q6702
SOT-563-HF
NTZD3154NT1H
4
5
3
Q6702
SOT-563-HF
NTZD3154NT1H
2
1
R6790
MF-LF
1/16W
5%
100K
402
2
1
R6795
5%
402
1/16W
100K
MF-LF
2
1C6750
0.0082UF
10%
X7R
25V
402
2
1
R6744
1/16W
39.2K
MF-LF
1%
402
2
1
R6794
MF
CRITICAL
20K
1/16W
402
0.1%
19 21
R6799
MF-LF
1/16W
5%
0
402
2
1C6797
402
0.1UF
16V
10%
NOSTUFF
X5R
21
R6796
0
1/16W
MF-LF
402
5%
2
1
R6701
1/16W
402
1%
10K
MF-LF
21
C6796
0.1UF
16V
402
X5R
10%
2
1
R6791
100K
5%
1/16W
402
MF-LF
60
60
56 61
5 56 58 59 60 61 62
60
60
5 56 58 59 60 61
62
56 61
60
56 61
47 56 57 61 62
2
1
R6798
402
100K
MF-LF
5%
1/16W
56
2
1
C6751
CRITICAL
4.7UF
TANT
20%
6.3V
603-HF
21
R6747
402
5%
0
MF-LF
NOSTUFF
1/16W
56
56
2
1
R6793
402
1%
1/16W
MF-LF
3.40K
2
1
R6792
3.40K
MF-LF
1%
1/16W
402
4
5
3
Q6701
NTZD3154NT1H
SOT-563-HF
2
1
R6797
MF-LF
5%
100K
1/16W
402
21
R6700
1%
1/16W
MF-LF
402
17.4K
2
1C6740
16V
X5R
402
10%
0.1UF
60
2
1
R6730
5%
MF-LF
402
1/16W
100K
5 56 58 59 60 61 62
1
2
6
Q6703
NTZD3154NT1H
SOT-563-HF
4
5
3
Q6700
SOT-563-HF
NTZD3154NT1H
2
1
R6762
402
100K
5%
1/16W
MF-LF
5 56 58 59 60 61 62
2
1
R6768
100K
402
MF-LF
5%
1/16W
1
2
6
Q6701
NTZD3154NT1H
SOT-563-HF
4
5
3
Q6703
SOT-563-HF
NTZD3154NT1H47
21
R6748
1/16W
NOSTUFF
MF-LF
0
5%
402
21
R6749
402
5%
0
MF-LF
NOSTUFF
1/16W
AUDIO: Detects/Grounding
SYNC_DATE=02/02/2010SYNC_MASTER=BREECE
=PP3V3_S0_AUDIO
AUD_SENSE_A
=PP3V3_S0_AUDIO
AUD_IP_PERPH_DET_DB
=PP3V3_S0_AUDIO
AUD_IP_PERPH_DET AUD_IP_PER_DEB
AUD_IP_PERPH_DET_INV
AUD_IP_PERIPHERAL_DET
=PP3V3_S0_AUDIO
AUD_HP_TIP_DET
=PP3V3_S0_AUDIO
AUD_SENSE_A
GND_AUDIO_CODEC
AUD_Q6702_D3 AUD_Q6701_D6
AUD_IP_PERPH_DET_R
AUD_LI_TIP_DET
AUD_HP_TYPE
GND_AUDIO_CODEC
AUD_SENSE_A
BDV_AV_MUX_SEL
AUD_HP_TIP_DET_INV
AUD_HP_TYPE_INV
AUD_LI_TIP_DET_INV
GND_AUDIO_CODEC
AUD_MIC1_IN_G GND_AUDIO_CODEC
AUD_CODEC_MICBIAS
AUD_MIC1_IN_N
AUD_MIC_INP_R
GND_AUDIO_CODEC
AUD_MIC_INN_R
AUD_MIC1_IN_P
AUD_INTMICBIAS
GND_AUDIO_CODEC
GND_AUDIO_HP_AMP_L GND_AUDIO_CODEC
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IN
BI
OUT
IN
IN
IN
OUT
OUT
IN
GND THM
ENABLE
AVDD
SDA
MICBIAS
DETECT
BYPASSINT*
SCL
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
BRANCH
REVISION
DRAWING NUMBER SIZE
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IV ALL RIGHTS RESERVED
SHEET
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C
A
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PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
87 54 21
MIKEY RECEIVER CKT
WRITE: 0X72 READ: 0X73
0X04
0X03
0X02
MIKEY
N/A
0X07
0X0D (13,V22,B,LEFT)
APN 353S2256
0X0D (B)
N/A
MIKEY
LINE IN
0X05
ENABLE/
CONVERTER
MCP GPIO_38
N/A
N/A
MIKEY
HEADPHONES
SPDIF IN
SPDIF OUT
0X04
0X03
0X02
0X06
0X06
0X08
N/A
0X06
N/A
0X06
N/A
0X05
VOLUME
GPIO 3
0X09 (A)
MCP GPIO_5
N/A
N/A
N/A
N/A
DETECT/INTERRUPTTYPE
HEADSET MICROPHONE
BUILT-IN MICROPHONE
LINE INPUT
0X09
0X0B
SECONDARY
PRIMARY
FUNCTION
0X0F
0X10
0X0A
PIN
N/A
N/A
MICBIAS 80%
FLP = 8.82 KHZ
FHP = 80 HZ
CNTRL
GPIO 3
0X0C
0X0D(13,B,RIGHT)
21
L6840
FERR-1000-OHM
0402
2
1
R6807
1/16W
402
MF-LF
5%
100K
21
R6802
402
MF-LF
5%
0
1/16W
21
R6803
MF-LF
402
1/16W
5%
0
21
R6804
5%
1/16W
402
MF-LF
0
21
R6805
5%
MF-LF
402
1/16W
0
49
49
19
20
2
1
C6854
4.7UF
603-HF
6.3V
20%
TANT
CRITICAL
60
60
56
56
5 56 58 59 60 61
2
1
R6808
100K
1/16W
MF-LF
402
5%
21
R6810
402
5%
MF-LF
1/16W
2.2K
2
1C6855
402
25V
X7R
10%
0.0082UF
21
C6801
10%
X5R
16V
402
0.1UF
21
C6802
X5R
16V
0.1UF
402
10%
11
5
6 1
7
49
8
2
10
3
U6806
DRC
CD3275
CRITICAL
2
1
R6806
402
MF-LF
1/16W
5%
10K
2
1C6852
402
10%
1UF
X5R
10V
2
1C6853
402
10%
0.1UF
X5R
16V
2
1
R6809
MF-LF
2.2K
1/16W
402
5%
2
1
R6852
MF-LF
1/16W
5%
402
1K
2
1C6899
25V
X7R
402
10%
0.01UF
SYNC_MASTER=BREECE SYNC_DATE=02/02/2010
AUDIO: Mikey
HS_SCL
GND_AUDIO_CODEC
HS_SW_DET
MIN_NECK_WIDTH=0.1MM
MIN_LINE_WIDTH=0.15MM
HS_MIC_BIAS
MIN_NECK_WIDTH=0.1MM
MIN_LINE_WIDTH=0.15MM
=PP3V3_S0_AUDIO
MIN_NECK_WIDTH=0.1MM
HS_MIC_HI
MIN_LINE_WIDTH=0.15MM
HS_RX_BP
MIN_NECK_WIDTH=0.1MM
MIN_LINE_WIDTH=0.15MM
MIN_NECK_WIDTH=0.1MM
MIN_LINE_WIDTH=0.15MM
AUD_MIC_INN_L
AUD_MIC_INF
MIN_LINE_WIDTH=0.15MM
MIN_NECK_WIDTH=0.1MM MIN_NECK_WIDTH=0.1MM
AUD_MIC_INP_L
MIN_LINE_WIDTH=0.15MM
=I2C_AUDIO_SCL
AUD_I2C_INT_L
AUD_IPHS_SWITCH_EN
GND_AUDIO_CODEC
=I2C_AUDIO_SDA
HS_RST
PP3V3_S0_HS_F
MIN_NECK_WIDTH=0.1MM
VOLTAGE=3.3V
MIN_LINE_WIDTH=0.15MM
HS_INT_L
HS_SDA
HS_MIC_LO
MIN_LINE_WIDTH=0.15MM
MIN_NECK_WIDTH=0.1MM
68 OF 110
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OUTIN
08
08
08
G S
D
OUT
OUT
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
BRANCH
REVISION
DRAWING NUMBER SIZE
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R
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SHEET
PAGE TITLE
C
A
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21
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
87 54 21
MEMVTT_EN SEQUENCE
ME RAILS TIED TO S0 ONLY
SLP_S4 ENABLES
SLP_S3 ENABLES
ENABLE REGULATOR
Battery Off (G3Hot)
CPUVTT VREG
Enable FET
Enable FET
PM_SLP_S4_L PM_SLP_M_L
11
1
0
1
0
0
1
1
1
0
0
PM_SLP_S3_LManageability SMC_PM_G2_ENABLE PM_S4_STATE_L
N/A 111
0
0
0
0
0
0
1
0
0
1
1
1
1
1
0
On
On
Off
N/A
State
Soft-Off (S5/M-Off)
Sleep (S3/M-Off)
Soft-Off (S5/M1)
Sleep (S3/M1)
Run (S0/M0)
Off
Enable regulator
Enable FET
ENABLE FET
UNUSED
Enable regulator
(PM_SLP_S3_L_BUF)
Enable regulator
PCHCORE VREG
PP1V8_S0 VREG (CPU PLL)
PLACE TOP SIDE
REWORK TO POWER UP WITH NO CPU
Enable FET
OTHER RAILS ENABLED BY P3V3_S0 AND P5V_S0:
TO ENABLE OF CPU VREG
Enable regulator
18 91 46 91
21
R6946
5%
33
1/16W
402
MF-LF
2
1
R6916
402
MF-LF
5%
1/16W
100K
2
1
R6915
402
10K
MF-LF
1/16W
5%
14
8
9
10
7
U6900
TSSOP-HF
74LVC08
14
3
2
1
7
U6900
74LVC08
TSSOP-HF
2
1
R6917
NOSTUFF
1/16W
402
MF-LF
0
5%
2
1
C6944
402
NOSTUFF
6.3V
CERM-X5R
10%
0.47UF
2
1
R6944
MF-LF
402
1/16W
1%
10K
21
C6910
0.1UF
20%
CERM
10V
402
2
1
C6921
NOSTUFF
6.3V
CERM-X5R
0.47UF
402
10%
2
1
C6920
10%
6.3V
402
CERM-X5R
0.47UF
NOSTUFF
2
1
C6946
NOSTUFF
10%
0.47UF
6.3V
CERM-X5R
402
2
1
C6945
NOSTUFF
0.47UF
402
6.3V
10%
CERM-X5R
2
1
R6910
100K
MF-LF
402
5%
1/16W
2
1
C6924
CERM-X5R
NOSTUFF
0.47UF
402
10%
6.3V
2
1
C6947
NOSTUFF
6.3V
CERM-X5R
10%
402
0.47UF
2
1
C6942
402
CERM
6.3V
10%
1UF
2
1
R6942
5%
10K
1/16W
MF-LF
402
2
1C6952
NOSTUFF
CERM-X5R
0.47UF
402
10%
6.3V
1
6
2
Q6911
SOT-363-LF
MMDT3904-X-G
2
1C6951
CERM
402
5%
50V
100PF
NOSTUFF
2
1
R6951
1/16W
10K
5%
MF-LF
402
4
3
5
Q6911
MMDT3904-X-G
SOT-363-LF
2
1C6953
NOSTUFF
16V
402
X5R
10%
0.1UF
21
R6950
402
5%
MF-LF
1/16W
100K
2
1
R6952
5%
MF-LF
1/16W
402
10K
14
6
5
4
7
U6900
TSSOP-HF
74LVC08
2
1
3
Q6910
SOT23-HF1
2N7002
21
R6901
402
0
1/16W
5%
MF-LF
73 91
73 91
2
1
R6941
NOSTUFF
1/16W
10K
5%
MF-LF
402
2
1
C6941
NOSTUFF
0.47UF
10%
402
CERM-X5R
6.3V
21
R6911
402
MF-LF
33
1/16W
5%
21
R6912
1/16W
MF-LF
5%
402
33
21
R6947
MF-LF
1/16W
402
33
5%
POWER SEQUENCING ENABLES
SYNC_MASTER=K74_MASTER SYNC_DATE=N/A
PM_RSMRST_PCH_LPM_RSMRST_L
PM_EN_PVCORE_CPU
DDRVTT_EN
P1V5_S0_EN
TP_PM_SLP_M_L
MAKE_BASE=TRUE
P3V3S0_EN
PM_SLP_S3_L
PM_PGOOD_DDRREG_S3
=PP3V3_S5_PWRCTL
=PP3V3_S5_PWRCTL
=PP3V3_S5_PWRCTL
CPU_SKTOCC
P5VS0_EN
PGOOD_P12V_S0
MAKE_BASE=TRUE
MAKE_BASE=TRUE
PGOOD_P5V_S0
CPUVTT_REG_EN
PM_SLP_S3_BUF_L
PM_SLP_S3_BUF_L
MAKE_BASE=TRUE
MAKE_BASE=TRUE
PCHCORE_REG_PGOOD
CPUVTT_REG_PGOOD
MAKE_BASE=TRUE
PCHCORE_REG_EN
CPU_SKTOCC_L
PM_SLP_S4_1_L
=PP3V3_S0_PWRCTL
=DDRREG_EN
=PP5V_S3_PWRCTL
MAKE_BASE=TRUE
P5VS3_REG_PGOOD
P1V05_ME_S0_EN
P3V3S3_EN
P5VS3_EN
S4_ENABLES
DDRVTT_EN
CPUVTT_REG_PGOOD
=PP3V3_S5_PWRCTL
=PP3V3_S0_PWRCTL
PM_SLP_M_L
PM_EN_USB_PWR
CPUVTT_REG_PGOOD_R
VTT_REG_PGOOD_L
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63 71 91
73 91
5 18 26 36 46 47 64 81 91
71 91
5 10 63 64
5 10 63 64
5 10 63 64
64
73 91
68 91
63 63
64 69 91
10 63 64 68 91
69 91
10
18 91
5 63 64 73
71
5
70
73 91
70 91
63 71 91
10 63 64 68 91
5 10 63 64
5 63 64 73
18 91
43
www.vinaﬁx.vn

OUT
OUT
OUT
08
08
08
08
08
GND
V+
G
D
S
G
D
S
GND
V+
IN
IN
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
BRANCH
REVISION
DRAWING NUMBER SIZE
D
R
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
21
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
87 54 21
To SMC (2)
DELAY IS ABOUT 200MS
PGOOD COMPARATORS FOR PP1V8_S0 AND PP12V_S0
IBEX PEAK EDS
OPTION FOR PCH PWROK AND SYSPWROK
(1.67V/1.22V; 132mV Hysteresis)
TO BE DRIVEN BY SAME SIGNAL
ALL_SYS_PWRGD CIRCUIT
SMC
PULL-UP ON MXM PAGE
APPROXIMATE DELAY OF 10-15MS
ASK INTEL: NEED 100K PULL-DOWN?
OPTION FOR SMC TO OUPUT
DELAYED PWRGD (BY 99MS)
(9.91V/9.58V; 330mV Hysteresis)
WHICH GOES INTO RSMRST_L OF PCH
FROM THIS SMC GENERATES PM_RSMRST_L
DISABLE CPUVTT_REG_PGOOD WHEN SLP_S3_L = 0 (PER PIKETON PDG)
S0 RAILS PGOOD
46 91
46 91
2
1
C7022
0.1UF
402
CERM
20%
10V
2
1
R7050
1/16W
1K
402
MF-LF
5%
NOSTUFF
2
1C7050
0.1UF
10%
X5R
402
16V
NOSTUFF
2
1
R7007
49.9K
402
1/16W
1%
MF-LF
21
R7022
MF-LF
33
1/16W
402
5%
21
R7023
5%
33
402
1/16W
MF-LF
5 91
2
1
R7020
64.9K
1%
402
1/16W
MF-LF
2
1
R7021
1%
10K
1/16W
MF-LF
402
21
R7002
1%
1/16W
MF-LF
402
2.0K
2
1
R7017
MF-LF
402
5%
1/16W
10K
2
1
R7018
10K
5%
1/16W
MF-LF
402
14
6
5
4
7
U7000
TSSOP-HF
74LVC08
14
8
9
10
7
U7000
74LVC08
TSSOP-HF
14
11
12
13
7
U7000
TSSOP-HF
74LVC08
14
3
2
1
7
U7000
74LVC08
TSSOP-HF
21
R7024
402
NOSTUFF
5%
1/16W
10K
MF-LF
4
3
5
Q7011
SOT-363-LF
MMDT3904-X-G
1
6
2
Q7011
SOT-363-LF
MMDT3904-X-G
21
R7028
1/16W
MF-LF
402
5%
33
21
R7030
402
5%
1/16W
MF-LF
0
2
1C7023
NOSTUFF
0.47UF
CERM-X5R
6.3V
10%
4022
1
R7031
100K
5%
NOSTUFF
MF-LF
402
1/16W
2
1
R7025
10K
1/16W
402
MF-LF
5%
4
3
5
Q7060
SOT-363-LF
MMDT3904-X-G
2
1
R7061
5%
10K
1/16W
402
MF-LF
1
6
2
Q7060
MMDT3904-X-G
SOT-363-LF
21
R7060
402
5%
1/16W
MF-LF
10K
14
11
12
13
7
U6900
TSSOP-HF
74LVC08
21
R7027
33
1/16W
MF-LF
5%
402
21
R7029
1/16W
5%
MF-LF
0
402
NOSTUFF
21
R7032
1/16W
MF-LF
402
33
5%
2
1
C7080
603
CERM
16V
20%
0.1UF
2
1
R7086
402
5%
MF-LF
1/16W
10K
2
1
R7084
10K
1/16W
5%
402
MF-LF
2
1
R7083
49.9K
1%
1/16W
402
MF-LF
8
1
3
2
4
U7080
SOI-HF
CRITICAL
LM393
2
1
R7080
1/16W
MF-LF
33.2K
1%
402
2
1
R7081
402
1%
1/16W
MF-LF
100K
21
R7082
1/16W
1%
MF-LF
402
2.0K
1
2
6
Q7080
SOT-363
2N7002DW-X-G 4
5
3
Q7080
SOT-363
2N7002DW-X-G
21
R7071
402
33
1/16W
MF-LF
5%
8
7
5
6
4
U7080
CRITICAL
LM393
SOI-HF
47 91
21
R6903
402
0
5%
1/16W
MF-LF
2
1
R6902
1/16W
5%
402
MF-LF
100K
70
SYNC_MASTER=K74_MASTER SYNC_DATE=N/A
POWER SEQUENCING PGOOD
=PP12V_S0_PWRCTL
1V60_COMP_REF
VTTS3PG_1
P3V3S5_REG_PGOOD
=PP12V_S5_PWRCTL
PGOOD_SYSPWROK
=PP3V3_S5_PWRCTL
PGOOD_SYSPWROK_R
PM_MXM_EN
12V_COMP_REF
ALL_SYS_PWRGD_SMC
PM_SPARE_PGOOD
PM_SLP_S3_L
VTTS3PG_2
=PP3V3_S5_PWRCTL
CPUVTT_REG_PGOOD
PGOOD_P12V_S0
=PP3V3_S3_PWRCTL
SMC_DELAYED_PWRGD
ALL_SYS_PWRGD
ALL_SYS_PWRGD_R
PM_ME_PWRGD
PM_SYS_PWRGD
PM_PCH_PWRGD
=PP3V3_S0_PWRCTL
=PP12V_S5_PWRCTL
=PP1V8_S0_CPU_PLL
PP12V_S0
PGOOD_P1V8_S0
PGOOD_1V8_S0_G2
PGOOD_PCH_S0
=PP3V3_S0_PWRCTL
=PP3V3_S0_MXM =PM_MXM_PGOOD_PULLUP
PM_MXM_PGOOD
PM_PGOOD_PVCORE_CPU
PGOOD_CPU_GFX_DDR
=PP3V3_S0_PWRCTL
PGOOD_P1V8_S0
PGOOD_P3V3_S0
=PP3V3_S0_PWRCTL
PCHCORE_REG_PGOOD
PGOOD_12V_S0_G1
PGOOD_12V_S0_G2
PGOOD_PCH_AND_P1V8
PGOOD_1V8_S0_G1
=PP3V3_S0_PWRCTL
=PP3V3_S0_PWRCTL
=PP3V3_S5_PWRCTL
1V80_COMP_REF
9V_91_COMP_REF
=PP3V3_S5_PWRCTL
RSMRST_PWRGD
70 OF 110
A.0.0
051-8337
64 OF 92
5
5 64 73
91
5 10 63 64
91
75
5 18 26 36 46 47 63 81 91
5 10 63 64
10 63 68 91
63
5 73
18 91
18 91
18
91
5 63 64 73
5 64 73
5 12 15
5 89
64 91
91
5 63 64 73
5 74 75 75
75 91
25 65 91
91
5 63 64 73
64 91
73 91
5 63 64 73
63 69 91
91
5 63 64 73
5 63 64 73
5 10 63 64
5 10 63 64
www.vinaﬁx.vn

IN
OUT
OUT
OUT
IN
IN
IN
OUT
IN
IN
OUT
IN
IN
IN
ISEN4-
EN_VTT
THRM_PAD
VR_HOT
VR_FAN
ISEN4+
ISEN3-
ISEN3+
ISEN2-
ISEN2+
ISEN1+
PWM2
FB
PWM1
TCOMP
PSI*
IMON
OFS
VCC
VID0
VR_RDY
VID7
VID5
VID4
VID3
VID2
VID6
VID1
SS
FS
PWM3
PWM4
TM
REF
DAC
EN_PWR
RGND
VSEN
VDIFF
ISEN1-
COMP
SYM_VER_2
IN
IN
OUT
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
BRANCH
REVISION
DRAWING NUMBER SIZE
D
R
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
21
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
87 54 21
CPU CORE REG 1.1V/???A O/P= PPVCORE_S0_CPU_REG
LOCAL 5V
152-0110
CPU CORE INPUT Filtering
AVG = ???A
PEAK = ???A
1.25 mOhm loadline
VR_HOT goes HIGH when VTM/VCC < 28%
CPU VCORE
VOUT = VCORE
and LOW when VTM/VCC > 33%.
IMAX = 10.5A
LAYOUT: PLACE RT7101 NEAR HOT SPOT.
2
1
R7135
MF-LF
1/16W
5%
1K
402
21
XW7101
SM
OMIT
2
1
C7135
CERM
402
10%
0.001UF
50V
7
6
5
4
3
2
1
0
2
1
R7115
1/16W
1%
402
MF-LF
49.9K
2
1
R7114
49.9K
1%
MF-LF
1/16W
402
2
1R7112
2.0K
1/16W
MF-LF
402
5%
2
1C7109
NOSTUFF
0.01UF
10%
16V
CERM
402
63
25 64 91
12 88 VR_CPU_IOUT
2
1C7103
0.0022UF
10%
CERM
50V
402
2
1C7102
0.0022UF
10%
CERM
50V
402
2
1C7101
SIGNAL_MODEL=EMPTY
10%
50V
CERM
402
0.0022UF
NOSTUFF
21
R7110
1K
1/16W
MF-LF
1%
402
21
C7110
1500PF
X7R
25V
402
10%
2
1
R7109
1%
402
100K
1/16W
MF-LF
2
1R7107
1/16W
21K
402
MF-LF
1%
2
1
R7105
20.0K
1/16W
402
1%
NOSTUFF
MF-LF
2
1
R7100
1.02K
1%
1/16W
MF-LF
402
2
1R7106
1/16W
MF-LF
402
0
5%
66 89
66 89
66 89
2
1C7132
0.1UF
10%
16V
X5R
402
66 89
66 89
66 89
2
1C7152
10%
16V
X5R
402
0.1UF
66 89
66 89
66 89
2
1C7142
10%
16V
0.1UF
X5R
402
12 89
2
1
R7145 0
402
1/16W
MF-LF
5%
2
1
R7104
402
MF-LF
1/16W
5%
0
12 15 89
17
36
38
37
40
1
2
3
4
5
6
7
15
19
39
41
18
35
16
12
25
31
20
26
8
9
23
24
29
30
22
21
28
27
10
34
14
33
32
11
13
U7100
CRITICAL
QFN
ISL6334
2
1
R7178
NOSTUFF
0
1/16W
402
MF-LF
5%
2
1
R7177
402
5%
MF-LF
1/16W
0
NOSTUFF
2
1C7180
20%
CERM
10V
0.1UF
402
2
1
R7147
0
MF-LF
1/16W
5%
402
NOSTUFF
2
1
R7148
0
402
NOSTUFF
5%
MF-LF
1/16W
2
1
R7144
402
MF-LF
0
1/16W
5%
2
1C7130
C0G
1%
50V
15PF
402
NOSTUFF
2
1C7140
50V
C0G
402
NOSTUFF
15PF
1%
2
1C7150
NOSTUFF
1%
50V
C0G
15PF
402
21
R7150
0
402
5%
1/16W
MF-LF
21
R7140
1/16W
402
MF-LF
0
5%
21
R7132
402
5%
MF-LF
1/16W
0
21
R7142
0
402
1/16W
5%
MF-LF
21
R7152
402
5%
MF-LF
0
1/16W
21
R7149
1/16W
MF-LF
402
1%
47.5
2
1
R7146
NOSTUFF
402
1/16W
5%
1M
MF-LF
12 50 89
21
R7139
402
MF-LF
5%
1/16W
10
21
R7137
402
10
5%
1/16W
MF-LF
21
R7127
MF-LF
1K
1/16W
5%
402
21
R7128
0
1/16W
MF-LF
5%
402
21
R7129
0
MF-LF
5%
402
1/16W
21
R7138
MF-LF
1/16W
402
5%
1K
12 89
21
XW7120
OMIT
SM
21
XW7130
SM
OMIT
2
1
RT7101
0603
6.8K
21
R7136
10K
1/16W
MF-LF
5%
402
50 89
2
1C7133
402
25V
CERM
220PF
5%
21
R7133
1.02K
1%
1/16W
MF-LF
402
2
1C7143
CERM
402
25V
220PF
5%
21
R7143
402
MF-LF
1%
1/16W
1.02K
2
1C7153
25V
CERM
402
220PF
5%
21
R7153
402
1%
1.02K
1/16W
MF-LF
21
D7171
SOD-923-HF
NOSTUFF
NSR0140P2T5G
2
1
R7172
402
MF-LF
1%
NOSTUFF
1.02K
1/16W
2
1C7171
NOSTUFF
402
50V
10%
0.020UF
CERM
21
R7171
0
1/16W
MF-LF
5%
402
21
R71110
5%
MF-LF
1/16W
402
2
1
R7108
1/16W
MF-LF
75K
1%
402
21
R7102
1/16W
1K
1%
MF-LF
402
21
L7100
TH-VERT-HF
CRITICAL
1UH-20A-4.5MOHM
21
C7104
47PF
5%
50V
CERM
402
21
R7103
1/16W
402
1%
MF-LF
287
21
R7131
165
402
MF-LF
1/16W
1%
21
R7141
165
MF-LF
402
1%
1/16W
21
R7151
1/16W
165
402
MF-LF
1%
2
1C7141
150PF
402
5%
50V
CERM
2
1C7151
150PF
402
5%
50V
CERM
2
1C7131
150PF
402
CERM
50V
5%
2
1C7112
10%
16V
CERM-X5R
402
0.022UF
2
1
R7117
402
1%
1/16W
MF-LF
10K
2
1
R7116
1.54K
402
MF-LF
1/16W
1%
21
R7118
1/8W
MF-LF
5%
805
2.2
21
C7106
50V
CERM
10%
470PF
402
21
R7179
402
MF-LF
1/16W
5%
0
2
1C7107
402
10%
X5R
10V
1UF
21
C7105
0.0022UF
10%
50V
402
CERM
21
R7101
MF-LF
16.5K
402
1%
1/16W
SYNC_MASTER=K74_MASTER SYNC_DATE=N/A
VREG: PPVCORE_S0_CPU
CPU_VID<7..0>
VR_CPU_PWM4_R
VR_CPU_ISNS3_R_P
VR_CPU_ISNS2_R_N
VR_CPU_ISNS2_N
DIFFERENTIAL_PAIR=VR_CPU_ISNS2
DIFFERENTIAL_PAIR=VR_CPU_ISNS2
VR_CPU_ISNS2_P
VR_CPU_PWM2
VR_CPU_PWM1
VR_CPU_ISNS1_RR_2
DIFFERENTIAL_PAIR=VR_CPU_ISNS1
VR_CPU_ISNS1_N
VR_CPU_OFS
VR_CPU_FS
VR_CPU_TCOMP
VR_CPU_FB
VR_CPU_VDIFF
VR_VDF_R1
VR_CPU_RGND
VR_CPU_FB_R
VR_CPU_ISNS3_R_N
VR_CPU_SS
VR_CPU_VSEN
AGND_CPU
VR_CPU_PWM3
VR_CPU_ISNS2_R_P
VR_CPU_ISNS1_R_N
VOLTAGE=12V
PP12V_S0_CPU_FLTRD
NET_PHYSICAL_TYPE=POWER
DIDT=TRUE
VR_CPU_PWM3_R
=PP5V_S0_VRD
PP5V_S0_CPU_VCORE_VCC
=PPVTT_S0_CPU
VR_CPU_EN_PWR
PM_EN_PVCORE_CPU
VR_CPU_VSNS_R_N
CPU_VCC_PKG_SENSE_N
CPU_VCC_PKG_SENSE_P
AGND_CPU
VR_VDF_R2
VR_CPU_VSNS_R_P
AGND_CPU
VR_CPU_VRDHOT
MAX_NECK_LENGTH=3MM
AGND_CPU
MIN_NECK_WIDTH=0.3MM
VOLTAGE=0V
MIN_LINE_WIDTH=0.6MM
VR_CPU_ISNS1_P
DIFFERENTIAL_PAIR=VR_CPU_ISNS1
VR_CPU_ISNS3_P
DIFFERENTIAL_PAIR=VR_CPU_ISNS3
VR_CPU_COMP_RC
VOLTAGE=1.1V
VR_CPU_VSNS_XW_P
NET_PHYSICAL_TYPE=SNS_DIFF
VOLTAGE=0V
VR_CPU_VSNS_XW_N
NET_PHYSICAL_TYPE=SNS_DIFF
VR_CPU_FAN
AGND_CPU
VR_CPU_EN_VTT
VR_CPU_TM
PP5V_S0_CPU_VCORE_VCC
VR_CPU_REF
VR_CPU_DAC
VR_CPU_ISNS3_N
DIFFERENTIAL_PAIR=VR_CPU_ISNS3
VR_CPU_PWM2_R
VR_CPU_COMP_R
VR_CPU_COMP
VR_CPU_ISNS2_RR_2
VR_CPU_ISNS3_RR_2
=PP12V_S0_VRD
VR_CPU_PSI_L
CPU_PSI_L
VR_CPU_IOUT_PD
=PP3V3_S0_VRD
PPVCORE_S0_CPU_REG
PM_PGOOD_PVCORE_CPU
VOLTAGE=5V
MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.3MM
MAX_NECK_LENGTH=3MM
PP5V_S0_CPU_VCORE_VCC
VR_CPU_ISNS1_R_P
VR_CPU_IMON
71 OF 110
A.0.0
051-8337
65 OF 92
89
89
89
89
89
89
89
89
89
89
89
65
89
89
66 89
89
5
65 89
5 10 12 15 47
65
65
65
89
89
89
89
65
89
65 89
89
89
89
89
89
5
89
5
5 66 67
65 89
89
www.vinaﬁx.vn

OUT
IN
IN
OUT
OUT
OUT
OUT
BOOT
UGATE
PHASE
NC
NC
GND
LGATE
VCC PVCC
THRML
PWM
PAD
BOOT
UGATE
PHASE
NC
NC
GND
LGATE
VCC PVCC
THRML
PWM
PAD
S
G
D
D
G
S
S
G
D
S
G
D
D
G
S
D
G
S
IN
GDSEL
LGATE
VCC
PWM
BOOT
UGATE
GND
THRML
PHASE
LVCCUVCC
PAD
OUT
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
BRANCH
REVISION
DRAWING NUMBER SIZE
D
R
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
21
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
87 54 21
152-0114
THESE TWO CAPS ARE FOR EMC
THESE TWO CAPS ARE FOR EMC
152-0114
THESE TWO CAPS ARE FOR EMC
152-0114
128S0209
OUTPUT BULK DECOUPLING:
???A MAX
PHASE 2
PHASE 3
376S0771
376S0772
376S0771
376S0772
376S0771
376S0772
PHASE 1
65 89
2
1C7227
603
16V
X5R
1UF
10%
2
1C7226
CRITICAL
0805
X5R-CERM
10UF
16V
10%
2
1
R7226
1
805
MF-LF
1/8W
5%
2
1C7206
X5R-CERM
CRITICAL
0805
10%
10UF
16V
2
1C7228
5%
1000PF
NP0-C0G
25V
402
2
1C7223
10%
0.22UF
16V
X7R
603
2
1
R7224
603
0
5%
1/10W
MF-LF
2
1C7221
X5R
10%
1UF
603
16V
2
1
R7221
5%
1/10W
10
MF-LF
603
2
1
R7225
NOSTUFF
1/10W
603
0
5%
MF-LF
2
1
R7222
1/10W
5%
603
MF-LF
10
2
1C7220
NOSTUFF
10%
16V
1UF
X5R
603
2
1C7222
603
X5R
16V
10%
1UF
2
1
R7227
0
5%
1/10W
603
MF-LF
NOSTUFF
65 89
2
1C7247
10%
1UF
16V
X5R
603
2
1C7246
CRITICAL
X5R-CERM
0805
10%
16V
10UF
2
1
R7206
1
MF-LF
805
5%
1/8W
2
1
R7246
1
5%
1/8W
MF-LF
805
2
1C7248
5%
1000PF
NP0-C0G
25V
402
2
1
C7243
603
X7R
10%
16V
0.22UF
2
1
R7244
1/10W
603
MF-LF
5%
02
1
C7241
603
X5R
16V
1UF
10%
2
1C7208
5%
1000PF
NP0-C0G
25V
402
2
1
R7241
10
5%
1/10W
603
MF-LF
2
1
R7245
603
NOSTUFF
MF-LF
1/10W
5%
0
2
1
R7242
MF-LF
1/10W
5%
10
603
2
1C7240
NOSTUFF
10%
16V
1UF
X5R
603
2
1C7242
603
10%
1UF
X5R
16V
2
1
R7247
NOSTUFF
5%
1/10W
603
0
MF-LF
65 89
2
1C7207
1UF
10%
16V
603
X5R
2
1C7211
0.001UF
X7R
50V
10%
402
2
1C7215
CRITICAL
10UF
10%
16V
0805
X5R-CERM
2
1C7229
10UF
0805
16V
10%
X5R-CERM
CRITICAL
2
1C7249
CRITICAL
16V
10%
0805
X5R-CERM
10UF
43
21
R7208
0612
1%
0.0005
1W
MF
CRITICAL
43
21
R7228
0612
CRITICAL
1%
0.0005
1W
MF
65 89
65 89
65 89
65 89
43
21
R7248
0612
1W
MF
CRITICAL
0.0005
1%
2
1
C7270
270UF
ELEC
20%
CRITICAL
16V
8X9-TH1
2
1
C7271
CRITICAL
270UF
16V
ELEC
8X9-TH1
20%
2
1C7203
603
X7R
16V
0.22UF
10%
2
1
C7205
8X9-TH1
20%
270UF
ELEC
16V
CRITICAL
2
1
C7225
270UF
ELEC
16V
CRITICAL
8X9-TH1
20%
2
1
C7245
270UF
20%
ELEC
16V
8X9-TH1
CRITICAL
7
1
11
4
9
10
8
3
6
5
2
U7221
ISL6612
CRITICAL
QFN1
7
1
11
4
9
10
8
3
6
5
2
U7241
ISL6612
CRITICAL
QFN1
21
L7201
CRITICAL
0.36UH-35A
MSQ1208-TH
21
L7221
CRITICAL
0.36UH-35A
MSQ1208-TH
21
L7241
CRITICAL
MSQ1208-TH
0.36UH-35A
2
1C7210
0.001UF
X7R
50V
10%
402
2
1C7230
0.001UF
X7R
50V
402
10%
2
1C7231
0.001UF
X7R
50V
10%
402
2
1C7250
10%
X7R
50V
402
0.001UF
2
1C7251
10%
0.001UF
X7R
50V
402
2
1
C7263
POLY
2V
20%
330UF-0.0045OHM
CASE-D2-SM
2
1
C7264
POLY
2V
20%
330UF-0.0045OHM
CASE-D2-SM
2
1
C7262
POLY
2V
20%
330UF-0.0045OHM
CASE-D2-SM
2
1
C7260
POLY
2V
20%
330UF-0.0045OHM
CASE-D2-SM
2
1
C7261
POLY
2V
20%
330UF-0.0045OHM
CASE-D2-SM
3
46
5
2
1
Q7201
CRITICAL
S1
IRF6710
43
5
7621
Q7202
CRITICAL
IRF6795
DIRECTFET-MX
3
46
5
2
1
Q7221
CRITICAL
S1
IRF6710
3
46
5
2
1
Q7241
CRITICAL
S1
IRF6710
2
1
R7204
1/10W
MF-LF
603
0
5%
43
5
7621
Q7222
CRITICAL
DIRECTFET-MX
IRF6795
43
5
7621
Q7242
CRITICAL
DIRECTFET-MX
IRF6795
65 89
9 8
1
11
4
10
7
6
5
32
U7201
ISL6622
DFN
CRITICAL
2
1C7202
1UF
10%
X5R
603
16V
65 89
2
1C7201
603
16V
10%
1UF
X5R
2
1
R7201
1/10W
603
NOSTUFF
5%
MF-LF
10
2
1
R7202
5%
10
603
MF-LF
1/10W
2
1
R7207
NOSTUFF
0
603
MF-LF
1/10W
5%
2
1R7205
1/10W
5%
0
603
MF-LF
2
1C7200
1UF
603
X5R
10%
16V
VREG: CPU CORE - PHASES 1-3
SYNC_MASTER=K74_MASTER SYNC_DATE=N/A
PPVCORE_S0_CPU_REG1
DIDT=TRUE
VR_CPU_DRV1_UGATE
NET_PHYSICAL_TYPE=VR_CTL_PHY
VR_CPU_PHASE1
NET_PHYSICAL_TYPE=POWER
DIDT=TRUE
VR_CPU_DRV1_LGATE
NET_PHYSICAL_TYPE=VR_CTL_PHY
DIDT=TRUE
NET_PHYSICAL_TYPE=POWER
VR_CPU_PHASE2
DIDT=TRUE
NET_PHYSICAL_TYPE=POWER
VR_CPU_PHASE3
DIDT=TRUE
DIDT=TRUE
VR_CPU_DRV3_LGATE
NET_PHYSICAL_TYPE=VR_CTL_PHY
VR_CPU_DRV3_UGATE
DIDT=TRUE
NET_PHYSICAL_TYPE=VR_CTL_PHY
DIDT=TRUENET_PHYSICAL_TYPE=VR_CTL_PHY
VR_CPU_DRV2_LGATE
NET_PHYSICAL_TYPE=VR_CTL_PHY
VR_CPU_DRV2_UGATE
DIDT=TRUE
VR_CPU_PWM2
NET_PHYSICAL_TYPE=VR_CTL_PHY
VR_CPU_DRV3_VCC
NET_PHYSICAL_TYPE=VR_CTL_PHY
VR_CPU_DRV1_PVCC
NET_PHYSICAL_TYPE=VR_CTL_PHY
DIDT=TRUE
VR_CPU_PH1_SNUB
PPVCORE_S0_CPU_REG
PPVCORE_S0_CPU_REG
NET_PHYSICAL_TYPE=VR_CTL_PHY
VR_CPU_DRV3_UVCC
VR_CPU_PH3_SNUB
DIDT=TRUE
NET_PHYSICAL_TYPE=VR_CTL_PHY
VR_CPU_BOOT1_RC
NET_PHYSICAL_TYPE=VR_CTL_PHY
DIDT=TRUE
VR_CPU_DRV2_VCC
NET_PHYSICAL_TYPE=VR_CTL_PHY
NET_PHYSICAL_TYPE=VR_CTL_PHY
VR_CPU_DRV1_VCC
PPVCORE_S0_CPU_REG3
VR_CPU_DRV2_GDSEL
VR_CPU_DRV3_GDSEL
VR_CPU_PWM3
DIDT=TRUENET_PHYSICAL_TYPE=VR_CTL_PHY
VR_CPU_DRV3_BOOT
DIDT=TRUE
VR_CPU_BOOT2_RC
NET_PHYSICAL_TYPE=VR_CTL_PHY
VR_CPU_BOOT3_RC
NET_PHYSICAL_TYPE=VR_CTL_PHY
DIDT=TRUE
VR_CPU_DRV1_GDSEL
NET_PHYSICAL_TYPE=VR_CTL_PHY DIDT=TRUE
VR_CPU_DRV1_BOOT
NET_PHYSICAL_TYPE=VR_CTL_PHY
VR_CPU_DRV2_PVCC
VR_CPU_DRV3_PVCC
NET_PHYSICAL_TYPE=VR_CTL_PHY
VR_CPU_DRV1_UVCC
NET_PHYSICAL_TYPE=VR_CTL_PHY
VR_CPU_PH2_SNUB
NET_PHYSICAL_TYPE=VR_CTL_PHY
DIDT=TRUE
PPVCORE_S0_CPU_REG2
VR_CPU_DRV2_UVCC
NET_PHYSICAL_TYPE=VR_CTL_PHY
DIDT=TRUE
VR_CPU_DRV2_BOOT
NET_PHYSICAL_TYPE=VR_CTL_PHY
PPVCORE_S0_CPU_REG
PPVCORE_S0_CPU_REG
VR_CPU_ISNS1_N
VR_CPU_ISNS1_P
VR_CPU_ISNS2_N
VR_CPU_ISNS2_P
VR_CPU_ISNS3_N
PP12V_S0_CPU_FLTRD
VR_CPU_ISNS3_P
VR_CPU_PWM1
72 OF 110
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89
89
89
89
89
89
89
89
89
89
89
5 65 66 67
5 65 66 67
89
89
89
89
89
89
89
89
89
89
89
89
89
5 65 66 67
5 65 66 67
65 89
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II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
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PAGE
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B
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87 54 21
2
1C7330
402
0.1UF
20%
10V
CERM
2
1C7331
CERM
10V
20%
0.1UF
402
2
1C7340
X5R
16V
10%
1UF
603
2
1C7341
X5R
16V
10%
1UF
603
2
1C7333
402
0.1UF
20%
10V
CERM
2
1C7332
CERM
10V
20%
0.1UF
402
2
1C7335
402
0.1UF
20%
10V
CERM
2
1C7334
CERM
10V
402
20%
0.1UF
2
1C7337
402
0.1UF
20%
10V
CERM
2
1C7336
CERM
10V
20%
0.1UF
402
2
1C7339
402
0.1UF
20%
10V
CERM
2
1C7338
CERM
10V
20%
0.1UF
402
2
1C7343
603
1UF
10%
16V
X5R
2
1C7342
603
1UF
10%
16V
X5R
2
1C7345
1UF
603
10%
16V
X5R
2
1C7344
603
1UF
10%
16V
X5R
2
1C7347
603
1UF
10%
16V
X5R
2
1C7346
603
X5R
1UF
10%
16V
2
1C7349
603
1UF
10%
16V
X5R
2
1C7348
603
1UF
10%
16V
X5R
VREG: CPU CORE - CAPS
SYNC_MASTER=K74_MASTER SYNC_DATE=N/A
PPVCORE_S0_CPU_REG
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D
G
S
NC
OUT
OUT
IN
SOFT
RBIAS VIN
UGATE
VW
VSS
VSEN
VR_ON
VO
VID1
VID0
THRM_PAD
RTN
PVCC
PHASEPGOOD
PGND
FDE
FB
BOOT
VDD
VID2
VID3
IMON
AF_EN
VDIFF
COMP
LGATE
ICOMP
ISN
OCSET
ISP
NC
S
G
D
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
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REVISION
DRAWING NUMBER SIZE
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R
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SHEET
PAGE TITLE
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21
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
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B
C
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87 54 21
CPU VTT REG 1.1V O/P= PPVTT_S0_CPU_REG
376S0771
OUTPUT BULK DECOUPLING
THESE TWO CAPS ARE FOR EMC
VID<2:0> Voltage
000 +1.100V
1.1V DEFAULT, OTHER VALUES TBD
(CPUVTTS0_VSEN)
(CPUVTTS0_VW)
(CPUVTTS0_COMP)
(CPUVTTS0_VDIFF)
(CPUVTTS0_FB)
(CPUVTTS0_ISP)
(CPUVTTS0_ISN)
(CPUVTTS0_ICOMP)
(CPUVTTS0_RTN)
(CPUVTTS0_VO)
(CPUVTTS0_LGATE)
376S0772
(CPUVTTS0_PHASE)
(CPUVTTS0_UGATE)
(CPUVTTS0_V0)
2
1
C7429
805
22UF
20%
6.3V
CERM-X5R
2
1
R7491
NOSTUFF
1/16W
1%
402
MF-LF
20.0K
2
1
R7492
MF-LF
20.0K
NOSTUFF
1/16W
1%
402
2
1
R7490
1%
MF-LF
1/16W
402
20.0K
43
5
7621
Q7421
IRF6795
DIRECTFET-MX
2
1
R7493
NOSTUFF
402
20.0K
1/16W
MF-LF
1%
2
1
R7494
20.0K
402
MF-LF
1/16W
1%
2
1
R7495
402
MF-LF
1/16W
1%
20.0K
2
1
R7476
402
MF-LF
1/16W
6.65K
1%
21
R7477
1%
56.2K
1/16W
MF-LF
402
21
C7480
33PF
5%
50V
CERM
402
21
C7481
402
0.0022UF
CERM
50V
10%
2
1
R7475
45.3K
402
1%
1/16W
MF-LF
2
1
R7484
402
MF-LF
1%
1/16W
NOSTUFF
20.0K
43
21
R7420
MF
1W
1%
0612
0.0005
50
10 63 64 91
2
1
C7430
402
10%
1UF
X5R
16V
21
R7480
2.2
5%
MF-LF
603
1/10W
2
1
C7465
402
10%
1UF
16V
X5R
NOSTUFF
21
R7467
603
5%
2.2
1/10W
MF-LF
2
1
R7462
5%
1
MF-LF
603
1/10W
2
1
C7463
5%
1000PF
NP0-C0G
25V
402
2
1
R7464
1/16W
MF-LF
1%
1K
402
2
1
R7470
NOSTUFF
402
10K
1/16W
1%
MF-LF
2
1
C7478
10%
0.1UF
25V
X5R
402
2
1
C7473
0.01UF
X7R
10%
402
50V
2
1
C7477
402
0.1UF
10%
25V
X5R
21
R7460
1/10W
5%
603
MF-LF
2.2
21
C7464
603
X7R
0.22UF
16V
10%
2
1
R7469
12.4K
1/16W
402
MF-LF
1%
2
1
C7462
402
X5R
1UF
16V
10%
21
R7474
603
MF-LF
5%
1/10W
0
2
1
R7473
402
1%
10K
1/16W
MF-LF
21
XW7461
SM
OMIT
2
1
C7461
402
1UF
10%
16V
X5R
2
1
R7461
MF-LF
5%
402
1K
1/16W
63 91
2
1
R7463
1/16W
100
402
1%
MF-LF
2
1
C7470
0.001UF
50V
402
X7R
10%
21
R7466
1%
MF-LF
1/16W
402
20
21
R7468
20
1%
MF-LF
402
1/16W
2
1
C7476
16V
10%
402
X7R-CERM
0.1UF
2
1
R7472
150K
1/16W
MF-LF
1%
402
2
1
R7471
MF-LF
100
402
1/16W
1%
2
1
C7479
402
0.001UF
X7R
10%
50V
21
C7482
560PF
10%
50V
CERM
402
21
R7478
100
1/16W
402
MF-LF
1%
21
R7479
1/16W
2.21K
MF-LF
402
1%
2
1
R7483
MF-LF
402
1%
1/16W
20.0K
4
15
8
29
12
14
27
26
25
24
7
16
18
33
2
9
1
22
1931
20
3
21
13
11
28
10
32
6
5
17
30
U7401
CRITICAL
ISL9563A
QFN
2
1
C7424
402
0.01UF
20%
16V
CERM
2
1
C7425
402
CERM
16V
20%
0.01UF
2
1
C7423
X5R
16V
10%
1UF
603
2
1
C7422
CRITICAL
0805
16V
10%
10UF
X5R-CERM
2
1
C7421
10UF
CRITICAL
0805
X5R-CERM
10%
16V
2
1
C7426
CRITICAL
8X9-TH1
270UF
ELEC
16V
20%
2
1
C7420
CRITICAL
270UF
20%
ELEC
8X9-TH1
16V2
1
C7434
6.3X6-TH
POLY
16V
20%
100UF
3
46
5
2
1
Q7420
IRF6710
S1
21
L7420
CRITICAL
MSQ1211R36LF-TH
0.36UH-45A-0.76MOHM
2
1
C7444
CASE-D2-SM
330UF-0.0045OHM
20%
2V
POLY
2
1
C7445
CASE-D2-SM
330UF-0.0045OHM
POLY
2V
20%
2
1
C7446
CASE-D2-SM
POLY
2V
20%
330UF-0.0045OHM
2
1
C7447
CASE-D2-SM
330UF-0.0045OHM
POLY
2V
20%
2
1
C7428
805
22UF
20%
6.3V
CERM-X5R
CPU VTT REGULATOR
SYNC_DATE=12/08/2009SYNC_MASTER=NICK
CPUVTTS0_ISP_R
CPUVTTS0_PHASE
SWITCHNODEMIN_LINE_WIDTH=0.5 MM
SWITCH_NODE=TRUE
MIN_NECK_WIDTH=0.2 MM
DIDT=TRUE
GND_CPUVTTS0_AGND
DIDT=TRUE
0.25 MM
0.2 MM
MCPCORES0_BOOT_R
CPUVTTS0_FB
DIDT=TRUE
MIN_NECK_WIDTH=0.2 MM
MIN_LINE_WIDTH=0.5 MM
CPUVTTS0_PHASE_L PPVTT_S0_CPU_REG
CPUVTTS0_VDIF_C
CPUVTTS0_ISP
CPU_VTTSENSE_P
CPU_VTTSENSE_N
CPUVTT_REG_EN
CPUVTTS0_LGATE
DIDT=TRUE
MIN_LINE_WIDTH=0.5 MM
GATE_NODE=TRUE
MIN_NECK_WIDTH=0.2 MM
PPVTT_S0_CPU_REG
CPUVTTS0_OCSET
PPVTT_S0_CPU_REG
MIN_NECK_WIDTH=0.4MM
MIN_LINE_WIDTH=0.4MM
MCPCORES0_SNUBBER
DIDT=TRUE
CPUVTTS0_COMP_C
VTT_REG_VID3
CPUVTTS0_ISN
CPUVTTS0_ICOMP
CPUVTTS0_VDIFF
0.25 MM
0.2 MM
DIDT=TRUE
CPUVTTS0_BOOT
0.6 mm
0.2 MM
VOLTAGE=12V
PP12V_S0_CPU_VTT_VREG_VIN
CPUVTTS0_UGATE
DIDT=TRUE
MIN_LINE_WIDTH=0.5 MM
GATE_NODE=TRUE
MIN_NECK_WIDTH=0.2 MM
=PP12V_S0_CPU_VTT_VREG
DIDT=TRUE
CPUVTTS0_COMP
CPUVTTS0_SOFT
CPUVTTS0_VW
CPUVTTS0_VSEN
CPUVTTS0_VO
CPUVTTS0_RTN
VTT_REG_VID2
0.2 MM
0.6 mm
VOLTAGE=5V
5V_S0_VTTREG_VIN
MIN_LINE_WIDTH=0.6 mm
VOLTAGE=0V
MIN_NECK_WIDTH=0.2 MM
GND_CPUVTTS0_AGND
0.6 mm
0.2 MM
VOLTAGE=5V
5V_S0_VTTREG_VDD
VTT_REG_VID1
VTT_REG_VID0
CPUVTTS0_FDE
CPUVTTS0_RBIAS
=PP3V3_S0_CPU_VTT_VREG
=PP5V_S0_CPU_VTT_VREG
CPUVTT_REG_PGOOD
CPUVTT_IMON
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VBST
TON
LL
DRVH
DRVL
V5FILT V5DRV
PGNDGND
EN_PSV
VOUT
TRIP
VFB
THRM_PAD
PGOOD
SYM 2
OUT
IN
D1
G1
S2
G2
S1/D2
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
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DRAWING NUMBER SIZE
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NOTICE OF PROPRIETARY PROPERTY:
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B
C
345678
D
B
87 54 21
(PPCHCORE_REG_FB)
376S0801
Vout= 0.75*( 1+R7615/R7616)
AVG = 3A
PEAK = 7.5A
(PP1V05_S0_FB)
OUTPUT BULK DECOUPLING
Vout= 0.75*( 1 + 8.45/21) = 1.05
IBEX PEAK CORE REG 1.05V OUTPUT = PP1V05_S0_REG
PP1V05_S0_REG
VOUT = 1.05V
3
5
14
4 10
11
2
15
6
8
12
7
1
9
13
U7600
QFN
CRITICAL
TPS51117RGY_QFN14
2
1
C7614
1000PF
5%
CERM
NOSTUFF
25V
603
2
1
R7614
NOSTUFF
1%
1/10W
MF
603
0.499
21
L7614
1.0UH-13A-5.6M-OHM
SM-IHLP-1
CRITICAL
2
1
R7615
1/16W
MF-LF
402
1%
8.45K
2
1
C7607
20%
6.3V
POLY-TANT
CASE-D3L-SM
330UF
CRITICAL
2
1
C7609
NOSTUFF
10%
0805
10UF
16V
X5R-CERM
CRITICAL
2
1
C7608
10UF
16V
10%
X5R-CERM
0805
CRITICAL
2
1
R7670
402
MF-LF
5%
1/16W
300
2
1C7670
1UF
402
X5R
16V
10%
21
XW7600
OMIT
SM
2
1
C7612
X5R-CERM
CRITICAL
16V
10UF
0805
10%
63 64 91
63 91
21
XW7601
OMIT
SM
21
XW7614
OMIT
SM
2
1
R7660
402
MF-LF
1%
6.98K
1/16W
21
R7651
MF-LF
1/16W
402
200K
1%
2
1
C7613
16V
10%
0805
X5R-CERM
10UF
CRITICAL
21
C7650
0.1UF
402
25V
10%
X5R
21
R7650
603
5%
MF-LF
1/10W
0
2
1
C7601
10UF
X5R
603
20%
6.3V
2
1
R7680
402
MF-LF
1/16W
1%
10K
2
1
R7616
402
MF-LF
1/16W
1%
21K
543
7
6
1
2
Q7601
RJK0384DPA
CRITICAL
WPAK
2
1
C7620
0.001UF
402
X7R
50V
10%
2
1
C7611
0.1UF
X5R
10%
16V
402
2
1
C7621
0.001UF
402
X7R
50V
10%
2
1
C7610
X5R-CERM
16V
10%
CRITICAL
10UF
0805
SYNC_MASTER=K74_MASTER SYNC_DATE=N/A
IBEX PEAK CORE
OP_1V05_S0_FB
=PP12V_S0_PCH_CORE_VREG
DIDT=TRUE
NET_PHYSICAL_TYPE=POWER
AGND_PCHCORE_REG
PCHCORE_REG_VFB
PP1V05_S0_REG
NET_PHYSICAL_TYPE=POWER
PCHCORE_REG_PGOOD
PCHCORE_REG_EN
PCHCORE_PGND_XW
PCHCORE_REG_TRIP
PCHCORE_REG_PHASE_C
DIDT=TRUE
MIN_NECK_WIDTH=0.2MM
MIN_LINE_WIDTH=0.6MM
PCHCORE_REG_BOOT_R
=PP5V_S0_PCH_CORE_VREG
NET_PHYSICAL_TYPE=POWER
=PP3V3_S0_PCH
PCHCORE_REG_5V_FLT
MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM
DIDT=TRUE
PCHCORE_REG_UGATE
DIDT=TRUE
MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM
PCHCORE_REG_BOOT
PCHCORE_REG_TON
MIN_NECK_WIDTH=0.2MM
DIDT=TRUE
PCHCORE_REG_LGATE
MIN_LINE_WIDTH=0.6MM
SWITCHNODEPCHCORE_REG_PHASE
MIN_NECK_WIDTH=0.2MM
DIDT=TRUE MIN_LINE_WIDTH=0.6MM
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OUT
D1
G1
S2
G2
S1/D2
S
D
G
S
D
G
OUT
UGATE2
VCC2VCC1
PGOOD1
LDO5
UGATE1
BOOT1
PHASE2PHASE1
LGATE2LGATE1
OCSET2OCSET1
ISEN1 ISEN2
VOUT1 VOUT2
FB2
EN1
PGND
THRM
BOOT2
FSET2
EN2
FSET1
FB1
VIN
FCCM
PGOOD2
PAD
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
BRANCH
REVISION
DRAWING NUMBER SIZE
D
R
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
21
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
87 54 21
376S0631
3V3 S5 REGULATOR
PLACE AT Q7330
Vout = 0.6V * (1 + Ra / Rb)
<Rb>
376S0631
EMC: C7763,C7764
PLACE AT L7750.2
Power Rating ?
5V OUTPUT
<Ra>
EMC CAPS
PLACE CLOSE
TO L
RA
(P3V3S5_PHASE)
OUTPUT BULK DECOUPLING:
128S0237
376S0801
EMC: C7754,C7755
(P3V3S5_LGATE)
RB
5V S3 REGULATOR
PLACE CLOSE TO FET
EMC CAPS
3V3 OUTPUT
OUTPUT BULK DECOUPLING:
(P3V3S5_UGATE)
2
1
C7762
330UF
POLY-TANT
CASE-D3L-SM
CRITICAL
20%
6.3V
2
1
R7747
16.5K
1%
1/16W
MF-LF
402
2
1
C7747
0.01UF
402
CERM
16V
10%
2
1
C7777
NOSTUFF
CERM
50V
10%
402
0.001UF
2
1
C7757
402
NOSTUFF
CERM
50V
10%
0.001UF
2
1
C7721
6.3V
CRITICAL
POLY-TANT
CASE-D3L-SM
330UF
20%
2
1
R7723
1/16W
MF-LF
402
33K
5%
2
1
R7722
402
MF-LF
1/16W
68K
5%
63
2
1
R7724
1/16W
MF-LF
402
1%
976
2
1
R7759
402
1/16W
1%
976
MF-LF
2
1
R7755
402
MF-LF
1/16W
1%
75K
5 4 3
7
6
1
2
Q7710
WPAK
RJK0384DPA
321
4
5
Q7750
MLP5X6-LFPAK-Q5A
CSD58851Q5A
CRITICAL
2
1
C7764
10%
402
50V
X7R
0.001UF
321
4
5
Q7751
CSD58851Q5A
CRITICAL
MLP5X6-LFPAK-Q5A
2
1
C7722
10%
0.1UF
16V
402
X5R
2
1
C7718
100UF
20%
16V
POLY
6.3X6-TH
2
1
C7719
100UF
20%
POLY
16V
6.3X6-TH
2
1
C7763
50V
402
X7R
10%
0.001UF
2
1
C7783
20%
1210
22UF
16V
X7R 2
1
C7752
16V
10%
10UF
X5R-CERM
0805
2
1
C7751
10%
16V
X5R-CERM
10UF
0805
2
1
C7766
270UF
20%
16V
ELEC
8X9-TH1
21
L7750
PAB0705AR-SM
CRITICAL
2.2UH-10A-12.5MOHM
64
2
1
XW7751SM
OMIT
2
1
C7761
330UF
20%
6.3V
POLY-TANT
CRITICAL
CASE-D3L-SM
2
1
C7760
10UF
6.3V20%
805-1CERM
2
1
C7759
NP0-C0G
1000PF
5%
402
25V
2
1
R7756
10K
1%
1/16W
MF-LF
402
5
4
3
2
1
D7750
TLM833
CRITICAL
CTLSH3-30M833
21
C7756
10%
0.1UF
402
X5R
25V
2
1
C7765
10UF
16V
10%
X5R-CERM
0805
2
1
R7752
NOSTUFF
MF
1/10W1%
603
0.499
21
R7750
603
1/10W
0
5%
MF-LF
2
1
C7711
0.1UF
16V
10%
402
X5R
2
1
C7758
X5R-CERM
16V
10%
10UF
0805
2
1
C7710
10UF
0805
10%
16V
X5R-CERM
2 1
XW7716
PLACEMENT_NOTE=PLACE NEXT TO C7716
OMIT
SM
2
1
C7720
25V
5%
402
1000PF
NP0-C0G
2
1
R7720
MF-LF
1%
402
1/16W
45.3K
2
1
C7755
402
10%
25V
X5R
0.1UF
2
1
R7721
MF
10.0K
402
0.5%
1/16W
2
1
C7712
10UF
16V
0805
10%
X5R-CERM
2
1
C7717
10%
10UF
X5R-CERM
16V
0805
2
1
C7754
25V
402
X5R
0.1UF
10%
2
1
C7715
10%
16V
0805
X5R-CERM
10UF
279
17
45
2214
29
2313
17
19
2511
2016
18
2610
26
3
288
2412
2115
U7700
CRITICAL
ISL62383
QFN
2
1
C7716
CERM
16V
20%
603
0.1UF
2
1
C7723
20%
603
CERM
16V
0.1UF
21
C7790
8200PF
CERM
603
50V
10%
2
1
R7791
402
1%
1/16W
MF-LF
16.5K
2
1
C7730
1000PF
NOSTUFF
NP0-C0G
402
25V
5%
2
1
R7730
NOSTUFF
0.499
1%
1/10W
MF
603
21
C7714
X7R10%
0.1UF
50V 603-1
21
R7710
0
603
5%
1/10W
MF-LF
21
R7790
16.5K
MF-LF
1/16W
1%
402
2
1
C7753
10UF
16V
10%
X5R-CERM
0805
21
R7770
14.3K
1%
402
1/16W
MF-LF
21
C7770
40210%
16V
0.01UF
CERM
2
1
R7771
14.3K
402
MF-LF
1/16W
1%
21
L7710
2.2UH-14A
CRITICAL
MMD06CZ-SM
2
1
C7740
X5R
1UF
10%
603
16V
2
1
C7741
X5R
1UF
10%
16V
603
2
1
R7740
2.2
1/8W
MF-LF
805
5%
2
1
C7742
603
CERM
6.3V
20%
4.7UF
2
1
C7701
402
CERM
0.01UF
16V
10%
2
1
R7701
16.5K
1%
1/16W
MF-LF
402
SYNC_DATE=12/08/2009
5V_S3 / 3V3_S5 VREGS
SYNC_MASTER=NICK
MIN_NECK_WIDTH=0.2MM
GATE_NODE=TRUE
MIN_LINE_WIDTH=0.6MM
P3V3S5_REG_LGATE
DIDT=TRUE
P3V3S5_REG_PGOOD
DIDT=TRUE
P3V3S5_REG_BOOT
MIN_NECK_WIDTH=0.2MM
MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM
MIN_LINE_WIDTH=0.6MM
GATE_NODE=TRUE
DIDT=TRUE
P3V3S5_REG_UGATE
=PP12V_S5_P3V3S5_VREG
NET_PHYSICAL_TYPE=POWER
DIDT=TRUE
DIDT=TRUE
P3V3S5_REG_PHASE
MIN_NECK_WIDTH=0.2MM
MIN_LINE_WIDTH=0.6MM
NET_PHYSICAL_TYPE=POWER
DIDT=TRUE
SWITCHNODE
PP5V_S5_LDO
NET_PHYSICAL_TYPE=POWER
MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2 MM
DIDT=TRUE
P5VS3_REG_UGATE
DIDT=TRUE NET_PHYSICAL_TYPE=POWER
P5VS3_REG_PHASE
DIDT=TRUE
MIN_NECK_WIDTH=0.2 MM
MIN_LINE_WIDTH=0.6MM
SWITCHNODE
P3V3S5_REG_OCSET
P5VS3_REG_PGOOD
P5V_S5_VCC1
P5V_S5_LDO_R
P3V3S5_REG_SNUB
DIDT=TRUE
TP_P5VS3_REG_FCCM
MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2 MM
DIDT=TRUE
P5VS3_REG_BOOT
PP3V3_S5_REG
P5VS5_REG_FB_R
P3V3S5_REG_FB_R
P3V3S5_REG_BOOT_R
MIN_NECK_WIDTH=0.2MM
MIN_LINE_WIDTH=0.6MM
DIDT=TRUE
P5VS3_REG_BOOT_R
DIDT=TRUE
MIN_LINE_WIDTH=0.25MM MIN_NECK_WIDTH=0.2 MM
DIDT=TRUE
MIN_NECK_WIDTH=0.2 MM
MIN_LINE_WIDTH=0.4MM
5V_SNUBBER
P3V3S5_REG_VOUT1
P5VS3_REG_ISEN
P3V3S5_REG_FSET1
P3V3S5_12VE_EN1
P3V3S5_REG_ISEN
P3V3S5_REG_FB
P5VS3_EN
P5VS3_REG_VOUT2
DIDT=TRUE MIN_LINE_WIDTH=0.6MM
P5VS3_REG_LGATE
MIN_NECK_WIDTH=0.2 MM
P5VS3_REG_FSET2
P5VS3_REG_FB
=PP12V_S5_P5VS3_VREG
NET_PHYSICAL_TYPE=POWER
DIDT=TRUE
NET_PHYSICAL_TYPE=POWER
PP5V_S3_REG
P5VS3_REG_OCSET
77 OF 110
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89
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S
D
G
S
D
G
MODE
VDDQSNSCOMP
NC0
NC1
VTTSNS
VTT
VTTREF
PGOOD
S3
S5
VTTGND THRM_PADGND CS_GNDPGND
CS
LL
DRVL
DRVH
VDDQSET
VBST
VLDOINV5FILTV5IN
SYM (2 OF 2)
NC
NC
IN
IN
VIN
LX
VFB
RSI
EN
POR
SKIP
GNDTHRM_PAD
OUT
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
BRANCH
REVISION
DRAWING NUMBER SIZE
D
R
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
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21
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
87 54 21
VDDQ/VTTREF Enable
VTTREFSTATE S3 VDDQ
OFF
1.5 V DDR SUPPLY
VTT Enable
(DDRREG_FB)
(DDRREG_VDDQSNS)
OUTPUT BULK DECOUPLING:
PLACE CLOSE TO L7830
EMC CAPS
PLACE CLOSE TO FET
EMC CAPS
(DDRREG_DRVL)
VTT
ON
SHOULD NOT NEED TP
OFF
ON
OFF
ON
LO
HI
S5
HILO
LO
HIS0
S5
S3
PPDDR_S3_REG
VOUT = 1.5V
PEAK = 11A
AVG = 6.7A
VDDQ PGOOD
(NOT USED)
1.8 V SUPPLY
<Ra>
<Rb>
Vout = 0.75V * (1 + Ra / Rb)
<Ra>
<Rb>
Vo=0.8*(1+ Ra/Rb)
Vo=0.8*(1+ 59/47)=1.804V
ON
ON
(DDRREG_CSGND)
(DDRREG_DRVH)
OFF
10mA max load
Vout = VDDQSNS/2
Vout = VTTREF
FEEDBACK THROUGH SHORT
(DDRREG_LL)
2
1
C7834
20%
16V
CERM
0.1UF
603
2
1
C7837
10UF
20%
6.3V
X5R
6032
1
C7836
CASE-D2-HF
330UF-0.009OHM
2V
20%
POLY
NOSTUFF
CRITICAL
21
L7830
1.5UH-22A-4MOHM
MSQ12111R5LF-TH
CRITICAL
2
1
C7835
330UF-0.009OHM
2V
POLY
CASE-D2-HF
20%
CRITICAL
2
1
C7841
NOSTUFF
5%
25V
402
NP0-C0G
1000PF
321
4
5
Q7830
CSD58851Q5A
CRITICAL
MLP5X6-LFPAK-Q5A
2
1
C7832
X5R-CERM
10%
10UF
0805
16V
2
1
C7833
CERM
16V
603
20%
0.1UF
321
4
5
Q7831
CRITICAL
CSD58850Q5A
MLP5X6-LFPAK-Q5A
2
1
R7831
1%
1/10W
MF
603
NOSTUFF
0.499
21
XW7831PLACEMENT_NOTE=PLACE NEXT TO Q7831
OMIT
SM
21
C7840
0.1UF
20%
603
25V
CERM
21
R7840
MF-LF
5%
1/10W
603
0
2
1
C7815
20%
X5R
603
6.3V
10UF
2
1
C7839
50V
X7R
402
0.001UF
10%
2
1R7810
6.04K
1%
402
MF-LF
1/16W
2
5
1
24
23
8
9
22
15 14
25
11
10
13
18
12
7
4
20
3
19
21
17
16
6
U7800
TPS51116
CRITICAL
QFN
2
1
XW7801
OMIT
SM
2
1
XW7800
SM
OMIT
2
1
C7801
10V
10%
402
X5R
1UF
21
R7801
4.7
5%
1/16W
MF-LF
402
2
1
C7805
10%
16V
X5R
0.033UF
402
2
1
C7800
4.7UF
20%
CERM
6.3V
603
21
XW7803
OMIT
SM
2
1
C7803
6.3V
805-3
CERM-X5R
CRITICAL
22UF
20%
2
1
C7804
6.3V
20%
22UF
CRITICAL
805-3
CERM-X5R
63 91
63
1
6
9
45
3
8
7
2
U7850
ISL8009B
DFN
CRITICAL
2
1
R7853
402
MF-LF
1/16W
5%
100K
2
1
XW7830
PLACEMENT_NOTE=PLACE NEXT TO L7830
OMIT
SM
2
1
R7852
5%
100K
402
MF-LF
1/16W
21
L7850
2.2UH-3.25A-68M-OHM
MMD04BZ-SM
CRITICAL
2
1
R7851
47.0K
1/16W
MF-LF
1%
402
2
1
R7850
1/16W
402
59.0K
1%
MF-LF
2
1
C7850
120PF
5%
CERM
50V
402
2
1
R7832
15.0K
MF-LF
1/16W
1%
402
2
1
C7854
10%
10UF
805
X5R
6.3V
2
1
C7855
10%
10UF
805
X5R
6.3V
5
4 3 2 1
D7831
TLM833
CTLSH3-30M833
CRITICAL
63 91
2
1C7852
CERM
20%
22UF
805
6.3V
2
1C7853
6.3V
805
22UF
20%
CERM
2
1
C7820
100PF
402
CERM
5%
50V
NO STUFF
2
1
C7830
8X9-TH1
ELEC
16V
270UF
20%
CRITICAL
2
1
C7831
8X9-TH1
CRITICAL
270UF
20%
ELEC
16V
2
1
C7851
16V
402
10%
1UF
X5R
2
1
R7833
1/16W
402
15.0K
1%
MF-LF
2
1
C7838
50V
X7R
402
0.001UF
10%
SYNC_DATE=11/30/2009SYNC_MASTER=K23F
1.5V / 1.8V VREGS
NET_PHYSICAL_TYPE=POWER
NET_PHYSICAL_TYPE=POWER
PP1V5_S3_REG
NET_PHYSICAL_TYPE=POWER
SWITCHNODE
MIN_NECK_WIDTH=0.2 mm
DIDT=TRUE
DDR_REG_PHASE
MIN_LINE_WIDTH=0.6 mm
DDR_REG_CS
AGND_DDR_REG
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=0V
PPVTT_S3_DDR_BUF
PPVTT_S0_DDR_LDO
NET_PHYSICAL_TYPE=POWER
=PP5V_S3_DDR_VREG
DIDT=TRUE
MIN_NECK_WIDTH=0.2 mm
MIN_LINE_WIDTH=0.6 mm
DDR_REG_BOOT_R
=PP5V_S0_P1V8_VREG
P1V8_REG_SKIP
DDR_REG_BOOT
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
DIDT=TRUE
MIN_LINE_WIDTH=0.4MM
DIDT=TRUE
MIN_NECK_WIDTH=0.4MM
1V5_SNUBBER
P1V8_REG_POR
MIN_LINE_WIDTH=0.2 mm
DDR_REG_PGND
MIN_NECK_WIDTH=0.2 mm
P1V8_REG_VFB
DDR_REG_FB
P1V8_REG_PHASE
NET_PHYSICAL_TYPE=POWER
DIDT=TRUE
SWITCHNODE
PP1V8_S0_REG
NET_PHYSICAL_TYPE=POWER
DDR_REG_LGATE
DIDT=TRUE
MIN_NECK_WIDTH=0.2 mm
MIN_LINE_WIDTH=0.6 mm
NO_TEST=TRUE
DDR_REG_VTTSNS
DDR_REG_VDDQSNS
MIN_NECK_WIDTH=0.2 mm
MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.2 mm
MIN_LINE_WIDTH=0.2 mm
DDR_REG_CSGND
NET_PHYSICAL_TYPE=POWER
PP5V_S3_DDR_REG_V5FILT
VOLTAGE=5V
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
DDR_REG_UGATE
DIDT=TRUE
MIN_NECK_WIDTH=0.2 mm
MIN_LINE_WIDTH=0.6 mm
DDRVTT_EN
=DDRREG_EN
PM_PGOOD_DDRREG_S3
NET_PHYSICAL_TYPE=POWER
DIDT=TRUE
=PP12V_S5_DDR_VREG
78 OF 110
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5
89
89
89
5
5
89
5
89
89
89
89
89
5
89
89
89
89
89
89
5
www.vinaﬁx.vn

SW
BOOSTVIN
BIAS
SHDN*
GND
NC
FB
PAD
THRM
NC
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
BRANCH
REVISION
DRAWING NUMBER SIZE
D
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IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
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21
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
87 54 21
250mA max output
353S2171
Vout = 1.25V * (1 + Ra / Rb)
<Rb>
<Ra>
3.425V "G3Hot" Supply
Supply needs to guarantee 3.31V delivered to SMC VRef generator
Vout = 3.425
(Switcher limit)
2
1C7910
25V
10%
X5R
10UF
805
6
9
48
5
1
3
2
U7900
CRITICAL
LT3470A
DFN
2
1C7900
0.22UF
X5R
402
20%
6.3V
21
L7900
CRITICAL
33UH
CDPH4D19FHF-SM
2
1
R7901
402
MF-LF
1/16W
1%
200K
2
1C7901
22pF
CERM
5%
50V
402 2
1
R7900
348K
402
1%
1/16W
MF-LF
2
1C7902
X5R-CERM
603
20%
6.3V
22UF
3.42 G3HOT SUPPLY
SYNC_DATE=N/ASYNC_MASTER=K74_MASTER
P3V42G3H_BOOST
SWITCH_NODE=TRUE
MIN_LINE_WIDTH=0.5 mm
DIDT=TRUE
P3V42G3H_SW
MIN_NECK_WIDTH=0.25 mm
P3V42G3H_FB
PP3V42_G3H_REG
PP12V_G3H
79 OF 110
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051-8337
72 OF 92
7
89
89
89
5
5 89
www.vinaﬁx.vn

SD
G
SD
G
SD
G
SD
G
G
PG
THRM
GND
NC
D
VCC
S
ON
PAD
IN
G
PG
THRM
GND
NC
D
VCC
S
ON
PAD
G
PG
THRM
GND
NC
D
VCC
S
ON
PAD
IN
IN
G
PG
THRM
GND
NC
D
VCC
S
ON
PAD
IN
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
BRANCH
REVISION
DRAWING NUMBER SIZE
D
R
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
21
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
87 54 21
3.3V S3 FET (2.9A PK / 1.2A AVG)
5V S0 FET (7A PK/2.7A AVG) 3.3V S0 FET (3.4APK / 1.9A AVG)
1.5V S0 FET (6.2A PK / 3A AVG)
2
1C8050
402
0.1UF
10%
X5R
16V
3
2
1
4
5
Q8000
CRITICAL
MLP3.3X3.3
FDMC8298
3
2
1
4
5
Q8053
FDMC8298
MLP3.3X3.3
CRITICAL
3
2
1
4
5
Q8050
CRITICAL
MLP3.3X3.3
FDMC8298
3
2
1
4
5
Q8025
CRITICAL
MLP3.3X3.3
FDMC8298
1
9
6
8
2
4
7
5
U8053
CRITICAL
SLG5AP001
TDFN
63 91
2
1C8000
0.1UF
10%
16V
X5R
402
1
9
6
8
2
4
7
5
U8000
SLG5AP001
CRITICAL
TDFN
2
1C8025
16V
X5R
10%
0.1UF
402
1
9
6
8
2
4
7
5
U8025
CRITICAL
SLG5AP001
TDFN
63 91
63 91
2
1C8053
402
0.1UF
10%
X5R
16V
1
9
6
8
2
4
7
5
U8050
TDFN
CRITICAL
SLG5AP001
2
1
R8000
402
5%
1/16W
10K
MF-LF
NOSTUFF
2
1
R8050
10K
402
5%
1/16W
MF-LF
2
1
R8051
MF-LF
1/16W
5%
402
10K
2
1
R8020
5%
1/16W
10K
MF-LF
402
63 91
SYNC_MASTER=K74_MASTER SYNC_DATE=N/A
S3+S0 FETS
P5VS0_EN
PGOOD_P3V3_S0
PGOOD_P3V3_S3
=PP12V_S5_PWRCTL
P3V3S0_EN
=PP3V3_S3_PWRCTL
=PP12V_S5_PWRCTL
=PP12V_S5_PWRCTL
PGOOD_P5V_S0
=PP3V3_S0_PWRCTL
P1V5_S0_EN
=PP3V3_S0_PWRCTL
PGOOD_P1V5_S0
=PP12V_S5_PWRCTL
PP5V_S0_FET
=PP5V_S3_S0FET
P5V_S0_EN_G
P3V3_S0_EN_G
=PP3V3_S5_S0FET
PP3V3_S0_FET
P3V3_S3_EN_G
PP3V3_S3_FET
=PP3V3_S5_S3FET
P1V5_S0_EN_G
PP1V5_S0_FET=PPDDR_S3_S0FET
P3V3S3_EN
=PP3V3_S0_PWRCTL
80 OF 110
A.0.0
051-8337
73 OF 92
3
3
3
3
64 91
5 64 73
5 64
5 64 73
5 64 73
63 91
5 63 64 73
5 63 64 73
10 91
5 64 73
5
5
5
5
5
5
5 50 5
5 63 64 73
www.vinaﬁx.vn

3V3
5V
PWR_SRC
(4 OF 4)
PCI-E
DP
(2 OF 4)
PEX_TX15*
DP_A_AUX*
PEX_TX1*
PEX_TX13
PEX_TX11*
PEX_TX7*
PEX_TX8*
PEX_TX9
PEX_TX10
PEX_STD_SW*
PEX_TX15
PEX_TX14*
PEX_TX14
PEX_TX13*
PEX_TX12*
PEX_TX12
PEX_TX11
PEX_TX10*
PEX_TX9*
PEX_TX8
PEX_TX7
PEX_TX6*
PEX_TX6
PEX_TX5*
PEX_TX5
PEX_TX4*
PEX_TX4
PEX_TX3*
PEX_TX3
PEX_TX2*
PEX_TX2
PEX_TX1
PEX_TX0*
PEX_TX0
PEX_REFCLK*
PEX_REFCLK
PEX_RST*
DP_C_HPD
DP_D_HPD
DP_B_HPD
DP_A_HPD
PEX_RX15*
PEX_RX15
PEX_RX14*
PEX_RX14
PEX_RX13*
PEX_RX13
PEX_RX12*
PEX_RX12
PEX_RX11*
PEX_RX11
PEX_RX10*
PEX_RX10
PEX_RX9*
PEX_RX9
PEX_RX8*
PEX_RX8
PEX_RX7*
PEX_RX7
PEX_RX6*
PEX_RX6
PEX_RX5*
PEX_RX5
PEX_RX4*
PEX_RX4
PEX_RX3*
PEX_RX3
PEX_RX2*
PEX_RX2
PEX_RX1*
PEX_RX1
PEX_RX0*
PEX_RX0
CLK_REQ*
DP_C_L0*
DP_C_L0
DP_C_L1*
DP_D_L0*
DP_C_L1
DP_D_L0
DP_C_L2*
DP_D_L1*
DP_C_L2
DP_D_L1
DP_C_L3*
DP_D_L2*
DP_C_L3
DP_D_L2
DP_D_L3*
DP_D_L3
DP_B_L0*
DP_B_L0
DP_B_L1*
DP_A_L0*
DP_B_L1
DP_A_L0
DP_B_L2*
DP_A_L1*
DP_B_L2
DP_A_L1
DP_B_L3*
DP_A_L2*
DP_B_L3
DP_A_L2
DP_A_L3*
DP_A_L3
DP_C_AUX*
DP_C_AUX
DP_D_AUX*
DP_D_AUX
DP_B_AUX*
DP_B_AUX
DP_A_AUX
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
BRANCH
REVISION
DRAWING NUMBER SIZE
D
R
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
21
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
87 54 21
- MXM
- =PPV_S0_MXM_PWRSRC
Power aliases required by this page:
5V
3V3 1.0 A
2.5 A
UP TO 10 A
CURRENT POWER
3.3 W
12.5 W
(NONE)
- =PP5V_S0_MXM
PWR (7-20V)
VOLTAGE
MXM SPEC POWER REQUIREMENTS
(NOT NECESSARILY THE SAME FOR EVERY MODULE)
PLATFORM DEPENDENT
- =PP3V3_S0_MXM
BOM options provided by this page:
APPLE P/N: 516S0699
Signal aliases required by this page:
Page Notes
2
1
C8400
22UF
35V
ELEC
6.3X5.5-SM1
20%
MXM
2
1C8401
805-3
CERM-X5R
MXM
6.3V
20%
22UF
2
1C8410
0.001UF
MXM
10%
X7R
402
50V
2
1C8412
MXM
X7R
10%
402
50V
0.001UF
2
1C8413
MXM
402
X7R
10%
50V
0.001UF
2
1C8414
MXM
X7R
10%
402
50V
0.001UF
2
1
R8400
100K
402
1/16W
5%
MF-LF
MXM
2
1C8416
805-3
CERM-X5R
MXM
6.3V
20%
22UF
2
1C8415
MXM
10%
X7R
402
50V
0.001UF
E2
E1
9
7
5
3
1
280
278
J8400
F-RT-SM
MXM
B35P101-0121
84
86
90
92
96
98
102
104
108
110
114
116
120
122
136
138
48
50
54
56
60
62
66
68
72
74
78
80
142
144
148
150
19
85
87
91
93
97
99
103
105
109
111
115
117
121
123
135
137
49
51
55
57
61
63
67
69
73
75
79
81
141
143
147
149
156
153
155
224
226
218
220
212
214
206
208
236
230
232
217
219
211
213
205
207
199
201
234
223
225
264
266
258
260
252
254
246
248
274
270
272
271
273
265
267
259
261
253
255
276
277
279
154
J8400
CRITICAL
F-RT-SM
MXM
B35P101-0121
SYNC_MASTER=K23F SYNC_DATE=11/30/2009
MXM PCIe, DP & Power
MXM_PCIE_STD_SWING_L
MXM_RESET_L
MXM_PCIE_D2R_P<1>
MXM_PCIE_D2R_N<6>
MXM_PCIE_D2R_N<10>
MXM_PCIE_D2R_N<11>
MXM_DP_A_ML_P<0>
MXM_DP_A_ML_N<1>
MXM_DP_A_ML_P<1>
MXM_DP_A_ML_N<2>
MXM_DP_A_ML_P<2>
MXM_PCIE_D2R_N<2>
MXM_PCIE_D2R_N<9>
MXM_PCIE_D2R_P<7>
MXM_PCIE_D2R_P<5>
MXM_PCIE_D2R_N<5>
MXM_PCIE_D2R_P<6>
MXM_PCIE_D2R_P<12>
MXM_PCIE_D2R_N<12>
MXM_PCIE_D2R_N<13>
MXM_PCIE_D2R_P<15>
MXM_PCIE_D2R_P<10>
MXM_PCIE_D2R_P<9>
MXM_PCIE_D2R_N<8>
MXM_PCIE_D2R_P<4>
MXM_PCIE_D2R_N<7>
MXM_PCIE_D2R_P<11>
MXM_PCIE_D2R_P<13>
MXM_PCIE_D2R_N<14>
MXM_PCIE_D2R_P<14>
MXM_PCIE_D2R_N<15>
MXM_PCIE_D2R_P<8>
MXM_PCIE_D2R_P<3>
MXM_PCIE_D2R_N<3>
MXM_PCIE_D2R_N<4>
MXM_PCIE_D2R_P<2>
MXM_PCIE_D2R_N<1>
MXM_PCIE_D2R_P<0>
MXM_PCIE_D2R_N<0>
MXM_PCIE_R2D_N<2>
MXM_PCIE_R2D_P<2>
MXM_PCIE_R2D_P<3>
MXM_PCIE_R2D_N<3>
MXM_PCIE_R2D_N<4>
MXM_PCIE_R2D_N<5>
MXM_PCIE_R2D_P<5>
MXM_PCIE_R2D_N<6>
MXM_PCIE_R2D_P<8>
MXM_PCIE_R2D_N<1>
MXM_PCIE_R2D_P<10>
MXM_PCIE_R2D_N<10>
MXM_PCIE_R2D_N<9>
MXM_PCIE_R2D_N<8>
MXM_PCIE_R2D_P<6>
MXM_PCIE_R2D_P<0>
MXM_PCIE_R2D_N<11>
MXM_PCIE_R2D_P<12>
MXM_PCIE_R2D_P<13>
MXM_PCIE_R2D_P<14>
MXM_PCIE_R2D_N<14>
MXM_PCIE_R2D_P<15>
MXM_PCIE_R2D_N<15>
MXM_PCIE_R2D_P<7>
MXM_PCIE_R2D_P<11>
MXM_PCIE_R2D_N<13>
MXM_PCIE_R2D_N<12>
MXM_PCIE_R2D_P<9>
MXM_PCIE_R2D_P<1>
MXM_PCIE_R2D_P<4>
MXM_PCIE_R2D_N<7>
MXM_PCIE_R2D_N<0>
MXM_DP_C_AUX_P
MXM_DP_B_ML_N<0>
MXM_CLKREQ_L
MXM_DP_B_AUX_P
MXM_DP_B_HPD
MXM_DP_B_ML_P<0>
CLK_100M_MXM_N
CLK_100M_MXM_P
MXM_DP_C_HPD
MXM_DP_D_HPD
MXM_DP_A_HPD
MXM_DP_C_ML_N<0>
MXM_DP_C_ML_P<0>
MXM_DP_C_ML_N<1>
MXM_DP_D_ML_N<0>
MXM_DP_C_ML_P<1>
MXM_DP_D_ML_P<0>
MXM_DP_C_ML_N<2>
MXM_DP_D_ML_N<1>
MXM_DP_C_ML_P<2>
MXM_DP_D_ML_P<1>
MXM_DP_C_ML_N<3>
MXM_DP_D_ML_N<2>
MXM_DP_C_ML_P<3>
MXM_DP_D_ML_P<2>
MXM_DP_D_ML_N<3>
MXM_DP_D_ML_P<3>
MXM_DP_B_ML_N<1>
MXM_DP_A_ML_N<0>
MXM_DP_B_ML_P<1>
MXM_DP_B_ML_N<2>
MXM_DP_B_ML_P<2>
MXM_DP_B_ML_N<3>
MXM_DP_B_ML_P<3>
MXM_DP_A_ML_N<3>
MXM_DP_A_ML_P<3>
MXM_DP_C_AUX_N
MXM_DP_D_AUX_N
MXM_DP_D_AUX_P
MXM_DP_B_AUX_N
=PP3V3_S0_MXM
MXM_DP_A_AUX_N
MXM_DP_A_AUX_P
=PPV_S0_MXM_PWRSRC
=PP3V3_S0_MXM
=PP5V_S0_MXM
84 OF 110
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051-8337
74 OF 92
75
8
76 84
76 84
76 84
76 84
80 87
80 87
80 87
80 87
80 87
76 84
76 84
76 84
76 84
76 84
76 84
76 84
76 84
76 84
76 84
76 84
76 84
76 84
76 84
76 84
76 84
76 84
76 84
76 84
76 84
76 84
76 84
76 84
76 84
76 84
76 84
76 84
76 84
76 84
76 84
76 84
76 84
76 84
76 84
76 84
76 84
76 84
76 84
76 84
76 84
76 84
76 84
76 84
76 84
76 84
76 84
76 84
76 84
76 84
76 84
76 84
76 84
76 84
76 84
76 84
76 84
76 84
76 84
76 84
76 84
80 87
77 87
8
77 87
77
77 87
8
8
80
77
80
80 87
80 87
80 87
77 87
80 87
77 87
80 87
77 87
80 87
77 87
80 87
77 87
80 87
77 87
77 87
77 87
77 87
80 87
77 87
77 87
77 87
77 87
77 87
80 87
80 87
80 87
77 87
77 87
77 87
5 64 74 75
80 87
80 87
50
5 64 74 75
5
www.vinaﬁx.vn

GPIO0
VGA_DISABLE*
TH_OVERT*
TH_PWM
LVDS_DDC_CLK
LVDS_UTX1
LVDS_UTX2*
RSVD1
PNL_PWR_EN
LVDS_UTX1*
RSVD2
LVDS_UTX2
LVDS_UTX3*
LVDS_LCLK
PRSNT_R*
LVDS_LTX3
DVI_HPD
PWR_EN
SMB_CLK
LVDS_LTX0
LVDS_LTX0*
LVDS_LTX1
LVDS_LTX2
LVDS_LTX2*
LVDS_LTX3*
LVDS_UTX0
LVDS_UTX0*
LVDS_UTX3
PNL_BL_EN
PRSNT_L*
PWRGOOD
VGA_BLUE
VGA_GREEN
VGA_HSYNC
VGA_RED
VGA_VSYNC
VGA_DDC_DAT
GPIO1
GPIO2
HDMI_CEC
OEM0
OEM1
OEM2
OEM3
OEM4
OEM5
OEM7
VGA_DDC_CLK
RSVD3
RSVD4
RSVD5
RSVD7
RSVD8
RSVD9
RSVD10
RSVD11
RSVD12
RSVD13
RSVD14
RSVD15
RSVD16
RSVD17
RSVD18
RSVD19
RSVD21
SMB_DAT
TH_ALERT*
LVDS_UCLK*
LVDS_UCLK
RSVD20
LVDS_LCLK*
LVDS_LTX1*
RSVD6
RSVD0
RSVD22
RSVD23
PWR_LEVEL
LVDS_DDC_DAT
PNL_BL_PWM
OEM6
WAKE*
SYSTEM MANAGEMENT
(1 OF 4)
LVDS
ANALOG DISPLAY
POWER/THERMAL
MANAGEMENT
GNDGND
(3 OF 4)
SCL
THRM_PAD
E0
E1
E2
VSS
SDA
VCC
WC*
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
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PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
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B
87 54 21
I2C ADDRESS: A8
- =PP3V3_S0_MXM
MXM SYSTEM INFORMATION ROM
STUFF FOR WRITE PROTECT
PLACE CLOSE TO J8400
FLOAT = LOW SWING
GND = HIGH SWING
Signal aliases required by this page:
Page Notes
Power aliases required by this page:
- =PM_MXM_PGOOD_PULLUP
BOM options provided by this page:
PULLED TO GROUND ON MXM
WE DON’T USE CARD DETECT
OR ANOTHER OPEN-DRAIN PGOOD SIGNAL DEPENDING ON DESIRED BEHAVIOR
SYSTEM INTEGRATOR MUST ALIAS THIS EITHER TO A VOLTAGE RAIL,
- =SMB_MXM_THRM_CLK
- =SMB_MXM_THRM_DATA PULLUPS & PULLDOWNS AT MXM CONNECTOR
FLOAT = NORMAL VGA MODE
GND = SECONDARY DISPLAY CARD
2
1
R8570
NOSTUFF
0
402
5%
1/16W
MF-LF
2
1C8570
402
CERM
20%
10V
0.1UF
MXM
21
R8500
100K
1/16W5%
402
MF-LF
21
R8501
100K
5%MF-LF 1/16W
402
21
R8503
402
MF-LF5%
10K
1/16W
4
162
168
164
170
21
158
160
172
24
20
22
32
34
231
229
227
167
165
163
161
16
14
249
247
12
245
243
242
241
240
239
238
237
235
233
159
10
6
18
8
2
281
23
27
25
45
44
43
42
41
40
39
38
175
177
181
183
187
189
193
195
169
171
182
184
188
190
194
196
200
202
176
178
33
35
29
30
28
2631
J8400
B35P101-0121
MXM
F-RT-SM
53
52
283
282
E4
275
269
268
263
47
262
257
256
251
250
E3
244
228
222
221
46
216
215
210
209
204
203
198
197
192
191
37
186
185
180
179
174
173
166
157
152
151
36
146
145
140
139
134
133
125
124
119
118
17
113
112
107
106
101
100
95
94
89
88
15
83
82
77
76
71
70
65
64
59
58
13
11
J8400
F-RT-SM
MXM
B35P101-0121
21
R8504
MXM
0
402
5%MF-LF 1/16W
21
R8510
NOSTUFF
0
5%
402
MF-LF 1/16W
7
4
8
9
5
6
3
2
1
U8570
MXM
M24C02
MLP8
CRITICAL
2
1
R8575
4.7K
MF-LF
1/16W
5%
402
2
1
R8576
402
5%
1/16W
MF-LF
4.7K
SYNC_MASTER=K74_MASTER
MXM I/O
SYNC_DATE=N/A
MXM_LVDS_A_CLK_P
TP_MXM_WAKE_L
PM_MXM_PGOOD
MXM_VGA_DISABLE_L
MXM_PCIE_STD_SWING_L
TP_MXM_VGA_GREEN
MXM_PNL_BL_EN
MXM_DETECT_R
=PP3V3_S0_MXM
MXM_LVDS_A_DATA_N<0>
MXM_LVDS_A_DATA_P<0>
MXM_VGA_DISABLE_L
MXM_DETECT_L
PM_MXM_EN
MXM_PWR_LEVEL
=SMB_MXM_THRM_SCL
=SMB_MXM_THRM_SDA
MXM_DETECT_L
MXM_LVDS_A_DATA_N<1>
MXM_LVDS_A_DATA_P<1>
MXM_LVDS_A_DATA_P<2>
MXM_LVDS_A_DATA_N<3>
MXM_LVDS_A_DATA_P<3>
MXM_LVDS_B_CLK_P
MXM_LVDS_B_CLK_N
MXM_LVDS_B_DATA_P<3>
MXM_LVDS_B_DATA_N<3>
MXM_LVDS_B_DATA_N<2>
MXM_LVDS_B_DATA_P<1>
MXM_LVDS_B_DATA_N<1>
MXM_LVDS_B_DATA_P<0>
MXM_LVDS_B_DATA_N<0>
MXM_LVDS_B_DATA_P<2>
PM_MXM_PGOOD
MXM_LVDS_A_DATA_N<2>
TP_MXM_VGA_BLUE
TP_MXM_VGA_RED
TP_MXM_VGA_DDC_DAT
TP_MXM_VGA_DDC_CLK
TP_MXM_TH_PWM
MXM_LVDS_A_CLK_N
TP_MXM_DVI_HPD
MXM_LVDS_DDC_DAT
MXM_LVDS_DDC_CLK
TP_MXM_GPIO0
TP_MXM_GPIO1
TP_MXM_GPIO2
TP_MXM_HDMI_CEC
=PM_MXM_PGOOD_PULLUP
MXM_PNL_PWR_EN
MXM_PNL_BL_PWM
MXM_ALERT_L
MXM_OVERT_L
TP_MXM_VGA_VSYNC
MXM_LVDS_DDC_CLK
MXM_ROM_WP
MXM_DETECT_R
MXM_LVDS_DDC_DAT
TP_MXM_VGA_HSYNC
=PP3V3_S0_MXM
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77 87
77 87
77 87
77 87
77 87
77 87
77 87
77 87
77 87
77 87
77 87
77 87
77 87
77 87
64 75 91
77 87
77 87
75
75
64
77
80
47
47
75
75
75
5 64 74 75
www.vinaﬁx.vn

OUT
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OUT
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
OUT
IN
IN
IN
IN
IN
OUT
IN
IN
IN
IN
IN
IN
OUT
IN
IN
IN
OUT
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OUT
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
OUT
OUT
OUT
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
BRANCH
REVISION
DRAWING NUMBER SIZE
D
R
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
21
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
87 54 21
MXM RX CAPS
MXM TX CAPS
8 84
21C8636
MXM
16V 402
0.1UF
X5R10%
74 84
74 84
21C8600
MXM
10% X5R
0.1UF
16V 402
21C8602
MXM 0.1UF
16V10% X5R 402
21C8601
MXM
40210% X5R16V
0.1UF
21C8604
MXM
16V 402X5R
0.1UF
10%
21C8603
MXM
16V10% X5R 402
0.1UF
8 84
8 84
8 84
74 84
8 84
8 84
21C8605
MXM
16V X5R
0.1UF
40210%
74 84
74 84
74 84
74 84
74 84
74 84
74 84
74 84
74 84
74 84
74 84
74 84
74 84
74 84
74 84
74 84
74 84
74 84
74 84
74 84
74 84
74 84
74 84
74 84
74 84
74 84
74 84
74 84
74 84
74 84
21C8606
MXM
X5R
0.1UF
40216V10%
21C8607
MXM
402
0.1UF
16V10% X5R
21C8608 10%
0.1UF
402X5R16V
MXM
21C8609
MXM 0.1UF
402X5R16V10%
21C8610
MXM
402X5R10% 16V
0.1UF
21C8611
MXM
402X5R16V10%
0.1UF
21C8612
MXM
16V 402
0.1UF
X5R10%
21C8613
MXM 0.1UF
402X5R16V10%
21C8614
MXM 0.1UF
402X5R10% 16V
21C8615
MXM 0.1UF
402X5R10% 16V
74 84
21C8616
MXM
402X5R10% 16V
0.1UF
21C8618
MXM 0.1UF
402X5R10% 16V
21C8617
MXM 0.1UF
402X5R10% 16V
21C8620
MXM 0.1UF
402X5R10% 16V
21C8619
MXM 0.1UF
402X5R10% 16V
21C8622
MXM
16V10% X5R 402
0.1UF
21C8621
MXM 0.1UF
402X5R10% 16V
8 84
8 84
8 84
21C8637
MXM
16V 402X5R
0.1UF
10%
8 84
8 84
8 84
8 84
8 84
8 84
8 84
8 84
8 84
8 84
8 84
8 84
8 84
8 84
8 84
8 84
21C8623
MXM
16V10% X5R 402
0.1UF
21C8624
MXM 0.1UF
402X5R10% 16V
21C8625
MXM 0.1UF
402X5R10% 16V
21C8626
MXM
16V10% X5R 402
0.1UF
21C8628
MXM 0.1UF
16V10% X5R 402
8 84
21C8627
MXM
16V10% X5R 402
0.1UF
21C8630
MXM
16V10% X5R 402
0.1UF
21C8629
MXM
16V10% X5R 402
0.1UF
21C8631
MXM
16V10% X5R 402
0.1UF
8 84
8 84
8 84
8 84
8 84
8 84
8 84
8 84
8 84
8 84
8 84
8 84
8 84
8 84
8 84
8 84
8 84
8 84
8 84
8 84
8 84
8 84
8 84
8 84
8 84
8 84
8 84
8 84
8 84
8 84
8 84
8 84
8 84
8 84
8 84
8 84
8 84
21C8638
MXM
16V 40210% X5R
0.1UF
21C8639
MXM
16V10% X5R 402
0.1UF
21C8641
MXM
10% X5R 40216V
0.1UF
21C8640
MXM
16V X5R10% 402
0.1UF
21C8642
MXM
16V10% X5R 402
0.1UF
21C8643
MXM 0.1UF
16V10% X5R 402
8 84
21C8644
MXM
16V10% X5R 402
0.1UF
21C8645
MXM 0.1UF
16V10% X5R 402
21C8646
MXM
16V10% X5R 402
0.1UF
21C8647
MXM
X5R 40216V10%
0.1UF
21C8648
MXM
402X5R10% 16V
0.1UF
21C8649
MXM 0.1UF
X5R10% 16V 402
21C8652
MXM 0.1UF
402X5R10% 16V
21C8653
MXM 0.1UF
402X5R10% 16V
21C8651
MXM
402X5R10% 16V
0.1UF
21C8650
MXM
402X5R10% 16V
0.1UF
21C8632
MXM
X5R16V10% 402
0.1UF
74 84
74 84
74 84
74 84
74 84
74 84
74 84
74 84
74 84
74 84
21C8633
MXM
X5R16V10% 402
0.1UF
74 84
74 84
74 84
74 84
74 84
74 84
74 84
21C8654
MXM
402
0.1UF
X5R10% 16V
21C8655
MXM
402
0.1UF
X5R10% 16V
21C8657
MXM
10%
0.1UF
402X5R16V
21C8635
MXM
X5R
0.1UF
40210% 16V
21C8656
MXM
16V
0.1UF
402X5R10%
21C8658
0.1UF
402X5R10% 16V
MXM
21C8662
MXM 0.1UF
40210% X5R16V
21C8663
MXM 0.1UF
402X5R10% 16V
21C8660
MXM 0.1UF
10% 402X5R16V
21C8659
MXM 0.1UF
402X5R10% 16V
21C8661
MXM 0.1UF
402X5R10% 16V
74 84
74 84
74 84
21C8634
MXM
X5R
0.1UF
10% 40216V
74 84
74 84
74 84
74 84
74 84
74 84
74 84
74 84
74 84
74 84
SYNC_DATE=11/30/2009SYNC_MASTER=K23F
MXM PCIE CAPS
PEG_R2D_C_N<1>
PEG_R2D_C_N<2>
PEG_R2D_C_P<3>
MXM_PCIE_R2D_P<9>
MXM_PCIE_R2D_P<8>
MXM_PCIE_D2R_P<3>
MXM_PCIE_D2R_N<3>
MXM_PCIE_D2R_P<2>
MXM_PCIE_D2R_N<2>
PEG_D2R_P<14>
MXM_PCIE_D2R_N<5>
PEG_R2D_C_P<4>
MXM_PCIE_R2D_N<14>
PEG_R2D_C_P<11>
PEG_R2D_C_N<13>
PEG_R2D_C_N<15>
MXM_PCIE_R2D_P<11>
MXM_PCIE_R2D_N<11>
MXM_PCIE_D2R_N<15>
PEG_D2R_N<0>
PEG_D2R_N<3>
PEG_D2R_N<12>
PEG_D2R_N<10>
PEG_R2D_C_N<5>
MXM_PCIE_D2R_P<4>
MXM_PCIE_D2R_N<1>
MXM_PCIE_D2R_P<0>
MXM_PCIE_D2R_N<0>
MXM_PCIE_D2R_P<1>
MXM_PCIE_D2R_P<13>
MXM_PCIE_D2R_N<13>
MXM_PCIE_D2R_P<12>
MXM_PCIE_D2R_N<12>
MXM_PCIE_R2D_N<15>PEG_R2D_C_N<0>
MXM_PCIE_R2D_P<14>
MXM_PCIE_R2D_P<12>
MXM_PCIE_R2D_N<10>
PEG_R2D_C_P<13>
PEG_R2D_C_P<14>
PEG_R2D_C_N<14>
PEG_R2D_C_P<15>
MXM_PCIE_R2D_P<15>
MXM_PCIE_R2D_P<13>
MXM_PCIE_R2D_N<12>
MXM_PCIE_D2R_N<14>
MXM_PCIE_D2R_P<14>
MXM_PCIE_R2D_P<10>
PEG_R2D_C_P<10>
MXM_PCIE_R2D_P<5>
PEG_D2R_P<4>
PEG_R2D_C_N<12>
PEG_R2D_C_P<12>
PEG_R2D_C_N<10>
PEG_R2D_C_P<5>
PEG_R2D_C_P<6>
PEG_R2D_C_N<6>
PEG_R2D_C_P<7>
PEG_R2D_C_P<8>
PEG_R2D_C_N<8>
PEG_R2D_C_N<11>
PEG_R2D_C_N<9>
PEG_R2D_C_P<9>
PEG_R2D_C_N<7>
MXM_PCIE_R2D_N<5>
MXM_PCIE_R2D_P<4>
MXM_PCIE_R2D_N<4>
MXM_PCIE_R2D_N<3>
MXM_PCIE_R2D_P<3>
MXM_PCIE_R2D_P<2>
MXM_PCIE_R2D_N<2>
MXM_PCIE_R2D_N<1>
MXM_PCIE_R2D_P<1>
MXM_PCIE_R2D_N<0>
MXM_PCIE_R2D_N<9>
MXM_PCIE_R2D_N<8>
MXM_PCIE_R2D_P<7>
MXM_PCIE_R2D_N<7>
MXM_PCIE_R2D_P<6>
MXM_PCIE_R2D_N<6>
MXM_PCIE_R2D_P<0>
MXM_PCIE_D2R_P<8>
MXM_PCIE_D2R_P<7>
MXM_PCIE_D2R_P<5>
MXM_PCIE_D2R_N<8>
MXM_PCIE_D2R_N<9>
MXM_PCIE_D2R_P<9>
MXM_PCIE_D2R_N<10>
MXM_PCIE_D2R_P<10>
MXM_PCIE_D2R_N<11>
MXM_PCIE_D2R_P<11>
PEG_D2R_P<7>
PEG_D2R_P<12>
PEG_D2R_N<6>
PEG_D2R_N<7>
PEG_D2R_P<10>
PEG_D2R_N<14>
PEG_D2R_N<4>
PEG_D2R_N<9>
PEG_D2R_P<9>
PEG_D2R_N<11>
PEG_D2R_P<13>
PEG_D2R_N<13>
PEG_D2R_P<15>
PEG_D2R_N<15>
PEG_D2R_P<5>
PEG_D2R_N<5>
PEG_D2R_P<11>
PEG_D2R_P<6>
PEG_D2R_P<2>
PEG_D2R_N<2>
MXM_PCIE_R2D_N<13>
PEG_D2R_P<3>
MXM_PCIE_D2R_N<4>
MXM_PCIE_D2R_P<15>
PEG_D2R_P<1>
PEG_D2R_N<1>
PEG_D2R_P<0>
MXM_PCIE_D2R_N<7>
MXM_PCIE_D2R_N<6>
MXM_PCIE_D2R_P<6>
PEG_D2R_P<8>
PEG_D2R_N<8>
PEG_R2D_C_P<0>
PEG_R2D_C_N<4>
PEG_R2D_C_N<3>
PEG_R2D_C_P<2>
PEG_R2D_C_P<1>
86 OF 110
A.0.0
051-8337
76 OF 92
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OUTIN
IN
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
BRANCH
REVISION
DRAWING NUMBER SIZE
D
R
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
21
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
87 54 21
DISPLAY AUDIO MUX NOT USED - SEND SPDIF TO CODEC
UNUSED MXM CONTROL SIGNALS
Page Notes
BOM options provided by this page:
(NONE)
Power aliases required by this page:
(NONE)
Signal aliases required by this page:
Unused MXM DP Interfaces
Unused MXM Interfaces
56 60 85
78
SYNC_MASTER=K74_MASTER SYNC_DATE=N/A
Display: Aliases
MXM_LVDS_B_DATA_N<3>
MXM_LVDS_A_DATA_P<3>
MXM_LVDS_B_CLK_N
NO_TEST=TRUEMAKE_BASE=TRUE
NC_MXM_LVDS_B_CLK_P
NC_MXM_LVDS_A_DATA_P<3>
NO_TEST=TRUEMAKE_BASE=TRUE
NC_MXM_PNL_PWR_EN
NO_TEST=TRUEMAKE_BASE=TRUE
MXM_LVDS_B_DATA_N<0>
NO_TEST=TRUE
NC_MXM_LVDS_B_DATA_N<1>
MAKE_BASE=TRUE
NC_MXM_PNL_BL_EN
MAKE_BASE=TRUE NO_TEST=TRUE
NO_TEST=TRUE
NC_MXM_DP_D_HPD
MAKE_BASE=TRUE
MXM_DP_D_HPD
MXM_DP_B_ML_P<0..3>
NO_TEST=TRUE
NC_MXM_LVDS_B_DATA_N<0>
MAKE_BASE=TRUE
NC_MXM_LVDS_B_DATA_P<0>
NO_TEST=TRUEMAKE_BASE=TRUE
MXM_DP_D_AUX_N
MAKE_BASE=TRUE NO_TEST=TRUE
NC_MXM_DP_D_ML_N<0..3>
MAKE_BASE=TRUE
NC_MXM_DP_D_AUX_P
NO_TEST=TRUE
MXM_LVDS_A_CLK_P
MXM_LVDS_A_DATA_N<0>
MXM_LVDS_B_DATA_P<3>
MXM_LVDS_B_DATA_P<2>
NO_TEST=TRUE
NC_MXM_LVDS_B_DATA_N<3>
MAKE_BASE=TRUE
MXM_LVDS_B_DATA_N<2>
MXM_LVDS_B_DATA_N<1>
MXM_LVDS_B_DATA_P<1>
MXM_LVDS_B_DATA_P<0>
MXM_LVDS_B_CLK_P
MAKE_BASE=TRUE NO_TEST=TRUE
NC_MXM_LVDS_B_CLK_N
MXM_LVDS_A_DATA_P<2>
MAKE_BASE=TRUE NO_TEST=TRUE
NC_MXM_LVDS_A_DATA_P<2>
MXM_LVDS_A_DATA_N<3>
NO_TEST=TRUE
NC_MXM_LVDS_A_DATA_N<3>
MAKE_BASE=TRUE
MXM_LVDS_A_DATA_N<2>
NO_TEST=TRUEMAKE_BASE=TRUE
NC_MXM_LVDS_A_DATA_N<2>
MXM_LVDS_A_DATA_N<1>
MAKE_BASE=TRUE NO_TEST=TRUE
NC_MXM_LVDS_A_DATA_N<1>
NO_TEST=TRUEMAKE_BASE=TRUE
NC_MXM_LVDS_A_DATA_P<1>
MAKE_BASE=TRUE NO_TEST=TRUE
NC_MXM_LVDS_A_DATA_N<0>
MXM_LVDS_A_DATA_P<0>
MAKE_BASE=TRUE NO_TEST=TRUE
NC_MXM_LVDS_A_DATA_P<0>
NO_TEST=TRUE
NC_MXM_LVDS_A_CLK_P
MAKE_BASE=TRUE
MXM_LVDS_A_CLK_N
NO_TEST=TRUE
NC_MXM_LVDS_A_CLK_N
MAKE_BASE=TRUE NC_MXM_DP_B_ML_P<0..3>
MAKE_BASE=TRUE NO_TEST=TRUE
MAKE_BASE=TRUE
NC_MXM_DP_B_ML_N<0..3>
NO_TEST=TRUE
MXM_DP_B_ML_N<0..3>
MAKE_BASE=TRUE
NC_MXM_DP_B_AUX_P
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_MXM_DP_B_AUX_N
NO_TEST=TRUE
MXM_DP_B_AUX_N
NO_TEST=TRUEMAKE_BASE=TRUE
NC_MXM_DP_B_HPDMXM_DP_B_HPD
MAKE_BASE=TRUE
NC_MXM_DP_D_ML_P<0..3>
NO_TEST=TRUE
NO_TEST=TRUEMAKE_BASE=TRUE
NC_MXM_DP_D_AUX_N
MXM_DP_D_ML_N<0..3>
MXM_DP_D_ML_P<0..3>
MXM_DP_B_AUX_P
AUD_SPDIF_IN
MAKE_BASE=TRUE
AUD_SPDIF_IN_CODEC
MAKE_BASE=TRUE
TP_DP_INT_SPDIF_AUDIODP_INT_SPDIF_AUDIO
MXM_LVDS_A_DATA_P<1>
MXM_PNL_PWR_EN
MXM_PNL_BL_EN
MXM_DP_D_AUX_P
NO_TEST=TRUEMAKE_BASE=TRUE
NC_MXM_LVDS_B_DATA_P<3>
MAKE_BASE=TRUE NO_TEST=TRUE
NC_MXM_LVDS_B_DATA_P<1>
NO_TEST=TRUEMAKE_BASE=TRUE
NC_MXM_LVDS_B_DATA_N<2>
NO_TEST=TRUE
NC_MXM_LVDS_B_DATA_P<2>
MAKE_BASE=TRUE
87 OF 110
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75 87
75 87
75 87
75 87
74
74 87
74 87
75 87
75 87
75 87
75 87
75 87
75 87
75 87
75 87
75 87
75 87
75 87
75 87
75 87
75 87
75 87
74 87
74 87
74
74 87
74 87
74 87
75 87
75
75
74 87
www.vinaﬁx.vn

OUT
OUT
IN
IN
IN
IN
IN
IN
IN
IN
BI
BI
OUT
OUT
OUT
OUT
BI
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
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PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
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87 54 21
FUTURE BOARDS MAY ROUTE THIS VIA MLB
A SEPARATE PANEL CONNECTOR
VSYNC WILL ROUTE TO BLC VIA
I2C MASTER ON TCON
INTERNAL DP INTERFACE
Power aliases required by this page:
Page Notes
- =SMB_DP_TCON_SCL, =SMB_DP_TCON_SDA
guarantee backlight is
BACKLIGHT CONTROL SUPPORT
Signal aliases required by this page:
only on when Panel has valid video
- =PP3V3_S0_DP
BOM options provided by this page:
used by diag LED
- =PP12V_S0_LCD
21
R9050
NOSTUFF
1/16W
MF-LF
5%
402
0
21
R9051
NOSTUFF
402
1/16W
5%
0
MF-LF
31
D9000
BAT54XG
SOT23
21
R9009
MF-LF
1/16W
1%
402
19.1K
21
R9011
1/16W
MF-LF
402
5%
1K
5
2
1
C9005
805
20%
6.3V
22UF
CERM
4
5
2
3
U9000
74AUP2G14GM
SOT886
5
80 87
80 87
80 87
80 87
80 87
80 87
80 87
80 87
80 87
80 87
80
77
78
49
49
6
5
2
1
U9000
74AUP2G14GM
SOT886
2
1
C9000
0.1UF
402
CERM
10V
20%
9
8
7
6
5
4
30
3
29
28
27
26
25
24
23
22
21
20
2
19
18
17
16
15
14
13
12
11
10
1
34
33
32
31
J9000
CRITICAL
F-RT-SM
20455-030E
2
1
C9020
10UF
16V
X5R-CERM
0805
10%
2
1
C9001
0.001UF
50V
20%
402
CERM
21
R9010
NOSTUFF
0
MF-LF
5%
402
1/16W
21
L9000
0603
220-OHM-1.4A
SYNC_MASTER=K74_MASTER
Display: Int DP Connector
SYNC_DATE=N/A
=PP3V3_S0_DP
DP_INT_VIDEO_ON
=PP3V3_S0_DP
VIDEO_ON_L_DLY LCD_BKL_ONLCD_BKL_ON_DLY
VIDEO_ON_L
=SMB_DP_TCON_SDA
=SMB_DP_TCON_SCL
PP3V3_DP
VOLTAGE=3.3V
MIN_NECK_WIDTH=0.2MM
MIN_LINE_WIDTH=0.4MM
=PP3V3_S0_DP
=PP12V_S0_LCD
DP_INT_ML_C_P<3>
DP_INT_ML_C_N<3>
I2C_TCON_SCL
I2C_TCON_SDA
DP_INT_AUX_N
DP_INT_AUX_P
DP_INT_ML_C_P<0>
DP_INT_ML_C_N<0>
DP_INT_ML_C_P<1>
DP_INT_ML_C_N<1>
DP_INT_ML_C_P<2>
DP_INT_ML_C_N<2>
DP_INT_SPDIF_AUDIO
DP_INT_VIDEO_ON
DP_INT_HPD
MIN_NECK_WIDTH=0.25MM
MIN_LINE_WIDTH=0.5MM
VOLTAGE=12V
PP12V_LCD
90 OF 110
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051-8337
78 OF 92
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78
5 78 79 80
5 78 79 80
5
www.vinaﬁx.vn

VCC
NC
CFGX
PC0/I2C_ADDR0
PC1/I2C_ADDR1
GND
REXT
AUX+
AUX-
CEXT
OUT4N
OUT4P
OUT3N
OUT3P
OUT2N
OUT2P
OUT1N
OUT1P
OE*
CA_DET
CFGY
SDA_CTL
SCL_CTL
MODE
IN1P
IN1N
IN2P
IN2N
IN3P
IN3N
IN4P
IN4N
THRM_PAD
I2C_CTL_EN*
HPD HPD_SINK
IN
OUT
IN OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
IN
IN
IN
IN
IN
IN
IN
IN
BI
IN
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
BRANCH
REVISION
DRAWING NUMBER SIZE
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IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
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PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
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87 54 21
NC
NC
NC
NC
INT_PD
EQ & Re-Driver for DP source
INT_PD
COMMON MODE BIAS FOR PS8121ED AUX INTERCEPTION
STRAPS SET FOR PIN CONTROL MODE, 1.5 DB EQ
DISCONNECT I2C IN PIN CONTROL MODE
INT_PD
INT_PD
2
1
C9185
0.1UF
20%
10V
CERM
402
2
1
C9184
20%
10V
CERM
402
0.1UF
2
1
C9183
20%
10V
0.1UF
CERM
402
21
C9186
20%
4.7UF
6.3V
X5R-CERM402
2
1
C9182
0.1UF
20%
10V
CERM
402
2
1
C9181
20%
10V
0.1UF
CERM
402
2
1
C9180
20%
10V
CERM
402
0.1UF
464033211511
49
34
35
6
4
3
14
13
17
16
20
19
23
22
25
29
28
136
47
48
44
45
41
42
38
39
26
307
433731241812
5
32
2
1027
8
9
U9180
PS8121ED
QFN
2
1
R9183
1%
1/16W
MF-LF
402
499
80 81
80
80 87 80 87
80 87
80 87
80 87
80 87
80 87
80 87
80 87
80 87
80 87
80 87
80 87
80 87
80 87
80 87
2
1
R9190
100K
MF-LF
402
5%
1/16W
2
1
R9191
MF-LF
402
5%
1/16W
100K
21C9190
40210%
0.1uF
X5R16V
21C9191
16V 402 X5R10%
0.1uF
80
2
1
R9150
MF-LF
402
5%
1/16W
1K
49
49
2
1
R9151
MF-LF
402
5%
1/16W
1K
NOSTUFF
2
1
R9152
1K
1/16W
5%
MF-LF
402
21
R9120
0
NOSTUFF
21
R9121
0
NOSTUFF
SYNC_DATE=01/07/2010SYNC_MASTER=DAVE
DISPLAY: DP REDRIVER
PS8121_PC0
RDRV_SDA
=PP3V3_S0_DP
PS8121_PC1
PS8121_REXT
RDRV_DP_EXT_AUX_P
RDRV_DP_EXT_AUX_N
PS8121_CEXT
RDRV_DP_EXT_ML_N<3>
RDRV_DP_EXT_ML_P<3>
RDRV_DP_EXT_ML_N<2>
RDRV_DP_EXT_ML_P<2>
RDRV_DP_EXT_ML_N<1>
RDRV_DP_EXT_ML_P<1>
RDRV_DP_EXT_ML_N<0>
RDRV_DP_EXT_ML_P<0>
DP_EXT_CA_DET
=PP3V3_S0_DP
RDRV_SCL
GPU_DP_EXT_ML_P<0>
GPU_DP_EXT_ML_N<0>
GPU_DP_EXT_ML_P<1>
GPU_DP_EXT_ML_N<1>
GPU_DP_EXT_ML_P<2>
GPU_DP_EXT_ML_N<2>
GPU_DP_EXT_ML_P<3>
GPU_DP_EXT_ML_N<3>
PS8121_I2C_EN_L
GPU_DP_EXT_HPD RDRV_DP_EXT_HPD
=I2C_DP_DRV_SCL
=I2C_DP_DRV_SDA
=PP3V3_S0_DP
=PP3V3_S0_DP
RDRV_DP_EXT_AUX_P
NO_TEST
RDRV_DP_EXT_AUX_N
NO_TEST
NO_TEST
DP_EXT_AUX_P
NO_TEST
DP_EXT_AUX_N
91 OF 110
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79 87
5 78 79 80
5 78 79 80
5 78 79 80
79 87
79 87
80 81 87
80 81 87
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OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
IN
IN
IN
IN
IN
IN
IN
IN
IN
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
IN
IN
IN
IN
IN
IN
IN
IN
INOUT
BI
DSG
D SG
BI
D
GS
D
GS
IN
INOUT
BI
BI
IN
IN
IN
IN
IN
IN
IN
IN
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUTIN
BI
BI
BI
BI
OUT
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
BRANCH
REVISION
DRAWING NUMBER SIZE
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SHEET
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PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
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A
B
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345678
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87 54 21
AUX/DDC SELECTION FOR EXTERNAL PORT
FROM GPU TO REDRIVER
REDRIVER TO EXTERNAL CONNECTOR
GPU TO INTERNAL CONNECTOR
21C9223
16V X5R10%
0.1uF
402
21C9224
X5R 40216V10%
0.1uF
21C9225
X5R10% 16V 402
0.1uF
21C9226
10% X5R16V 402
0.1uF
21C9227
10% X5R16V
0.1uF
402
78 87
78 87
78 87
78 87
78 87
78 87
78 87
78 87
74 87
74 87
74 87
74 87
74 87
74 87
74 87
74 87
78
79 87
79 87
79 87
79 87
79 87
79 87
79 87
79 87
74 87
74 87
74 87
74 87
74 87
74 87
74 87
74 87
79 74
21C9212
40210% 16V X5R
0.1uF
21C9213
10% 16V X5R 402
0.1uF
21C9214
10% X5R16V
0.1uF
402
21C9215
16V
0.1uF
10% X5R 402
21C9216
X5R 40216V
0.1uF
10%
21C9217 0.1uF
40210% 16V X5R
21C9218 0.1uF
402X5R16V10%
21C9219 0.1uF
402X5R16V10%
2
1
R9210
402
100K
1%
1/16W
MF-LF
21
C9210
0.1UF
10%
16V
X5R
402
74 87
1
2
6
Q9250
SSM6N15FEAPE
SOT563
21
C9211
0.1UF
X5R
10%
402
16V
4
5
3
Q9250
SOT563
SSM6N15FEAPE
74 87
2
1
R9252
402
100K
5%
1/16W
MF-LF
2
1
3
Q9251
SOD-VESM-HF
SSM3K15FV
2
1
R9202
100K
402
MF-LF
5%
1/16W
2
1
3
Q9201
SSM3K15FV
SOD-VESM-HF
79 81
81 79
79 81 87
79 81 87
79 87
79 87
79 87
79 87
79 87
79 87
79 87
79 87
81 87
81 87
81 87
81 87
81 87
81 87
81 87
81 87
5
21
L9170
CRITICAL
FERR-220-OHM
0402
21
R9170
MF-LF
402
47
1/16W
5%
75
2
1
R9215
402
100K
MF-LF
5%
1/16W
2
1
R9216
402
100K
MF-LF
5%
1/16W
2
1
R9201
1%
1/16W
MF-LF
100K
402
2
1
R9200
MF-LF
1/16W
1%
100K
402
21C9200
X5R 40210% 16V
0.1uF
21C9201
X5R 402
0.1uF
16V10%
74 87
74 87
21C9230
X5R16V 402
0.1uF
10%
21C9231
X5R 40210%
0.1uF
16V
21C9233
10% X5R 40216V
0.1uF
21C9232
X5R 40210%
0.1uF
16V
21C9234
10% 40216V X5R
0.1uF
21C9235
40216V10% X5R
0.1uF
21C9237
X5R 402
0.1uF
10% 16V
21C9236 0.1uF
16V 402 X5R10%
78 87
78 87
74
21C9220
10%
0.1uF
40216V X5R
21C9221
16V10% 402 X5R
0.1uF
21C9222
10% X5R
0.1uF
40216V
SYNC_MASTER=DAVE SYNC_DATE=01/07/2010
DISPLAYPORT CONNECTIONS
RDRV_DP_EXT_ML_N<0> NO_TEST
DP_EXT_ML_C_P<3>NO_TEST
LCD_PWM_FILT LCD_PWM
NO_TESTMXM_DP_C_ML_P<2>
NO_TESTMXM_DP_C_ML_N<1>
DP_INT_ML_C_P<3>NO_TEST
NO_TEST DP_INT_ML_C_N<2>
NO_TEST DP_INT_ML_C_P<2>
NO_TEST DP_INT_ML_C_P<1>
NO_TEST DP_INT_ML_C_P<0>
=PP3V3_S0_DP
DP_EXT_ML_C_N<2>NO_TEST
DDC_CA_DET_LS5V_L
GPU_DP_EXT_ML_P<0>NO_TEST
NO_TEST GPU_DP_EXT_ML_N<1>
NO_TEST GPU_DP_EXT_ML_P<2>
GPU_DP_EXT_ML_N<2>NO_TEST
GPU_DP_EXT_ML_P<3>NO_TEST
GPU_DP_EXT_ML_N<3>NO_TEST
MXM_DP_A_HPD
NO_TESTMXM_DP_A_ML_N<0>
NO_TESTMXM_DP_A_ML_P<3>
NO_TESTMXM_DP_A_ML_N<3>
NO_TEST GPU_DP_EXT_ML_N<0>
NO_TEST GPU_DP_EXT_ML_P<1>
NO_TESTMXM_DP_A_ML_N<2>
MXM_DP_A_ML_P<2> NO_TEST
NO_TESTMXM_DP_A_ML_P<0>
RDRV_DP_EXT_ML_P<1> NO_TEST
NO_TESTRDRV_DP_EXT_ML_N<2>
NO_TESTRDRV_DP_EXT_ML_P<2>
RDRV_DP_EXT_ML_P<3> NO_TEST
RDRV_DP_EXT_ML_N<3> NO_TEST DP_EXT_ML_C_N<3>NO_TEST
DP_EXT_ML_C_N<1>NO_TEST
NO_TEST DP_EXT_ML_C_P<1>
RDRV_DP_EXT_HPD
DP_EXT_ML_C_N<0>NO_TEST
RDRV_DP_EXT_ML_N<1> NO_TEST
DP_EXT_ML_C_P<0>NO_TEST
NO_TEST DP_INT_ML_C_N<0>
NO_TEST DP_INT_ML_C_N<1>
DP_INT_AUX_PNO_TEST
MXM_PNL_BL_PWM
NO_TESTMXM_DP_C_ML_P<0>
NO_TESTMXM_DP_C_ML_N<0>
MXM_DP_C_ML_N<3> NO_TEST
NO_TESTMXM_DP_C_AUX_N
NO_TESTMXM_DP_C_AUX_P
NO_TESTMXM_DP_C_ML_P<3>
NO_TESTMXM_DP_C_ML_N<2>
DP_INT_HPD
MAKE_BASE=TRUE
MXM_DP_C_HPD
NO_TESTMXM_DP_A_ML_P<1>
MAKE_BASE=TRUE
DP_EXT_HPD
DP_EXT_ML_C_P<2>NO_TEST
NO_TESTRDRV_DP_EXT_ML_P<0>
GPU_DP_EXT_HPD
MAKE_BASE=TRUE
=PP5V_S0_DP_AUX_MUX
MXM_DP_A_AUX_N
=PP5V_S0_DP_AUX_MUX
MXM_DP_A_AUX_P
MXM_DP_C_ML_P<1> NO_TEST
DP_EXT_CA_DET
DP_INT_AUX_NNO_TEST
NO_TEST DP_INT_ML_C_N<3>
DP_EXT_AUX_P
=PP3V3_S0_DP
DP_EXT_AUX_N
DDC_CA_DET_LS5V
MXM_DP_A_ML_N<1> NO_TEST
92 OF 110
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5 80
5 80
5 78 79 80
www.vinaﬁx.vn

IN
OC*
OUT
EN
GND
IN
IO
NC NC
IO
GND
IO
NC NC
IO
GND
BI
BI
OUT
BI
BI
BI
BI
BI
BI
BI
BI
ML_LANE2P
ML_LANE2N
RETURN
GND
ML_LANE1N
ML_LANE0N
GND
ML_LANE1P
ML_LANE0P
GND
AUX_CHP
AUX_CHN
DP_PWR
GND
ML_LANE3N
ML_LANE3P
GND
HPD
CONFIG1
CONFIG2
SHIELD PINS
OUT
IO
NC NC
IO
GND
IO
NC NC
IO
GND
SYM_VER-2
SYM_VER-2
SYM_VER-2
SYM_VER-2
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
BRANCH
REVISION
DRAWING NUMBER SIZE
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SHEET
PAGE TITLE
C
A
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PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
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87 54 21
CRITICAL BOM OPTION
TABLE_5_HEAD
PART# DESCRIPTIONQTY REFERENCE DESIGNATOR(S)
TABLE_5_ITEM
TABLE_5_ITEM
APPLE PART NO 514-0727
1
3
5
2
4
U9400
TPS2051B
SOT23
CRITICAL
2
1C9480
6.3V
X5R
20%
10UF
603
2
1C9481
0.1UF
CERM
20%
402
10V
2
1C9485
CRITICAL
20%
X5R
6.3V
603
10UF
5 18 26 36 46 47 63 64 91
45
3
D9410
NOSTUFF
CRITICAL
RCLAMP0524P
SLP2510P8
12
3
D9410
NOSTUFF
SLP2510P8
RCLAMP0524P
CRITICAL
21
R9400
0
21
R9401
0
21
R9402
0
21
R9403
0
21
R9404
0
21
R9405
0
21
R9406
0
21
R9407
0
79 80 87
79 80 87
80
80 87
80 87
80 87
80 87
80 87
80 87
80 87
80 87
21
L9400
0603
220-OHM-1.4A
19
10
12
15
17
9
11
3
5
2221
2
1413
87
1
20
6
4
16
18
J9400
MDP-PLST-K74-K75
CRITICAL
F-ANG-TH
OMIT_TABLE
79 80
52
6
4
3
1
D9400
CRITICAL
RCLAMP0504F
SC70-6-1
45
3
D9411
NOSTUFF
SLP2510P8
RCLAMP0524P
CRITICAL
2
1
R9425
1/16W
402
5%
MF-LF
1M
12
3
D9411
NOSTUFF
CRITICAL
SLP2510P8
RCLAMP0524P
2
1
C9400
CERM
603
50V
20%
0.01UF
2
1
R9422
1M
5%
1/16W
MF-LF
402
4
32
1
FL9400
NOSTUFF
12-OHM-100MA
TCM1210-4SM
4
32
1
FL9401
12-OHM-100MA
NOSTUFF
TCM1210-4SM
4
32
1
FL9402
NOSTUFF
12-OHM-100MA
TCM1210-4SM
4
32
1
FL9403
NOSTUFF
12-OHM-100MA
TCM1210-4SM
PLASTIC_IO1514-0727 K74/K75 MDP, PLASTIC, PD/NI
CRITICAL
J9400
METAL_IO1
CRITICAL
514-0686 K22/K23 PROD. MDP J9400
SYNC_DATE=N/ASYNC_MASTER=K74_MASTER
Display: Ext DP Connector
DP_ML_CONN_P<0>NO_TEST
DP_EXT_AUX_P
DP_EXT_AUX_N
NO_TESTDP_ML_CONN_N<3>
NO_TESTDP_ML_CONN_P<3>
HDMI_CEC
DP_EXT_ML_C_P<2>
DP_EXT_ML_C_N<2>
DP_EXT_ML_C_N<0>
DP_EXT_ML_C_N<1>
DP_EXT_ML_C_P<1>
DP_EXT_ML_C_P<0>
TP_DP_OC
DP_EXT_ML_C_P<3>
DP_EXT_ML_C_N<3>
=PP3V3_S0_DPCONN
VOLTAGE=3.3V
MIN_NECK_WIDTH=0.20 MM
PP3V3_S0_DPFUSE
MIN_LINE_WIDTH=0.38 MM
PM_SLP_S3_L
DP_ML_CONN_P<1>NO_TEST
DP_EXT_HPD
DP_ML_CONN_N<1>NO_TEST
DP_ML_CONN_P<2>NO_TEST
DP_ML_CONN_N<2>NO_TEST
DP_EXT_CA_DET
VOLTAGE=3.3V
MIN_NECK_WIDTH=0.20 MM
MIN_LINE_WIDTH=0.38 MM
PP3V3_S0_DPPWR
NO_TEST DP_ML_CONN_N<0>
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87
87
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TABLE_SPACING_ASSIGNMENT_ITEM
AREA_TYPE SPACING_RULE_SETNET_SPACING_TYPE1 NET_SPACING_TYPE2
TABLE_SPACING_ASSIGNMENT_HEAD
TABLE_SPACING_ASSIGNMENT_ITEM
AREA_TYPE SPACING_RULE_SETNET_SPACING_TYPE1 NET_SPACING_TYPE2
TABLE_SPACING_ASSIGNMENT_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
MINIMUM LINE WIDTH
ALLOW ROUTE
ON LAYER?
LAYER MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
TABLE_BOARD_INFO
VERSION
ALLEGRO
(MIL or MM)
BOARD UNITS
BOARD LAYERS BOARD AREAS
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
PHYSICAL_RULE_SETAREA_TYPENET_PHYSICAL_TYPE
TABLE_PHYSICAL_ASSIGNMENT_HEAD
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
LINE-TO-LINE SPACINGLAYERSPACING_RULE_SET WEIGHT
TABLE_SPACING_RULE_HEAD
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
LINE-TO-LINE SPACINGLAYERSPACING_RULE_SET WEIGHT
TABLE_SPACING_RULE_HEAD
LINE-TO-LINE SPACINGLAYERSPACING_RULE_SET WEIGHT
TABLE_SPACING_RULE_HEAD
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
LINE-TO-LINE SPACINGLAYERSPACING_RULE_SET WEIGHT
TABLE_SPACING_RULE_HEAD
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
LINE-TO-LINE SPACINGLAYERSPACING_RULE_SET WEIGHT
TABLE_SPACING_RULE_HEAD
AREA_TYPE SPACING_RULE_SETNET_SPACING_TYPE1 NET_SPACING_TYPE2
TABLE_SPACING_ASSIGNMENT_HEAD
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_PHYSICAL_RULE_ITEM
MINIMUM LINE WIDTH
ALLOW ROUTE
ON LAYER?
LAYER MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
MINIMUM LINE WIDTH
ALLOW ROUTE
ON LAYER?
LAYER MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
MINIMUM LINE WIDTH
ALLOW ROUTE
ON LAYER?
LAYER MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
MINIMUM LINE WIDTH
ALLOW ROUTE
ON LAYER?
LAYER MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
MINIMUM LINE WIDTH
ALLOW ROUTE
ON LAYER?
LAYER MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
MINIMUM LINE WIDTH
ALLOW ROUTE
ON LAYER?
LAYER MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
MINIMUM LINE WIDTH
ALLOW ROUTE
ON LAYER?
LAYER MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
MINIMUM LINE WIDTH
ALLOW ROUTE
ON LAYER?
LAYER MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_ASSIGNMENT_ITEM
TABLE_PHYSICAL_ASSIGNMENT_ITEM
TABLE_PHYSICAL_ASSIGNMENT_ITEM
TABLE_PHYSICAL_ASSIGNMENT_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
MINIMUM LINE WIDTH
ALLOW ROUTE
ON LAYER?
LAYER MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
MINIMUM LINE WIDTH
ALLOW ROUTE
ON LAYER?
LAYER MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
MINIMUM LINE WIDTH
ALLOW ROUTE
ON LAYER?
LAYER MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
II NOT TO REPRODUCE OR COPY IT
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I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
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K74/K75 BOARD-SPECIFIC SPACING & PHYSICAL CONSTRAINTS
SPACING RULE SET
PHYSICAL CONSTRAINTS
CONSTRAINTS FOR BGA AREA
SYNC_MASTER=K74_MASTER SYNC_DATE=N/A
K74/K75 RULE DEFINITIONS
* 0.12 MM45_OHM_SE =STANDARD0.085 MM =STANDARDY =STANDARD
0.1 MM =STANDARDY =STANDARD0.085 MM* =STANDARD50_OHM_SE
=STANDARD0.085 MMTOP,BOTTOM 0.085 MMY55_OHM_SE
Y 0.076 MM 0.075 MM =STANDARD =STANDARD =STANDARD55_OHM_SE *
0.135 MMTOP,BOTTOM45_OHM_SE Y 0.085 MM =STANDARD
0.2 MM* ?BGA_P2MM
Y 0.085 MM=STANDARD =STANDARD 0.1 MM*1:1_DIFFPAIR =STANDARD
*YPOWER_WIDTH 0.200 MM 3.0 MM =STANDARD =STANDARD0.600 MM
0.300 MM*Y 3.0 MM =STANDARD =STANDARDPOWER_CTL 0.200 MM
0.254 MMRCOMP 0.200 MM =STANDARD=STANDARD3.0 MMY*
VR_CTL_PHY DEFAULTBGA_P1MM
VR_CTL_PHY POWER_CTL*
POWER_WIDTH*POWER
POWER_CTLBGA_P1MMPOWER
0.075 MM 0.085 MM =STANDARD 0.320 MMY110_OHM_DIFF TOP,BOTTOM 0.15 MM
=STANDARD110_OHM_DIFF =STANDARD =STANDARD =STANDARDN* =STANDARD
0.091 MMTOP,BOTTOM100_OHM_DIFF =STANDARD0.085 MM 0.1 MM0.25 MMY
0.081 MM100_OHM_DIFF =STANDARDYISL3,ISL6 0.25 MM 0.1 MM0.085 MM
=STANDARD=STANDARD =STANDARD* =STANDARD =STANDARD100_OHM_DIFF N
0.110 MMTOP,BOTTOM =STANDARD90_OHM_DIFF Y 0.085 MM 0.200 MM 0.1 MM
0.099 MM 0.1 MM0.200 MM90_OHM_DIFF ISL3,ISL6 0.085 MM 12 MMY
=STANDARD =STANDARD=STANDARD =STANDARD90_OHM_DIFF N* =STANDARD
=STANDARD85_OHM_DIFF * =STANDARDN =STANDARD=STANDARD =STANDARD
0.165 MM =STANDARDY 0.1 MM70_OHM_DIFF TOP,BOTTOM 0.085 MM 0.130 MM
=STANDARD =STANDARDN =STANDARD70_OHM_DIFF * =STANDARD =STANDARD
50_OHM_SE 0.1 MMTOP,BOTTOM Y 15 MM0.085 MM
0.16 MM =STANDARDY* =STANDARD0.085 MM39_OHM_SE =STANDARD
0.085 MMYTOP,BOTTOM =STANDARD0.175 MM39_OHM_SE
=STANDARDY 0.085 MM* 0.19 MM35_OHM_SE =STANDARD=STANDARD
=STANDARDTOP,BOTTOM 0.085 MMY 0.21 MM35_OHM_SE
0.155 MMY 0.1 MM70_OHM_DIFF ISL3,ISL6 =STANDARD0.085 MM 0.135 MM
* BGA_P1MMBGA_P1MMCLK_LPC
BGA_P1MM BGA_P1MM*CLK_PCIE
BGA_P1MMMEM_CLK * BGA_P2MM
BGA_P1MM BGA_P1MM**
SWITCHNODE 0.8 MM 1000*
PWR_P2MM 1000* 0.2 MM
1000GND_P2MM 0.2 MM*
=STANDARD ?GND *
0.6 MM ?*6:1_SPACING
?0.5 MM5:1_SPACING *
4X_DIELECTRIC 0.300 MM ?*
TOP,BOTTOM 0.240 MM ?3X_DIELECTRIC
TOP,BOTTOM 0.320 MM ?4X_DIELECTRIC
?0.220 MM*3X_DIELECTRIC
0.160 MMTOP,BOTTOM2X_DIELECTRIC ?
2X_DIELECTRIC * ?0.150 MM
0.1 MM ?*DEFAULT
*STANDARD =DEFAULT ?
0.2 MM* ?2:1_SPACING
?0.25 MM*2.5:1_SPACING
4:1_SPACING * ?0.4 MM
0.15 MM* ?1.5:1_SPACING
5X_DIELECTRIC 0.380 MM ?*
5X_DIELECTRIC ?0.400 MMTOP,BOTTOM
BGA_P1MM BGA_P1MM*CLK_PCI
0.125 MM85_OHM_DIFF Y 0.1 MM0.2 MM0.085 MM =STANDARDTOP,BOTTOM
0.115 MMY 0.085 MM85_OHM_DIFF ISL3,ISL6 =STANDARD 0.2 MM 0.1 MM
=DEFAULT ?*BGA_P1MM
0.3 MM ?*3:1_SPACING
15.5.1MMTOP,ISL2,ISL3,ISL4,ISL5,ISL6,ISL7,BOTTOM NO_TYPE,BGA_P1MM
0 MM=50_OHM_SE =50_OHM_SE 0 MMY 100 MM*DEFAULT
12.7 MM =DEFAULTY* =DEFAULTSTANDARD =DEFAULT =DEFAULT
STANDARD**GND
STANDARD**POWER
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II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
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REVISION
DRAWING NUMBER SIZE
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R
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
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PAGE
NOTICE OF PROPRIETARY PROPERTY:
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C
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B
87 54 21
TABLE_PHYSICAL_RULE_ITEM
LINE-TO-LINE SPACINGLAYERSPACING_RULE_SET WEIGHT
TABLE_SPACING_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
MINIMUM LINE WIDTH
ALLOW ROUTE
ON LAYER?
LAYER MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
TABLE_SPACING_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
AREA_TYPE SPACING_RULE_SETNET_SPACING_TYPE1 NET_SPACING_TYPE2
TABLE_SPACING_ASSIGNMENT_HEAD
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
AREA_TYPE SPACING_RULE_SETNET_SPACING_TYPE1 NET_SPACING_TYPE2
TABLE_SPACING_ASSIGNMENT_HEAD
TABLE_SPACING_ASSIGNMENT_ITEM
AREA_TYPE SPACING_RULE_SETNET_SPACING_TYPE1 NET_SPACING_TYPE2
TABLE_SPACING_ASSIGNMENT_HEAD
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
AREA_TYPE SPACING_RULE_SETNET_SPACING_TYPE1 NET_SPACING_TYPE2
TABLE_SPACING_ASSIGNMENT_HEAD
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
AREA_TYPE SPACING_RULE_SETNET_SPACING_TYPE1 NET_SPACING_TYPE2
TABLE_SPACING_ASSIGNMENT_HEAD
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
MINIMUM LINE WIDTH
ALLOW ROUTE
ON LAYER?
LAYER MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
LINE-TO-LINE SPACINGLAYERSPACING_RULE_SET WEIGHT
TABLE_SPACING_RULE_HEAD
TABLE_PHYSICAL_ASSIGNMENT_ITEM
PHYSICAL_RULE_SETAREA_TYPENET_PHYSICAL_TYPE
TABLE_PHYSICAL_ASSIGNMENT_HEAD
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_PHYSICAL_RULE_ITEM
AREA_TYPE SPACING_RULE_SETNET_SPACING_TYPE1 NET_SPACING_TYPE2
TABLE_SPACING_ASSIGNMENT_HEAD
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
AREA_TYPE SPACING_RULE_SETNET_SPACING_TYPE1 NET_SPACING_TYPE2
TABLE_SPACING_ASSIGNMENT_HEAD
TABLE_SPACING_ASSIGNMENT_ITEM
LINE-TO-LINE SPACINGLAYERSPACING_RULE_SET WEIGHT
TABLE_SPACING_RULE_HEAD
MINIMUM LINE WIDTH
ALLOW ROUTE
ON LAYER?
LAYER MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
MEMORY POWER PROPERTIES
PHYSICAL
Memory Net Properties
VOLTAGE
NET_TYPE
SPACING
Memory Bus Constraints
SPACING
NET_TYPE
Memory Net Properties
Memory Bus Spacing Group Assignments
Need to support MEM_*-style wildcards!
ELECTRICAL_CONSTRAINT_SET SPACINGPHYSICAL
PHYSICALELECTRICAL_CONSTRAINT_SET
NET_TYPE
I159
I160
I161
MEM_CMD2MEM*MEM_DQSMEM_CMD
MEM_CMD2CMDMEM_CMD *MEM_CMD
MEM_CMD2MEM*MEM_CMD MEM_CTRL
MEM_CLK ** MEM_2OTHER
MEM_DQ_ODD2DQ_ODDMEM_DQ_ODD *MEM_DQ_ODD
MEM_DQS MEM_DQ_ODD2MEMMEM_DQ_ODD *
MEM_DQ_EVENMEM_CTRL * MEM_CTRL2MEM
MEM_DQ_EVEN2DQ_ODDMEM_DQ_ODD *MEM_DQ_EVEN
*MEM_CLK MEM_CLK2MEMMEM_DQ_ODD
* ?0.2 MMMEM_RCOMP
0.2 MM ?*MEM_POWER
0.175 MM =STANDARDMEM_RCOMP_PHY =STANDARD=STANDARDY* 0.175 MM
MEM_CTRL MEM_CLK * MEM_CTRL2MEM
MEM_CTRL *MEM_CTRL MEM_CTRL2CTRL
* MEM_CTRL2MEMMEM_CTRL MEM_CMD
*MEM_POWER_PHY MEM_POWER_WIDTH
MEM_CTRL2MEM*MEM_CTRL MEM_DQ_ODD
=STANDARD0.500 MM 0.175 MM =STANDARD=STANDARD*MEM_POWER_WIDTH Y
MEM_DQS2MEMMEM_DQ_EVENMEM_DQS *
MEM_DQ_EVEN2MEMMEM_DQ_EVEN MEM_DQS *
MEM_DQ_EVEN2DQ_EVENMEM_DQ_EVENMEM_DQ_EVEN *
MEM_DQ_EVEN2MEMMEM_DQ_EVEN MEM_CLK *
MEM_CLK2MEMMEM_CLK *MEM_DQ_EVEN
MEM_DQ_EVEN MEM_DQ_EVEN2MEMMEM_CTRL *
MEM_DQS2MEMMEM_DQS *MEM_DQ_ODD
MEM_CLK MEM_CLK2MEM*MEM_CMD
MEM_CLK2MEM*MEM_CLK MEM_CTRL
MEM_CLK2MEM*MEM_CLK MEM_DQS
MEM_DQ_ODD2MEMMEM_DQ_ODD *MEM_CLK
MEM_DQ_ODD2MEMMEM_DQ_ODD *MEM_CTRL
MEM_DQ_ODD2MEMMEM_DQ_ODD *MEM_CMD
MEM_DQSMEM_CTRL * MEM_CTRL2MEM
?=3:1_SPACINGMEM_DQ_EVEN2DQ_EVEN *
MEM_2OTHER =3:1_SPACING ?*
* ?=3:1_SPACINGMEM_DQS2MEM
=5:1_SPACINGMEM_DQ_EVEN2DQ_ODD * ?
=2.5:1_SPACINGMEM_CTRL2MEM * ?
MEM_CLK *MEM_CLK MEM_CLK2MEM
=3:1_SPACING* ?MEM_DQ_EVEN2MEM
=3:1_SPACING ?MEM_DQ_ODD2MEM *
MEM_2OTHER*MEM_DQS *
* MEM_2OTHERMEM_DQ_EVEN *
MEM_2OTHERMEM_CMD **
MEM_DQ_ODD2DQ_ODD ?* =3:1_SPACING
MEM_CMD2MEM * ?=3:1_SPACING
=1.5:1_SPACINGMEM_CMD2CMD ?*
?MEM_CTRL2CTRL * =2:1_SPACING
MEM_DQS * MEM_DQS2MEMMEM_DQS
MEM_DQ_EVEN2DQ_ODDMEM_DQ_EVEN *MEM_DQ_ODD
MEM_2OTHERMEM_DQ_ODD **
MEM_2OTHERMEM_CTRL **
=45_OHM_SE* =45_OHM_SE =STANDARDMEM_45S =45_OHM_SE=45_OHM_SE =STANDARD
MEM_DQS2MEM*MEM_DQS MEM_CMD
MEM_DQS2MEMMEM_DQS *MEM_CTRL
MEM_DQS2MEMMEM_DQS *MEM_CLK
MEM_DQ_EVEN2MEMMEM_DQ_EVEN MEM_CMD *
MEM_CMD2MEMMEM_CMD *MEM_CLK
*MEM_CMD MEM_DQ_ODD MEM_CMD2MEM
MEM_CMD2MEMMEM_CMD *MEM_DQ_EVEN
=39_OHM_SE =STANDARD=STANDARD* =39_OHM_SE=39_OHM_SE=39_OHM_SEMEM_39S
=4:1_SPACING ?MEM_CLK2MEM *
=STANDARD=35_OHM_SE=35_OHM_SE* =35_OHM_SE =35_OHM_SEMEM_35S =STANDARD
=70_OHM_DIFF* =70_OHM_DIFF =70_OHM_DIFFMEM_70D =70_OHM_DIFF =70_OHM_DIFF=70_OHM_DIFF
SYNC_DATE=N/ASYNC_MASTER=K74_MASTER
Memory Constraints
MEM_B_DQ<39..32>MEM_DQ_EVENMEM_45S
MEM_B_DM<4>MEM_45S MEM_DQ_EVEN
MEM_B_DQ<47..40>MEM_45S MEM_DQ_ODD
MEM_B_DM<5>MEM_DQ_ODDMEM_45S
MEM_RCOMP_PHY MEM_RCOMP CPU_SM_RCOMP0
MEM_70D MEM_DQS MEM_B_DQS_N<5>
MEM_B_CAS_LMEM_35S MEM_CMD
MEM_B_DQ<63..56>MEM_45S MEM_DQ_ODD
MEM_DQ_EVEN MEM_B_DM<0>MEM_45S
MEM_B_DM<1>MEM_45S MEM_DQ_ODD
MEM_DQ_EVEN MEM_B_DQ<7..0>MEM_45S
MEM_B_RAS_LMEM_35S MEM_CMD
MEM_35S MEM_CMD MEM_B_BA<2..0>
MEM_45S MEM_B_DQ<23..16>MEM_DQ_EVEN
MEM_B_DM<3>MEM_45S MEM_DQ_ODD
MEM_39S MEM_CTRL MEM_A_ODT<3..0>
MEM_35S MEM_CMD MEM_A_BA<2..0>
MEM_B_DQ<15..8>MEM_45S MEM_DQ_ODD
MEM_B_DQ<55..48>MEM_45S MEM_DQ_EVEN
MEM_DQ_EVEN MEM_B_DM<6>MEM_45S
MEM_A_A<15..0>MEM_35S MEM_CMD
MEM_DQSMEM_70D MEM_B_DQS_P<1>
MEM_35S MEM_CMD MEM_A_RAS_L
MEM_B_DQS_N<3>MEM_70D MEM_DQS
MEM_B_DQS_P<4>MEM_70D MEM_DQS
MEM_RCOMP_PHY MEM_RCOMP CPU_SM_RCOMP1
MEM_B_DQS_P<3>MEM_70D MEM_DQS
MEM_B_DQS_N<2>MEM_DQSMEM_70D
MEM_70D MEM_DQS MEM_B_DQS_N<4>
MEM_DQ_ODD MEM_B_DM<7>MEM_45S
MEM_CTRL MEM_A_CKE<3..0>MEM_39S
MEM_B_DM<2>MEM_45S MEM_DQ_EVEN
MEM_B_DQ<31..24>MEM_45S MEM_DQ_ODD
MEM_39S MEM_A_CS_L<3..0>MEM_CTRL
MEM_CLK MEM_A_CLK_P<3..0>MEM_70D
MEM_DQS MEM_A_DQS_N<1>MEM_70D
MEM_70D MEM_DQS MEM_A_DQS_N<5>
MEM_A_DQS_P<5>MEM_70D MEM_DQS
MEM_B_WE_LMEM_35S MEM_CMD
MEM_70D MEM_A_DQS_N<2>MEM_DQS
MEM_DQS MEM_A_DQS_N<7>MEM_70D
MEM_B_CLK_P<3..0>MEM_CLKMEM_70D
MEM_B_CLK_N<3..0>MEM_CLKMEM_70D
MEM_B_CKE<3..0>MEM_CTRLMEM_39S
MEM_39S MEM_B_CS_L<3..0>MEM_CTRL
MEM_39S MEM_B_ODT<3..0>MEM_CTRL
MEM_35S MEM_B_A<15..0>MEM_CMD
MEM_A_DQS_P<7>MEM_70D MEM_DQS
MEM_DQSMEM_70D MEM_A_DQS_P<2>
MEM_A_DQ<15..8>MEM_45S MEM_DQ_ODD
MEM_A_DM<1>MEM_45S MEM_DQ_ODD
MEM_CMDMEM_35S MEM_A_WE_L
MEM_DQ_EVEN MEM_A_DQ<7..0>MEM_45S
MEM_70D MEM_B_DQS_P<7>MEM_DQS
MEM_RCOMP_PHY CPU_SM_RCOMP2MEM_RCOMP
MEM_70D MEM_B_DQS_N<7>MEM_DQS
MEM_70D MEM_DQS MEM_B_DQS_P<6>
MEM_DQ_ODDMEM_45S MEM_A_DQ<47..40>
MEM_CLK MEM_A_CLK_N<3..0>MEM_70D
MEM_A_DM<2>MEM_DQ_EVENMEM_45S
MEM_DQ_EVEN MEM_A_DQ<23..16>MEM_45S
MEM_A_CAS_LMEM_35S MEM_CMD
MEM_A_DQS_N<4>MEM_70D MEM_DQS
MEM_70D MEM_DQS MEM_A_DQS_N<6>
MEM_A_DQS_P<6>MEM_70D MEM_DQS
MEM_DQS MEM_A_DQS_N<3>MEM_70D
MEM_A_DQS_P<3>MEM_DQSMEM_70D
MEM_DQSMEM_70D MEM_B_DQS_P<0>
MEM_DQSMEM_70D MEM_B_DQS_N<1>
MEM_DQ_ODDMEM_45S MEM_A_DM<5>
MEM_45S MEM_DQ_EVEN MEM_A_DM<6>
MEM_DQ_EVENMEM_45S MEM_A_DQ<55..48>
MEM_DQ_ODDMEM_45S MEM_A_DQ<63..56>
MEM_A_DQS_P<1>MEM_70D MEM_DQS
MEM_A_DQS_P<4>MEM_70D MEM_DQS
MEM_DQSMEM_70D MEM_B_DQS_N<0>
MEM_DQSMEM_70D MEM_B_DQS_P<2>
MEM_70D MEM_DQS MEM_B_DQS_P<5>
MEM_70D MEM_DQS MEM_B_DQS_N<6>
CPU_DIMM_VREF_BMEM_POWERMEM_POWER_PHY
MEM_POWERMEM_POWER_PHY CPU_DIMM_VREF_A
MEM_DQ_ODDMEM_45S MEM_A_DM<7>
MEM_70D MEM_DQS MEM_A_DQS_N<0>
MEM_A_DQS_P<0>MEM_70D MEM_DQS
MEM_45S MEM_A_DM<4>MEM_DQ_EVEN
MEM_DQ_ODDMEM_45S MEM_A_DM<3>
MEM_A_DM<0>MEM_DQ_EVENMEM_45S
MEM_A_DQ<31..24>MEM_45S MEM_DQ_ODD
MEM_DQ_EVENMEM_45S MEM_A_DQ<39..32>
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TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
MINIMUM LINE WIDTH
ALLOW ROUTE
ON LAYER?
LAYER MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
LINE-TO-LINE SPACINGLAYERSPACING_RULE_SET WEIGHT
TABLE_SPACING_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
LINE-TO-LINE SPACINGLAYERSPACING_RULE_SET WEIGHT
TABLE_SPACING_RULE_HEAD
TABLE_SPACING_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
MINIMUM LINE WIDTH
ALLOW ROUTE
ON LAYER?
LAYER MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
TABLE_SPACING_RULE_ITEM
LINE-TO-LINE SPACINGLAYERSPACING_RULE_SET WEIGHT
TABLE_SPACING_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
LINE-TO-LINE SPACINGLAYERSPACING_RULE_SET WEIGHT
TABLE_SPACING_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
MINIMUM LINE WIDTH
ALLOW ROUTE
ON LAYER?
LAYER MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
LINE-TO-LINE SPACINGLAYERSPACING_RULE_SET WEIGHT
TABLE_SPACING_RULE_HEAD
TABLE_SPACING_RULE_ITEM
II NOT TO REPRODUCE OR COPY IT
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CPU ITP
ANY OTHER LYNNFIELD CONSTRAINTS NOT COVERED ON PAGES 101 AND 107 SHOULD GO ON THIS PAGE TOO
ELECTRICAL_CONSTRAINT_SET
PCIE I/O
SPACINGPHYSICAL
PCI-Express
NET_TYPE
PCIE GRAPHICS
CLOCKS
SATA
NET_TYPE
PHYSICAL SPACING
CPU_MISC
CPU
ELECTRICAL_CONSTRAINT_SET
PCIE REF CLOCKS
DMI
FDI
SATA Interface Constraints
SYNC_DATE=N/ASYNC_MASTER=K74_MASTER
PCIE/DMI/FDI/SATA CONSTRAINTS
TOP,BOTTOMSATA ?=5X_DIELECTRIC
* 0.2 MMCPU_ITP ?
CPU_RCOMP * ?0.2 MM
=STANDARD ?*CPU_AGTL
CPU_RCOMP_PHY 0.200 MM =STANDARD=STANDARD3.0 MMY* 0.254 MM
=85_OHM_DIFF=85_OHM_DIFFSATA_85D * =85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF
?0.5 MMCLK_PCIE *
=STANDARD=50_OHM_SE =50_OHM_SE=50_OHM_SE =50_OHM_SE* =STANDARDCPU_50S
=4X_DIELECTRICPCIE * ?
=100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF* =100_OHM_DIFF =100_OHM_DIFFCLK_PCIE_100D
=85_OHM_DIFFPCIE_85D =85_OHM_DIFF=85_OHM_DIFF=85_OHM_DIFF* =85_OHM_DIFF=85_OHM_DIFF
PCIE TOP,BOTTOM ?=4X_DIELECTRIC
?*SATA =5X_DIELECTRIC
CPU_50S CPU_ITP XDP_OBSDATA_A<3..0>
CPU_50S CPU_ITP CPU_CFG<17..0>
PCIE_85D PCIE PCIE_MINI_R2D_C_N
PCIEPCIE_85D PCIE_MINI_D2R_N
PCIE_85D PCIE PCIE_MINI_R2D_N
PCIE_FW_R2D_C_NPCIE_85D PCIE
CLK_PCIECLK_PCIE_100D GPU_CLK100M_PCIE_P
SATA_HDD_R2D_PSATA_85D SATA
SATA_HDD_D2R_PSATA_85D SATA
SATA_HDD_D2R_C_PSATA_85D SATA
GFX_CLK120M_DPLLSS_NCLK_PCIE_100D CLK_PCIE
CLK_PCIE PCIE_CLK100M_CPU_NCLK_PCIE_100D
PCIE_CLK100M_PCH_NCLK_PCIECLK_PCIE_100D
CPU_RCOMP_PHY CPU_COMP2CPU_RCOMP
PCIE_CLK100M_PCH_PCLK_PCIECLK_PCIE_100D
PCIE_FW_R2D_C_PPCIE_85D PCIE
PCIE_85D PCIE PCIE_FW_R2D_P
PCIE_85D PCIE PCIE_FW_D2R_C_P
CPU_RCOMP_PHY CPU_RCOMP CPU_COMP3
PCIE_85D PCIE PCIE_FW_D2R_C_N
GPU_CLK100M_PCIE_NCLK_PCIECLK_PCIE_100D
DMI_S2N_N<3..0>PCIEPCIE_85D
PCIE_FW_D2R_NPCIE_85D PCIE
PCIE_FW_D2R_PPCIE_85D PCIE
SATA_HDD_D2R_NSATA_85D SATA
SATA_HDD_R2D_NSATA_85D SATA
PCIE_85D PCIE PEG_D2R_N<15..0>
PCIE_85D PCIE MXM_PCIE_R2D_P<15..0>
PCIE_85D PCIE MXM_PCIE_D2R_N<15..0>
PCIE_85D PCIE PEG_D2R_P<15..0>
PCIE_85D PCIE MXM_PCIE_D2R_P<15..0>
PCIE_85D PCIE PCIE_MINI_D2R_P
PCIE_85D PCIE PCIE_MINI_R2D_C_P
PCIE_85D PCIE PCIE_MINI_R2D_P
PCIE_85D PCIE MXM_PCIE_R2D_N<15..0>
PCIE_85D PCIE PEG_R2D_C_N<15..0>
PCIE_85D PCIE PEG_R2D_C_P<15..0>
PCIE_FW_R2D_NPCIE_85D PCIE
DMI_N2S_N<3..0>PCIEPCIE_85D
PCIE_CLK100M_MINI_NCLK_PCIE_100D CLK_PCIE
PCIE_CLK100M_MINI_PCLK_PCIE_100D CLK_PCIE
CLK_PCIE_100D PCIE_CLK100M_FW_PCLK_PCIE
PCIE_CLK100M_ENET_NENET_100D ENET_MII
PCIE_CLK100M_ENET_PENET_MIIENET_100D
CLK_PCIE_100D PCIE_CLK100M_FW_NCLK_PCIE
SATA_85D SATA_HDD_R2D_C_PSATA
SATA_HDD_R2D_C_NSATA_85D SATA
SATA_HDD_D2R_C_NSATA_85D SATA
SATA_ODD_R2D_C_PSATA_85D SATA
SATA_85D SATA SATA_ODD_R2D_C_N
SATA_85D SATA SATA_ODD_R2D_P
SATA_85D SATA SATA_ODD_R2D_N
SATA_85D SATA_ODD_D2R_PSATA
SATA_85D SATA SATA_ODD_D2R_N
SATA_85D SATA SATA_ODD_D2R_C_P
SATA_85D SATA_ODD_D2R_C_NSATA
FSB_CLK133M_ITP_NCLK_PCIECLK_PCIE_100D
PCIE_CLK100M_CPU_PCLK_PCIECLK_PCIE_100D
FSB_CLK133M_ITP_PCLK_PCIE_100D CLK_PCIE
GFX_CLK120M_DPLLSS_PCLK_PCIE_100D CLK_PCIE
CLK_PCIECLK_PCIE_100D FSB_CLK133M_CPU_N
CLK_PCIE_100D FSB_CLK133M_CPU_PCLK_PCIE
CLK_PCIECLK_PCIE_100D FSB_CLK133M_PCH_P
CLK_PCIE_100D CLK_PCIE PCH_CLK96M_DOT_P
CLK_PCIECLK_PCIE_100D PCH_CLK96M_DOT_N
CLK_PCIECLK_PCIE_100D PCH_CLK100M_SATA_P
CLK_PCIECLK_PCIE_100D PCH_CLK100M_SATA_N
CLK_PCIE FSB_CLK133M_PCH_NCLK_PCIE_100D
DMI_N2S_P<3..0>PCIEPCIE_85D
DMI_S2N_P<3..0>PCIEPCIE_85D
CPU_RCOMP_PHY CPU_RCOMP CPU_COMP0
CPU_RCOMP_PHY CPU_RCOMP CPU_COMP1
CPU_RCOMP_PHY CPU_RCOMP CPU_PEG_COMP
CPU_RCOMP_PHY CPU_PEG_RBIASCPU_RCOMP
CPU_50S CPU_ITP XDP_BPM_L<7..0>
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II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
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REVISION
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SHEET
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Apple Inc.
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87 54 21
TABLE_PHYSICAL_RULE_ITEM
MINIMUM LINE WIDTH
ALLOW ROUTE
ON LAYER?
LAYER MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_SPACING_RULE_ITEM
LINE-TO-LINE SPACINGLAYERSPACING_RULE_SET WEIGHT
TABLE_SPACING_RULE_HEAD
MINIMUM LINE WIDTH
ALLOW ROUTE
ON LAYER?
LAYER MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
MINIMUM LINE WIDTH
ALLOW ROUTE
ON LAYER?
LAYER MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
MINIMUM LINE WIDTH
ALLOW ROUTE
ON LAYER?
LAYER MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
TABLE_SPACING_RULE_ITEM
MINIMUM LINE WIDTH
ALLOW ROUTE
ON LAYER?
LAYER MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_SPACING_RULE_ITEM
MINIMUM LINE WIDTH
ALLOW ROUTE
ON LAYER?
LAYER MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
LINE-TO-LINE SPACINGLAYERSPACING_RULE_SET WEIGHT
TABLE_SPACING_RULE_HEAD
LINE-TO-LINE SPACINGLAYERSPACING_RULE_SET WEIGHT
TABLE_SPACING_RULE_HEAD
LINE-TO-LINE SPACINGLAYERSPACING_RULE_SET WEIGHT
TABLE_SPACING_RULE_HEAD
TABLE_SPACING_RULE_ITEM
LINE-TO-LINE SPACINGLAYERSPACING_RULE_SET WEIGHT
TABLE_SPACING_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
LINE-TO-LINE SPACINGLAYERSPACING_RULE_SET WEIGHT
TABLE_SPACING_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
LINE-TO-LINE SPACINGLAYERSPACING_RULE_SET WEIGHT
TABLE_SPACING_RULE_HEAD
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
LINE-TO-LINE SPACINGLAYERSPACING_RULE_SET WEIGHT
TABLE_SPACING_RULE_HEAD
LINE-TO-LINE SPACINGLAYERSPACING_RULE_SET WEIGHT
TABLE_SPACING_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_SPACING_RULE_ITEM
MINIMUM LINE WIDTH
ALLOW ROUTE
ON LAYER?
LAYER MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
MINIMUM LINE WIDTH
ALLOW ROUTE
ON LAYER?
LAYER MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
ELECTRICAL_CONSTRAINT_SET
ELECTRICAL_CONSTRAINT_SET
SPI Interface Constraints
USB 2.0 Interface Constraints
HD Audio Interface Constraints
SMBus Interface Constraints
SPACING
NET_TYPENET_TYPE
PHYSICAL
XTAL Constraints
SPACING
PHYSICAL
PCI Bus Constraints
LPC Bus Constraints
PCH CONSTRAINTS
* ?0.2 MMCLK_PCH
=55_OHM_SECLK_PCH_55S =STANDARD=55_OHM_SE =STANDARD* =55_OHM_SE =55_OHM_SE
=STANDARDPCI * ?
0.2 MMCLK_PCI * ?
XTAL =4X_DIELECTRIC ?*
SPI ?* 0.2 MM
=100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF* =100_OHM_DIFFCLK_XTAL =100_OHM_DIFF
* 0.15 MM ?LPC
* ?USB =2x_DIELECTRIC
=55_OHM_SE =STANDARD=55_OHM_SE =55_OHM_SESMB_55S * =STANDARD=55_OHM_SE
=2x_DIELECTRICSMB * ?
=STANDARDCLK_PCI_55S =STANDARD* =55_OHM_SE =55_OHM_SE =55_OHM_SE =55_OHM_SE
=4x_DIELECTRICTOP,BOTTOMUSB ?
0.2 MM*CLK_LPC ?
=90_OHM_DIFF=90_OHM_DIFF =90_OHM_DIFF=90_OHM_DIFF =90_OHM_DIFFUSB_90D * =90_OHM_DIFF
=STANDARD*LPC_55S =55_OHM_SE=55_OHM_SE =55_OHM_SE =55_OHM_SE =STANDARD
=STANDARD=55_OHM_SECLK_LPC_55S * =55_OHM_SE =55_OHM_SE =STANDARD=55_OHM_SE
* =STANDARD=STANDARDHDA_55S =55_OHM_SE =55_OHM_SE=55_OHM_SE =55_OHM_SE
=55_OHM_SE* =STANDARD =STANDARDSPI_55S =55_OHM_SE =55_OHM_SE=55_OHM_SE
=2x_DIELECTRICHDA * ?
0.2 MM ?*COMP_PCH
PCH_55S * =55_OHM_SE =55_OHM_SE =STANDARD=55_OHM_SE=55_OHM_SE =STANDARD
=STANDARD=55_OHM_SEPCI_55S =STANDARD=55_OHM_SE=55_OHM_SE =55_OHM_SE*
IBEX PEAK CONSTRAINTS
SYNC_MASTER=K74_MASTER SYNC_DATE=N/A
HDA AUD_SPKR_OUTLO2L_NOUTHDA_55S
PCH_XCLK_RCOMP
COMP_PCHPCH_55S
SPI_55S SPI SPI_MOSI
SPI_55S SPI_MISOSPI
XTALCLK_XTAL PCH_CLK32K_RTCX2
CLK_XTAL XTAL CK505_XTAL_IN
CLK_XTAL XTAL CK505_XTAL_OUT
USB_90D USB
USB_HUB1_UP_P
USB_90D USB
USB_HUB1_UP_N
USBUSB_90D
USB_HUB2_UP_P
USB_90D USB
USB_HUB2_UP_N
USBUSB_90D
USB_D_MUXED_N
USBUSB_90D
USB_EXTB_N
CLK_XTAL XTAL
USB_HUB2_XTAL1
CLK_XTAL XTAL
USB_HUB2_XTAL2
PCH_CLK25M_XTALIN
XTALCLK_XTAL
XTALCLK_XTAL
PCH_CLK25M_XTALOUT
AUD_SPKR_OUTLO1R_POUTHDAHDA_55S
HDA AUD_SPKR_OUTLO1R_NOUTHDA_55S
HDA_BIT_CLK_RHDA_55S HDA
HDA AUD_SPKR_OUTLO1L_NOUTHDA_55S
LPCLPC_55S
LPC_FRAME_L
CLK_LPC_55S CLK_LPC
LPC_CLK33M_SMC_R
USBUSB_90D
USB_PORT0_N
USBUSB_90D
USB_EXTD_N
USB_90D USB
USB_CAMERA_L_N
XTALCLK_XTAL PCH_CLK32K_RTCX1
SPISPI_55S SPI_CLK
SPISPI_55S SPI_MOSI_R
SPIROM_USE_MLBSPISPI_55S
CLK_LPCCLK_LPC_55S
LPC_CLK33M_LPCPLUS
USBUSB_90D
USB_EXTB_P
USB_90D USB
USB_CAMERA_N
USBUSB_90D
USB_EXTD_P
USBUSB_90D
USB_PORT1_P
USB_PORT3_N
USBUSB_90D
USBUSB_90D
USB_CAMERA_P
HDA_BIT_CLKHDAHDA_55S
SPI_ALT_MISOSPISPI_55S
SPI_ALT_MOSISPI_55S SPI
HDA_55S HDA HDA_SYNC_R
USBUSB_90D
USB_PORT0_P
SPI_CLK_RSPISPI_55S
SPI SPI_MISO_RSPI_55S
SPI_ALT_CLKSPISPI_55S
AUD_SPDIF_CHIPHDAUSBUSB_90D
USB_EXTC_N
USBUSB_90D
USB_EXTC_P
HDA HDA_RST_LHDA_55S
USBUSB_90D
USB_D_MUXED_P
COMP_PCHPCH_55S
PCH_SATAICOMP
COMP_PCHPCH_55S
USB_HUB1_RBIAS
COMP_PCHPCH_55S
USB_HUB2_RBIAS
USB_CAMERA_L_P
USBUSB_90D
USB_90D USB
USB_SDCARD_L_N
CLK_LPCCLK_LPC_55S
LPC_CLK33M_LPCPLUS_R
PCI_55S PCI
PCI_REQ0_L
PCI_REQ1_L
PCI_55S PCI
CLK_PCI_55S CLK_PCI
PCH_CLK33M_PCIOUT
CLK_PCICLK_PCI_55S
PCH_CLK33M_PCIIN
LPC_55S LPC
LPC_AD<3..0>
CLK_LPCCLK_LPC_55S
LPC_CLK33M_SMC
PMCLK_LPC_55S
PM_CLK32K_SUSCLK_R
PMCLK_LPC_55S
PM_CLK32K_SUSCLK
USB_90D USB
USB_EXTA_P
USBUSB_90D
USB_EXTA_N
USBUSB_90D
USB_PORT1_N
USBUSB_90D
USB_PORT2_P
USBUSB_90D
USB_PORT2_N
USB_PORT3_P
USBUSB_90D
USBUSB_90D
USB_BT_P
USBUSB_90D
USB_BT_N
USBUSB_90D
USB_BT_L_P
USB_90D USB
USB_BT_L_N
USB_90D
USB_IR_P
USB
USBUSB_90D
USB_IR_L_P
USB_90D USB
USB_SDCARD_N
USB_90D USB
USB_SDCARD_L_P
USB_90D USB
USB_SDCARD_P
USBUSB_90D
USB_IR_L_N
USB_90D
USB_IR_N
USB
CLK_PCHCLK_PCH_55S PCH_CLK14P3M_REFCLK
HDA HDA_RST_R_LHDA_55S
HDA HDA_SDOUTHDA_55S
HDA_SDOUT_RHDA_55S HDA
SPI_CS0_R_LSPI_55S SPI
SPI_CS0_LSPI_55S SPI
SPI_55S SPI SPI_MLB_CS_L
SPISPI_55S SPI_ALT_CS_L
HDA_55S HDA_SYNCHDA
HDA_SDIN0HDA_55S HDA
HDAHDA_55S AUD_SDI_R
AUD_SPDIF_INHDA
AUD_SPDIF_OUTHDA
HDA AUD_SPKR_OUTLO1L_POUTHDA_55S
AUD_SPKR_OUTLO2L_POUTHDAHDA_55S
HDA AUD_SPKR_OUTLO2R_NOUTHDA_55S
HDA AUD_SPKR_OUTLO2R_POUTHDA_55S
PCH_55S COMP_PCH
PCH_USB_RBIAS
PCH_55S COMP_PCH
PCH_DMI_COMP
CLK_XTAL
USB_HUB1_XTAL1
XTAL
CLK_XTAL XTAL
USB_HUB1_XTAL2
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II NOT TO REPRODUCE OR COPY IT
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MINIMUM LINE WIDTH
ALLOW ROUTE
ON LAYER?
LAYER MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
LINE-TO-LINE SPACINGLAYERSPACING_RULE_SET WEIGHT
TABLE_SPACING_RULE_HEAD
MINIMUM LINE WIDTH
ALLOW ROUTE
ON LAYER?
LAYER MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
MINIMUM LINE WIDTH
ALLOW ROUTE
ON LAYER?
LAYER MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
LINE-TO-LINE SPACINGLAYERSPACING_RULE_SET WEIGHT
TABLE_SPACING_RULE_HEAD
PHYSICAL_RULE_SETAREA_TYPENET_PHYSICAL_TYPE
TABLE_PHYSICAL_ASSIGNMENT_HEAD
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_PHYSICAL_ASSIGNMENT_ITEM
TABLE_PHYSICAL_RULE_ITEM
LINE-TO-LINE SPACINGLAYERSPACING_RULE_SET WEIGHT
TABLE_SPACING_RULE_HEAD
LINE-TO-LINE SPACINGLAYERSPACING_RULE_SET WEIGHT
TABLE_SPACING_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
LINE-TO-LINE SPACINGLAYERSPACING_RULE_SET WEIGHT
TABLE_SPACING_RULE_HEAD
MINIMUM LINE WIDTH
ALLOW ROUTE
ON LAYER?
LAYER MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
CAESAR II (ETHERNET) CONSTRAINTS
AUDIO NET PROPERTIES
ELECTRICAL_CONSTRAINT_SET
AUDIO CONSTRAINTS
PHYSICAL
NET_TYPE
SPACING
FireWire Interface Constraints
CAESAR IV (SD) CONSTRAINTS
NET_TYPE
SPACING
SOURCE:BROADCOM 5764M-DS04-RDS. PAGE 38
CAESAR II (ETHERNET) CONSTRAINTS
ELECTRICAL_CONSTRAINT_SET PHYSICAL
FireWire Net Properties
SPACINGPHYSICAL
NET_TYPE
ELECTRICAL_CONSTRAINT_SET
UNUSED FW NETS PHYSICAL PROPERTIES
PORT 1 & 2 NOT USED
?* =STANDARDENET_SE
ENET_MII * 0.3 MM ?
BUF0_CLK ?* =3:1_SPACING
=STANDARDENET_50S =STANDARD* =50_OHM_SE=50_OHM_SE=50_OHM_SE =50_OHM_SE
* ?0.6 MMENET_DIFF
=100_OHM_DIFF=100_OHM_DIFF=100_OHM_DIFF =100_OHM_DIFF* =100_OHM_DIFF=100_OHM_DIFFENET_100D
FW_110D =110_OHM_DIFF* =110_OHM_DIFF =110_OHM_DIFF =110_OHM_DIFF =110_OHM_DIFF=110_OHM_DIFF
AUD_DIFF 1:1_DIFFPAIR*
AUDIO =3:1_SPACING ?*
=3:1_SPACING* ?SD
* =3:1_SPACING ?FW_TP
=50_OHM_SE =STANDARD*SD_50S =50_OHM_SE =STANDARD=50_OHM_SE=50_OHM_SE
ENET/SD/FW/AUD CONSTRAINTS
SYNC_DATE=N/ASYNC_MASTER=K74_MASTER
FIT;
FW_PORT0_TPA_F_PFW_110D FW_TP
FW_110D FW_PORT0_TPB_NFW_TP
FW_PORT0_TPA_PFW_TPFW_110D
FW_PORT0_TPA_F_NFW_110D FW_TP
FW_PORT0_TPB_F_NFW_TPFW_110D
FW_PORT0_TPB_F_PFW_TPFW_110D
FW_PORT0_TPA_NFW_TPFW_110D
FW_PORT0_TPB_PFW_110D FW_TP
FW_P2_TPA_PFW_TPFW_110D
FW_P1_TPA_NFW_110D FW_TP
FW_P1_TPA_PFW_110D FW_TP
FW_110D FW_TP FW_P0_TPB_L_N
FW_TPFW_110D FW_P0_TPB_L_P
FW_TP FW_P0_TPA_L_NFW_110D
FW_110D FW_TP FW_P0_TPA_L_P
FW_TP FW_P2_TPA_NFW_110D
BCM57765_CR_DATA<7..4>SDSD_50S
ENET_100D ENET_MII PCIE_ENET_R2D_C_N
ENET_MIIENET_100D PCIE_ENET_D2R_N
ENET_MIIENET_100D PCIE_ENET_D2R_P
PCIE_ENET_D2R_C_NENET_100D ENET_MII
ENET_100D ENET_MII PCIE_ENET_R2D_P
ENET_100D ENET_MII PCIE_ENET_R2D_N
ENET_MII PCIE_ENET_D2R_C_PENET_100D
BCM5764_RDACENET_50S ENET_SE
ENET_50S BCM5764_CLK25M_XTALOBUF0_CLK
ENET_50S BUF0_CLK BCM5764_CLK25M_XTAL
ENET_100D ENET_DIFF ENET_MDI_P<3..0>
ENET_MDI_T_P<3..0>ENET_DIFFENET_100D
ENET_DIFF ENET_MDI_T_N<3..0>ENET_100D
ENET_100D ENET_DIFF ENET_MDI_N<3..0>
ENET_50S BUF0_CLK BCM5764_CLK25M_XTALI
PCIE_ENET_R2D_C_PENET_100D ENET_MII
SDCONN_CMDSD_50S SD
SD SDCONN_CLKSD_50S
SDCONN_CLK_RSDSD_50S
SDCONN_DATA<7..0>SDSD_50S
AUDIOAUD_DIFF AUD_LO1_N_R
AUDIOAUD_DIFF AUDAMPINRN
AUD_DIFF AUDIO AUDAMPINBRN
AUD_DIFF AUDIO AUDAMPINBRP
AUD_LO2_N_RAUDIOAUD_DIFF
AUDAMPINCLNAUDIOAUD_DIFF
AUD_LO2_N_LAUD_DIFF AUDIO
AUDAMPINCRPAUDIOAUD_DIFF
AUDAMPINCRNAUD_DIFF AUDIO
AUD_LO2_P_LAUD_DIFF AUDIO
AUD_AMPINLNAUD_DIFF AUDIO
AUD_LO1_P_LAUD_DIFF AUDIO
AUD_DIFF AUD_LO1_N_LAUDIO
AUD_AMPINLPAUD_DIFF AUDIO
AUDAMPINCLPAUDIOAUD_DIFF
AUD_AMPINRNAUD_DIFF AUDIO
AUD_DIFF AUD_AMPINRPAUDIO
AUDIOAUD_DIFF AUD_LO1_P_R
AUDAMPINRPAUDIOAUD_DIFF
AUD_LO2_P_RAUDIOAUD_DIFF
AUDIOAUD_DIFF AUDAMPINLP
AUDAMPINLNAUDIOAUD_DIFF
AUD_DIFF AUDIO AUDAMPINBLP
AUDAMPINBLNAUD_DIFF AUDIO
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TABLE_PHYSICAL_RULE_ITEM
TABLE_SPACING_RULE_ITEM
LINE-TO-LINE SPACINGLAYERSPACING_RULE_SET WEIGHT
TABLE_SPACING_RULE_HEAD
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
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MINIMUM LINE WIDTH
ALLOW ROUTE
ON LAYER?
LAYER MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
PAIRS SHOULD BE WITHIN 100 MILS OF CLOCK LENGTH.
NET_TYPE
DIsplayPort AUX CH intra-pair matching should be 5 ps. No relationship to other signals.
PHYSICAL
UNUSED VIDEO NET PHYSICAL CONSTRAINTS
DisplayPort/TMDS intra-pair matching should be 5 ps. Inter-pair matching should be within 150 ps.
SPACING
Max length of LVDS/DisplayPort/TMDS traces: 12 inches.
ASSINGED IN CONT. MGR.
ELECTRICAL_CONSTRAINT_SET
I113
I114
GRAPHICS CONSTRAINTS
SYNC_MASTER=DAVE SYNC_DATE=01/07/2010
DISPLAYPORT * ?=3:1_SPACING
=85_OHM_DIFF =85_OHM_DIFFDP_85D =85_OHM_DIFF=85_OHM_DIFF 0.08MM* =85_OHM_DIFF
DP_85D DP_EXT_ML_C_P<3..0>DISPLAYPORT
MXM_DP_C_ML_P<3..0>DISPLAYPORTDP_85D
MXM_DP_C_AUX_PDISPLAYPORTDP_85D
DISPLAYPORTDP_85D RDRV_DP_EXT_ML_P<3..0>
DISPLAYPORT DP_INT_AUX_PDP_85D
DISPLAYPORT MXM_DP_C_AUX_NDP_85D
MXM_DP_C_ML_N<3..0>DISPLAYPORTDP_85D
DP_85D DP_INT_ML_C_N<3..0>DISPLAYPORT
DP_INT_ML_C_P<3..0>DP_85D DISPLAYPORT
DISPLAYPORTDP_85D DP_ML_CONN_N<3..0>
MXM_DP_A_AUX_PDISPLAYPORTDP_85D
DISPLAYPORTDP_85D MXM_DP_A_AUX_N
DISPLAYPORTDP_85D DP_ML_CONN_P<3..0>
DP_EXT_ML_C_N<3..0>DP_85D DISPLAYPORT
DISPLAYPORT DP_INT_AUX_NDP_85D
DISPLAYPORT MXM_DP_A_ML_P<3..0>DP_85D
DISPLAYPORT MXM_DP_A_ML_N<3..0>DP_85D
DP_85D DISPLAYPORT GPU_DP_EXT_ML_P<3..0>
DP_85D DISPLAYPORT RDRV_DP_EXT_AUX_P
DP_85D DISPLAYPORT RDRV_DP_EXT_AUX_N
DISPLAYPORTDP_85D DP_EXT_AUX_P
DP_85D DISPLAYPORT DP_EXT_AUX_N
DP_85D MXM_DP_D_AUX_NDISPLAYPORT
MXM_LVDS_A_DATA_N<3..0>DP_85D DISPLAYPORT
DP_85D MXM_DP_B_AUX_NDISPLAYPORT
DP_85D MXM_LVDS_B_DATA_P<3..0>DISPLAYPORT
DISPLAYPORTDP_85D MXM_LVDS_A_DATA_P<3..0>
DP_85D DISPLAYPORT MXM_LVDS_B_CLK_P
DP_85D DISPLAYPORT MXM_LVDS_B_CLK_N
DP_85D MXM_DP_D_ML_P<3..0>DISPLAYPORT
DP_85D MXM_LVDS_B_DATA_N<3..0>DISPLAYPORT
DP_85D MXM_DP_D_ML_N<3..0>DISPLAYPORT
DP_85D MXM_LVDS_A_CLK_NDISPLAYPORT
DP_85D DISPLAYPORT MXM_DP_B_ML_P<3..0>
DP_85D DISPLAYPORT MXM_DP_B_ML_N<3..0>
DP_85D MXM_LVDS_A_CLK_PDISPLAYPORT
DP_85D MXM_DP_D_AUX_PDISPLAYPORT
DP_85D MXM_DP_B_AUX_PDISPLAYPORT
RDRV_DP_EXT_ML_N<3..0>DP_85D DISPLAYPORT
DP_85D DISPLAYPORT GPU_DP_EXT_ML_N<3..0>
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LINE-TO-LINE SPACINGLAYERSPACING_RULE_SET WEIGHT
TABLE_SPACING_RULE_HEAD
TABLE_SPACING_RULE_ITEM
TABLE_PHYSICAL_ASSIGNMENT_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
PHYSICAL_RULE_SETAREA_TYPENET_PHYSICAL_TYPE
TABLE_PHYSICAL_ASSIGNMENT_HEAD
TABLE_PHYSICAL_ASSIGNMENT_ITEM
AREA_TYPE SPACING_RULE_SETNET_SPACING_TYPE1 NET_SPACING_TYPE2
TABLE_SPACING_ASSIGNMENT_HEAD
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
MINIMUM LINE WIDTH
ALLOW ROUTE
ON LAYER?
LAYER MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
II NOT TO REPRODUCE OR COPY IT
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SMC VOLTAGE/CURRENT NET PROPERTIES
SPACINGSPACING
NET_TYPE
ELECTRICAL_CONSTRAINT_SET
NET_TYPE
PHYSICALELECTRICAL_CONSTRAINT_SET
SMBus Interface Constraints
NET_TYPE
SPACING
SMC SMBus Net Properties
PHYSICALELECTRICAL_CONSTRAINT_SET
SMC THERMAL NET PROPERTIES
PHYSICAL
SMC Constraints
SYNC_MASTER=TEMP SYNC_DATE=12/09/2009
THERMAL *GND GND_P2MM
THERMAL * 4:1_SPACING*
THERM_DIFF * 1:1_DIFFPAIR
POWER PWR_P2MMTHERMAL *
=55_OHM_SESMB_55S * =STANDARD=55_OHM_SE =55_OHM_SE =STANDARD=55_OHM_SE
SNS_DIFF 1:1_DIFFPAIR*
?=2x_DIELECTRIC*SMB
SENSE_VTT_R_PTHERM_DIFF THERMAL
SENSE_CPU_VTT_NTHERM_DIFF THERMAL
SMBSMB_55S SMBUS_SMC_A_S3_SCL
SMBUS_SMC_B_S0_SCLSMB_55S SMB
THERMAL VR_ISNS_CPU_PTHERM_DIFF
SNS_T1_DN2_DP3THERMALTHERM_DIFF
SNS_T1_DP2_DN3THERMALTHERM_DIFF
THERMAL SNS_T1_DP1THERM_DIFF
SNS_T2_DP1THERMALTHERM_DIFF
SNS_T2_DN1THERM_DIFF THERMAL
SNS_T2_DP2THERM_DIFF THERMAL
SNS_T2_DN2THERMALTHERM_DIFF
THERMALTHERM_DIFF SNS_ODD_P
THERM_DIFF SNS_ODD_NTHERMAL
THERM_DIFF THERMAL SNS_CPU_H_P
THERM_DIFF SNS_SKIN_PTHERMAL
SNS_AMB_PTHERM_DIFF THERMAL
SNS_AMB_NTHERMALTHERM_DIFF
THERM_DIFF THERMAL SNS_MXM_P
SNS_MXM_NTHERM_DIFF THERMAL
SMC_CPU_ISENSETHERMAL
VR_ISNS_CPU_NTHERMALTHERM_DIFF
VR_CTL VR_CPU_IOUTVID_PHY
THERMAL SMC_CPU_VSENSE
THERMAL SMC_CPU_1V5_ISENSE
SMB SML_PCH_1_CLKSMB_55S
SMBSMB_55S SML_PCH_1_DATA
SMC_EXTALCLK_XTAL XTAL
SNS_T1_DN1THERMALTHERM_DIFF
THERMALTHERM_DIFF SNS_T2_DN3
THERM_DIFF SNS_CPU_H_NTHERMAL
THERM_DIFF SNS_SKIN_NTHERMAL
THERMALTHERM_DIFF SNS_T2_DP3
SMBUS_SMC_A_S3_SDASMB_55S SMB
SMBUS_SMC_B_S0_SDASMBSMB_55S SENSE_VTT_R_NTHERMALTHERM_DIFF
THERM_DIFF THERMAL SENSE_MXM_N
THERMALTHERM_DIFF SENSE_MXM_P
THERMAL SENSE_CPU_VTT_PTHERM_DIFF
THERM_DIFF SENSE_CPU_1V5_NTHERMAL
THERM_DIFF SENSE_CPU_1V5_PTHERMALSMBSMB_55S SMBUS_SMC_0_S0_SCL
SMBUS_SMC_BSA_SDASMBSMB_55S
SMB_55S SMB SMBUS_SMC_MGMT_SDA
SMB_55S SMB SMBUS_SMC_MGMT_SCL
SMBSMB_55S SMBUS_PCH_DATA
SMBSMB_55S SMBUS_SMC_0_S0_SDA
SMBSMB_55S SMBUS_SMC_BSA_SCL
THERMAL SNS_PS_CPU_ISNS
THERMAL SMC_CPU_1V5_VSENSE
THERMAL SMC_CPU_1V5_ISENSE_R
THERMAL GND_SMC_AVSS
HDD_OOB_TEMP_RTHERMAL
SMC_HDD_OOB_TEMPTHERMAL
SMBUS_SMC_MGMT_SDASMBSMB_55S
SMB_55S SMB SMBUS_PCH_CLK
SML_PCH_0_CLKSMB_55S SMB
SMC_XTALCLK_XTAL XTAL
SML_PCH_0_DATASMB_55S SMB
SMB_55S SMB SMBUS_SMC_MGMT_SCL
THERMAL HDD_OOB_TEMP_FILT
HDD_OOB_TEMPTHERMAL
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TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_PHYSICAL_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
LINE-TO-LINE SPACINGLAYERSPACING_RULE_SET WEIGHT
TABLE_SPACING_RULE_HEAD
TABLE_SPACING_RULE_ITEM
PHYSICAL_RULE_SETAREA_TYPENET_PHYSICAL_TYPE
TABLE_PHYSICAL_ASSIGNMENT_HEAD
TABLE_SPACING_ASSIGNMENT_ITEM
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
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PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
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345678
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87 54 21
AREA_TYPE SPACING_RULE_SETNET_SPACING_TYPE1 NET_SPACING_TYPE2
TABLE_SPACING_ASSIGNMENT_HEAD
TABLE_SPACING_ASSIGNMENT_ITEM
PHYSICAL
POWER NET PROPERTIES
NET_TYPE
NET_TYPE
NET_TYPE
PHYSICAL
PHYSICAL
VOLTAGE
SPACING
SPACING
NET_TYPE
VR CTRL NET PROPERTIES
NET_TYPE
SPACING
SPACING
SPACING
VID LENGTH SKEW < 1-INCH
PULL-UP STUB < 1-INCH
VID LENGTH RANGE< 1 TO 15-INCH
PHYSICAL
VR CTRL NET PROPERTIES
VOLTAGESPACING
VR VID NET PROPERTIES
PHYSICAL
PHYSICAL
SENSING NET PROPERTIES
NET_TYPE
POWER NET PROPERTIES
I128
I129
I130
I132
I133
I134
I136
I137
I139
I140
I141
I142
I143
I144
I145
I148
I149
I151
I152
I153
I154
I155
I156
I157
I158
I159
I160
I161
I162
I163
I164
I165
I166
I171
I172
I173
I174
I175
I177
I178
I179
I180
I182
I183
I184
I185
I186
I188
I193
I194
I195
I198
I203
I205
I206
I207
I208
I209
I210
I211
I212
I214
I215
I216
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I263
I265
I266
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I269
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I273
I274
I278
I338
I339
I341
I342
I343
I344
I345
I347
I348
I349
I350
I351
I352
I353
I354
I355
I356
I357
I358
I359
I360
I361
I363
I365
I367
I368
I370
I371
I374
I376
I377
I387
I388
I389
I390
I391
I393
I394
I395
I396
I397
I398
I399
I401
I402
I403
I404
I405
I406
I408
I410
I411
I412
I413
I415
I418
I419
I437
I439
I441
I442
I443
I444
I449
I450
I451
I452
I453
I454
I455
I457
I458
I459
I461
I462
I463
I464
I466
I491
I492
I521
I522
I523
I524
I525
I526
I536
I544
I545
I546
I554
I557
I56
I563
I564
I57
I575
I577
I578
I579
I58
I587
I59
I594
I595
I596
I604
I606
I607
I608
I610
I613
I614
I615
I616
I617
I618
BGA_P2MMSWITCHNODE BGA_P1MM*
POWER CONSTRAINTS
SYNC_MASTER=K74_MASTER SYNC_DATE=N/A
** SWITCHNODESWITCHNODE
0.2MMVR_CTL * ?
GNDSWITCHNODE BGA_P2MMBGA_P1MM
*SWITCHNODE 6:1_SPACINGPOWER
*VID_PHY 39_OHM_SE
BGA_P1MMPOWERSWITCHNODE BGA_P2MM
BGA_P1MMSWITCHNODE SWITCHNODE BGA_P2MM
SWITCHNODE * 6:1_SPACINGGND
PP3V3_S0_HS_F
3.3VPOWER POWER
POWERPOWER PP3V3_S03.3V
VTT_OFS
VR_CTLVR_CTL_PHY
VR_CTLVR_CTL_PHY P3V42G3H_FB
PP1V5_S0_CK505_R
1.5VPOWERPOWER
PP1V5_S0
POWERPOWER 1.5V
PP1V5_S0_CK505_F
POWER POWER 1.5V
POWER POWER PP1V5_FW_VDDA1.5V
VR_CPU_DRV2_BOOT
VR_CTLVR_CTL_PHY
THERMAL VR_CPU_ISNS2_R_P
SNS_DIFF
THERMAL
VR_CPU_ISNS3_R_P
SNS_DIFF
SNS_DIFF VR_CPU_VSEN
SNS_DIFF VR_CPU_VSNS_R_N
SNS_DIFF VR_CPU_VSNS_XW_P
SWITCHNODE VR_CPU_DRV3_UGATE
VR_CTL_PHY
DDR_REG_VTTSNS
VR_CTLVR_CTL_PHY
DDR_REG_VDDQSNS
VR_CTLVR_CTL_PHY
VR_CPU_ISNS1_P
SNS_DIFF THERMAL
VR_CPU_ISNS1_N
THERMALSNS_DIFF
THERMAL VR_CPU_ISNS1_R_P
SNS_DIFF
VR_CPU_DRV1_GDSEL
VR_CTLVR_CTL_PHY
POWER POWER PPVBATT_G3_RTC3.3V
VTT_REG_ISNS_N
SNS_DIFF
CPU_VTTSENSE_R_N
SNS_DIFF
SNS_DIFF CPU_VTTSENSE_R_P
SNS_DIFF VR_CPU_RGND
3.3VPOWERPOWER PPVTT_S3_DDR_BUF
3.3VPOWERPOWER PPV_S0_MXM_PWRSRC
3.3VPOWER POWER PPVOUT_SO_PCH_VCCRTC_NCTF
POWER PP3V3_FW_AVDD
3.3VPOWER
PCHCORE_REG_TRIP
VR_CTLVR_CTL_PHY
PP3V3_S3_BT_FLT
POWER POWER 3.3V
SNS_DIFF CPU_VTTSENSE_P
VTT_REG_FB
VR_CTL_PHY VR_CTL
VTT_REG_PH1_SNUB
VR_CTLVR_CTL_PHY
VR_CTL_PHY VR_CTL P3V42G3H_BOOST
VTT_REG_OCSET
VR_CTLVR_CTL_PHY
VTT_REG_LGATE
SWITCHNODEVR_CTL_PHY
VTT_REG_FS
VR_CTLVR_CTL_PHY
SNS_DIFF VTT_REG_ISNS_P
3.3V PP3V3_S0_TSENS_R
POWERPOWER
CPU_VID<6>
VR_CTLVID_PHY
VR_CTL CPU_VID<7>
VID_PHY
CPU_PSI_LVR_CTLVID_PHY
CPU_VID<4>
VID_PHY VR_CTL
CPU_VID<0>
VR_CTLVID_PHY
PP1V5_S3
POWER POWER 1.5V
POWER 1.5VPOWER PP1V5_CPU_MEM
PP1V05_S0_PCH_VCCAPLL_SATA
1.05VPOWERPOWER
PPVP_FW_PHY_CPS
POWER POWER 12V
POWER PP12V_S0_CPU_FLTRD
12VPOWER
POWER 1.5VPOWER PP0V75_S3_MEM_VREFDQ_A
SWITCHNODEPOWER 1.8V P1V8_REG_PHASE
PCHCORE_REG_PHASE
SWITCHNODE 1.05VPOWER
VR_CPU_PHASE2
1.5VPOWER SWITCHNODE
POWER POWER 12V PP12V_S5
12VPOWER PP12V_S0_FAN0_L
POWER
12VPOWER POWER FW_PORT0_VP_F
12VPOWER POWER FW_PORT0_VP
POWER 3.3V
PP3V3_S0_CK505_F
POWER
VR_CTL
DDR_REG_CS
VR_CTL_PHY
P3V3S5_REG_BOOT_R
VR_CTL_PHY VR_CTL
PP5V_S5
POWER POWER 5V
POWERPOWER 1.96V
PP1V96_FW_PLLVDD
VR_CTL P3V3S5_REG_BOOT
VR_CTL_PHY
DDR_REG_BOOT
VR_CTL_PHY VR_CTL
SWITCHNODEVR_CTL_PHY DDR_REG_UGATE
VR_CTL VTT_REG_COMP
VR_CTL_PHY
VR_CTLVR_CTL_PHY VTT_REG_BOOT
VR_CTLVR_CTL_PHY PCHCORE_REG_BOOT
PCHCORE_REG_TON
VR_CTLVR_CTL_PHY
VR_CPU_SS
VR_CTLVR_CTL_PHY
SWITCHNODEVR_CTL_PHY
DDR_REG_LGATE
DDR_REG_BOOT_R
VR_CTLVR_CTL_PHY
VR_CTL PCHCORE_REG_BOOT_R
VR_CTL_PHY
SWITCHNODEVR_CTL_PHY PCHCORE_REG_UGATE
THERMAL VR_CPU_ISNS3_P
SNS_DIFF
POWER PP5V_USB2_PORT0_F
5VPOWER
POWER PP5V_USB2_PORT15VPOWER
POWER PP5V_USB2_PORT2
5VPOWER
POWERPOWER PP5V_USB2_PORT3
5V
VR_CTL_PHY VR_CTL VTT_REG_COMP
VR_CPU_BOOT2_RC
VR_CTLVR_CTL_PHY
VR_CPU_PH2_SNUB
VR_CTLVR_CTL_PHY
VR_CPU_PH3_SNUB
VR_CTLVR_CTL_PHY
VR_CPU_PWM1
VR_CTLVR_CTL_PHY
VR_CPU_PWM2_R
VR_CTLVR_CTL_PHY
VR_CPU_PWM3
VR_CTLVR_CTL_PHY
VR_CPU_PWM3_R
VR_CTLVR_CTL_PHY
VR_CPU_REF
VR_CTLVR_CTL_PHY
POWER PP5V_USB2_PORT1_F
5VPOWER
POWER PP5V_USB2_PORT2_F
5VPOWER
POWER DDR_REG_PGNDPOWER
POWERPOWER DDR_REG_CSGND
P3V3S5_REG_FB
VR_CTL_PHY VR_CTL
DDR_REG_PHASE
POWER 1.5VSWITCHNODE
PP5V_S5_PCH_V5REFSUS
POWERPOWER 5V
POWER
PP5V_USB2_PORT3_F
5VPOWER
VR_CTL_PHY VR_CTL DDR_REG_FB
5V
PP5V_S3_IR_FLT
POWERPOWER
POWER PP5V_S0_CPU_VCORE_VCC
POWER 5V
PCHCORE_REG_LGATE
SWITCHNODEVR_CTL_PHY
VR_CPU_IOUT_PD
VR_CTLVR_CTL_PHY
POWER POWER PP5V_USB2_PORT0
5V
POWER POWER 3.3V PP3V3_S3_SDCARD_FLT
SWITCHNODE 1.1VPOWER VTT_REG_PHASE
1.1VPOWER POWER PPVCORE_S0_CPU
POWER 1.1VPOWER
PPVCORE_S0_CPU_REG2
1.05VPOWERPOWER PP1V05_S0_CK505_F
3.4V PP3V3_G3H_SMC_AVCC
POWER POWER
POWER 12V
PP12V_S0_FAN1_L
POWER
POWER 12VPOWER PP12V_S0_FAN2_L
POWER POWER 12V PP12V_G3H
1.1VPOWERPOWER PPVCORE_S0_CPU_REG1
1.05VPOWERPOWER PP1V05_S0_PCH_VCCADPLLA
1.5VPOWERPOWER PP1V8_S0
POWER PP1V8R1V5_S0_PCH_VCCVRM
POWER 1.5V
VR_CPU_PWM2
VR_CTLVR_CTL_PHY
VR_CPU_PH1_SNUB
VR_CTLVR_CTL_PHY
VR_CPU_DRV1_BOOT
VR_CTLVR_CTL_PHY
VR_CPU_DRV1_UGATE
SWITCHNODEVR_CTL_PHY
VR_CPU_DRV2_GDSEL
VR_CTLVR_CTL_PHY
VR_CPU_DRV2_UGATE
SWITCHNODEVR_CTL_PHY
VR_CPU_DRV2_LGATE
VR_CTL_PHY SWITCHNODE
VR_CPU_DRV1_LGATE
SWITCHNODEVR_CTL_PHY
VR_CPU_COMP
VR_CTLVR_CTL_PHY
VR_CTLVR_CTL_PHY VR_CPU_TM
POWERPOWER 3.3V PP3V3_S0_PCH_VCCA_DAC
3.3V PP3V3_S3
POWER POWER
PP3V3_S5
3.3VPOWER POWER
THERMALSNS_DIFF VR_CPU_ISNS2_R_N
VR_CPU_ISNS1_R_N
THERMALSNS_DIFF
VR_CPU_IMON
VR_CTLVR_CTL_PHY
VR_CTL VR_CPU_FB_R
VR_CTL_PHY
VR_CTLVR_CTL_PHY VR_CPU_DRV3_BOOT
VR_CPU_BOOT3_RC
VR_CTLVR_CTL_PHY
VR_CTL_PHY VR_CTL VR_CPU_BOOT1_RC
VR_CTL_PHY
VR_CPU_TCOMP
VR_CTL
VR_CPU_PWM4_R
VR_CTLVR_CTL_PHY P1V8_REG_POR
VR_CTLVR_CTL_PHY
VR_CTL_PHY P3V3S5_REG_ISEN
VR_CTL
SWITCHNODEVR_CTL_PHY
P3V3S5_REG_LGATE
P3V3S5_REG_OCSET
VR_CTLVR_CTL_PHY
VR_CTL_PHY SWITCHNODE P3V3S5_REG_UGATE
P3V3S5_REG_SNUB
VR_CTLVR_CTL_PHY
VR_CTL_PHY VR_CTL P5VS3_REG_BOOT
VR_CTL_PHY VR_CTL P5VS3_REG_FB
VR_CTL_PHY P5VS3_REG_ISEN
VR_CTL
P5VS3_REG_LGATE
VR_CTL_PHY SWITCHNODE
P5VS3_REG_OCSET
VR_CTL_PHY VR_CTL
P5VS3_REG_UGATE
VR_CTL_PHY SWITCHNODE
CPU_VID<1>
VR_CTLVID_PHY
CPU_VID<2>
VR_CTLVID_PHY
CPU_VID<3>
VR_CTLVID_PHY
POWERPOWER 12V PP12V_S0
POWER 1.96VPOWER PP1V95_FW_FWPHY
CPU_VID<5>
VR_CTLVID_PHY
SWITCHNODEVR_CTL_PHY VR_CPU_DRV3_LGATE
VR_CTLVR_CTL_PHY VR_CPU_DRV3_GDSEL
PCHCORE_REG_VFB
VR_CTLVR_CTL_PHY
VR_CTLVR_CTL_PHY
VR_CPU_FS
VR_CPU_FB
VR_CTLVR_CTL_PHY
VR_CPU_FAN
VR_CTLVR_CTL_PHY
VR_CPU_COMP_R
VR_CTLVR_CTL_PHY
VR_CPU_COMP_RC
VR_CTLVR_CTL_PHY
VR_CPU_DAC
VR_CTLVR_CTL_PHY
SNS_DIFF CPU_VTTSENSE_N
PP5V_S3_DDR_REG_V5FILT
5VPOWER POWER
5VPOWERPOWER PP5V_S3
VTT_REG_VSENSNS_DIFF
VTT_REG_RGND
SNS_DIFF
VTT_REG_RTO1SNS_DIFF
PP5V_S3_CAMERA_FLT
POWER POWER 5V
POWERPOWER
PP5V_S0_PCH_V5REF
5V
POWER 3.3V PP3V3_G3_RTC
POWER
POWER POWER PP3V3_FW_VDDA
3.3V
POWER POWER 3.3V PP3V3_FW_PLLVDD
POWER PP3V3_FW_ESD
POWER 3.3V
POWER PP3V3_AUDIO_SPDIF_JACK3.3VPOWER
POWER PPVBATT_G3_RTC_R3.3VPOWER
POWERPOWER 3.3V PP_ENET_CTRL12
4V5_REG_IN4.5VPOWERPOWER
PP4V5_AUDIO_ANALOG
POWER 4.5VPOWER
5VPOWER POWER PP5V_S0
3.42VPOWERPOWER PP3V42_G3H
VTT_REG_RTR1
SNS_DIFF
POWER 3.3V PPVOUT_G3_PCH_DCPRTC
POWER
PPVOUT_S5_PCH_DCPSUSBYP3.3VPOWER POWER
PPVOUT_S5_PCH_DCPSUS
3.3VPOWERPOWER
POWER PPVOUT_S0_PCH_DCPSST3.3VPOWER
PPVCORE_S0_CPU_REG3
POWER POWER 1.1V
1.5VPOWER POWER PP0V75_S3_MEM_VREFCA_B
P5VS3_REG_PHASE
5VSWITCHNODEPOWER
POWER 3.3VSWITCHNODE P3V3S5_REG_PHASE
3.3V PP3V3_S0_DPFUSE
POWERPOWER
POWER 1.5VSWITCHNODE VR_CPU_PHASE1
VR_CPU_PHASE3
POWER SWITCHNODE 1.5V
P3V42G3H_SW
3.4VPOWER SWITCHNODE
PP0V75_S3_MEM_VREFCA_A
1.5VPOWER POWER
POWER 1.5VPOWER
PP0V75_S3_MEM_VREFDQ_B
PP12V_AUD_SPKRAMP_PLANE
12VPOWER POWER
1.05VPOWERPOWER PP1V05_S0
PP0V75_S0
0.75VPOWER POWER
PPVTT_S0_DDR0.75VPOWER POWER
1.1VPOWER POWER PPVTT_S0
PP1V05_SM_PCH_LAN1.05VPOWER POWER
CPU_VCC_PKG_SENSE_N
SNS_DIFF
CPU_VCC_PKG_SENSE_P
SNS_DIFF
VR_CPU_VSNS_XW_N
SNS_DIFF
SNS_DIFF VR_CPU_ISNS3_R_N
THERMAL
VR_CPU_ISNS2_P
SNS_DIFF THERMAL
THERMAL VR_CPU_ISNS2_N
SNS_DIFF
THERMAL VR_CPU_ISNS3_N
SNS_DIFF
SNS_DIFF VR_CPU_VSNS_R_P
POWER 3.3V PP3V3_G3H_AVREF_SMC
POWER
PP1V05_S0_PCH_VCCAPLL_EXP
POWER 1.05VPOWER
PP1V05_S0_PCH_VCCAPLL_FDI
1.05VPOWERPOWER
PP1V05_S0_PCH_VCCADPLLB_F
POWER 1.05VPOWER
PP1V05_S0_PCH_VCCADPLLB1.05VPOWER POWER
1.05VPOWERPOWER PP1V05_S0_PCH_VCCA_CLK
VR_CTL_PHY VR_CTL
VTT_REG_UGATE
VR_CTL VTT_REG_REF
VR_CTL_PHY
VTT_REG_REF
VR_CTLVR_CTL_PHY
3.3V PP3V3_S0_DPPWR
POWERPOWER
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II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
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36
BRANCH
REVISION
DRAWING NUMBER SIZE
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SHEET
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PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
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NOTICE OF PROPRIETARY PROPERTY:
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I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
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36
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REVISION
DRAWING NUMBER SIZE
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87 54 21
TABLE_SPACING_ASSIGNMENT_ITEM
AREA_TYPE SPACING_RULE_SETNET_SPACING_TYPE1 NET_SPACING_TYPE2
TABLE_SPACING_ASSIGNMENT_HEAD
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
PM NET PROPERTIES
(PM, RESET, EN, PGOOD)
NET_TYPE
PHYSICAL
NET_TYPE
PHYSICAL SPACING
SPACING
I1
I10
I100
I101
I103
I104
I117
I12
I120
I122
I2
I24
I25
I29
I3
I30
I31
I32
I33
I34
I35
I36
I37
I39
I4
I41
I42
I43
I44
I45
I46
I47
I48
I49
I5
I50
I52
I54
I56
I57
I59
I6
I60
I62
I63
I64
I65
I66
I67
I68
I69
I7
I70
I73
I74
I75
I76
I77
I78
I79
I80
I81
I82
I83
I84
I85
I86
I87
I88
I89
I9
I90
I91
I92
I95
I96
I97
I98
I99
*PM 2:1_SPACING*
DEFAULTGNDPM_VTT *
PM_VTT 3:1_SPACING**
PM_VTTPM_VTT * 2:1_SPACING
DEFAULTGND *PM
SYNC_DATE=N/ASYNC_MASTER=K74_MASTER
PM RESETS ENABLES PGOOD CONST
PM_SLP_S3_L
PM
PM_PGOOD_PVCORE_CPU
PM
PM_RSMRST_PCH_L
PM
PM PM_ACDC_PS_ON
PM_CLKRUN_L
PM
PM_CLK32K_SUSCLK_R
PM
PM_CLK32K_SUSCLK
PM
PM PM_BATLOW_L
CK505_27MHZ_EN
PM
PM RSMRST_PWRGD
PLT_RESET_LS1V1_L
PM_VTT
4V5_REG_EN
PM
PM
ALL_SYS_PWRGD_R
SMC_RESET_L
PM
ALL_SYS_PWRGD_SMC
PM
PLT_RESET_L
PM
CPUVTT_REG_EN
PM
CPUVTT_REG_PGOOD
PM_VTT
DDRVTT_EN
PM
PM PGOOD_P1V8_S0
PM P1V5_S0_EN
PM PGOOD_P5V_S0
PM PGOOD_P3V3_S3
PM PGOOD_CPU_GFX_DDR
PM PGOOD_1V8_S0_G2
PM PGOOD_P1V5_S0
SMC_DELAYED_PWRGD
PM
DEBUG_RESET_L
PM
FWXIO_SNOOP_EN
PM
PM SDCARD_RESET
PEG_RESET_L
PM
PCHCORE_REG_PGOOD
PM
PM P5VS3_EN
PM P12V_S3_EN
PM PGOOD_PCH_AND_P1V8
PM PGOOD_P3V3_S0
PM RTC_RESET_L
XDP_PWRGD
PM_VTT
MINI_RESET_L
PM
PM RTC_RESET_L
PM
PGOOD_SYSPWROK_R
PM PGOOD_SYSPWROK
PM PGOOD_PCH_S0
PM PCHCORE_REG_EN
PM_MEM_PWRGD
PM_VTT
PM_MXM_PGOOD
PM
PM_RSMRST_L
PM
PM PM_SYS_PWRGD
PM
PM_EXT_TS_L<0>
PM PM_EXT_TS_L<1>
PM_LAN_PWRGD
PM
FSB_CPURSTOUT_L
PM_VTT
PM_SLP_M_L
PM
PM_VTT CPU_PWRGD
PM CPU_RESET_L
PM_SYSRST_L
PM
PM_SYNC
PM_VTT
PM PM_SLP_S4_1_L
PM PM_SLP_S4_L
PM PM_SLP_S5_L
PM PM_SUS_PWR_ACK
SDCARD_PLT_RST_L
PM
PM
PGOOD_1V8_S0_G1
PM P3V3S0_EN
PM
P5VS0_EN
PM P3V3S3_EN
PM_VTT XDP_DBRESET_L
PM_VTT XDP_CPUPWRGD
SMC_LRESET_L
PM
MEM_RESET_L
PM
PM ENET_RESET_L
PM FW_RESET_L
FWPHY_RESET_L
PM
CPU_MEM_RESET_L
PM
PM_PGOOD_DDRREG_S3
PM
PM_PCH_PWRGD
PM
PM_VTT PM_THRMTRIP_L
PM_ME_PWRGD
PM
PM PM_PWRBTN_L
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II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
36
BRANCH
REVISION
DRAWING NUMBER SIZE
D
R
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
21
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Apple Inc.
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
87 54 21
1 GROUND TESTPOINT NEAR J4780
1 GROUND TESTPOINT NEAR J5700
1 Ground Testpoint near J6601
J5700 CPU FAN
J5560 SKIN TEMP SENSOR
1 GROUND TESTPOINTS NEAR J5400
J5400 HDD TEMP SENSOR
J5601 HD FAN
2 Ground Testpoints near J4750
1 PP3V3_S3 Testpoint near J4750
J6602 AUDIO RIGHT SPEAKER
4 GROUND TESTPOINTS NEAR J6600
2 TP’S
2 TP’S
J6600 AUDIO AUXILIARY CONNECTOR
J6603 AUDIO LEFT SPEAKER
J4700 USB CAMERA
J6601 AUDIO MICROPHONE
1 TP’S
J5600 ODD FAN
FUNCTIONAL TESTPOINTS FOR MAC-1 & ICT
J5551 ODD TEMP SENSOR
J4750 USB CARD READER
6 GROUND TESTPOINTS NEAR J4700
1 PP3V3_S3 TESTPOINT NEAR J4700
1 PP5V_S3_REG Testpoint near J4700
J4780 IR BOARD
1 PP5V_S0 Testpoint near J4520
1 GROUND TESTPOINTS NEAR J4520
J4520 SATA ODD (HIGH SPEED)
17 TP’S
44 85
44 85
44 85
44 85
44 85
44 85
53
53
53 89
53
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5 89
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SYNC_MASTER=K74_MASTER
K74/K75 ICT/FCT
SYNC_DATE=N/A
FUNC_TEST=TRUESMC_ODD_DETECT
FAN_2_GND FUNC_TEST=TRUE
FAN_2_PWR_L FUNC_TEST=TRUE
MIN_ALLOWED_TPS=1
FUNC_TEST=TRUEPP5V_S3_REG
FUNC_TEST=TRUE
MIN_ALLOWED_TPS=1
PP5V_S0
=SMB_ALS_SDA FUNC_TEST=TRUE
=SMB_ALS_SCL FUNC_TEST=TRUE
FUNC_TEST=TRUESNS_ODD_P
FUNC_TEST=TRUESNS_ODD_N
FUNC_TEST=TRUEHDD_OOB_TEMP_FILT
FUNC_TEST=TRUEAUD_MIC_IN1_N_CONN
FUNC_TEST=TRUEAUD_SPKR_OUTLO1L_POUT
AUD_SPKR_OUTLO2L_NOUT FUNC_TEST=TRUE
FUNC_TEST=TRUEAUD_SPKR_OUTLO2L_POUT
SNS_AMB_P FUNC_TEST=TRUE
FUNC_TEST=TRUESDCARD_RESET
FUNC_TEST=TRUEAUD_HP_R_JACK
FUNC_TEST=TRUEAUD_HP_TYPEDET_JACK
FUNC_TEST=TRUEAUD_IP_PERPH_JACK
FUNC_TEST=TRUEAUD_HP_TIPDET_JACK
AUD_SPDIFIN_JACK FUNC_TEST=TRUE
AUD_SPDIF_OUT_JACK FUNC_TEST=TRUE
AUD_LI_DET_JACK FUNC_TEST=TRUE
HS_MIC_LO_JACK FUNC_TEST=TRUE
HS_MIC_HI_JACK FUNC_TEST=TRUE
FUNC_TEST=TRUEAUD_SPKR_OUTLO1L_NOUT
FUNC_TEST=TRUEFAN_TACH0_L
FUNC_TEST=TRUEGND_AUDIO_MIC1_CONN
AUD_LI_GND_JACK FUNC_TEST=TRUE
AUD_LI_L_JACK FUNC_TEST=TRUE
FAN_0_GND FUNC_TEST=TRUE
PP12V_S0_FAN0_L FUNC_TEST=TRUE
USB_CAMERA_L_P FUNC_TEST=TRUE
MIN_ALLOWED_TPS=1
FUNC_TEST=TRUEPP5V_S3
FUNC_TEST=TRUEUSB_SDCARD_L_N
AUD_LI_R_JACK FUNC_TEST=TRUE
PP3V3_AUDIO_SPDIF_JACK
MIN_ALLOWED_TPS=2
FUNC_TEST=TRUE
FUNC_TEST=TRUEAUD_HP_L_JACK
FUNC_TEST=TRUEAUD_HP_GND_JACK
USB_IR_L_P FUNC_TEST=TRUE
PP3V3_S3
MIN_ALLOWED_TPS=2
FUNC_TEST=TRUE
FUNC_TEST=TRUEAUD_SPKR_OUTLO2R_NOUT
FUNC_TEST=TRUEAUD_SPKR_OUTLO2R_POUT
AUD_MIC_IN1_P_CONN FUNC_TEST=TRUE
FUNC_TEST=TRUEAUD_SPKR_OUTLO1R_POUT
AUD_SPKR_OUTLO1R_NOUT FUNC_TEST=TRUE
USB_SDCARD_L_P FUNC_TEST=TRUE
FUNC_TEST=TRUEUSB_IR_L_N
PP5V_S3_IR_FLT FUNC_TEST=TRUE FUNC_TEST=TRUEFAN_1_GND
FUNC_TEST=TRUEFAN_TACH1_L
FUNC_TEST=TRUEFAN_1_PWR_L
FUNC_TEST=TRUEPP12V_S0_FAN1_L
FUNC_TEST=TRUESNS_SKIN_P
FUNC_TEST=TRUESNS_SKIN_N
SNS_AMB_N FUNC_TEST=TRUE
FUNC_TEST=TRUEPP12V_S0_FAN2_L
FAN_TACH2_L FUNC_TEST=TRUE
FAN_0_PWR_L FUNC_TEST=TRUE
FUNC_TEST=TRUEUSB_BT_L_N
FUNC_TEST=TRUEUSB_BT_L_P
USB_CAMERA_L_N FUNC_TEST=TRUE
GND FUNC_TEST=TRUE
MIN_ALLOWED_TPS=17
110 OF 110
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