ARM_CPSR_Full_Detailed_Presentation.pptx

arm cpsr in detail

1. Current Program Status Register (CPSR) in ARM Comprehensive Explanation with Detailed Breakdown Across Multiple Slides

2. Introduction to CPSR • CPSR (Current Program Status Register) is a 32-bit register in ARM processors. • It controls execution flow, processor modes, and interrupt handling. • Plays a key role in exception handling and determining instruction execution. • Used to monitor and modify processor behavior dynamically.

3. Importance of CPSR • CPSR provides status of the ARM processor during execution. • It allows the processor to switch between modes efficiently. • Used in debugging and exception handling. • Helps in conditional execution of instructions based on flag conditions.

4. CPSR Register Layout • CPSR consists of four fields: - Flags: Condition flags (N, Z, C, V, Q) - Status: Reserved for future use - Extension: Reserved for future use - Control: Determines processor mode, state, and interrupt masking.

5. Processor Modes in ARM - Overview • ARM supports 7 modes for different execution needs: - User (usr) – Non-privileged mode for applications. - Supervisor (svc) – Privileged mode for OS kernel. - IRQ (irq) – Handles standard interrupts. - FIQ (fiq) – Handles fast interrupts. - Abort (abt) – Handles memory access violations. - Undefined (und) – Handles unsupported instructions. - System (sys) – Privileged user mode.

6. Privileged vs Non-Privileged Modes • **Privileged Modes**: - Allow full access to CPSR. - Used for handling exceptions, OS-level tasks, and interrupts. • **Non-Privileged Modes**: - Limited access to CPSR. - Used for user applications. • Mode switching is done using CPSR.

7. Processor Mode Switching • The ARM core can switch between modes using specific instructions. • When an interrupt occurs, the processor moves to IRQ or FIQ mode. • CPSR is saved into SPSR before switching modes. [Insert Figure Here]

8. Banked Registers in ARM • Certain registers are banked, meaning they have separate copies for each mode. • This allows efficient context switching without affecting user mode registers. • Example: IRQ mode has separate R13 (SP) and R14 (LR), preventing conflicts.

9. Why Banked Registers are Used? • Avoids conflicts when switching between modes. • Allows each mode to maintain its own stack pointer. • Speeds up exception and interrupt handling.

10. Banked Register Mapping • Each mode has a subset of the registers that are banked. • Example: IRQ mode has R13_irq, R14_irq, and SPSR_irq. • These registers are not accessible in User mode .

11. Another important feature to note is that the cpsr is not copied into the spsr when a mode change is forced due to a program writing directly to the cpsr .The saving of the cpsr only occurs when an exception or interrupt is raised. When power is applied to the core, it starts in supervisor mode, which is privileged. Starting in a privileged mode is useful since initialization code can use full access to the cpsr to set up the stacks for eachof the other modes. The following Table lists the various modes and the associated binary patterns.The last column of the table gives the bit patterns that represent each of the processor modes in the cpsr

12. State andInstruction Sets : The state of the core determines which instruction set is being executed. There are three instruction sets : ARM Thumb Jazelle . The ARM instructionset: isonlyactive when the processorisin ARMstate . The Thumb instructionset is only active when the processor is in Thumbstate.Once in Thumb state the processor is executing purely Thumb 16-bitinstructions. You cannot inter-mingles equential ARM, Thumb,and Jazelle instructions . The Jazelle J and Thumb T bits in the cpsr reflect the state of the processor . When both J and T bits are 0 , the processor is in ARM state and executes ARM instructions.This is the case when power is applied to the processor . When the T bit is 1, then the processor is in Thumb state. To change states the core executes a specialized branch instruction . ThefollowingTablecomparesthe ARMandThumb instructionsetfeatures .

13. Interrupts in ARM • Interrupts allow the processor to respond to external events. • Two types: - **IRQ (Interrupt Request):** General-purpose interrupts. - **FIQ (Fast Interrupt Request):** Higher-priority, faster response.

14. Interrupt Handling Process 1. An interrupt signal is received by the processor. 2. The processor switches to IRQ or FIQ mode. 3. CPSR is saved in SPSR. 4. Execution jumps to the interrupt handler. 5. After execution, CPSR is restored, resuming normal operation.

15. Types of Exceptions Exceptions are special conditions that alter normal execution. 1 . **Reset** – Occurs on processor startup or reset signal. 2. **Undefined Instruction** – Triggered when an unknown instruction is executed. 3. **Software Interrupt (SWI)** – Used for OS calls and system services. 4. **Prefetch Abort** – When instruction fetch fails due to memory issues. 5. **Data Abort** – Occurs when an invalid memory access happens.

16. Software Interrupt (SWI) in Detail • SWI is a special instruction used to invoke system calls. • Used to switch from user mode to supervisor mode. • Common in OS kernels and embedded system calls. • The processor jumps to the SWI vector in the vector table.

17. Exception Handling Process 1. Processor saves CPSR into SPSR of the mode handling the exception. 2. The processor switches to the relevant mode (e.g., Abort mode). 3. Execution jumps to the corresponding address in the vector table. 4. Exception handler executes necessary routines. 5. The handler restores CPSR and resumes normal execution.

18. Condition Flags in CPSR • CPSR contains condition flags that store ALU operation results: - **N (Negative Flag):** Set if result is negative. - **Z (Zero Flag):** Set if result is zero. - **C (Carry Flag):** Set if an unsigned overflow occurs. - **V (Overflow Flag):** Set if a signed overflow occurs. [Insert Figure Here]

19. Conditional Execution: Conditional execution controls whether or not the core will execute an instruction. Prior to execution, the processor compares the condition attribute with the condition flags in the cpsr . If they match, then the instruction is executed; otherwise the instruction is ignored. The condition attribute is post-fixed to the instruction mnemonic ,which is encoded into the instruction. The following Table lists the conditional execution code mnemonics. When a condition mnemonic is not present, the default behavior is to set it to always(AL) execute.

20. ARM Pipeline Execution • ARM processors use pipelining to enhance instruction throughput. • Three-stage pipeline: 1. **Fetch:** Instruction is fetched from memory. 2. **Decode:** Instruction is interpreted. 3. **Execute:** Instruction is processed .

21. Advantages of Pipelining • Increases execution speed by overlapping instructions. • Reduces instruction latency. • Allows continuous flow of instructions through the processor.

22. Core Extensions in ARM • ARM cores include hardware extensions to improve performance and efficiency. • Three major core extensions: - Cache & Tightly Coupled Memory (TCM) - Memory Management (MMU, MPU) - Coprocessor Interface.

23. Cache and Tightly Coupled Memory (TCM) • Cache stores frequently accessed data to speed up execution. • ARM processors may have **separate instruction and data caches** (Harvard architecture). • TCM is a high-speed SRAM used for real-time tasks requiring predictable memory access.

24. • Diagram comparing cache-based and TCM-based architectures. • Shows how memory access latency is reduced .

25. Memory Management – MMU & MPU • **Memory Protection Unit (MPU):** - Defines memory regions with access permissions. - Used in embedded systems with simple memory maps. • **Memory Management Unit (MMU):** - Provides virtual memory mapping. - Supports multitasking operating systems (Linux, Android).

26. Coprocessors in ARM • ARM supports coprocessors to enhance specific functionalities. • Example: Vector Floating Point (VFP) coprocessor for floating-point arithmetic. • Coprocessor 15 (CP15) controls cache, MMU, and system configuration.