ASIC design Flow (Digital Design)

This Presentation discusses the various terminology involved in ASIC design. Each step is described with the help of a flowchart.

1. ASIC DESIGN FLOW
(DIGITAL FLOW)
SUDHANSHU JANWADKAR
S. V. NATIONAL INSTITUTE OF TECHNOLOGY,
SURAT

2. Introduction
ASIC:ApplicationSpecificIntegratedCircuits
-Electroniccircuitryrealisedonasiliconwafer
-Performsadedicatedapplication
-Inherently,notprogrammable
-Customizedforaparticularapplication
WhatisrequiredtofabricateASICs?
-Amongotherrequirements,Masksareapre-
requisite

3. •Amaskisaspecificationofgeometricshapesthat
needtobecreatedonacertainlayer.
•Masksareusedtoproduceapatternonasubstrate,
(normallyathinsliceofsiliconknownasawafer).
•Severalmasksareusedinturn,eachone
reproducingalayerofthecompleteddesign
•Masksareusedtocreateaspecificpatternsofeach
materialinasequentialmannerandcreatea
complexpatternofseverallayers
Introduction

4. Introduction

5. Introduction
•Integratedcircuitlayoutistherepresentationofan
integratedcircuitintermsofplanargeometric
shapes.
•Theshapescorrespondtothepatternsofmetal,
oxide,orsemiconductorlayers,thatmakeupthe
componentsoftheintegratedcircuit.
•Drawingacustomlayoutisfeasible
whenthenumberoftransistorsin
circuitarelessinnumber.

6. Motivation
•Modern day chips contain millions of transistors.
•Would it be feasible to design such a complex
system with help of truth table and K-maps?
•Would it be feasible to draw custom layout?
Obviously Impossible!!

7. Contd..
•Today’ssemiconductorsandelectronicsystemsare
complexthatdesigningthemwouldbeimpossible
withoutelectronicdesignautomation(EDA)tools.
•UsingtheseEDAtools,thelayoutengineerplacesand
connectsallofthecomponentsthatmakeupthechip.
•EDAtoolsrunscriptsinbackgroundwhichemploy
complexalgorithmstoeffecttheprocesses.
•Thetypicalstepsarediscussed.

8. Digital Design Flow
Verilog/
VHDL
Library
Std., Cell.
Library
Tech file
For layout
values
Look up
Table for
timing
Tech file
For RC
Parasite
extraction
Design Analysis
Design Specification
Synthesis
Design Implementation using HDL
Simulation
Timing Analysis
Place & Route
Extraction
Verification

9. Design Analysis
Design Analysis
Design Specification
Synthesis
Design Implementation using HDL
Simulation
Timing Analysis
Place & Route
Extraction
Verification
Thisisaverycrucialstepin
digitaldesignwherethedesign
functionalityisstated.
Likeifwearemakingaprocessor,
whattypeoffunctionalityis
expected??

10. Design Specification
Design Analysis
Design Specification
Synthesis
Design Implementation using HDL
Simulation
Timing Analysis
Place & Route
Extraction
Verification
Thisstepinvolvedstatingin
definitetermstheperformanceof
thechip.
Likeifwearemakingaprocessor,
datasize,processorspeed,special
functions,poweretc.isclearly
statedatthispoint.
So,itdealswitharchitecturalpart
ofthedesignathighestlevel
possible.
Basedonthesefoundation,the
wholedesignisbuilt.

11. Design Implementation using
HDL
Design Analysis
Design Specification
Synthesis
Design Implementation using HDL
Simulation
Timing Analysis
Place & Route
Extraction
Verification
HardwareDescriptionLanguage
isusedtorunthesimulations.
Itisveryexpensivetobuildthe
entirechipandthenverifythe
performanceofthearchitecture.
Imagineifafterdesigning
achipforawholeyear,thechip
fabricated,doesnotcomeeven
closertothespecifications.

12. Design Implementation using HDL
(contd..)
Design Analysis
Design Specification
Synthesis
Design Implementation using HDL
Simulation
Timing Analysis
Place & Route
Extraction
Verification
Hardwaredescriptionlanguages
providesawaytoimplementa
designwithoutgoingintomuch
architecture,simulateandverify
designoutputandfunctionality.
Forexample,ratherthanbuilding
amuxdesigninhardware,we
canwriteverilogcodeandverify
theoutputathigherlevelof
abstraction.
ExamplesofHDL:VHDL,
VerilogHDL

13. Synthesis
Design Analysis
Design Specification
Synthesis
Design Implementation using HDL
Simulation
Timing Analysis
Place & Route
Extraction
Verification
Mostofthedigitaldesignsare
buildupofsomebasic
elementsorcomponentslike
logicgates,registers,counters,
adders,substractors,shifters,
comparators,RAM,ROMetc.
StandardCellLibraryisthe
collectionofsuchbuilding
blockswhichcomprisesmost
ofthedigitaldesigns.
Thesecelllibrariesarespecific
totechnologynode(foundry).

14. Synthesis (contd..)
Design Analysis
Design Specification
Synthesis
Design Implementation using HDL
Simulation
Timing Analysis
Place & Route
Extraction
Verification
Whenthesynthesistool(e.g.
genus)encountersaspecific
constructinHDL,itreplacesit
withthecorresponding
StandardCellfromthelibrary
tobuildtheentiredesign.
Theremaybedifferentoptions
ofstandardcellsavailableto
customizechiparea,delayetc.
Likeifweuseaforloop,it
getsconvertedtocounteranda
combinationalcircuit.

15. Synthesis (contd..)
Design Analysis
Design Specification
Synthesis
Design Implementation using HDL
Simulation
Timing Analysis
Place & Route
Extraction
Verification
Attheendofthisstage,wehave
thelogiccircuiti.e.intermsof
gatesandmemories
Theoutputofsynthesisisagate
levelnetlist.
NetlistisanASCIIfilewhich
enlistsandindicatesthedevices
andtheinterconnectionsbetween
them.

16. Simulation
Design Analysis
Design Specification
Synthesis
Design Implementation using HDL
Simulation
Timing Analysis
Place & Route
Extraction
Verification
Afterthenetlistisgeneratedaspart
ofsynthesis,thisnetlistis
simulatedtoverifythefunctionality
ofthisgatelevelimplementationof
design.
Tillthisstep,onlysimulationmeant
onlyfunctionalverification.
Hereonwards,simulationisdone
alsotoverifyifthedesignmeets
specification(mostlyintermsof
delayparameters).

17. Timing Analysis
Design Analysis
Design Specification
Synthesis
Design Implementation using HDL
Simulation
Timing Analysis
Place & Route
Extraction
Verification
RTLandGateLevelsimulation
doesn’ttakeintoaccountthe
physicaltimedelayinsignal
propagationfromonedeviceto
anotherandthrough
thedevice.
Thistimedelayisdependenton
thefabricationprocessadopted.
Eachcomponentinstandardcell
libraryisassociatedwithsome
specificdelay.

18. Timing Analysis (contd..)
Design Analysis
Design Specification
Synthesis
Design Implementation using HDL
Simulation
Timing Analysis
Place & Route
Extraction
Verification
DelayLookupTableslistthedelays
associatedwiththecomponents.
Delaysareintheformofrisetime,
falltimeetc.
Intiminganalysis,usingDelay
LookupTables,alltheinputsand
outputsofcomponentsareverified
withtimingintroduced.
Designproceedstofurtherstepsof
physicaldesignonlyiftimingis
met.Iftimingisnotmet,then
varioustechniquessuchasresizing
ofstandardcells,insertionof
buffersetc.maybecarriedout.

19. Place and Route
Design Analysis
Design Specification
Synthesis
Design Implementation using HDL
Simulation
Timing Analysis
Place & Route
Extraction
Verification
Semiconductorlayouthastofollow
certaindesignrulestolaydevices
atsemiconductorlevel.
Thesedesignrulesarefabrication
processdependent.
Thelayoutuseslayersasp/n
diffusion,nwell,pwell,metals,via
etc.
Rulesinvolvingminimumspacing
betweentwolayers,widthofeach
layer,minimumareaofcontact
betweentwolayersetc.areknown
asDesignRules.

20. Place and Route (contd..)
Design Analysis
Design Specification
Synthesis
Design Implementation using HDL
Simulation
Timing Analysis
Place & Route
Extraction
Verification
PlacementandRoutinginvolves
layingofthedevices,placing
themandmakinginterconnection
betweenthem,followingthe
DesignRules.
Theresultisthedesign
implementedintheformof
semiconductorlayers.

21. Extraction
Design Analysis
Design Specification
Synthesis
Design Implementation using HDL
Simulation
Timing Analysis
Place & Route
Extraction
Verification
Oncethelayoutismade,there
alwaysisparasiticcapacitances
andresistancesassociatedwith
thedesign.
Thisisbecauseofthecompact
layoutstomakethechipssmaller.
Moreyoumakecompactlayout
morewillitintroducethese
parasiticcomponents.
Theseinterferesinthe
functioningandperformanceof
thecircuitintermsoftiming,
speedandpowerconsumption.

22. Extraction (contd..)
Design Analysis
Design Specification
Synthesis
Design Implementation using HDL
Simulation
Timing Analysis
Place & Route
Extraction
Verification
Duetothesefactorsitbecomes
verymuchimportanttoextract
thesedevicesfromlayoutand
checkthedesignfor
performanceandfunctionality.
Extractionwouldextractfrom
thelayout,thedevicesformed
becauseofjunctionsofdifferent
semiconductorandmetallayers
andtheinterconnections.

23. Verification
Design Analysis
Design Specification
Synthesis
Design Implementation using HDL
Simulation
Timing Analysis
Place & Route
Extraction
Verification
Verificationwouldeitherbejust
beforetapeoutstageofthechipor
thestagewheredesignisagaintaken
backthroughthesameflowfor
optimizationormodification.
Itverifiestheextractedviewofthe
chipforperformanceand
functionality.
VariousDesignRuleCheck(DRC),
LayoutvsSchematic(LVS),Antenna
rulechecketc.areperformed.

24. What Next?
•Whenallverificationiscomplete,layoutpost
processingisappliedwherethedataisalso
translatedintoanindustry-standardformat(typically
calledGDSII).
•Thisissenttoasemiconductorfoundry.The
milestonecompletionofthelayoutprocessof
sendingthisdatatothefoundryiscalled"tapeout".
•Thefoundryconvertsthedataintomaskdataand
usesittogeneratethephoto-masksusedina
photolithographicprocessofsemiconductordevice
fabrication.