Asynchronous Sequential Circuit-Unit 4 ppt

Asynchronous Sequential Circuit-Unit 4 ppt,races,cycles,fundamental mode-analysis and design.
analysis of pulse mode.

1. UNIT 4 ASYNCHRONOUS SEQUENTIAL CIRCUIT PRESENTED BY Mrs. P.SIVALAKSHMI ASSISTANT PROFESSOR ECE/RMKCET Welcome Students

2. Types of Asynchronous Sequential Circuits Analysis & Design of Pulse mode circuits Analysis & Design of Fundamental mode circuits Design Of Hazard free Switching Circuits TOPICS TO BE DISCUSSED

3. ASYNCHRONOUS SEQUENTIAL CIRCUITS Quite often it resembles a combinational circuit with feedback. Sequential Circuits is specified by a time sequence of inputs, outputs and internal states. In which the change of internal state occurs in response to the synchronized clock pulses. Asynchronous sequential circuits do not use clock pulses. The change of internal state occurs in response to the change in the input variable. The memory elements in asynchronous sequential circuits are either unclocked FF or delay elements. Delay elements are again gates through which signals are made to propagate and create delay for finite amount of time.

4. Asynchronous Sequential Circuits When an input variable changes in value, the y secondary variables do not change instantaneously.

5. In steady-state condition, the y 's and the Y' s are the same, but during transition they are not. Asynchronous Sequential Circuits Higher speed More economical

6. Asynchronous Sequential Circuits

7. Asynchronous Sequential circuit-Fundamental Mode 1.Determine Next secondary State equations & output equations. 2. Construct State Table. 3. Construct the Transition table & output map. 4. Construct flow table. Analysis Procedure Design Procedure 2.Primitive Flow table. 3.Reduce PFT using Implication table &Merger graph 4.K-map simplification 5. Draw the circuit 1.State Diagram

8. 1. Analysis Procedure 1.Consider the asynchronous sequential circuit shown in below circuit. Analyze the circuit. Y 1 = xy 1 + x'y 2 Y 2 = xy' 1 + x'y 2 Step:1 Next State secondary equations

9. Step:2 State Table INPUTS X PRESENT STATE y 1 PRESENT STATE y 2 NEXT STATE Y 1 NEXT STATE Y 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Y 1 = xy 1 + x'y 2 Y 2 = xy' 1 + x'y 2

10. Analysis Procedure Y 1 = xy 1 + x'y 2 Y 2 = xy' 1 + x'y 2 Step:3 Transition table

11. Analysis Procedure For a state to be stable, the value of Y must be the same as that of y = y 1 y 2 Step:3 Transition table

12. Analysis Procedure The Unstable states, Y ≠ y Step:3 Transition table

13. Analysis Procedure Consider the square for x = 0 and y = 00. It is stable. x changes from 0 to 1. The circuit changes the value of Y to 01. The state is unstable. The feedback causes a change in y to 01. The circuit reaches stable. Step:3 Transition table

14. Analysis Procedure In general, if a change in the input takes the circuit to an unstable state, y will change until it reaches a stable state. Step:3 Transition table

15. Transition table whose states are named by letter symbol instead of binary values. Flow Table Analysis Procedure Step:4 Flow table

16. It is called primitive flow table because it has only one stable state in each row. It is a flow table with more than one stable state in the same row. Analysis Procedure Step:4 Flow table or Primitive Flow table

17. 2 . Analysis Procedure Y = x 1 x’ 2 + x 1 y Step:1 Next State secondary equations Output equations Z = x 1 x 2 y

18. Step:2 State Table INPUTS X 1 X 2 PRESENT STATE NEXT STATE OUTPUT 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Y = x 1 x’ 2 + x 1 y Z = x 1 x 2 y

19. Step:3 Transition table & output map. Step:4 Flow table

20. Asynchronous Sequential circuit-Pulse Mode sequential circuits. 1.Determine Next secondary State equations & output equations. 2. Characteristics Equation for FF’s. 3. Transition table. 4. Flow table. 5.State Diagram Analysis Procedure Design Procedure 2.state table & assignment 3. Choose FF& its excitation table 4.K-map simplification determine FF inputs & output expression. 5. Draw the circuit 1.State Diagram

21. 1.Consider the asynchronous sequential circuit with pulse input shown in below circuit. Analyze the circuit.

22. Step:2 State Table INPUTS W X Y Z PRESENT STATE Q A PRESENT STATE Q B NEXT STATE Q A + NEXT STATE Q B + OUTPUT C 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Q A + = W+X+YA Q B + = Y+Z’B C = (W+X).B

23. Step:2 State Table INPUTS W X Y Z PRESENT STATE Q A PRESENT STATE Q B NEXT STATE Q A + NEXT STATE Q B + OUTPUT C 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Q A + = W+X+YA Q B + = Y+Z’B C = (W+X).B

24. Step:3 Transition table Step:4 Flow table Step:5 state diagram

25. Two or more binary state variables change value in response to a change in an input variable Noncritical Race: State variables change from 00 to 11. The possible transition could be 00 11 00 01 11 00 10 11 It is a noncritical race. The final stable state that the circuit reaches does not depend on the order in which the state variables change. Race Conditions

26. Critical Race: State variables change from 00 to 11. The possible transition could be 00 11 00 01 11 00 10 It is a critical race. The final stable state depends on the order in which the state variables change. Race Conditions

27. Race Conditions Cycle It starts with y 1 y 2 =00, then input changes from 0 to 1. 00 01 11 10 When a circuit goes through a unique sequence of unstable states, it is said to have a cycle. The sequence is as follows,

28. Stability Consideration Column 11 has no stable state. With input x 1 x 2 = 11, Y and y are never the same. This will cause unstability .

29. Asynchronous Sequential circuit-Fundamental Mode 1.Determine Next secondary State equations & output equations. 2. Construct State Table. 3. Construct the Transition table & output map. 4. Construct flow table. Analysis Procedure Design Procedure 2.Primitive Flow table. 3.Reduce PFT using Implication table &Merger graph 4.K-map simplification 5. Draw the circuit 1.State Diagram

30. 1.Design a gated latch circuit with two inputs G (gate) and D (data), and one output Q . Accept the value of D when G=1 Retain this value after G goes to 0 (D has no effects now) Obtain the flow table by listing all possible states DG/Q 00/0 01/0 10/0 Step:1 State diagram Accept the value of D when G=1 Otherwise no change. 11/1 00/0 11/1 00/0 10/1 01/0 11/1 00/1 10/1 01/0 a b c d e f

31. State Inputs Output comments D G Q a b c d e f 0 1 1 1 0 0 1 0 1 0 0 0 1 1 1 D = Q because G = 1 D = Q because G = 1 After state a or d After state c After state b or f After state e Gated-Latch Total States Step:2 State Table

32. Dash marks are given when both inputs change simultaneously. „Outputs of unstable states are don’t care. Step:3 Primitive Flow Table DG/Q 00/0 01/0 10/0 11/1 00/0 11/1 00/0 10/1 01/0 11/1 00/1 10/1 01/0 a b c d e f

33. Step:4 Reduction of the Primitive Flow Table Two of more rows in the primitive flow table can be merged into one row if there are non-conflicting states and outputs in each of the columns.

34. Reduction of the Primitive Flow Table

35. Transition Table and Logic Diagram

36. Thank you!