AVR Programming of ATmega32 detailed .pdf

AVR Programming of ATmega32

1. PROGRAMMING OF AVR
Mr. P. Pavan Kumar, Assistant Professor, MVGRCE

2. Content
Addressing modes
Assembler directives

3. Addressing modes

4. Register Direct, Single register Rd
The operand value is specified in the register Rd.
The operand will be given 5 bits in the opcode
equivalent.
INC Rd
0 ≤ d ≤ 31
Rd ←Rd + 1
DEC Rd
0 ≤ d ≤ 31
Rd ←Rd -1
TST Rd
0 ≤ d ≤ 31
Rd ←Rd • Rd
CLR Rd
0 ≤ d ≤ 31
Rd ←Rd ⊕Rd
SER Rd
0 ≤ d ≤ 31
Rd ←$FF

5. Register Direct, Two registers Rd & Rr
The operand values are stored in Rr & Rd registers
and the result is stored in Rr. Both the operand will
be given 5 bits each in the opcode equivalent.
ADD Rr, Rd
Rr ←Rr + Rd
0 ≤ d ≤ 31,
0 ≤ r ≤ 31
SUB Rr, Rd
Rr ←Rr -Rd
0 ≤ d ≤ 31,
0 ≤ r ≤ 31
AND Rr, Rd
Rr ←Rr • Rd
0 ≤ d ≤ 31,
0 ≤ r ≤ 31
OR Rr, Rd
Rr ←Rr V Rd
0 ≤ d ≤ 31,
0 ≤ r ≤ 31
EOR Rr, Rd
Rr ←Rr ⊕Rd
0 ≤ d ≤ 31,
0 ≤ r ≤ 31

6. I/O Direct
Inthismodeeitherthesourceordestination
operandwillbealocationorregisterfromthe
standardI/Omemory.
Operandaddressisgiveninthe6bitsofthe
instructionword.‘n’isthedestinationorsource
addressregister.

7. I/O Direct

8. I/O Port Registers and their addresses

9. Data Direct
A 16 bit data address is given as LSB in the two
byte instruction word. Rd/Rr specify the source or
destination registers.
STS k, Rr
(k) ←Rr
0 ≤ r ≤ 31
0 ≤ k ≤ 65535

10. Data Indirect
OperandaddressinthecontentofX,YorZ
registers,whicharecalledpointerregisters.InAVR
deviceswithoutSRAMthedataindirectaddressingis
calledRegisterindirectaddressing.

11. Pointer registers-X, Y & Z

12. Data Indirect with displacement
OperandaddressistheresultsoftheYorZregister
addedtotheaddresscontainedin6-bitsofthe
instructionword.‘n’iseitherthedestinationorsource
register.

13. Register Indirect with post increment

14. Register Indirect with post decrement

15. Assembler directives

16. Assembler directives
WhiletheinstructionstelltheCPUwhattodo,directivesgive
directionstotheassembler.
Thesearealsocalledaspseudoinstructions.
ThefollowingaremostlyusedassemblerdirectivesinAVR
programming
.EQU
.SET
.ORG
.INCLUDE
.DB
.DEF
.UNDEF

17. .EQU
Thisdirectiveisusedtodefine/nameaconstantor
afixedaddress.
The.EQUdirectivedoesnotsetasidestoragefora
dataitem/addresslabel,butassociatesaconstant
numberwithadataoranaddresslabel,sothat
whenthelabelappearsintheprogram,itsconstant
willbesubstitutedforthelabel.
.EQU COUNT=0×25 ……. LDI R21, COUNT
.EQU SUM=0×12 ……. LDI R18, SUM

18. .SET
Thisdirectiveisusedtodefineaconstantvalueora
fixedaddress.
.SETand.EQUdirectivesareidentical.
Theonlydifferenceisthatthevalueassignedby
the.SETdirectivemaybereassignedlater.

19. .ORG
The.ORGdirectiveisusedtoindicatethebeginning
oftheaddress.Itcanbeusedforbothcodeand
data.
.ORG0×200;startataddress200

20. .INCLUDE
The .INCLUDE directive tells the AVR assembler to
add the contents of a file to the program (like the
#include directive in C language).
For example, when you want to use ATmega32, you
must write the following instruction at the beginning
of your program: .INCLUDE “M32DEF.INC”

21. .DB
Thisdirectiveisusedtodefinebyteforthegiven
addresslocationordefinesetofbytesforthe
consecutivememorylocations.
TheDBdirectivereservesmemoryresourcesinthe
programmemoryortheEEPROMmemory.

22. .DEF
TheDEFdirectiveallowstheregisterstobereferredto
throughsymbols.Adefinedsymbolcanbeusedinthe
restoftheprogramtorefertotheregisteritis
assignedto.
Aregistercanhaveseveralsymbolicnamesattachedto
it.Thesymbolcanberedefinedlaterintheprogram.
Syntax:
.DEF Symbol=Register
Example:
.DEF temp=R16
.DEF ior=R0

23. .UNDEF
TheUNDEFdirectiveisusedtoun-defineasymbol
previouslydefinedwiththe.DEFdirective.
Thisprovidesawaytoobtainasimplescopingofregister
definitions,toavoidwarningsaboutregisterreuse.
Syntax:
.UNDEF symbol
Example:
.DEF var1 = R16
LDI var1, 0x20
... ; do something more with var1
.UNDEF var1

24. Program

25. Program

26. Program contd.,

27. Arithmetic and logical instructions
Branch/Jump/Call instructions
Data Transfer instructions
Instruction set of ATmega32

28. Arithmetic Instructions

29. ADD (Addition without Carry)
Description:AddstworegisterswithouttheCflag
andplacestheresultinthedestinationregisterRd.
Operation:Rd←Rd+Rr
Syntax:ADDRd,Rr0≤d≤31,0≤r≤31
Cycles:1
ADDR1,R2 ; Add r2 to r1 (r1=r1+r2)
ADD R28,R28 ; Add r28 to itself (r28=r28+r28)

30. ADC (Addition with Carry)
Description:Addstworegistersandthecontentsof
theCflagandplacestheresultinthedestination
registerRd.
Operation:Rd←Rd+Rr+C
Syntax:ADCRd,Rr0≤d≤31,0≤r≤31
Cycles:1
Add R1:R0 to R3:R2
ADDR2,R0 ; Add low byte
ADCR3,R1 ; Add with carry high byte

31. ADIW (Add Immediate to Word)
Description:Addsanimmediatevalue(0-63)toa
registerpairandplacestheresultintheregister
pair.ThisinstructionoperatesontheupperTHREE
registerpairs,andiswellsuitedforoperationson
thepointerregisters.
Thisinstructionisnotavailableinalldevices.
Operation:[Rd+1:Rd]←[Rd+1:Rd]+K
Syntax: ADIW Rd+1:Rd, K
where, d={26,28,30}, 0 <= K <= 63

32. ADIW (Add Immediate to Word)
Cycles: 2
Example:
ADIWR27:26,1 ; Add 1 to R27:R26
ADIWZH:ZL,63 ; Add 63 to the Z pointer(R31:R30)

33. SUB (Subtract without Carry)
Description:Subtractstworegistersandplacesthe
resultinthedestinationregisterRd.
Operation:Rd←Rd-Rr
Syntax:SUBRd,Rrwhere,0≤d≤31,0≤r≤31
Cycles:1
Example:
SUBR13,R12 ; Subtract R12 from R13
BRNEnoteq ; Branch if R12⇔R13
...
noteq: nop ; Branch destination (do nothing)

34. SBC (Subtract with Carry)
Description: Subtracts two registers and subtracts
with the C flag and places the result in the
destination register Rd.
Operation: Rd ←Rd -Rr -C
Syntax: SBC Rd, Rr where, 0 ≤ d ≤ 31, 0 ≤ r ≤ 31
Cycles: 1
Example:
Subtract R1:R0 from R3:R2
SUBR2,R0 ; Subtract low byte
SBCR3,R1 ; Subtract with carry high byte

35. SBIW (Subtract Immediate from Word)
Description:Subtractsanimmediatevalue(0-63)
fromaregisterpairandplacestheresultinthe
registerpair.Thisinstructionoperatesontheupper
fourregisterpairs,andiswellsuitedforoperationson
thepointerregisters.
This instruction is not available in all devices.
Operation: [Rd+1:Rd] ←[Rd+1:Rd] -K
Syntax: SBIW Rd+1:Rd, K d={26,28,30}, 0 ≤ K ≤ 63
Cycles: 2

36. SBIW (Subtract Immediate from Word)
Example:
SBIWR27:R26,1 ; Subtract 1 from r25:r24
SBIWYH:YL,63 ; Subtract 63 from the Y pointer(r29:r28)

37. SUBI (Subtract Immediate)
Description:Subtractsaregisterandaconstantand
placestheresultinthedestinationregisterRd.This
instructionisworkingonRegisterR16toR31andis
verywellsuitedforoperationsontheX,YandZ
pointers.
Operation: Rd ←Rd -K
Syntax: SUBI Rd, K where, 16 ≤ d ≤ 31, 0 ≤ K ≤ 255
Cycles: 1

38. SUBI (Subtract Immediate)
Cycles: 1
Example:
SUBIR22,$11 ; Subtract $11 from R22
BRNEnoteq ; Branch if R22⇔$11
....
noteq: nop ; Branch destination (do nothing)

39. SBCI (Subtract Immediate with Carry)
Description: Subtracts a constant from a register and
subtracts with the C flag and places the result in the
destination register Rd.
Operation: Rd ←Rd -K -C
Syntax: SBCI Rd, K where, 16 ≤ d ≤ 31, 0 ≤ K ≤ 255
Cycles: 1
Example:
Subtract $4F23 from R17:R16
SUBIR16,$23 ; Subtract low byte
SBCIR17,$4F ; Subtract with carry high byte

40. MUL (Multiply Unsigned)
Description: This instruction performs 8-bit ×8-bit →
16-bitunsigned multiplication.
ThemultiplicandRdandthemultiplierRraretwo
registerscontainingunsignednumbers.The16-bit
unsignedproductisplacedinR1(highbyte)andR0
(lowbyte).Notethatifthemultiplicandorthemultiplier
isselectedfromR0orR1theresultwilloverwritethose
aftermultiplication.
Operation: R1:R0 ←Rd ×Rr (unsigned ←unsigned ×
unsigned)
Syntax: MUL Rd, Rr where, 0 ≤ d ≤ 31, 0 ≤ r ≤ 31

41. MUL (Multiply Unsigned)
Cycles: 2
Example:
MULR5,R4 ; Multiply unsigned R5 and R4

42. MULS (Multiply Signed)
Description: This instruction performs 8-bit ×8-bit
→16-bit signed multiplication.
The multiplicand Rd and the multiplier Rr are two
registers containing signed numbers. The 16-bit
signed product is placed in R1 (high byte) and R0
(low byte).
Operation: R1:R0 ←Rd ×Rr (signed ←signed ×
signed)
Syntax: MULS Rd, Rr where,16 ≤ d ≤ 31, 16 ≤ r ≤
31

43. MULS (Multiply Signed)
Cycles: 2
Example:
MULSR21,R20 ; Multiply signed R21 and R20

44. No DIVIDE instruction in AVR
AVRhasnoinstructionfordivideoperation.
Thedivisionoperationcanbeperformedbydoing
subtractionoperationrepeatedly.
Thequotientisthenumberoftimeswesubtracted
andtheremainderisintheregisterupon
completion.

45. INC (Increment)
Description: Adds one ‘1’ to the contents of register
Rd and places the result in the destination register
Rd.
Operation: Rd ←Rd + 1
Syntax: INC Rd where,0 ≤ d ≤ 31
Cycles: 1
Example:
INCR22 ; increment R22

46. DEC (Decrement)
Description: Subtracts one ‘1’ from the contents of
register Rd and places the result in the destination
register Rd.
Operation: Rd ←Rd -1
Syntax: DEC Rd where, 0 ≤ d ≤ 31
Cycles: 1
Example:
DECR17 ; Decrement R17

47. Logical Instructions

48. AND (Logical AND)
Description: Performs the logical AND between the
contents of register Rd and register Rr and places the
result in the destination register Rd.
Operation: Rd ←Rd • Rr
Syntax: AND Rd, Rr where, 0 ≤ d ≤ 31, 0 ≤ r ≤ 31
Cycles: 1
Example:
ANDR2,R3 ; Bitwise and R2 and R3, result in R2
LDIR16,1 ; Set bitmask 0000 0001 in R16
ANDR2, R16 ; Isolate bit 0 in R2

49. ANDI (Logical AND with Immediate)
Description: Performs the logical AND between the
contents of register Rd and a constant and places the
result in the destination register Rd.
Operation: Rd ←Rd • K
Syntax: ANDI Rd, K where, 16 ≤ d ≤ 31, 0 ≤ K ≤ 255
Cycles: 1
Example:
ANDIR17,$0F ; Clear upper nibble of r17
ANDIR18,$10 ; Isolate bit 4 in r18
ANDIR19,$AA ; Clear odd bits of r19

50. OR (Logical OR)
Description: Performs the logical OR between the
contents of register Rd and register Rr and places
the result in the destination register Rd.
Operation: Rd ←Rd v Rr
Syntax: OR Rd, Rr where, 0 ≤ d ≤ 31, 0 ≤ r ≤ 31
Cycles: 1
Example:
ORR15,R16 ; Do bitwise ‘OR’between registers R15 &R16

51. ORI (Logical OR with Immediate)
Description: Performs the logical OR between the
contents of register Rd and a constant and places the
result in the destination register Rd.
Operation: Rd ←Rd v K
Syntax: ORI Rd, Kwhere, 16 ≤ d ≤ 31, 0 ≤ K ≤ 255
Cycles: 1
Example:
ORIR16,$F0 ; Set high nibble of r16
ORIR17,1 ; Set bit 0 of r17

52. EOR -Exclusive OR
Description: Performs the logical EOR between the
contents of register Rd and register Rr and places
the result in the destination register Rd.
Operation: Rd ←Rd ⊕Rr
Syntax: EOR Rd, Rr where, 0 ≤ d ≤ 31, 0 ≤ r ≤ 31
Cycles: 1
Example:
EORR4,R4 ; Clear R4
EORR0,R22 ; Bitwise exclusive or between R0 and R22

53. COM (One's Complement)
Description: This instruction performs a one's
complement of register Rd.
Operation: Rd ←$FF -Rd
Syntax: COM Rd where, 0 ≤ d ≤ 31
Cycles: 1
Example:
COMR4 ; Take one's complement of R4

54. NEG (Two's Complement)
Description: Replaces the contents of register Rd
with its two's complement; the value $80 is left
unchanged.
Operation: Rd ←$00 -Rd
Syntax: NEG Rd where, 0 ≤ d ≤ 31
Example:
NEGR11 ; Take two's complement of R11

55. CLR (Clear Register)
Description: Clears a register. This instruction
performs an Exclusive OR between a register and
itself. This will clear all bits in the register.
Operation: Rd ←Rd ⊕Rd
Syntax: CLR Rd where, 0 ≤ d ≤ 31
Cycles: 1
Example:
CLRR18 ; clear R18

56. SER (Set all bits in Register)
Description: Loads $FF directly to register Rd.
Operation: Rd ←$FF
Syntax: SER Rd where, 16 ≤ d ≤ 31
Cycles: 1
Example:
SERR17 ; Set R17

57. Jump instructions
Call instructions
Branch instructions
Branch Instructions

58. JMP
RJMP
IJMP
Jump Instructions

59. JMP (Jump)
Description: It is an unconditional jump that can
jump to any address within the entire 4M (words)
program memory of AVR.
It is a 4-byte instruction in which 10bits are used for
opcode and the other 22 bits (0×000000 to
0×3FFFFF) represent the target address location.
Operation: PC ←k
Syntax: JMP k where, 0 ≤ k < 4M
Cycles: 3
JMPfarplc ; Unconditional jump ...
farplc:nop ; Jump destination (do nothing)

60. RJMP (Relative Jump)
Description:Itisanunconditionaljumpwhichjumpsto
anaddresswithinPC-2K+1andPC+2K(words).In
theassembler,labelsareusedinsteadofrelative
operands.
Itis2-byteinstruction,inwhichthefirst4-bitsare
opcodeandtheremaining12-bitsistherelative
addressofthetargetlocation.
Therelativeaddressrangeof0×000to0×FFFis
dividedintoforwardandbackwardjumps;withinthe-
2048to+2047wordsofmemoryrelativetocurrentPC
value.

61. RJMP (Relative Jump)
Operation: PC ←PC + k + 1
Syntax: RJMP k -2K ≤ k < 2K
Cycles: 2
Example:
CPIR16,$42 ; Compare R16 to $42
BRNEerror ; Branch if R16 ⇔$42
RJMP ok ; Unconditional branch
error: ADDr16,R17 ; Add R17 to R16
INC R16 ; Increment R16
ok: nop ; Destination for RJMP(do nothing)

62. IJMP (Indirect Jump)
Description:Indirectjumptotheaddresspointedby
theZ(16bits)pointerregisterintheregisterfile,
unconditionally.TheZpointerregisteris16bits
wideandallowsjumpwithinthe128Kbytessection
ofprogrammemory.
Inotherjumpinstructionthetargetaddressisstatic,
butinthecaseofIJMPthetargetaddresscanbe
changeddynamicallybychangingtheZ-registers
contentthroughtheprogram.

63. IJMP (Indirect Jump)
Operation: PC ←Z(15:0) Devices with 16 bits PC,
128K bytes program memory maximum.
Syntax: IJMP
Cycles: 2
Example:
MOVR30,R0 ; Set offset to jump table
IJMP ; Jump to routine pointed to by R31:R30

64. CALL
RCALL
ICALL
RET
RETI
CALL instructions

65. CALL (Long Call to a Subroutine)
Description:Callstoasubroutinewithintheentire
programmemory.Thereturnaddress(addressnexttothe
instructionaftertheCALL)willbestoredontothestack.
Thentheexecutionjumpstothesubroutinecalled.
Thestackpointerusesapost-decrementschemeduring
CALL.
Whenthesubroutineexecutionhasfinishedand
executestheRETinstruction,theaddressofthe
instructionbelowtheCALLisloadedintothePCandthe
instructionbelowtheCALLinstructionisexecuted.

66. CALL (Long Call to a Subroutine)
Operation: PC ←k Devices with 16 bits PC, 128K
bytes program memory maximum.
Syntax: CALL k where, 0 ≤ k < 64K
Cycles: 4

67. CALL (Long Call to a Subroutine)
Example:
MOVR16,R0 ; Copy r0 to r16
CALLcheck ; Call subroutine
nop ; Continue (do nothing)
...
check: CPI R16, $42 ; Check if r16 has a special value
BREQerror ; Branch if equal
RET ; Return from subroutine
...
error: RJMP error ; Infinite loop

68. RCALL (Relative Call to Subroutine)
Description:Itistheinstructionwhichcallssubroutine
havingaddresswithinPC-2K+1andPC+2K
(words).Intheassembler,labelsareusedinsteadof
relativeoperands.
Itis2-byteinstruction,inwhichthefirst4-bitsare
opcodeandtheremaining12-bitsistherelative
addressofthetargetlocationofthesubroutinetobe
called.
Therelativeaddressrangeof0×000to0×FFFis
dividedintoforwardandbackwardcalls;withinthe-
2048to+2047wordsofmemoryrelativetocurrentPC
value.

69. RCALL (Relative Call to Subroutine)
Operation:
(i)PC ←PC + k + 1 Devices with 16 bits PC, 128K
bytes program memory maximum.
Syntax: RCALL k -2K ≤ k < 2K
Cycles: 3
RCALLroutine ; Call subroutine
...
routine: PUSH R14 ; Save R14 on the stack
...
POPR14 ; Restore R14
RET ; Return from subroutine

70. ICALL (Indirect Call to Subroutine)
Description:Indirectcallofasubroutinepointedby
theZ(16bits)pointerregisterintheregisterfile.
TheZpointerregisteris16bitswideandallows
calltoasubroutinewithinthelowest64Kwords
(128Kbytes)sectionintheprogrammemoryspace.
Thestackpointerusesapost-decrementscheme
duringICALL.

71. ICALL (Indirect Call to Subroutine)
Operation: PC(15:0) ←Z(15:0) Devices with 16
bits PC, 128K bytes program memory maximum.
Syntax: ICALL;STACK ←PC + 1; SP ←SP -2 (2
bytes, 16 bits)
Cycles: 3
Example:
MOVR30,R0 ; Set offset to call table
ICALL ; Call routine pointed to by R31:R30

72. RET (Return from Subroutine)
Description:Returnsfromsubroutine.Thereturn
addressisloadedfromtheStack.Thestackpointer
usesapre-incrementschemeduringRET.
Operation:PC(15:0)←STACK,Deviceswith16bits
PC,128Kbytesprogrammemorymaximum.
Syntax:RET;SP←SP+2,(2bytes,16bits)Cycles:4
RCALLroutine ; Call subroutine
...
routine: PUSH R14 ; Save R14 on the stack
...
POPR14 ; Restore R14
RET ; Return from subroutine

73. RETI (Return from Interrupt)
Description:Returnsfrominterrupt.Thereturnaddress
isloadedfromtheStackandtheglobalinterruptflag
isset.
Notethatthestatusregisterisnotautomaticallystored
whenenteringaninterruptroutine,anditisnotrestored
whenreturningfromaninterruptroutine.Thismustbe
handledbytheapplicationprogram.Thestackpointer
usesapre-incrementschemeduringRETI.
Operation:PC(15:0)←STACK,Deviceswith16bits
PC,128Kbytesprogrammemorymaximum.
Syntax:RETI;SP←SP+2(2bytes,16bits)

74. RETI (Return from Interrupt)
Cycles: 4
Example:
...
extint: PUSH R0 ; Save R0 on the stack
...
POPR0 ; Restore R0
RETI ; Return and enable interrupts

75. Branch Instructions

76. BRBS (Branch if Bit in SREG is Set)
Description:Conditionalrelativebranch.Testsasingle
bitinSREGandbranchesrelativelytoPCifthebitisset.
ThisinstructionbranchesrelativelytoPCineither
direction(PC-63≤destination≤PC+64).The
parameterkistheoffsetfromPCandisrepresentedin
two'scomplementform.
Operation:IfSREG(s)=1thenPC←PC+k+1,else
PC←PC+1
Syntax:BRBSs,kwhere,0≤s≤7,-64≤k≤+63

77. BRBS (Branch if Bit in SREG is Set)
Cycles: 1 if condition is false 2 if condition is true
Example:
BSTR0,3 ; Load T bit with bit 3 of r0
BRBS6, bitset; Branch T bit was set
...
bitset: nop ; Branch destination (do nothing)

78. BRBC (Branch if Bit in SREG is Cleared)
Description:Conditionalrelativebranch.Testsasingle
bitinSREGandbranchesrelativelytoPCifthebitis
cleared.
ThisinstructionbranchesrelativelytoPCineither
direction(PC-63≤destination≤PC+64).The
parameterkistheoffsetfromPCandisrepresentedin
two'scomplementform.
Operation:IfSREG(s)=1thenPC←PC+k+1,else
PC←PC+1
Syntax:BRBCs,kwhere,0≤s≤7,-64≤k≤+63

79. BRBC (Branch if Bit in SREG is Cleared)
Cycles: 1 if condition is false 2 if condition is true
Example:
CPIR20,5 ; Compare R20 to the value 5
BRBC1,noteq ; Branch if zero flag cleared
...
noteq:nop ; Branch destination (do nothing)

80. BREQ (Branch if Equal)
Description:Conditionalrelativebranch.TeststheZero
flag(Z)andbranchesrelativelytoPCifZisset.Ifthe
instructionisexecutedimmediatelyafteranyofthe
instructionsCP,CPI,SUBorSUBI,thebranchwilloccurif
andonlyiftheunsignedorsignedbinarynumber
representedinRd(Rd=Rr)wasequaltotheunsignedor
signedbinarynumberrepresentedinRr.
ThisinstructionbranchesrelativelytoPCineither
direction(PC-63≤destination≤PC+64).The
parameterkistheoffsetfromPCandisrepresentedin
two'scomplementform.

81. BREQ (Branch if Equal)
Operation: If Rd = Rr (Z = 1) then PC ←PC + k +
1, else PC ←PC + 1
Syntax: BREQ k -64 ≤ k ≤ +63; PC ←PC + k +
1, if condition is true and PC ←PC + 1, if condition
is false
Cycles: 1 if condition is false 2 if condition is true
Example:
CPR1, R0 ; Compare registers R1 and R0
BREQequal ; Branch if registers equal
...
equal: nop ; Branch destination (do nothing)

82. BRNE (Branch if Not Equal)
Description:Conditionalrelativebranch.TeststheZero
flag(Z)andbranchesrelativelytoPCifZiscleared.If
theinstructionisexecutedimmediatelyafteranyofthe
instructionsCP,CPI,SUBorSUBI,thebranchwilloccurif
andonlyiftheunsignedorsignedbinarynumber
representedinRd(Rd≠Rr)wasnotequaltothe
unsignedorsignedbinarynumberrepresentedinRr.
ThisinstructionbranchesrelativelytoPCineither
direction(PC-63≤destination≤PC+64).The
parameterkistheoffsetfromPCandisrepresentedin
two'scomplementform.

83. BRNE (Branch if Not Equal)
Operation: If Rd ≠Rr (Z = 1) then PC ←PC + k +
1, else PC ←PC + 1
Syntax: BRNE k -64 ≤ k ≤ +63; PC ←PC + k +
1, if condition is true and PC ←PC + 1, if condition
is false
Cycles: 1 if condition is false 2 if condition is true
Example:
CPIR16, 5 ; Compare register R16 with5
BRNEnequal ; Branch if they are not equal
...
nequal: nop ; Branch destination (do nothing)

84. BRCS -Branch if Carry Set
Description:
Conditionalrelativebranch.TeststheCarryflag(C)
andbranchesrelativelytoPCifCisset.This
instructionbranchesrelativelytoPCineither
direction(PC-63≤destination≤PC+64).The
parameterkistheoffsetfromPCandis
representedintwo'scomplementform.
Operation:IfC=1thenPC←PC+k+1,else
PC←PC+1
Syntax:BRCSkwhere,-64≤k≤+63

85. BRCC -Branch if Carry Cleared
Description:
Conditionalrelativebranch.TeststheCarryflag(C)
andbranchesrelativelytoPCifCiscleared.This
instructionbranchesrelativelytoPCineither
direction(PC-63≤destination≤PC+64).The
parameterkistheoffsetfromPCandis
representedintwo'scomplementform.
Operation:IfC=0thenPC←PC+k+1,else
PC←PC+1
Syntax:BRCCkwhere,-64≤k≤+63

86. BRIE -Branch if Global Interrupt is Enabled
Description:
Conditionalrelativebranch.TeststheGlobal
Interruptflag(I)andbranchesrelativelytoPCifIis
set.ThisinstructionbranchesrelativelytoPCin
eitherdirection(PC-63≤destination≤PC+64).
TheparameterkistheoffsetfromPCandis
representedintwo'scomplementform.
Operation: If I = 1 then PC ←PC + k + 1, else PC
←PC + 1
Syntax: BRIE k where, -64 ≤ k ≤ +63

87. BRID -Branch if Global Interrupt is Disabled
Description:
Conditionalrelativebranch.TeststheGlobal
Interruptflag(I)andbranchesrelativelytoPCifIis
cleared.ThisinstructionbranchesrelativelytoPCin
eitherdirection(PC-63≤destination≤PC+64).
TheparameterkistheoffsetfromPCandis
representedintwo'scomplementform.
Operation:IfI=0thenPC←PC+k+1,elsePC
←PC+1
Syntax:BRIDkwhere,-64≤k≤+63

88. CP-Compare
Description:
Thisinstructionperformsacomparebetweentwo
registersRdandRr.Noneoftheregistersare
changed.Allconditionalbranchescanbeusedafter
thisinstruction.
Operation: Rd -Rr
Syntax: CP Rd, Rr where, 0 ≤ d ≤ 31, 0 ≤ r ≤ 31
Cycles: 1

89. CPC-Compare with Carry
Description:
This instruction performs a compare between two
registers Rd and Rr and also takes into account the
previous carry. None of the registers are changed.
All conditional branches can be used after this
instruction.
Operation: Rd -Rr -C
Syntax: CPC Rd, Rr where, 0 ≤ d ≤ 31, 0 ≤ r ≤ 31
Cycles: 1

90. CPI-Compare with Immediate
Description:
Thisinstructionperformsacomparebetweenregister
Rdandaconstant.Theregisterisnotchanged.All
conditionalbranchescanbeusedafterthis
instruction.
Operation: Rd -K
Syntax: CPI Rd, K where,16 ≤ d ≤ 31, 0≤ K ≤ 255
Cycles: 1