Basic operational concepts.ppt

1.Programs reside in the memory & usually get these through the I/P unit.
2. Execution of the program starts when the PC is set to point at the first instruction of the program.
3. Contents of PC are transferred to MAR and a Read Control Signal is sent to the memory.
4. After the time required to access the memory elapses, the address word is read out of the memory and loaded into the MDR.
5. Now contents of MDR are transferred to the IR & now the instruction is ready to be decoded and executed.
6. If the instruction involves an operation by the ALU, it is necessary to obtain the required operands.
7. An operand in the memory is fetched by sending its address to MAR & Initiating a read cycle.
When the operand has been read from the memory
to the MDR, it is transferred from MDR to the ALU.
After one or two such repeated cycles, the ALU
can perform the desired operation.
10. If the result of this operation is to be stored in the memory, the result is sent to MDR.
11. Address of location where the result is stored is sent to MAR & a write cycle is initiated.
12. The contents of PC are incremented so that PC points to the next instruction that is to be executed.
1.Programs reside in the memory & usually get these through the I/P unit.
2. Execution of the program starts when the PC is set to point at the first instruction of the program.
3. Contents of PC are transferred to MAR and a Read Control Signal is sent to the memory.
4. After the time required to access the memory elapses, the address word is read out of the memory and loaded into the MDR.
5. Now contents of MDR are transferred to the IR & now the instruction is ready to be decoded and executed.
6. If the instruction involves an operation by the ALU, it is necessary to obtain the required operands.
7. An operand in the memory is fetched by sending its address to MAR & Initiating a read cycle.
When the operand has been read from the memory
to the MDR, it is transferred from MDR to the ALU.
After one or two such repeated cycles, the ALU
can perform the desired operation.
10. If the result of this operation is to be stored in the memory, the result is sent to MDR.
11. Address of location where the result is stored is sent to MAR & a write cycle is initiated.
12. The contents of PC are incremented so that PC points to the next instruction that is to be executed.
1.Programs reside in the memory & usually get these through the I/P unit.
2. Execution of the program starts when the PC is set to point at the first instruction of the program.
3. Contents of PC are transferred to MAR and a Read Control Signal is sent to the memory.
4. After the time required to access the memory elapses, the address word is read out of the memory and loaded into the MDR.
5. Now contents of MDR are transferred to the IR & now the instruction is ready to be decoded and executed.
6. If the instruction involves an operation by the ALU

1. Basic Operational Concepts
•ToExecuteagiventaskasperthe
appropriateprogram
•Programconsistsoflistofinstructions
storedinmemory
1

2. Interconnection between Processor and Memory 2

3. Registers
Registersarefaststand-alonestoragelocationsthatholddata
temporarily.Multipleregistersareneededtofacilitatethe
operationoftheCPU.
Someoftheseregistersare
Tworegisters-MAR(MemoryAddressRegister)and
MDR(MemoryDataRegister):Tohandlethedata
transferbetweenmainmemoryandprocessor.MAR-
Holdsaddresses,MDR-Holdsdata
Instructionregister(IR):HoldtheInstructionsthatis
currentlybeingexecuted
Programcounter:Pointstothenextinstructionsthatis
tobefetchedfrommemory
3

4. Examples: -ADD LOCA, R0
•This instruction adds the operand at memory
location LOCA, to operand in register R0 & places
the sum into register.
•This instruction requires the performance of
several steps,
1. First the instruction is fetched from the memory into
the processor.
2. The operand at LOCA is fetched and added to the
contents of R0
3. Finally the resulting sum is stored in the register R0

5. Operating steps
1.Programsresideinthememory&usuallygetthese
throughtheI/Punit.
2.ExecutionoftheprogramstartswhenthePCissettopoint
atthefirstinstructionoftheprogram.
3.ContentsofPCaretransferredtoMARandaReadControl
Signalissenttothememory.
4.Afterthetimerequiredtoaccessthememoryelapses,the
addresswordisreadoutofthememoryandloadedinto
theMDR.
5.NowcontentsofMDRaretransferredtotheIR&nowthe
instructionisreadytobedecodedandexecuted.
6.IftheinstructioninvolvesanoperationbytheALU,itis
necessarytoobtaintherequiredoperands.

6. Operating steps
7.Anoperandinthememoryisfetchedbysendingits
addresstoMAR&Initiatingareadcycle.
8.Whentheoperandhasbeenreadfromthememory
totheMDR,itistransferredfromMDRtotheALU.
9.Afteroneortwosuchrepeatedcycles,theALU
canperformthedesiredoperation.
10.Iftheresultofthisoperationistobestoredinthe
memory,theresultissenttoMDR.
11.Addressoflocationwheretheresultisstoredis
senttoMAR&awritecycleisinitiated.
12.ThecontentsofPCareincrementedsothatPC
pointstothenextinstructionthatistobeexecuted.

7. Bus Structures and Bus
Operation
7

8. Buses
•Abusisasharedcommunicationlink,whichuses
onesetofwirestoconnectmultiplesubsystems.
•Thetwomajoradvantagesofthebus
organizationareversatilityandlowcost.
•Mostmoderncomputersusesinglebus
arrangementforconnectingI/OdevicestoCPU&
Memory.
•Thebusenablesallthedevicesconnectedtoitto
exchangeinformation.
8

9. Buses
•Busconsistsof3setoflines:Address,Data,
Control
•Processorplacesaparticularaddress(uniquefor
anI/ODev.)onaddresslines.
•Devicewhichrecognizesthisaddressrespondsto
thecommandsissuedontheControllines.
•ProcessorrequestsforeitherRead/Write.
•ThedatawillbeplacedonDatalines.

10. Data Bus
•Carries data
–Remember that there is no difference between
“data” and “instruction” at this level
•Width is a key determinant of performance
–8, 16, 32, 64 bit
10

11. Address bus
•Identify the source or destination of data
•e.g. CPU needs to read an instruction (data)
from a given location in memory
•Bus width determines maximum memory
capacity of system
–e.g. 8080 has 16 bit address bus giving 64k
address space
11

12. Control Bus
•Control and timing information
–Memory read/write signal
–Interrupt request
–Clock signals
–Reset
–Bus request / bus grant
–Transfer ACK
–I/O read and I/O write
12

13. Bus Interconnection Scheme
13

14. Big and Yellow?
•What do buses look like?
–Parallel lines on circuit boards
–Ribbon cables
14

15. Bus Types
•Bus is a shared communication link.
•It is used to connect multiple subsystems.
Single bus structure
Multiple bus structure
15

16. Single bus structure
16

17. Multiple bus structure -Traditional (ISA)
(with cache)
17

18. High Performance Bus
18

19. Bus Operations
•Bus includes:
1.Address lines
2.Data lines
3.Control lines
•Data transfer can be in two ways:
1.Synchronous bus
2.Asynchronous bus
19

20. Bus Operations
1.Synchronousbus-Alldevicesderivetiming
informationfromacommonclockcycle.
2.Asynchronousbus–commonclockcycleis
eliminatedanddatatransferisachievedby
handshakebetweenprocessoranddevice
beingconnected
20

21. Bus Operations
Handshake
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22. BUS Arbitration
•BusArbitrationreferstotheprocessbywhichthecurrentbusmaster
accessesandthenleavesthecontrolofthebusandpassesittothe
anotherbusrequestingprocessorunit.
•ThecontrollerthathasaccesstoabusataninstanceisknownasBus
master.
•AconflictmayariseifthenumberofDMAcontrollersorother
controllersorprocessorstrytoaccessthecommonbusatthesame
time,butaccesscanbegiventoonlyoneofthose.
•OnlyoneprocessororcontrollercanbeBusmasteratthesamepoint
oftime.
•Toresolvetheseconflicts,BusArbitrationprocedureisimplemented
tocoordinatetheactivitiesofalldevicesrequestingmemory
transfers.
•Theselectionofthebusmastermusttakeintoaccounttheneedsof
variousdevicesbyestablishingaprioritysystemforgainingaccessto
thebus.
•TheBusArbiterdecideswhowouldbecomecurrentbusmaster.

23. BUS Arbitration
•There are two approaches to bus arbitration:
–Centralized bus arbitration –A single bus
arbiter performs the required arbitration.
–Distributed bus arbitration –All devices
participate in the selection of the next bus
master.
•Methods of BUS Arbitration –
There are three bus arbitration methods:
•Daisy Chaining method
•Polling or Rotating Priority method
•Fixed priority or Independent Request method

24. Daisy Chaining method
•It is a centralized bus arbitration method. During
any bus cycle, the bus master may be any device –
the processor or any DMA controller unit,
connected to the bus.

25. Polling or Rotating Priority
method
•Inthismethod,thedevicesareassignedunique
prioritiesandcompletetoaccessthebus,butthe
prioritiesaredynamicallychangedtogiveevery
deviceanopportunitytoaccessthebus.

26. Fixed priority or Independent Request
method
•In this method, the bus control passes from one
device to another only through the centralized
bus arbiter.