Basics of Digital Design and Verilog

This presentation gives basics of Digital Design as well as Verilog HDL

1. Digital Design & Verilog
PRITHIVIRAJ. R, RITHIK NAMBIAR
SRMIST, KTR.

2. Digital Systems
uThe foundation of all digital systems is binary numbers.
uThe binary representation has only two digits -0 & 1.
uBinary representation simplifies the design process and the circuitry itself.
uIt also provides a higher efficiency and smaller area/footprint.
uThe mathematics/algebra of binary numbers is called Boolean algebra.
uBasic Boolean operations are implemented as a circuit/hardware in the
form of logic gates.
uBoolean algebra is used to design, simplify and analyze digital circuits.
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3. Binary to Decimal Conversion
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4. Logic Gates
uIt is the building block of all digital systems.
uThey implement the basic Boolean operations like AND, OR, NOT, XOR, etc.
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5. Combinational Circuits
uThe output depends only on a combination of the present inputs.
uBecause of its dependence only on the present inputs, there is no
feedback loop involved.
uExamples include adders, multipliers, multiplexers, encoders, PLA, PLDs, etc.
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6. Classification of Combinational Circuits
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7. Sequential Circuits
uSequential Circuits the inputs depend on present as well as past inputs.
uSequential Circuits involve combinational blocks of logic and memory
elements.
uExamples include flip flops, FSM, RAM, etc.
uSequential Circuits are of two types:
uSynchronous: They output changes are synchronized to edges of the clock
(positive/rising edge or negative/falling edge)
uAsynchronous: The output changes are triggered by the value of the clock(high
or low), i.e., it is level sensitive.
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8. 8
Asynchronous vs Synchronous Circuits –Timing Diagram

9. Finite State Machines (FSMs)
uIts is generally used to control the behavior of systems and dataflow paths.
uIt is typically implemented in control units in the digital system.
uIt consists of multiple states, with each state being associated with a particular function or condition.
uEg. The system may go into low power mode when it is in ‘IDLE’ state and so on.
uDepending on the state, different events/functions may be triggered.
uEg. When registers are full, the FSM can enter the ‘OVERLOAD’ state. Upon entering the OVERLOAD state, we can force the processor to put a hold on any future instructions to be executed until any registers are freed up.
uThere are two types of FSMs, Moore and Mealey.
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10. 10
An FSM used to
control the Data
Link Layer of a
PCIeGen3 Link

11. Modern Digital Design
uModern Digital Design uses the concept of Datapathand Control Units.
uThe Datapathinclude functional blocks like ALUs.
uThe Control Units are typically implemented as FSMs.
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12. 12
An Example of Datapathand Control Unit of a Processor

13. Verilog
uDuring the early days of IC Design, engineers drew the circuits by hand.
uThis was a very difficult, complex, time consuming and error prone process.
uVHDL was introduced in order to simplify this process.
uThe idea behind this is that the designer will “describe” the circuit using the
HDL and the tools would infer a circuit that matches the designersintent.
uVerilog was later designed in order to make the Hardware Description
Language (HDL) more robust.
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14. Verilog vs Conventional Programming
Languages
uVerilog is used to describe hardware, while programming languages are
instructions for the hardware to do certain tasks.
uVerilog is a concurrent(parallel) language.
uThe above code would infer two separate “AND” logic gates, whilea
similar statement in C++ would merely “and” the values of the variables.
uIn C++, the value of ‘A’ will be calculated first and then the value of ‘D’
will be calculated
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15. Types of Modelling:
uThere are three types of modelling in Verilog:
uGate Level Modelling
uBehavioral Modelling
uDataflow Modelling
uSwitch Level Modelling
uRTL or Register transfer level is a mixture of behavioral and dataflow
modelling that is used for designing synthesizable circuits.
uRTL models the dataflow between registers and logical operations
performed on the data.
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16. Gate Level Modelling
uIt is practically the lowest level of abstraction as switch level is rarely used.
uIt is used to implement modules in the lower levels of hierarchy like adders,
multipliers, etc.
uHere the connection between the pins of the logic gates are manually
specified.
uNetlist obtained from synthesis tools are generally gate level models in
Verilog.
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17. A NAND gate designed using AND & NOT
gates using gate level modelling in Verilog.
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18. Behavioral Level Modelling
uIt is one of the highest level of abstraction provided by Verilog.
uProcedural blocks and ‘reg’ variables are used the describe the behavior
of the intended hardware.
uOther statements like case, if, loops are used to model the behavior of the
hardware.
uIt is not necessarily synthesizable.
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19. Behavioral Level Model o 4x1 Multiplexer
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20. Dataflow Modelling
uThis involves the use of operators to model the flow of data in the digital
system, mainly using assign statements.
uIt is mainly used for designing combinational circuits.
uIt is always synthesizable.
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21. 2x1 Multiplexer using Dataflow Modelling
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22. Switch Level Modelling
uThis is the lowest level of modelling in Verilog.
uIt is similar to gate level modelling except that connections between the
pins of the transistor is specified(like gate, drain ,etc.)
uIt involves the use of transistor primitives.
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23. NOT gate using Switch Level Modelling
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24. References
uMorris Mano Digital Design 5thedition
uwww.chipverify.com
uwww.asic-world.com
uPCI Express Technology 3.0 -Mindshare
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25. Thank You
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