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Bei VLSI_Design conference__________.ppt
Bei VLSI_Design conference__________.ppt
junzf
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Sep 16, 2025
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About This Presentation
VLSI Design
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535.39 KB
Language:
en
Added:
Sep 16, 2025
Slides:
23 pages
Slide Content
Slide 1
VLSI Design & Embedded Systems Conference
January 2015
Bengaluru, India
Diagnostic Tests for Pre-Bond
TSV Defects
Bei Zhang
Vishwani Agrawal
Slide 2
Purpose of Pre-bond TSV Test
09/16/25
© VLSI Design & Embedded Systems Conference -
2015
2
Defects arise in TSV manufacturing. Pre-
bond TSV test helps identify defective dies
early in the process.
Pre-bond TSV test provides known good die
(KGD) information for die-on-die or die-on-
wafer or wafer-on-wafer fabrication process.
Slide 3
Outline
•3D IC Structure and TSV Models
•Pre-bond TSV Probing technique
•Test Session Generation
•Experimental Results
•Conclusion
09/16/25
© VLSI Design & Embedded Systems Conference -
2015
3
Slide 4
4
TSV-based 3D IC Structure
3D face-to-back stacked IC:
09/16/25
© VLSI Design & Embedded Systems Conference -
2015
4
Slide 5
RC Models of Defective
TSVs After Wafer Thinning
09/16/25
© VLSI Design & Embedded Systems Conference -
2015
5
Resistance-defective TSVCapacitance-defective TSV
S
u
b
s
t
r
a
t
e
InsulatorRTSV1
CTSV2
RTSV2
CTSV1
Rvoid
S
u
b
s
t
r
a
t
e
Insulator
CTSV
RTSV
Rleak
B. Noia and K. Chakrabarty, Design-for-Test and Test Optimization Techniques for
TSV-based 3D Stacked ICs. Springer, 2014.
Slide 6
Illustration of Pre-bond
TSV Probing on the Substrate Side
09/16/25
© VLSI Design & Embedded Systems Conference -
2015
6
GSF: Gated scan flip-flop
Slide 7
Circuit Model of Pre-bond
TSV Test
09/16/25
© VLSI Design & Embedded Systems Conference -
2015
7
Slide 8
09/16/25
© VLSI Design & Embedded Systems Conference -
2015
8
1
1
1
1
Circuit Model of Pre-bond
TSV Test
Slide 9
09/16/25
© VLSI Design & Embedded Systems Conference -
2015
9
1
1
1
1
Circuit Model of Pre-bond
TSV Test
Slide 10
09/16/25
© VLSI Design & Embedded Systems Conference -
2015
10
1
1
1
1
Circuit Model of Pre-bond
TSV Test
Slide 11
Capacitor Charging Time Through
Parallel TSVs
09/16/25
© VLSI Design & Embedded Systems Conference -
2015
11
Number of
TSVs charging
in parallel (q)
Capacitor
charging time
t(q) (μs)
1 0.80
2 0.53
3 0.42
4 0.38
S. K. Roy, S. Chatterjee, C. Giri, and H. Rahaman, “Faulty TSVs Identification and
Recovery in 3D Stacked ICs During Pre-bond Testing,” Proc. International 3D
Systems Integration Conference, 2013, pp. 1–6.
Slide 12
Two Important Observations
1) Any faulty TSV within a parallel test will cause
the test to fail but we cannot tell which TSV(s)
is (are) faulty.
2) A good parallel test implies that all TSVs
within the parallel test are fault-free.
09/16/25
© VLSI Design & Embedded Systems Conference -
2015
12
Slide 13
Terminology
09/16/25
© VLSI Design & Embedded Systems Conference -
2015
13
TSV network TSVs simultaneously contacted by probe.
Test session (S
i
)TSVs grouped for parallel charging of capacitor.
Maximum number
of faulty TSVs in
network (m)
m is the number of redundant TSVs within the
TSV network.
Session size (q) q is the number of active TSVs within a session.
Resolution (r) r is an upper bound on session size.
Test time of a
session (t(q))
Charging time of C
charge
, related to session size.
Fault map (ρ) Fault map represents positions of defective
TSVs within the TSV network.
Slide 14
Test Session Generation
Motivation
Compared to individual TSV test, large test
time saving is possible if we test TSVs in
parallel without losing the capability of
identifying up to m faulty TSVs, while
guaranteeing that the size of each test session
does not exceed the resolution constraint r.
09/16/25
© VLSI Design & Embedded Systems Conference -
2015
14
Slide 15
Test Session Generation
Problem Statement
Given:
Test times t(q) for different session sizes q
(q[1, r]), and
∈
Maximum number (m) of faulty TSVs in a
network of T TSVs.
Determine: A set of test sessions of size less than
r, such that up to m faulty TSVs are uniquely
identified and the total test time is minimized.
09/16/25
© VLSI Design & Embedded Systems Conference -
2015
15
Slide 16
Test Session Generation
Sufficient condition
If each TSV
i is included in m + 1 sessions (say,
S
1, S
2, · · · , S
m+1) and the intersection of a pair
of these m + 1 sessions contains only TSV
i, i.e.,
S
i ∩ S
j = TSV
i for i ≠ j [1,
∈
m + 1], then up to
m faulty TSVs within the network can be
uniquely identi
fied. These
m + 1 sessions are
called unique test sessions for TSV
i .
09/16/25
© VLSI Design & Embedded Systems Conference -
2015
16
B. Noia and K. Chakrabarty, “Identification of Defective TSVs in Pre-Bond
Testing of 3D ICs,” Proc. 20th Asian Test Symposium (ATS), 2011, pp. 187–
194.
Slide 17
A Previous Heuristic Method
To pinpoint 1 faulty TSV in a 6-TSV
network
with resolution constraint r = 4, the
heuristic-based sessions are
{1,2,3,4}, {1,5,6}, {2,5}, {3,6}, {4}.
Careful examination shows:
•Each TSV resides in two unique test
sessions!
•The heuristic sessions reduce the total test
time compared to individual TSV testing.
09/16/25
© VLSI Design & Embedded Systems Conference -
2015
17
B. Noia and K. Chakrabarty, “Identification of Defective TSVs in Pre-Bond
Testing of 3D ICs,” Proc. 20th Asian Test Symposium (ATS), 2011, pp. 187–194.
Slide 18
Limitation of the
Heuristic Method
Sessions {1,2,3,4}, {1,5,6}, {2,5}, {3,6}, {4} are not optimal.
The optimal set of sessions are
{1,2,3}, {1,4,5}, {2,4,6}, {3,5,6}
As we can see every TSV still resides in 2
unique sessions, but the total test time is
further reduced by 36.8%!
09/16/25
© VLSI Design & Embedded Systems Conference -
2015
18
Slide 19
ILP based Session Generation
Three general constraints for ILP model (ILP
model 1):
C1. Each TSV should be included in at least m + 1
test sessions.
C2. The size of a test session ranges anywhere
from 0 (empty session) to r.
C3. Any non-empty session is supposed to be a
unique session for any TSV within it.
Objective: Minimize total test time of all sessions.
09/16/25
© VLSI Design & Embedded Systems Conference -
2015
19
Slide 20
Experimental Results
09/16/25
© VLSI Design & Embedded Systems Conference -
2015
20
Test time comparison for a 20-TSV network
Slide 21
Experimental Results
09/16/25
© VLSI Design & Embedded Systems Conference -
2015
21
Test time comparison for resolution constraint r = 3
Slide 22
Experimental Results
09/16/25
© VLSI Design & Embedded Systems Conference -
2015
22
Comparison of number of sessions for r = 4
Slide 23
Conclusion
09/16/25
© VLSI Design & Embedded Systems Conference -
2015
23
•An ILP model is proposed to generate near-
optimal set of test sessions for pre-bond
TSV testing.
•ILP model always reduces pre-bond TSV
identification time compared to that of a
previous heuristic method.
•Future exploration can be possibly deriving
necessary and sufficient conditions to
generate globally optimal set of sessions.
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