Block Diagram of Combinational Circuit.pptx

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1. ∙ ∙ Combinational circuit ∙ n inputs m outputs Fig. 4-1 Block Diagram of Combinational Circuit

2. Fig. 4-2 Logic Diagram for Analysis Example A B A B C A B C A C B C F 2 F 1 T 3 T 2 T 1 F ' 2

3. 11 CD 1 11 A C B 10 D z = D ' X 01 1 X X 1 X 10 1 X AB 00 1 X 1 1 1 1 1 X X X X 1 X X AB 00 01 11 10 CD 1 11 A C B 10 D y = CD + C ' D ' 1 1 1 X X X X 1 1 X X AB 00 01 11 10 CD 1 11 A C B 10 D w = A + BC + BD D X = B ' C + B ' D + BC ' D ' 1 1 1 1 X X X X 1 X X AB 00 01 11 10 CD 1 11 A C B 10 Fig. 4-3 Maps for BCD to Excess-3 Code Converter

4. x © 2002 Prentice Hall, Inc. M. Morris Mano DIGITAL DESIGN, 3e. z y w D C ( C + D ) ' C + D CD D ' B A Fig. 4-4 Logic Diagram for BCD to Excess-3 Code Converter

5. x y ' x ' y x y S C x y S C (a) S = xy ' + x ' y C = xy (b) S = x 8 y C = xy Fig. 4-5 Implementation of Half- Adder

6. 1 1 1 1 x yz 1 x 1 y z S = x ' y ' z + x ' yz '+ xy ' z ' + xyz 11 10 x yz 1 x 1 y 11 10 1 1 1 1 z S = xy + xz + yz = xy + xy ' z + x ' yz Fig. 4-6 Maps for Full Adder

7. x y x z y z C x ' y ' z x ' y z ' x y ' z ' x y z S Fig. 4- 7 Implementation of Full Adder in Sum of Products

8. x y z Fig. 4-8 Implementation of Full Adder with Two Half Adders and an OR Gate S C

9. B 3 A 3 C 4 S 3 FA B 2 A 2 C 3 S 2 FA B 1 A 1 C 2 S 1 FA B A C 1 S FA C Fig. 4-9 4-Bit Adder

10. S i C i + 1 A i B i P i G i C i Fig. 4-10 Full Adder with P and G Shown

11. C 3 C 2 C 1 P 2 G 2 P 1 G 1 P G C Fig. 4-11 Logic Diagram of Carry Lookahead Generator

12. B 3 A 3 P 3 P 3 G 3 P 2 P 2 G 2 P 1 P 1 G 1 P P G C C 3 S 3 C 4 C 4 C 2 S 2 C 1 S 1 S B 2 A 2 B 1 A 1 B A C Carry Look ahead generator Fig. 4-12 4-Bit Adder with Carry Lookahead

13. B 3 A 3 C 4 C V S 3 FA B 2 A 2 C 3 S 2 FA B 1 A 1 C 2 S 1 FA B A C 1 S FA C M Fig. 4-13 4-Bit Adder Subtractor

14. Output carry Carry out Carry in Addend Augend 4- bit binary adder 4- bit binary adder K Z 8 Z 4 Z 2 Z 1 Fig. 4-14 Block Diagram of a BCD Adder S 8 S 4 S 2 S 1

15. HA HA C 3 C 2 B 1 A 1 A B B 1 B C 1 C B 1 A 1 B A A 1 B 1 A B 1 A 1 B A B C 3 C 2 C 1 C Fig. 4-15 2-Bit by 2-Bit Binary Multiplier

16. B 3 A A 1 B 2 B 1 B B 3 B 2 B 1 B Addend Augend 4- bit adder Sum and output carry A 2 B 3 B 2 B 1 B Addend Augend 4- bit adder Sum and output carry C 2 C 1 C C 3 C 4 C 5 C 6 Fig. 4-16 4-Bit by 3-Bit Binary Multiplier

17. ( A < B ) ( A > B ) ( A = B ) x 3 A 3 B 3 A 2 B 2 A 1 B 1 A B x 2 x 1 x Fig. 4-17 4-Bit Magnitude Comparator

18. D = x ' y ' z ' Fig. 4-18 3-to-8-Line Decoder D 1 = x ' y ' z D 2 = x ' yz ' D 3 = x ' yz D 4 = xy ' z ' D 5 = xy ' z D 6 = xyz ' D 7 = xyz z y x

19. D D 1 D 2 A B E D 3 E A B D D 1 D 2 D 3 1 X X 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 (a) Logic diagram (b) Truth table Fig. 4-19 2-to-4-Line Decoder with Enable Input

20. x y z w D to D 7 D 8 to D 15 3 × 8 decoder E 3 × 8 decoder E Fig. 4-20 4 × 16 Decoder Constructed with Two 3 × 8 Decoders

21. S C x y z 1 2 2 2 2 1 2 3 4 5 6 7 3 × 8 decoder Fig. 4-21 Implementation of a Full Adder with a Decoder

22. 00 01 11 10 1 D D 2 D 1 11 10 D 3 x = D 2 + D 3 X 1 1 1 1 1 1 1 1 1 1 1 1 00 01 11 10 1 D D 2 D 1 11 10 D 3 y = D 3 + D 1 D ' 2 X 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Fig. 4- 22 Maps for a Priority Encoder

23. D 3 D 2 D 1 D y x V Fig. 4- 23 4-Input Priority Encoder

24. I S Y I 1 Y I I 1 S (a) Logic diagram (b) Block diagram MUX 1 Fig. 4-24 2-to-1-Line Multiplexer

25. Y (a) Logic diagram Fig. 4-25 4-to-1-Line Multiplexer (b) Function table I I 1 I 2 I 3 s 1 s s 1 s Y 1 1 1 1 I I 1 I 2 I 3

26. A Fig. 4-26 Quadruple 2-to-1-Line Multiplexer Y Y 1 Y 2 Y 3 A 1 A 2 A 3 B B 1 B 2 B 3 S (select) E (enable) E S Output Y 1 X all ' s select A 1 select B Function table

27. S S 1 1 2 3 y x z z ' 1 F (a) Truth table (b) Multiplexer implementation Fig. 4-27 Implementing a Boolean Function with a Multiplexer 4 × 1 MUX x y z F F = z 1 1 1 1 1 1 F = z ' 1 F = 1 1 1 1 1 F = 1 1 1 1 1

28. S S 1 S 2 1 2 3 4 5 6 7 8 × 1 MUX C B A D F 1 A B C D F 1 1 F = D 1 1 1 F = D 1 1 1 1 1 F = D ' 1 1 F = 1 1 1 1 F = 1 1 1 1 1 1 1 F = D 1 1 1 1 F = 1 1 1 1 1 1 1 1 1 F = 1 1 1 1 1 1 Fig. 4-28 Implementing a 4-Input Function with a Multiplexer

29. Normal input A Output Y = A if C = 1 High–impedance if C = Control input C Fig. 4-29 Graphic Symbol for a Three- State Buffer

30. I I 1 I 2 I 3 S 1 S EN Select Enable Y A B Y Select (a) 2-to-1- line mux (b) 4 - to - 1 line mux Fig. 4-30 Multiplexers with Three- State Gates 1 2 3 2 × 4 decoder

31. in out control bufifl in out control bufif0 in out control notifl in out control notif0 Fig. 4-31 Three- State Gates

32. A B select Fig. 4-32 2-to-1-Line Multiplexer with Three- State Buffers out

33. Stimulus module Design module circuit cr (TA, TB, TC); wire TC; reg TA, TB; module testcircuit module circuit (A, B, C); input A, B; output C; Fig. 4-33 Stimulus and Design Modules Interaction

34. A B C D T 1 T 3 T 4 F 1 F 2 T 2 Fig. P4- 1

35. A F G B C D Fig. P4- 2

36. b c b a g d c f e (a) Segment designation (b) Numerical designation for display Fig. P4- 9