Capstone one final report presentation slides.pdf

project report slides

1. BPF LNA
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LPF
LPF
I (Baseband)
Q (Baseband)
Local
Oscillator

2. Design of a 2.45 GHz RF (Radio Frequency)
Receiver in CMOS 45nm technology

3. Co-Supervisor:
Dr. Raqibul Mostafa
Professor, Dept. of EEE
Co-Supervisor:
Dr. Md. Hasanuzzaman
Assistant Professor, Dept. of EEE
Coordinator:
Dr. Kaled Masukur Rahman
Professor, Dept. of EEE & Head of Dept.
Chair:
Azad Hossain Saykat
021 221 017
Member:
Sazzad Hossen
021 221 026
Member:
Md. Tahman Hossain
021 221 099
Recorder:
Suvom Karmakar
021 221 027

4. 01 02 03 04 05 06
Why RF
Receivers
Matter?
Background
&
Introduction
Literature
Review
Methodology
Project
Attributes
Conclusion

5. Why RF Receivers Matter?
Motivation
➢Growing demand for compact and low-power RF
receivers.
➢RF front-end performance directly affects signal
quality and power usage.
➢Receiver performance defines signal sensitivity,
power consumption, and noise tolerance.
➢2.45 GHz band is globally license-free - huge
scope in IoT, medical, and industrial fields.
➢CMOS-based design allows integration in a single
chip.
Fig: 2.45 GHz Band Applications in IoT, Medical,
and Industrial Fields
[Courtesy: Online Source]
Presented By:
Azad Hossain Saykat 1

6. Background & Introduction
Real-Life Applications
➢Wireless communication: Wi-Fi, Bluetooth,
Zig-bee etc.
➢Internet of Things (IoT) and wearable devices
➢Smart health monitoring (wireless ECG,
fitness trackers)
➢Industrial automation, smart homes, wireless
sensors
Fig: Wireless Technology for IoT Edge Devices
[Courtesy: Online Source]
Presented By:
Azad Hossain Saykat
2

7. Background & Introduction
Project Purpose and Objectives
➢Design and simulate a complete RF front-end receiver in the 2.45 GHz ISM band.
➢Study and implement blocks with optimized power, gain, noise figure, and linearityetc.
➢Learn the design flow in Cadence using 45 nm technology.
Presented By:
Azad Hossain Saykat 3

8. Understanding RF Receiver Design
•Each block plays a vital role in ensuring optimal performance of the receiver chain.
Fig: Proposed RF receiver Architecture
Background & Introduction
Presented By:
Azad Hossain Saykat
4

9. Literature Review
Band Pass Filter Design
Low Noise Amplifier
Design
Mixer Design
Low Pass Filter Design
Radio Frequency
(RF) Receiver
Design Literature
Review
01
02
03
04
Presented By:
Suvom Karmakar
5

10. Literature ReviewReference
B. Razavi, "CMOS RF receiver design for wireless
LAN applications," RAWCON 99. 1999 IEEE Radio
and Wireless Conference (Cat. No.99EX292), Denver,
CO, USA, 1999, pp. 275-280, doi:
10.1109/RAWCON.1999.810984.
Wenjun Sheng, A. Emira and E. Sanchez-Sinencio, "CMOS RF receiver
system design: a systematic approach," in IEEE Transactions on Circuits
and Systems I: Regular Papers, vol. 53, no. 5, pp. 1023-1034, May
2006, doi: 10.1109/TCSI.2005.862286.
Michailidis, Anastasios, Alexandros Chatzis, Panayiota Tsimpou,
Vasiliki Gogolou, and Thomas Noulis. 2025. "A Unified Design
Methodology for Front-End RF/mmWave Receivers" Electronics
14, no. 2: 235. https://doi.org/10.3390/electronics14020235
Block Diagram
CMOS RF Receiver System Design: A Systematic
Approach (2006)
A Unified design Methodology for Front-end
RF/mmWave Receivers (2025)
Paper Title
CMOS RF Receiver Design for Wireless
LAN Application (1999)
6
Presented By:
Suvom Karmakar

11. Literature Review
Paper
Title
CMOS RF Receiver Design for
Wireless LAN Application (1999)
CMOS RF Receiver System Design:
A Systematic Approach (2006)
A Unified design Methodology for
Front-end RF/mmWave Receivers (2025)
Key
Focus
A 2.4-GHz receiver using CMOS
technology for wireless networks,
designed to reduce noise and manage
signal interference for better
performance.
A structured methodology for designing
CMOS RF receiver systems, emphasizing
the optimization of total power consumption
through integrated system-level
specifications and the use of equations to
compute noise factors and power
coefficients for each block.
Proposes a streamlined method using S, Z, and
Y parameters to design high-performance LNAs
and VCOs for RF/mmWave receivers in 65 nm
CMOS, optimizing noise, gain, and resonance.
Findings
Features an LNA and channel-select
filters with I/Q amplifiers, achieving 8.3
dB noise (signal clarity), 2.2 dBm
interference tolerance, 34 dB gain, and
80 mW power use with DC offset
removal.
The study found that a systematic simulation
process with predefined rules optimized
power and noise in CMOS RF receivers, with
Bluetooth tests confirming a close match
between simulated and actual performance.
Achieves excellent signal processing with
minimal signal reflection (-43 dB), strong LNA
signal boost (17 dB, 15.5 dB after real-world
adjustments), and ensures stable 5 GHz VCO
signals, while simplifying design with fewer
adjustments.
Gap
Built on 0.6µm CMOS technology (less
efficient than 45nm), tuned for 2.4GHz
(not 2.45GHz), and characterized by
high power consumption with outdated
integration.
Concentrates on power but neglects modern
requirements like DC offset removal or I/Q
signal improvement.
Designed for 65 nm CMOS and 5 GHz, not 45
nm or 2.45 GHz; misses focus on low-power
optimization and integrating full receiver systems,
needing adjustments for 45 nm technology and
2.45 GHz applications.
Presented By:
Suvom Karmakar
7

12. Proposed Improvements Based on Literature Review
2. CMOS Technology Scaling
Leverage 45nm CMOS advances for integrated system-level design to achieve target 45mW power
consumption.
1. 2.45 GHz LNA Optimization
Apply systematic S-parameter methodology for achieving 15-20 dB gain
with < 2 dB noise figure at 1.2V supply.
2. CMOS Technology Scaling
Leverage 45nm CMOS advances for integrated system-level design to
achieve target 20mW power consumption.
3. Integrated BPF Design
Implement optimized bandpass filtering for 2.45 GHz range with precise
20-100 MHz passband control.
4. System-Level Architecture
Focus on total RF receiver system integration for 2.45 GHz applications.
Presented By:
Suvom Karmakar
8

13. RF Receiver Design Specification
Band Pass Filter (BPF) Specification
Parameter Value
Passband Width 20 MHz to 100 MHz
Center Frequency 2.45 GHz
Upper Cutoff Frequency 2.45 GHz + 10 MHz
Lower Cutoff Frequency 2.45 GHz - 10 MHz
Low Noise Amplifier (LNA) Specification
Parameter Value
Supply voltage 1.2 V
Power Consumption 20 mW
Frequency 2.45 GHz
NF (50 Ω) < 2dB
Gain 15-20 dB
Mixer Specification
Parameter Specification
Supply voltage 1.2 V
Power Consumption 20 mW
RF frequency 2.45 GHz
Low Pass Filter (LPF) Specification
Parameter Specification
Passband Frequency 2.45 GHz
Stopband Frequency Starts at 2.7 GHz
Stopband Attenuation 40 dB to 60 dB
Bandwidth 2.45 GHz to 2.6 GHz
1
3
2
4
Presented By:
Suvom Karmakar
9

14. Methodology
System
Architecture
Planning
Schematic Design
& Simulation
Future
Perspective
Physical
Verification &
Layout
Presented By:
Sazzad Hossen 10

15. BPF LNA
??????
??????
LPF
LPF
I (Baseband)
Q (Baseband)
Local
Oscillator
RF INPUT BPF LNA MIXER LPF OUTPUT
Fig: RF Receiver Design Model
System Architecture Planning
Presented By:
Sazzad Hossen 11

16. 1 Purpose 2 Working 3 Importance
System Block Explanation Band Pass Filter Block
Low Noise Amplifier Block
Mixer Block
Low Pass Filter Block
BPF
in out
in out
LNA
Mixer
LPF
in out
Presented By:
Sazzad Hossen 12

17. 1 BPF
Centre Frequency
Noise Figure
2 LNA 3 Mixer
Frequency Conversion
IQ Demodulation
Linearity & Isolation
4 LPF
Cutoff Frequency
Filter Type
AttenuationImpedance Matching
Bandwidth
Gain
Each block will be simulated independently for:
❑Gain and bandwidth (AC analysis)
❑Noise figure (Noise analysis)
❑Impedance matching (S-parameter analysis)
❑Transient behavior
•The entire circuit will be designed in Cadence Virtuoso Schematic Editor and will be simulated using Spectre.
Schematic Design & Simulation (CP-2)
Real-World Considerations:
Impedance Matching
Noise Performance
Frequency Planning Linearity and Gain
Presented By:
Sazzad Hossen 13

18. Physical Verification & Layout (CP-3)
•After completing the schematic design verification, we will proceed with the layout design in Cadence
Virtuoso Layout Editor. Our primary considerations will be:
LAYOUT LVS DRC
Future Perspective:
•Since the project is academic, we did not proceed as far as chip-level. However, the entire receiver
front-end is validated through simulation and layout and is ready for future tape-out or integration into
a larger RF system.
Presented By:
Sazzad Hossen 14

19. Project Attributes
1
PO2: Problem Analysis
Addressing challenges in
the 2.45 GHz ISM band,
including interference and
weak signal detection.
2
PO3: Design/Development of
Solutions
Focus on performance optimization
and interference reduction using
LNA, BPF, LPF, and mixer
components.
3
PO4: Investigation
Circuit-level analysis, simulation,
and exploring design ideas for
improved performance.
4
PO5: Modern Tool Usage
Simulation with Cadence for power consumption and
operability.
5
PO6: Engineer and Society
Reusable RF receiver block design for future
communication systems.
Program Outcomes (POs) Justifications
Presented By:
Md. Tahman Hossain 15

20. K3 & K5
Systematic & Engineering
Design Knowledge:
Simulation-based RF receiver
design grounded in first-
principles.
1
K4
Specialist Knowledge:
Addressing signal sensitivity,
power efficiency, and
optimization challenges.
2
K1 & K8
Theory & Research-Based
Knowledge: Innovation through
creative design for signal
interference and weak signal
challenges.
3
Knowledge Profile (K) Justifications
Presented By:
Md. Tahman Hossain 16

21. Sustainability & SDG Alignment
SDG 4 -Quality Education: Real-world RF engineering experience aligned with education standards.
SDG 7 -Affordable and Clean Energy: Low-power RF design for energy-efficient systems.
SDG 9 -Industry, Innovation, and Infrastructure: Reliable RF receiver design for telecom and IoT
SDG 11 -Sustainable Cities and Communities: Supporting smart cities and healthcare connectivity
SDG 12 -Responsible Consumption and Production: Promoting sustainable practices with
simulation-based design
SDG 17 -Partnerships for the Goals: Academia, industry, and research collaboration for innovative
solutions.
Presented By:
Md. Tahman Hossain 17

22. ✓CP 1
✓CP 2
✓CP 3
Project Management & Timeline
18

23. Weekly Meetings
Regular check-ins with
supervisors to discuss
progress, address challenges,
and plan next steps.
Work Division
Specific responsibilities for
BPF, LNA, Mixer, and LPF
design, with cross-support for
testing and integration.
Documentation
Comprehensive technical
reports and design logs to
ensure knowledge transfer
and traceability.
Communication & Co-ordination
Key Takeaways
•Robust RF receiver design for ISM
band applications.
•Strong alignment with engineering program
outcomes and knowledge profiles.
Next Steps
•Schematic and Layout Design
•Real-world deployment and
performance validation.
Presented By:
Md. Tahman Hossain 19

24. Conclusion
•We will design a 2.45GHz RF receiver front-end using 45nm CMOS technology.
•Each block (BPF, LNA, Mixer, LPF) will be simulated and verified in Cadence.
•The design will aim to achieve optimal gain, low noise figure, and power efficiency.
•After layout verification, it will be ready for future integration or tape-out.
•The project will align with academic goals and support real-world RF applications in
IoTandhealthcare.
Presented By:
Md. Tahman Hossain 20

25. THANK YOU