chapter 6-kamelvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv -.pdf

vvvvvvvvvvvvvvvv

1. An-NajahNational University
Faculty of Engineering
Electrical Engineering Department
Field-Effect Transistors (FETs)
Introduction
FETs are unipolardevices.
Only one type of carrier is used per transistor (either holes or electrons).
Two main types:
Junction field-effect transistor (JFET).
Metal oxide field-effect transistor (MOSFET).
While the BJT is a current-controlled device (base current controls the collector current), the
FET is a voltage-controlled device (voltage between two of the terminals controls the current
through the device).
FETs have very high input resistance.

2. An-NajahNational University
Faculty of Engineering
Electrical Engineering Department
Field-Effect Transistors (FETs)
The Junction Field-Effect Transistor (JFET)
The JFET is a type of FET that operates with a reverse-biased pnjunction.
The pnjunction controls current in a channel.
the channel may be either of n or p type material.
It has three leads:
Drain
Gate
Source
In the n-channel JFET, the gate is connected to both p regions.
In the p-channel JFET, the gate is connected to both n regions.
Only one gate lead is shown for simplicity.

3. An-NajahNational University
Faculty of Engineering
Electrical Engineering Department
Field-Effect Transistors (FETs)
The Junction Field-Effect Transistor (JFET)
Let’s look at an n-channel JFET.
V
DD provides a drain-to-source voltage, thus supplying a current from the drain to the source.
V
GGsets the reverse-bias voltage between the gate and the source.
Note that the gate-source pnjunction should ALWAYSbe reverse biased.
The reverse biasing of the gate source junction produces
a depletion region along the pnjunction.
The depletion formed extends into the n channel.

4. An-NajahNational University
Faculty of Engineering
Electrical Engineering Department
Field-Effect Transistors (FETs)
The Junction Field-Effect Transistor (JFET)
By increasing the depletion region, the width of the n channel becomes thinner.
Making the channel thinner creates more resistance against current flow.

5. An-NajahNational University
Faculty of Engineering
Electrical Engineering Department
Field-Effect Transistors (FETs)
The Junction Field-Effect Transistor (JFET)
The symbol for the JFET is:

6. An-NajahNational University
Faculty of Engineering
Electrical Engineering Department
Field-Effect Transistors (FETs)
The Junction Field-Effect Transistor (JFET)
The JFET is a voltage-controlled, constant-current device.
To understand this, consider the case when the gate-to-source voltage is zero (V
GS=0).
To get this, we need to short the gate to the source.
As V
DDincreases, V
DS increases as well.
I
D, the drain current, will also increase
proportionally to increases in V­
DD.
This increase in drain current is linear,
because the depletion region is NOT large
enough to have significant effect.
This is shown between points A and B.
JFET Characteristics and Parameters

7. An-NajahNational University
Faculty of Engineering
Electrical Engineering Department
Field-Effect Transistors (FETs)
The Junction Field-Effect Transistor (JFET)
The region between points A and B is called the ohmicregion.
At point B, I
Dbecomes essentially constant.
This occurs because the reverse bias voltage from gate to drain (V
GD) produces a depletion
region large enough to offset the
increase in V
DS.
The offset is enough to keep I
Dconstant.
I
D­ will remain constant until point C, where
we reach breakdown.
JFET Characteristics and Parameters

8. An-NajahNational University
Faculty of Engineering
Electrical Engineering Department
Field-Effect Transistors (FETs)
The Junction Field-Effect Transistor (JFET)
Connecting a bias voltage, V
GG, to the gate produces a family of curves as shown next.
Notices that I
Ddecreases as V
GSis made more negative.
This occurs because the channel is narrowing.
Also notice that pinch-off occurs at different V
P’s for different V
GSvalues.
Thus, the drain current is controlled
by V
GS.
JFET Characteristics and Parameters

9. An-NajahNational University
Faculty of Engineering
Electrical Engineering Department
Field-Effect Transistors (FETs)
The Junction Field-Effect Transistor (JFET)
The value of V
GSthat makes I­
Dapproximately zero is called the cutoff voltage, V
GS(off).
Note that the value of V
GSthat sets I
Dto zero (i.e. widening the depletion region to a point
where the channel is completely closed) is the most negative value V
GScan take
The operation of a p-channel is the same as the n-channel, but requires a negative V­
DDand a
positive V
GS.
JFET Characteristics and Parameters

10. An-NajahNational University
Faculty of Engineering
Electrical Engineering Department
Field-Effect Transistors (FETs)
The Junction Field-Effect Transistor (JFET)
V
P ­is the value of V
DSat which the drain current becomes constant.
It is always measured at V­
GS= 0.
Pinch-off occurs for V
DSvalues less than V
P, when V
GSis nonzero.
So, although V
Pis a constant, the minimum value of V
DSat which I
Dbecomes constant varies
with V
GS.
V
GS(off)and V
P are always equal in magnitude, but opposite in sign.Thus, knowing one, we have
the other.
Data sheets will generally list only one of the two.
For example, if V
GS(off)= -5 V, then V
P= +5 V.
Relation between Pinch-Off and Cutoff voltages

11. An-NajahNational University
Faculty of Engineering
Electrical Engineering Department
Field-Effect Transistors (FETs)
The Junction Field-Effect Transistor (JFET)
Determine the minimum vale of V
DDrequired to put the JFET below in the constant-current
region of operation.
Example

12. An-NajahNational University
Faculty of Engineering
Electrical Engineering Department
Field-Effect Transistors (FETs)
The Junction Field-Effect Transistor (JFET)
Since V
GS(off)= –4 V, V
P= 4 V. The minimum value of V
DS for the JFET to enter the constant current
region is
V
DS= V
P= 4 V
In the constant current area with V
GS= 0 V,
I
D= I
DSS= 12 mA
The drop across the drain resistor is
V
R(D)= I
­DR
D= (12 mA)(560 Ω) = 6.72 V
Using KVL around the drain circuit
V
DD= V
DS+ V
R(D)= 4 V + 6.72 V = 10.72 V
Thus, V
DDmust be 10.72 V for the device to enter the constant current area, i.e. to make V
DS= V
P.
Solution

13. An-NajahNational University
Faculty of Engineering
Electrical Engineering Department
Field-Effect Transistors (FETs)
The Junction Field-Effect Transistor (JFET)
A particular p-channel JFET has a V
GS(off)­ = +4 V. What is I
Dwhen V
GS= +6 V?
Solution
Recall a p-channel JFET requires a positive gate-to-source voltage. The more positive V
GS, the
less the drain current. When V
GS= 4 V, I
D= 0 (cutoff). Any further increase in V
GSkeeps the JFET
cut off, so I
Dremains at 0.
Example

14. An-NajahNational University
Faculty of Engineering
Electrical Engineering Department
Field-Effect Transistors (FETs)
The Junction Field-Effect Transistor (JFET)
A range of V
GSvalues between 0 and V
GS(off)controls the drain current.
For an n channel JFET, V
GS(off)is negative.
For a p channel JFET, V
GS(off)is positive.
The relation between V
GSand I
Dis shown below:
The voltage ranges from V
GS= V
GS(off)to zero.
The current ranges from 0 to I
DSS.
The curve shows the operational limits of the transistor.
JFET Transfer Characteristic

15. An-NajahNational University
Faculty of Engineering
Electrical Engineering Department
Field-Effect Transistors (FETs)
The Junction Field-Effect Transistor (JFET)
The equation for the JFET characteristic curve is:
I
D= I­
DSS(1 –V
GS/V
GS(off))
2
Thus, if I
DSSand V
GS(off)­ are known,
I
D­ can be determined for any V
GS.
Notice that the characteristic curve
is parabolic.
Because of this, JFET and MOSFET
are often referred to as square-law
devices.
JFET Transfer Characteristic

16. An-NajahNational University
Faculty of Engineering
Electrical Engineering Department
Field-Effect Transistors (FETs)
The Junction Field-Effect Transistor (JFET)
Example
Determine the drain current for V
GS= 0 V, -1 V and –4 V for a 2N5459 JFET.
JFET Transfer Characteristic

17. An-NajahNational University
Faculty of Engineering
Electrical Engineering Department
Field-Effect Transistors (FETs)
The Junction Field-Effect Transistor (JFET)
JFET Transfer Characteristic

18. An-NajahNational University
Faculty of Engineering
Electrical Engineering Department
Field-Effect Transistors (FETs)
The Junction Field-Effect Transistor (JFET)
Looking at the data sheet we find that I
DSS= 9 mAand V
GS(off)= -8 V(maximum).
Thus, we can say that for V
GS= 0
I
D= I
DSS= 9mA
For V
GS= –1 V we use the equation shown above:
I
D= I­
DSS(1 –V
GS/V
GS(off))
2
= (9 mA)(1 –(-1 V/-8 V))
2
= 6.89 mA
For V
GS= –4 V :
I
D= I­
DSS(1 –V
GS/V
GS(off))
2
= (9 mA)(1 –(-4 V/-8 V))
2
= 2.25 mA
JFET Transfer Characteristic

19. An-NajahNational University
Faculty of Engineering
Electrical Engineering Department
Field-Effect Transistors (FETs)
The Junction Field-Effect Transistor (JFET)
Since the JFET operates with the gate-source junction reverse-biased, the input resistance is
very high.
This is one advantage of JFET over BJTs.
The input resistance can be calculated by:
R
IN­ = |V
GS/I
GSS|
Input Resistance

20. An-NajahNational University
Faculty of Engineering
Electrical Engineering Department
Field-Effect Transistors (FETs)
The Junction Field-Effect Transistor (JFET)
Just as with the BJTs, we need to establish the right dc gate-to-source voltage to get the
desired value of drain current.
We will study to biasing methods:
Self Bias
Voltage-Divider Bias
JFET Biasing

21. An-NajahNational University
Faculty of Engineering
Electrical Engineering Department
Field-Effect Transistors (FETs)
The Junction Field-Effect Transistor (JFET)
Most common biasing method for JFETs.
We need a negative V
GS for an n channel JFET.
We need a positive V
GS for a p channel JFET.
We achieve that with the circuit shown below.
The gate resistor, R
G, does NOT affect the bias since there is almost no drop across it.
Thus, the gate remains at zero.
R
Gis used to isolate an ac signal from ground in amplifier applications.
JFET Biasing
Self Bias

22. An-NajahNational University
Faculty of Engineering
Electrical Engineering Department
Field-Effect Transistors (FETs)
The Junction Field-Effect Transistor (JFET)
Consider the n-channel JFET circuit.
I
Sproduces a voltage drop across R
S.
This makes the source positive with respect to ground.
Since I
S= I
Dand V
G= 0, then V
S= I
DR
S.
Thus:
V
GS= V
G–V
S= 0 –I
DR
S= –I
DR
S
JFET Biasing
Self Bias_ n-channel

23. An-NajahNational University
Faculty of Engineering
Electrical Engineering Department
Field-Effect Transistors (FETs)
The Junction Field-Effect Transistor (JFET)
For the p-channel JFET, the current through R
Sproduces a negative voltage at the source.
This makes the gate positivewith respect to the source.
Thus I
S= I
D, and V
GS= +I
DR
S
Consider again the n-channel transistor.
V
D= V
DD–I
DR
D
Since V
S= I
DR
S, the drain-to-source voltage is
V
DS= V­
D–V
S
= V
DD–I
D(R
D+ R
S)
JFET Biasing
Self Bias_ p-channel

24. An-NajahNational University
Faculty of Engineering
Electrical Engineering Department
Field-Effect Transistors (FETs)
The Junction Field-Effect Transistor (JFET)
Solution
V
S= I
DR
S= (5 mA)(220 Ω) = 1.1 V
V
D= V
DD–I
D­R
­D= 15 V –(5 mA)(1.0 kΩ) = 10 V
Thus,
V
DS= V
D–V
S= 10 V –1.1 V = 8.9 V
Since V
G= 0 V:
V
GS= V
G–V
S= 0 V –1.1 V = –1.1 V
JFET Biasing
Self Bias-channel

25. An-NajahNational University
Faculty of Engineering
Electrical Engineering Department
Field-Effect Transistors (FETs)
The Junction Field-Effect Transistor (JFET)
Determine I
Dfor a desired value of V
GSor viceversa.
Then, calculate the value of R
Sby using:R
S= |V
GS/I
D|
JFET Biasing
Setting the Q-point of a Self-Biased JFET

26. An-NajahNational University
Faculty of Engineering
Electrical Engineering Department
Field-Effect Transistors (FETs)
The Junction Field-Effect Transistor (JFET)
Determine the value of R
S(at V
GS= -5 V) required to self-bias an n-channel JFET that has the
transfer characteristic curve shown next.
JFET Biasing
Setting the Q-point of a Self-Biased JFET
Example

27. An-NajahNational University
Faculty of Engineering
Electrical Engineering Department
Field-Effect Transistors (FETs)
The Junction Field-Effect Transistor (JFET)
From the graph, I
D= 6.25 mAat V
GS = -5 V.
Then
R
S= |V
GS/I
D| = 5 V/6.25 mA= 800 Ω
JFET Biasing
Setting the Q-point of a Self-Biased JFET

28. An-NajahNational University
Faculty of Engineering
Electrical Engineering Department
Field-Effect Transistors (FETs)
The Junction Field-Effect Transistor (JFET)
Determine the value of R
Srequired to self-bias a p-channel JFET with I
DSS=25 mAand V
GS(off)= 15
V. V
GSis to be 5 V.
JFET Biasing
Setting the Q-point of a Self-Biased JFET
Example

29. An-NajahNational University
Faculty of Engineering
Electrical Engineering Department
Field-Effect Transistors (FETs)
The Junction Field-Effect Transistor (JFET)
Solution
Use the square-law equation:
I
D= I
DSS(1 –V
GS/V
GS(off))
2
= (25 mA)(1–5V/15V)
2
= 11.1mA
Now determine R
­S:
R
S= | V
GS/I
D| = 5 V/11.1 mA= 450 Ω
JFET Biasing
Setting the Q-point of a Self-Biased JFET

30. An-NajahNational University
Faculty of Engineering
Electrical Engineering Department
Field-Effect Transistors (FETs)
The Junction Field-Effect Transistor (JFET)
It is generally desirable to bias a JFET near the midpoint of its transfer characteristic, that is,
where I
D= I
DSS/2.
At this point we allow the maximum amount of drain current swing between I
DSSand 0.
It can be shown that we get approximately that value for I
DwhenV
GS=V
GS(off)/3.4.
To select a drain voltage at midpoint (V
D= V
DD/2), select a value of R
Dto produce the desired
voltage drop.
JFET Biasing
Setting the Q-point of a Self-Biased JFET
NOTE

31. An-NajahNational University
Faculty of Engineering
Electrical Engineering Department
Field-Effect Transistors (FETs)
The Junction Field-Effect Transistor (JFET)
Consider the circuit shown below.
From data sheet, plot the characteristic curve.
To determine the Q-point of the circuit, find V
GSat I
D= 0.
V
GS= -I
DR
S= (0)(470 Ω) = 0 V
Now, using I
DSS, calculate V
GSwhen I
D= I
DSS:
V
GS= -I
DR
S= -(10 mA)(470 Ω) = -4.7 V
JFET Biasing
Setting the Q-point of a Self-Biased JFET
Graphical Analysis of a Self Biased JFET

32. An-NajahNational University
Faculty of Engineering
Electrical Engineering Department
Field-Effect Transistors (FETs)
The Junction Field-Effect Transistor (JFET)
Draw a line connecting the two points.
This line is the load line.
Wherever the load line intersects the characteristic curve,
we have the Q-point of the circuit.
JFET Biasing
Setting the Q-point of a Self-Biased JFET
Graphical Analysis of a Self Biased JFET

33. An-NajahNational University
Faculty of Engineering
Electrical Engineering Department
Field-Effect Transistors (FETs)
The Junction Field-Effect Transistor (JFET)
Draw a line connecting the two points.
This line is the load line.
Wherever the load line intersects the characteristic curve,
we have the Q-point of the circuit.
JFET Biasing
Setting the Q-point of a Self-Biased JFET
Graphical Analysis of a Self Biased JFET

34. An-NajahNational University
Faculty of Engineering
Electrical Engineering Department
Field-Effect Transistors (FETs)
The Junction Field-Effect Transistor (JFET)
Determine the following for the network shown below
1-I
DQand V
GSQ
2-V
D
3-V
S
4-V
DS
5-V
DG
JFET Biasing
Self Biased JFET

35. An-NajahNational University
Faculty of Engineering
Electrical Engineering Department
Field-Effect Transistors (FETs)
The Junction Field-Effect Transistor (JFET)
Voltage at source needs to be more positive than voltage at gate to keep
the gate-source junction reverse biased.
Source voltage is V
S= I
SR
S.
The voltage at the gate is:
V
G= V
DD(R
2/(R
2+ R
1))
Thus, V
GS= V
G-V
S
Combining these equations we get:
I
D= (V
G-V
GS)/R
S
JFET Biasing
Voltage-Divider Bias

36. An-NajahNational University
Faculty of Engineering
Electrical Engineering Department
Field-Effect Transistors (FETs)
The Junction Field-Effect Transistor (JFET)
Determine I
Dand V
GSfor the FET with voltage-divider bias shown below. For this particular FET,
the internal parameters are such that V
D7 V.
Solution
I
D= (V
DD –V
D)/R
D= (12 V –7 V)/3.3 kΩ= 1.52 mA
V
S= I
DR
S= (1.52 mA)(2.2 kΩ) = 3.34 V
V
G= R
2/(R
1+R
2)V
DD= (1 MΩ)/(7.8 MΩ) 12 V = 1.54 V
V
GS= V
G –V
S= 1.54 V –3.34 V =–1.8V
JFET Biasing
Voltage-Divider Bias

37. An-NajahNational University
Faculty of Engineering
Electrical Engineering Department
Field-Effect Transistors (FETs)
The Junction Field-Effect Transistor (JFET)
Determine I
Dand V
GSfor the FET with voltage-divider bias shown below. For this particular FET,
the internal parameters are such that V
D7 V.
Solution
I
D= (V
DD –V
D)/R
D= (12 V –7 V)/3.3 kΩ= 1.52 mA
V
S= I
DR
S= (1.52 mA)(2.2 kΩ) = 3.34 V
V
G= R
2/(R
1+R
2)V
DD= (1 MΩ)/(7.8 MΩ) 12 V = 1.54 V
V
GS= V
G –V
S= 1.54 V –3.34 V =–1.8V
JFET Biasing
Voltage-Divider Bias

38. An-NajahNational University
Faculty of Engineering
Electrical Engineering Department
Field-Effect Transistors (FETs)
The Junction Field-Effect Transistor (JFET)
Determine the following for the network shown below
1-I
DQand V
GSQ
2-V
D
3-V
S
4-V
DS
5-V
DG
JFET Biasing
Voltage-Divider Bias

39. An-NajahNational University
Faculty of Engineering
Electrical Engineering Department
Field-Effect Transistors (FETs)
The Metal Oxide Semiconductor Field-Effect Transistor (MOSFET)
The MOSFET differs from the JFET in that it has nopnjunctions.
Instead, the gate of the MOSFET is insulated from the channel by a silicon dioxide (SiO
2) layer.
There are two basic types of MOSFETs:
Depletion (D) MOSFETs.
Enhancement (E) MOSFETs.

40. An-NajahNational University
Faculty of Engineering
Electrical Engineering Department
Field-Effect Transistors (FETs)
The Metal Oxide Semiconductor Field-Effect Transistor (MOSFET)
The D MOSFET can operate both in the enhancementand depletionmodes.
Since the gate is insulated from the channel, either a positive or a negative gate voltage can be
applied.
An n-channel MOSFET operates in depletion mode when a negative gate-to-source voltage is
applied.
It operates in an enhancement mode when a positive
Depletion MOSFET.

41. An-NajahNational University
Faculty of Engineering
Electrical Engineering Department
Field-Effect Transistors (FETs)
The Metal Oxide Semiconductor Field-Effect Transistor (MOSFET)
Depletion MOSFET.
The symbol for an D-MOSFET is shown next.

42. An-NajahNational University
Faculty of Engineering
Electrical Engineering Department
Field-Effect Transistors (FETs)
The Metal Oxide Semiconductor Field-Effect Transistor (MOSFET)
Depletion MOSFET.
Drain and source are diffused into the
substrate material and then connected
by a narrow channel adjacent to the
insulated gate.

43. An-NajahNational University
Faculty of Engineering
Electrical Engineering Department
Field-Effect Transistors (FETs)
The Metal Oxide Semiconductor Field-Effect Transistor (MOSFET)
Depletion MOSFET.
When the gate and source are connected to the
Ground and VDD is applied the current will pass
Through the channel from drain to source similar to
The FET operation.

44. An-NajahNational University
Faculty of Engineering
Electrical Engineering Department
Field-Effect Transistors (FETs)
The Metal Oxide Semiconductor Field-Effect Transistor (MOSFET)
Depletion MOSFET.
With a negative gate voltage, the negative charges on
the gate repel conduction electrons from the channel,
leaving positive ions in their place.
Thus, the n channel is depleted of some of its conducting
electrons.
Conductivity is decreased.
The greater the negative voltage on the gate, the greater the depletion of n channel
electrons.

45. An-NajahNational University
Faculty of Engineering
Electrical Engineering Department
Field-Effect Transistors (FETs)
The Metal Oxide Semiconductor Field-Effect Transistor (MOSFET)
Depletion MOSFET.
At a sufficiently large gate-to-source voltage, V
GS(off), the channel is completely depleted and
I
Dbecomes zero.
Just like the n-channel FET, the n-channel D-MOSFET conducts drain current for gate-to-
source voltages between V
GS(off) and zero.

46. An-NajahNational University
Faculty of Engineering
Electrical Engineering Department
Field-Effect Transistors (FETs)
The Metal Oxide Semiconductor Field-Effect Transistor (MOSFET)
Operates ONLY in the enhancement mode. It has nodepletion mode.
It has no actual channel.
The substrate extends completely to the SiO­
2layer.
Enhancement MOSFET.

47. An-NajahNational University
Faculty of Engineering
Electrical Engineering Department
Field-Effect Transistors (FETs)
The Metal Oxide Semiconductor Field-Effect Transistor (MOSFET)
For the n channel device, a positive gate
voltage above a threshold value inducesa channel
by creating a thin layer of negative charges in the
substrate region adjacent to the SiO
2layer.
Conductivity is enhanced by increasing the
gate-to-source voltage.
This pulls more electrons into the channel area.
Enhancement MOSFET.

48. An-NajahNational University
Faculty of Engineering
Electrical Engineering Department
Field-Effect Transistors (FETs)
The Metal Oxide Semiconductor Field-Effect Transistor (MOSFET)
For any voltage below the threshold value,
there is no channel.
Enhancement MOSFET.

49. An-NajahNational University
Faculty of Engineering
Electrical Engineering Department
Field-Effect Transistors (FETs)
The Metal Oxide Semiconductor Field-Effect Transistor (MOSFET)
The symbol for an E-MOSFET is shown next.
The dashed line indicates the absence of a channel.
Enhancement MOSFET.

50. An-NajahNational University
Faculty of Engineering
Electrical Engineering Department
Field-Effect Transistors (FETs)
The Metal Oxide Semiconductor Field-Effect Transistor (MOSFET)
Enhanced MOSFET.
There is no drain current when V­
GS= 0.
Ideally, there is no drain current until V
GSreaches a certain non-zero value called the threshold
voltage, V
GS(th).
The square law equation for the drain current, thus, becomes:
I
D= K(V
GS–V
GS(th))
2
The constant K depends on the particular MOSFET.
It can be found from the data sheet by looking at the
specified value of I
D, called the on-state value or I
D(on), at
the given value of V
GS­.
Substitute the two parameters into the equation above
and solve for K.

51. An-NajahNational University
Faculty of Engineering
Electrical Engineering Department
Field-Effect Transistors (FETs)
The Metal Oxide Semiconductor Field-Effect Transistor (MOSFET)

52. An-NajahNational University
Faculty of Engineering
Electrical Engineering Department
Field-Effect Transistors (FETs)
The Metal Oxide Semiconductor Field-Effect Transistor (MOSFET)
K=I
D/(V
GS(on)–V
GS(th))
2
=3 mA/(10-3V)
2
=0.061x10
-3
A/V
2

53. An-NajahNational University
Faculty of Engineering
Electrical Engineering Department
Field-Effect Transistors (FETs)
The Metal Oxide Semiconductor Field-Effect Transistor (MOSFET)
ALL MOS DEVICES ARE SUBJECT TO DAMAGE FROM ELECTROSTATIC DISCHARGE (ESD).
Since the gate of a MOSFET is insulated form the channel, the input resistance is very high.
The gate leakage current (I
GSS) is in the pArange.
The gate reverse current for a JFET is in the nArange.
The input capacitance results from the insulated gate structure.
Excess static charge can be accumulated because the input capacitance combines with the
very high input resistance.
This can result in damaging the device.
Handling precautions!!

54. An-NajahNational University
Faculty of Engineering
Electrical Engineering Department
Field-Effect Transistors (FETs)
The Metal Oxide Semiconductor Field-Effect Transistor (MOSFET)
Example :-for n-channel depletion-type MOSFET. Determine
I
DQ, V
GSQ, V
DS
Repeat with Rs=150
D-MOSFET Biasing

55. An-NajahNational University
Faculty of Engineering
Electrical Engineering Department
Field-Effect Transistors (FETs)
The Metal Oxide Semiconductor Field-Effect Transistor (MOSFET)
Example :-for n-channel depletion-type MOSFET. Determine
I
DQ, V
GSQ, V
DS
Repeat with Rs=150
D-MOSFET Biasing

56. An-NajahNational University
Faculty of Engineering
Electrical Engineering Department
Field-Effect Transistors (FETs)
The Metal Oxide Semiconductor Field-Effect Transistor (MOSFET)
V
GSmust be greater than the threshold value V
GS(th).
Thus, zero bias cannot be used.
We use either a voltage-divider or a drain-feedback bias arrangement.
The goal is to make the gate voltage more positive than the source by an amount exceeding
V
GS(th).
The drain-feedback bias circuit has a negligible gate
current.
Thus, there is no drop across R
G.
Thus, V
GS= V
DS.
E-MOSFET Biasing

57. An-NajahNational University
Faculty of Engineering
Electrical Engineering Department
Field-Effect Transistors (FETs)
The Metal Oxide Semiconductor Field-Effect Transistor (MOSFET)
Example :-for n-channel enhanced-type MOSFET. Determine
I
DQ, V
GSQ,
E-MOSFET Biasing

58. An-NajahNational University
Faculty of Engineering
Electrical Engineering Department
Field-Effect Transistors (FETs)
The Metal Oxide Semiconductor Field-Effect Transistor (MOSFET)
Example :-for n-channel enhanced-type MOSFET. Determine
I
DQ, V
GSQ,
E-MOSFET Biasing