chip design flow Introduction to Chip Designchapter_6.ppt

chip design flow

1. Chapter 6 -- Introduction to Sequential Devices

2. The Sequential Circuit Model
x
1
z
1
x
n
z
m
(a )
y
1
Y
r
y
r
Y
1
M e m o ry
C o m b in atio n a l
lo g ic
C o m b in atio n a l
lo g ic
(b )
x
1
z
1
x
n
z
m
Figure 6.1

3. State Tables and State Diagrams
P re se n t sta te
In p u t
(a ) (b )
In p u t/o u tp u t
P re se n t sta te
N ex t sta te
y
x
Y /z
x /z
N ex t
sta te/o u tp u t
y
Y
Figure 6.2

4. Sequential Circuit Example
1 /1
P r e se n t
s ta te
A C
B D
( a )
( b )
0 1
0 /1
0 /0
1 /1
x/z
I n p u t x
0 /0
1 /0 1 /0
D/0
B/1
C/ 1
A/0
C/1
A/0
D/0
B/1
A
B
C
D
0 /1
Figure 6.3

5. Latch and Flip-flop Timing
S e t
R e se t
(a )
( b )
C lo c k
Q
S e t
R e se t
Q
Figure 6.4

6. TTL Memory Elements

7. Set Latch
(a ) (b ) (c) (d )
0
0
0
S
Q
0
0
0
1
S
Q1
1
1
S
Q0
1
Figure 6.5

8. Reset Latch
( d ) ( e )
10
Q
R
R = 0
Q
Q
1
( c )
10
Q
R = 1
1
( b )
01
Q
R = 0
0
( a )
0
1
Q
0
0
0
1
0
S
Figure 6.6

9. Set-Reset Latch (SR latch)
(a )
( c ) (d )
S
Q
N1
N2 Q
(b )
S
Q
N1
N2 Q
R
S
R
Q
QN1
N2
Q
Q
S
R
Figure 6.7

10. NAND SR Latch
( b )
( d )
QR = 0 R = 1
S = 1S = 0
Q
( a )
Q
R
R
S
S
QN1
N2
( c )
Q
R
S
Q
Q
Q
R
S
( e )
Q
Q
R
S
Figure 6.8

11. Set-Reset Latch Timing Diagram
( a )
S
R
Q
S e t R e s e t I ll e g a l
i n p u t s
U n k n o w n v a l u e s
Q
S e t
( b )
S
R
Q
S e t R e s e t I ll e g a l
i n p u t s
U n k n o w n v a l u e s
Q
S e t
Figure 6.9

12. SR Latch Propagation Delays
S
R
Q
t
P LH
(S to Q)
t
P LH
(N 2 )
t
P H L
(N 1 )
t
P H L
(R to Q)
t
P H L
(N 2 )
t
P LH
(N 1 )
Q

13. SR Latch Characteristics
S R Q Q*
( a )
E x c ita tio n
in p u ts
P r e se n t
sta te
N ex t
sta te
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
0
1
1


N o c h a n g e
R ese t
S e t
N o t a llo w e d
Q
S R
0
0 0 0 1 1 1 1 0
R
Q
0 Ð 1
1 0 Ð 1
S
0
1
1 0
0 1
0d d0
( b )
S R
0 1
(c )
Figure 6.11
Q* = S + RQ

14. SN74279 Latch with Two Set Inputs
(b)(a)
Q
Q
R
Q
R
S1
S2
S1
S2
Figure 6.12

15. Gated SR Latch
( a )
C* R
S
C
R
S
R
Q
Q
( b )
( c )
Q
Q
C* S
S
C
R
S
R
Q
Q
S
C
R
S
C
R
Q
Q
( d )
Figure 6.13

16. Gated SR Latch Characteristics
E x c ita tio n
in p u ts
S R
N e x t
sta te
Q*
0
0
1
1
1
1
1
1
1
1

´
0
0
0
0
1
1
1
1
E n a b le
in p u ts
C

´
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
1
1


H o ld
N o c h a n g e
R e se t
S e t
N o t a llo w e d
P re se n t
sta te
Q
1 1 0
1 0 1
0d d, 1 0d 0d d, 1d0
(a ) (b )
C S R
0 1
Figure 6.14
Q* = SC + RQ + C Q

17. Delay Latch (D latch)
( b )
Q
Q
D
C
S
R
S R la t c h
( c )
Q
Q
D
C
S
R
S R la t c h
D
C
Q
Q
( a )
Figure 6.15

18. D Latch Characteristics
E x c ita tio n
in p u t
D
N ex t
sta te
Q*
0
0
1
1
1
1
E n a b le
in p u t
C

´
0
0
1
1
0
1
0
1
0
1
0
1
0
0
1
1
H o ld
S to re 0
S to re 1
P re sen t
sta te
Q
1 1
1 0
0d, 1 0 0d, 1 1
(a ) (b )
C D
0 1
Figure 6.16
Q* = DC + CQ

19. D Latch Timing Diagram
Q
D
C
E n a b le d
H o ld
E n a b led
H o ld
E n a b led
Figure 6.17

20. D Latch Timing Constraints
t
w
M in im u m e n a b le
p u lse w id th
Q
D
C
D m a y n o t
c h a n g e S e tu p tim e
v io la tio n
H o ld tim e
v io la tio n
t
s u
(setu p )
t
s u
U n k n o w n sta te
t
h
(h o ld ) t
h
Figure 6.18

21. The SN74LS75 D Latch
C D
C Q
Q Q*
( a )
D
C
Q
Q
D
C
Q
Q
( b )
( c )
D
C
Q
Q
D
C
( d )
0
0
1
0
1
0
Dt
Figure 6.19

22. Propagation Delays and Time Constraints
for the SN74LS75

23. Hazard-Free D Latch, the SN74116
D
C
Q
D
C
Q
C1
C2
P R E ( o r S)
C L R ( o r R)
Q
( c )
D
Q
Q
( d )
1
1 1 1
( a )
Q
D
C
1
1 1 1
( b )
Figure 6.20
Q* = DC + CQ + DC

24. Master-Slave SR Flip-flop
S
C
R
S
C
R
S
C
R
Q
M
M a s te r S l a v e
( c )
( d )
M a s te r
S l a v e
Q
M
F l i p -fl o p o u t p u t c a n c h a n g e
t
s u
( s e t u p )
S a n d R m a y
n o t c h a n g e
t
w
C lo w p u l s e w id th
( m a s t e r e n a b l e d )
t
w
C h i g h p u l s e w i d t h
( s l a v e e n a b l e d )
Q
g a t e dh o ld g a t e d h o ld g a t e dh o ld g a t e dh o ld
h o ld g a t e d h o ld g a t e dh o ld g a t e dh o ld g a t e d
t
h
( h o ld )
S
C
R
Q
Q
Q
Q
S
C
R
Q
Q
S
C
R
Q
Q
( a ) ( b )
( c l o c k )
Figure 6.20

25. SR Master-Slave Flip-Flop Characteristics
R CQ Q*
0
0
1
1
0
1
0
1
0
1
0
0
N o ch a n g e
R eset 1 0
0 1
0d 0d
(b )
S R
0 1
S
0
0
0
0
0
0
1
1
0
1
0
1
1
1


S et
(a )
1
1
1
1
N ot a llo w ed
Figure 6.22
Q* = S + RQ

26. Master-Slave D Flip-Flop
D
C
M a ste r S la v e
Q
M
D
C
Q
Q
Q
Q
D
C
Q
Q
D
C
Q
Q
(a ) (b )
(clo ck )
Figure 6.23

27. Master-Slave D Flip-Flop Characteristics
M S
D CQ Q*
0
0
1
1
0
1
0
1
0
0
1
1
S t o r e 0
S t o r e 1
( a )
( b )
( c )
D
Q
M
E n a b l e d : M S M S M S M
Q = Q
S
C
10 D
1
0
 
Figure 6.24
Q* = D

28. Pulse-Triggered JK Flip-Flop Characteristics
K CQ Q*
0
0
1
1
0
1
0
1
0
1
0
0
H o ld
R e set
1d
d1
0d d0
(b )
J R
0 1
J
0
0
0
0
0
0
1
1
0
1
0
1
1
1
1
0
S et
(a )
1
1
1
1
T o g g le
Q
J K
0
0 0 0 1 1 1 1 0
0
1
K
0 1 1
1 0 0 1
J
Q
(c )
Figure 6.25
Q* = KQ + JQ

29. Pulse-Triggered JK Flip Realization
D
C
Q
Q
J
C
K
Q
Q
K
J
C
Q*
Q
Q
K Q
J Q
(a )
(b)
Figure 6.26

30. The SN7476 Dual Pulse-Triggered JK Flip-Flop
J
C
K
(a )
Q
Q
( b )
P R E
C L R
1 P R E
2 P R E
1 C L K
1 C L R
2 C L K
2 C L R
1K
1J
2J
1K
1J
S
R
C1
1Q
1Q
2Q
2Q
(2 )
(4 )
(1 )
(1 6 )
(3 )
(7 )
(9 )
(6 )
(1 2 )
(8 )
(1 5 )
(1 4 )
(1 1 )
(1 0 )
2K
Q
Q
'7 6
Figure 6.27

31. SN7474 Dual Positive-Edge-Triggered D Flip-Flop
( b )
( c )
P R E
C L R
1 P R E
2 P R E
1D
1 C L R
2 C L K
2 C L R
1 C L K
1D
S
R
C1 1Q
1Q
2Q
2Q
( 4 )
( 3 )
( 2 )
( 1 )
( 1 0 )
( 1 1 )
( 1 2 )
( 1 3 )
( 5 )
( 6 )
( 9 )
( 8 )
2D
Q
Q
Q
Q
( a )
Q
Q
P R E
D
C L R
C L K
' 7 4
Figure 6.28

32. SN7474 Excitation Table
Inp u ts O u tpu ts
M o deP R EC L R D C L K Q Q
L
H
L
H
H
H
H
L
L
H
H
H



H
L






L
H
L
H
H
L
Q
0
L
H
H
L
H
Q
0
S et
C lea r
N o t a llow ed
C lock ed o pera tion
C lock ed o pera tion
H o ld
Figure 6.29

33. SN7474 Flip-Flop Timing Specifications
D
C
Q
D sh o u ld b e s ta b le
t
s u
t
h
t
s u
t
h
t
P H L
t
P LH
T o O u tp u t Q
fr o m : D e la y P a r a m e te rV a lu e ( n s)
( a )
t
P LH
t
P H L
t
P LH
t
P H L
t
P LH
t
P H L
2 5
4 0
2 5
4 0
2 5
4 0
C lo c k
P R E
C L R
I n p u t
P in C o n str a in t
M in im u m
V a lu e ( n s)
t
s u
t
h
t
w
lo w
t
w
h ig h
t
w
lo w
t
w
lo w
2 0
5
3 0
3 7
3 0
3 0
D
D
C lo c k
C lo c k
C L R
P R E
( b )
( c )
Figure 6.30

34. SN74175 Positive-Edge-Triggered D Flip-Flop
C L E A R
C K
1D D 1Q
( 2 )
Q
Q
( 3 )
( 4 )
1Q
C L E A R
C K
2D D 2Q
( 7 )
Q
Q
( 6 )
( 5 )
2Q
C L E A R
C K
3D D 3Q
( 1 0 )
Q
Q
( 1 1 )
( 1 2 )
3Q
C L E A R
C K
4D D 4Q
( 1 5 )
Q
Q
( 1 4 )
( 1 3 )
4QC L O C K
C L E A R
( 9 )
( 1 )
( a )
Figure 6.31 (a)

35. SN74273 Positive-Edge-Triggered D Flip-Flop
C L O C K
C L E A R
R
C1
1D
( 3 )
1D
( 1 1 )
1Q
( 2 )
R
C1
2D
( 4 )
1D
2Q
( 5 )
R
C1
3D
( 7 )
1D
3Q
( 6 )
R
C1
4D
( 8 )
1D
4Q
( 9 )
R
C1
5D
( 1 3 )
1D
5Q
( 1 2 )
R
C1
6D
( 1 4 )
1D
6Q
( 1 5 )
R
C1
7D
( 1 7 )
1D
7Q
( 1 6 )
R
C1
8D
( 1 8 )
1D
8Q
( 1 9 )
( 1 )
( b )
Figure 6.31 (b)

36. SN74LS73A Edge-Triggered JK Flip-Flop
Logic Diagram
Q
K
J
Q
C L R
C L K
Figure 6.32 (a)

37. SN74LS73A Logic Symbols
J
C
K
Q
Q
(b )
C L
R
(c )
1J
2J
1
K
1C L
R
2C L
K
2C L
R
1C L
K
1
K
1J
R
C
1 1Q
1Q
2Q
2Q
(1 4 )
(1 )
(3 )
(2 )
(7 )
(5 )
(1 0 )
(6 )
(1 2 )
(1 3 )
(9 )
(8 )2
K
'L S 7 3 A
Figure 6.32 (b) and (c)

38. SN74276 and SN74111 Edge-Triggered
JK Flip-Flops
'1 1 1
(d )
1J
2J
1K
1C L R
2C L K
2C L R
1C L K
1
K
1J
R
C
1
1Q
1Q
2Q
2Q
(7 )
(6 )
(9 )
(1 0 )
2K
P R E
1K
1J
1C L K
2J
2K
C L K
2C L K
3K
3J
3C L K
4J
4K
4C L K
(1 1 )
(1 )
(2 )
(3 )
(4 )
(9 )
(8 )
(7 )
(1 2 )
(1 3 )
(1 4 )
(1 9 )
(1 8 )
(1 7 )
1Q
2Q
3Q
4Q
(5 )
(6 )
(1 5 )
(1 6 )
S
R
1JC
11
K
S1P R E
(2 )
(4 )
(5 )
(1 )
(3 )
(1 4 )
(1 2 )
(1 1 )
(1 5 )
(1 3 )
2P R E
(e )
'2 7 6
Figure 6.32 (d) and (e)

39. Negative-Edge-Triggered T Flip-Flop
P R E
C L R
Q
Q
T
(a) (b )
V
C
C
P R E
C L R
Q
Q
C
J
K
Figure 6.33

40. Edge-Triggered T Flip-Flop Characteristics
0
1
1
0
T o ggle
T o ggle
1
1
0 0
(a) (b)
T
0 1
Q Q*T
Figure 6.34
Q* = Q

41. Clocked T Flip-Flop
P R E
C L R
Q
QC
(a ) (b )
P R E
C L R
Q
Q
C
J
T
T
K
Figure 6.35

42. Excitation Table for Clocked T Flip-Flops
TQ CQ*
0
0
1
1
0
1
0
1
0
1
1
0




Hold
Toggle
Figure 6.36
Q* = TQ + TQ

43. The Clocked T Flip-Flop Timing Diagram
C lo ck
C lo c k
(a )
(b )
Q
Q
Dt
T
c
T
c
T
Q
Q
Q
Q

T
Figure 6.37

44. Summary of Latch and Flip-Flop Characteristics

45. SE555 Precision Timing Module
V
CC
R e se t
C o n tr o l
C o m p a r a to r
Q
R1
R
R
T h r e sh o ld
T r ig g e r
G r o u n d
Q1
O u tp u t
D isc h a rg e
C1
S E 5 5 5
R
S
R
C2
1
Figure 6.38

46. Astable Operation of The SE555
R
A
R
B
C
S E 5 5 5
2
6
7
4
5 8
3
V
C C
R
L
0 .0 1mF
1
C o n t
O u t
R E S E T
D IS C H
T H R E S
S q u a re w a v e
T R IG
G N D
V
C C
Figure 6.39

47. Monostable (One shot) Device Realization
R
A
C
S E 5 5 5
2
6
7
4
5 8
3
VC C
R
L
0 .0 1 mF
1
C o n t
O u t
R E S E T
D I S C H
T H R E S
T R I G
G N D
V
C C
T r i g g e r
O u t p u t
3 .3 -m s p u lse i f
R
A
= 3 kOh m a n d C = 1 mF
Figure 6.40

48. PROM-based Sequential Circuits
y
P R O M 1
N e x t
s t a te
I n p u t
x
R e g i s t e r
O u t p u t
z
( b ) ( c )
P r e s e n t s t a te
Y/z
P R O M
x
A d d r e s s
y
P R O M 1
Y
P R O M 2
z
C o n t e n ts
N e x t s t a te /
o u tp u t
P R O M 2
( a )
C l o c k
P r e s e n t
s t a t e
I n p u t
x
y
Y
Figure 6.41

49. PROM-based Sequential Circuit Example
1
1
0
0
0
1
0
1
0
0
0
0
1
1
1
1
D
C lo c k
0 0
0 1
1 0
1 1
0 1
x
Y
2
Y
1
/z
xy
2
y
1
Y
2
Y
1
z
1 0 /1
1 1 /0
0 1 /1
0 0 /0
0 0 /1
1 1 /1
0 0 /0
1 1 /0
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1
1
0
0
0
1
0
1
0
1
1
0
0
1
0
1
1
0
1
0
1
1
0
0
( c )
x
z
y
2
y
1
Q
0
1
2
3
4
5
6
7
0
1
1
0
0
1
0
1
1
0
1
0
1
1
0
0
( b )
( a )
Y
2
Y
1
Q
C C
D
y
2
y
1
Figure 6.41

50. Prime Number Sequencer
S N 7 4 2 7 3
( 8 D flip -fl o p s )
0
1
2
3
4
5
6
7
8
9
1 0
1 1
1 2
1 3
1 4
2 5 1
2 5 2
2 5 3
2 5 4
2 5 5
1D2D3D4D5D6D7D8D
1Q2Q3Q4Q5Q6Q7Q8Q
C lo c k
C l o c k
2 5 6 x 8 P R O M
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
1
1
0
0
0
1
1
0
1
0
0
1
0
1
1
0
0
1
1
1
1
1
1
1
0
Figure 6.43