Circuito eletrônico da placa J44 4G_820-3536.pdf

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DESCRIPTION REFERENCE DES BOM OPTIONQTYPART NUMBER CRITICAL
Apple Inc.
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
8
1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%.
IV ALL RIGHTS RESERVED
II NOT TO REPRODUCE OR COPY IT
3
B
7
BRANCH
DRAWING NUMBER SIZE
D
SHEET
R
DATE
D
A
C
PAGE
A
C
3456
D
B
87 6 5 4 21
12
APPD
CK
3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.
2. ALL CAPACITANCE VALUES ARE IN MICROFARADS.
DRAWING TITLE
DESCRIPTION OF REVISIONREV ECN
REVISION
PROPRIETARY PROPERTY OF APPLE INC.
Schematic / PCB #’s
08/20/2013
J44 MLB-4GB SCHEMATIC
ALIASES RESOLVED
1 OF 78
<PART_DESCRIPTION>
<SCH_NUM>
<ECODATE><ECN><REV> <ECO_DESCRIPTION>
1 OF 120
<BRANCH>
<E4LABEL>
LPC+SPI Debug Connector45
08/12/201361
J44
Fan44
08/12/201360
J44
Thermal Sensors43
08/12/201358
J44
Power Sensors: Extended42
08/12/201356
J44
Power Sensors: Load Side41
08/12/201355
J44
Power Sensors: High Side40
08/12/201354
J44
SMBus Connections39
08/12/201353
J44
SMC Project Support38
08/12/201352
J44
SMC Shared Support37
08/12/201351
J44
SMC36
08/12/201350
J44
KEYBOARD/TRACKPAD (2 OF 2)35
08/12/201349
J44
KEYBOARD/TRACKPAD (1 OF 2)34
08/12/201348
J44
External A USB3 Connector33
08/12/201346
J44
Camera 2 of 232
08/12/201340
J44
Camera 1 of 231
08/12/201339
J44
SSD Connector30
08/12/201337
J44
WIRELESS SUPPORT29
08/12/201335
J44
DDC Crossbar28
08/12/201334
J44
Thunderbolt Connector B27
08/12/201333
J44
Thunderbolt Connector A26
08/12/201332
J44
Thunderbolt Mobile Support25
08/12/201330
J44
Thunderbolt Host (2 of 2)24
08/12/201329
J44
Thunderbolt Host (1 of 2)23
08/12/201328
J44
DDR3 Termination22
04/02/201327
J44_YONAS-4GB
DDR3 SDRAM BANK B (RANK 0)21
MASTER25
MASTER
DDR3 SDRAM Bank A (Rank 0)20
MASTER23
MASTER
DDR3 VREF MARGINING19
08/12/201322
J44
Project Chipset Support18
08/12/201320
J44
Chipset Support17
08/12/201319
J44
CPU/PCH Merged XDP16
08/12/201318
J44
PCH GPIO/MISC/LPIO15
08/12/201316
J44
PCH PCIe/USB/LPC/SPI/SMBus14
08/12/201315
J44
PCH PM/PCI/GFX13
08/12/201314
J44
PCH Audio/JTAG/SATA/CLK12
08/12/201313
J44
PCH Decoupling11
08/12/201312
J44
CPU Decoupling10
08/12/201310
J44
CPU/PCH GROUNDS9
08/12/20139
J44
CPU/PCH POWER8
08/12/20138
J44
CPU DDR3/LPDDR3 Interfaces7
08/12/20137
J44
CPU Misc/JTAG/CFG/RSVD6
08/12/20136
J44
CPU GFX/NCTF/RSVD5
08/12/20135
J44
PD Parts4
08/12/20134
J44
BOM Configuration3
01/03/20133
J44
BOM Configuration2
08/20/20132
J44
120
78 Reference
08/12/2013
J44
118
77 Project Specific Constraints
08/12/2013
J44
117
76 SMC Constraints
08/12/2013
J44
116
75 Camera Constraints
08/12/2013
J44
115
74 TBT,DP,HDMI Constraints
08/12/2013
J44
114
73 Memory Constraints
01/03/2013
J44
113
72 PCH Constraints
08/12/2013
J44
112
71 USB Constraints
08/12/2013
J44
111
70 CPU & PCIe Constraints
08/12/2013
J44
110
69 PCB Rule Definitions
08/12/2013
J44
104
68 Functional / ICT Test
08/12/2013
J44
103
67 Memory Bit/Byte Swizzle
01/03/2013
J44
102
66 Signal Aliases
MASTER
MASTER
100
65 Power Aliases
08/12/2013
J44
97
64 Display Mux: HDMI vs DP
08/12/2013
J44
95
63 RIO Connector
08/12/2013
J44
83
62 eDP Display Connector
08/12/2013
J44
81
61 Power Control
08/12/2013
J44
80
60 Power FETs
08/12/2013
J44
78
59 Misc Power Supplies
08/12/2013
J44
77
58 LCD AND KBD BKLT DRIVER
08/12/2013
J44
76
57 1.05V S0 Power Supply
08/12/2013
J44
75
56 5V / 3.3V Power Supply
08/12/2013
J44
74
55 1.35V DDR3 SUPPLY
08/12/2013
J44
73
54 CPU VR12.5 VCC Power Stage
08/12/2013
J44
72
53 CPU VR12.6 VCC Regulator IC
08/12/2013
J44
71
52 PBus Supply & Battery Charger
08/12/2013
J44
70
51 DC-In & Battery Connectors
08/12/2013
J44
66
50 AUDIO: JACK TRANSLATORS
08/12/2013
J44
65
49 AUDIO: JACK
08/12/2013
J44
64
48 AUDIO: SPEAKER AMP
08/12/2013
J44
63
47 AUDIO:CODEC, DIGITAL
08/12/2013
J44
Contents SyncPage
Date(.csa)
Table of Contents1
01/13/20121
D2_KEPLER
SyncContentsPage
(.csa) Date
62
46 AUDIO:CODEC, ANALOG
08/12/2013
J44
SCHEM,MLB-4GB,J44051-0052 CRITICAL 1 SCH
820-3536 CRITICAL 1 PCBPCBF,MLB-4GB,J44www.rosefix.com

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DESCRIPTION REFERENCE DES BOM OPTIONQTYPART NUMBER CRITICAL
TABLE_ALT_ITEM
PART NUMBER
ALTERNATE FORPART NUMBER BOM OPTION REF DES COMMENTS:
TABLE_ALT_HEAD
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
DESCRIPTION REFERENCE DES BOM OPTIONQTYPART NUMBER CRITICAL
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
BOM OPTIONSBOM GROUP
TABLE_BOMGROUP_HEAD
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
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NOTICE OF PROPRIETARY PROPERTY:
PAGE
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PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
D
SIZEDRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
PSOC
EFI ROM
SMC
Programmables (All Builds)
TBT
Module Parts
Alternate Parts
BOM Groups
BOM Configuration
SYNC_DATE=08/20/2013SYNC_MASTER=J44
128S0329128S0311 ALL NEC alt to Sanyo
ALL138S0739 138S0706 Samsung alt to Murata
Epson alt to NDK197S0480197S0481ALL
Cyntec alt to Vishay152S1645 ALL152S0461
Sanyo 2nd Factory alt128S0264 ALL128S0364
353S1286
Maxim alt to MicrochipALL353S3452
NXP Alt for Diodes Single376S1128376S1089 ALL
LOADISNS,OTHERISNS,DDRISNS,TBTISNS,BMONISNSENGISNS
ALTERNATE,COMMON,J44_COMMON1,J44_COMMON2,J44_COMMON3,J44_COMMON4,J44_PROGPARTSJ44_COMMON
J44_COMMON1 TBTHV:P15V,SKIP_5V3V3:AUDIBLE,SPI:DUAL_IO
J44_COMMON2 EDP,EDP_LS_CAP,CAMERA_3V3:S0,CAM_WAKE:NO,CAM_XTAL:NO,MEM_ODT:PU,VCORE_FETS
J44_COMMON3 XDP,LPCPLUS,BKLT:PROD,CPUTHRM:ALRT,LOADRC:NO,OTHERRC:NO,DDRRC:NO,TBTRC:NO,BMONRC:NO
SMC_PROG:PVT,BOOTROM:PVT,TBTROM:PVT,TPAD_PSOC:PROGJ44_PROGPARTS
376S1194 2 Q7310,Q7320 CRITICAL VCORE_FET:VSHYMOSFET,N-CH,30V,15.3A,12M,8P 3.3X3.3 DFN
338S1186 U3900 CRITICAL1 IC,BCM15700A2,S2 PCIE CAMERA PROCESSOR
HSWULT,SR188,PRQ,C0,2.8,28W,2+3,4M,BGA
CPU_HSW:2.8GCRITICALU0500337S4598 1
CPU_HSW:2.4GU0500 CRITICAL337S45961 HSWULT,SR18A,PRQ,C0,2.4,28W,2+3,3M,BGA
353S3812 TI alt to NXPALL353S3814
353S4069
ALL353S4068 NXP alt to TI DP Mux U9750
ALL353S4070 353S4069 Pericom alt to TI DP Mux U9750
Cyntec alt to TFTALL107S0248107S0250
Rohm alt to Vishay127S0162 ALL127S0164
Cyntec alt to TFT107S0255 ALL107S0240
TDK alt to Toko152S1876 ALL152S1804
Epson alt to TXC
ALL197S0545 197S0544
NDK alt to TXC197S0542 197S0544 ALL
Samsung alt to Murata (BKLT)ALL138S0846 138S0811
Samsung alt to Murata (BKLT)ALL138S0803 138S0639
138S0843
ALL138S0674 Samsung alt to Murata (BKLT)
Cyntec alt to TFT107S0241107S0254 ALL
Renesas alt to VishayALL376S1180 376S0761
376S0855376S1032
ALL Toshiba alt for Diodes Dual
138S0724138S0725 ALL Samsung alt to Murata
Diodes alt to Fairchild376S1053 376S0604 ALL
U2800
CRITICAL1338S1247 IC,TBT,FR-4C,A0,PRQ,CIO,SR1JC,FCBGA288
CPU_HSW:2.6GU0500 CRITICAL337S45971 HSWULT,SR189,PRQ,C0,2.6,28W,2+3,3M,BGA
376S1193 Q7311,Q7321 VCORE_FET:VSHYCRITICAL2 MOSFET,N-CH,30V,22A,6.0M,8P 3.3X3.3 DFN
Q7310,Q7320MOSFET,N-CH,25V,30A,9.6M,8P 3.3X3.3 DFN376S0964 VCORE_FET:RENCRITICAL2
Q7311,Q7321 CRITICAL376S1104MOSFET,N-CH,25V,30A,6.1M,8P 3.3X3.3 DFN2 VCORE_FET:REN
EPROM,FALCON RIDGE (V13.7) J44 TBTROM:PVT341S3918 1 CRITICALU2890
SMC_PROG:PVTIC,SMC-B1,EXT(V2.16F39),PVT,J44341S3922 CRITICAL U50001
BOOTROM:PVTIC,EFI ROM (V0116),PVT,J44341S3924 1 CRITICALU6100
IC,TRKPD/KYBD PSOC,CU ONLY(V224) J441 CRITICAL341S3862U4801 TPAD_PSOC:PROG
ALL NXP Alt for Diodes Dual376S0855376S1129
376S1080
Diodes alt to On Semi376S0820 ALL
Panasonic alt to TDKALL155S0583155S0667
ONsemi alt to ToshibaALL311S0649 311S0541
ALL128S0392128S0436 Kemet alt to Sanyo
<BRANCH>
<SCH_NUM>
<E4LABEL>
2 OF 120
2 OF 78www.rosefix.com

Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
124578
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NOTICE OF PROPRIETARY PROPERTY:
PAGE
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PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
D
SIZEDRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
BOM OPTIONSBOM NAMEBOM NUMBER
TABLE_BOMGROUP_HEAD
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
PART NUMBER
ALTERNATE FORPART NUMBER BOM OPTION REF DES COMMENTS:
TABLE_ALT_HEAD
TABLE_ALT_ITEM
TABLE_BOMGROUP_ITEM
BOM OPTIONSBOM GROUP
TABLE_BOMGROUP_HEAD
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
BOM OPTIONSBOM GROUP
TABLE_BOMGROUP_HEAD
DESCRIPTION REFERENCE DES BOM OPTIONQTYPART NUMBER CRITICAL
DESCRIPTION REFERENCE DES BOM OPTIONQTYPART NUMBER CRITICAL
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
BOM OPTIONSBOM GROUP
TABLE_BOMGROUP_HEAD
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
DESCRIPTION REFERENCE DES BOM OPTIONQTYPART NUMBER CRITICAL
Alternate Parts
DRAM PARTS
DRAM SPD Straps
NOTE: 1866 PARTS BEING STRAPPED TO RUN AT 1600
13" MBP VARIABLE BOM GROUPS
DEVELOPMENT/BASE BOM
SUB-BOMS
DRAM SPD Straps
DRAM Parts
BOM Variants
J44_COMMON685-0054 COMMON,MLB-4GB,J44
985-0053 DEV,MLB-4GB,J44 XDP_CONN
CAMDRAM:MICRON CAMDRAM_TYPE:MICRON
IC,SDRAM,4GBIT,DDR3L-1600,HUMA,96B FBGA333S0700 CAMDRAM_TYPE:HYNIX_H1 CRITICALU4000
333S0704
IC,SDRAM,4GBIT,DDR3L-1600,DIE F,96B FBGA U40001 CAMDRAM_TYPE:ELPIDACRITICAL
1 U4000333S0698
IC,SDRAM,4GBIT,DDR3L-1600,REV E,96B FBGA CAMDRAM_TYPE:MICRONCRITICAL
CAMDRAM_TYPE:ELPIDACAMDRAM:ELPIDA
CAMDRAM_TYPE:HYNIX_HCAMDRAM:HYNIX_H
639-5275 PCBA,MLB-4GB,2.8G,4GB-HYNIX,J44 BASE_BOM,CPU_HSW:2.8G,RAM_4G_HYNIX_H,CAMDRAM:HYNIX_H
VCORE_FET:VSHYVCORE,FET,VSHY,J44685-0074
VCORE_FETSVCOREFETSVCORE,FET,VSHY,J44685-0074 1 CRITICAL
985-0053
DEVEL_BOMCRITICALDEVEL1J44 MLB DEVEL BOM
685-0054 CRITICAL BASE1 BASE_BOMJ44 MLB COMMON BOM
SMCBOARDID:8J44_COMMON4
RAM_4G_ELPIDA_1866 4G_ELPIDA_1866,RAMCFG3:L,RAMCFG2:L,RAMCFG1:L,RAMCFG0:L,PPDDR:1V5
RAM_4G_HYNIX_H_1866 4G_HYNIX_H_1866,RAMCFG3:L,RAMCFG2:L,RAMCFG1:L,RAMCFG0:H,PPDDR:1V5
RAM_4G_MICRON_1866 4G_MICRON_1866,RAMCFG3:L,RAMCFG2:L,RAMCFG1:H,RAMCFG0:L,PPDDR:1V5
RAM_4G_MICRON 4G_MICRON,RAMCFG3:L,RAMCFG2:L,RAMCFG1:H,RAMCFG0:L,PPDDR:1V35
RAM_4G_HYNIX_H 4G_HYNIX_H,RAMCFG3:L,RAMCFG2:L,RAMCFG1:L,RAMCFG0:H,PPDDR:1V35
4G_ELPIDA,RAMCFG3:L,RAMCFG2:L,RAMCFG1:L,RAMCFG0:L,PPDDR:1V35RAM_4G_ELPIDA
4G_MICRON_1866CRITICALIC,SDRAM,4GBIT,256MX16,DDR3-1866,REV E,96FBGA U2300,U2320,U2340,U2360,U2500,U2520,U2540,U25608333S0720
4G_ELPIDA_1866CRITICALIC,SDRAM,4GBIT,256MX16,DDR3-1866,F DIE,96FBGA333S0715 U2300,U2320,U2340,U2360,U2500,U2520,U2540,U25608
4G_HYNIX_H_1866CRITICALIC,SDRAM,4GBIT,256MX16,DDR3-1866,HUMA,96FBGA U2300,U2320,U2340,U2360,U2500,U2520,U2540,U25608333S0717
4G_MICRONCRITICALIC,SDRAM,4GBIT,256MX16,DDR3-1600,REV E,96FBGA333S0698 8 U2300,U2320,U2340,U2360,U2500,U2520,U2540,U2560
4G_ELPIDACRITICALIC,SDRAM,4GBIT,256MX16,DDR3-1600,F DIE,96FBGA333S0704 8 U2300,U2320,U2340,U2360,U2500,U2520,U2540,U2560
4G_HYNIX_HCRITICALIC,SDRAM,4GBIT,256MX16,DDR3-1600,HUMA,96FBGA333S0700 8 U2300,U2320,U2340,U2360,U2500,U2520,U2540,U2560
RENESAS ALT TO VISHAY685-0074685-0075 ALL
639-5272 BASE_BOM,CPU_HSW:2.6G,RAM_4G_HYNIX_H,CAMDRAM:HYNIX_HPCBA,MLB-4GB,2.6G,4GB-HYNIX,J44
639-5273 PCBA,MLB-4GB,2.6G,4GB-ELPIDA,J44 BASE_BOM,CPU_HSW:2.6G,RAM_4G_ELPIDA,CAMDRAM:ELPIDA
639-5274 PCBA,MLB-4GB,2.6G,4GB-MICRON,J44 BASE_BOM,CPU_HSW:2.6G,RAM_4G_MICRON,CAMDRAM:MICRON
639-5276 PCBA,MLB-4GB,2.8G,4GB-ELPIDA,J44 BASE_BOM,CPU_HSW:2.8G,RAM_4G_ELPIDA,CAMDRAM:ELPIDA
639-5277 PCBA,MLB-4GB,2.8G,4GB-MICRON,J44 BASE_BOM,CPU_HSW:2.8G,RAM_4G_MICRON,CAMDRAM:MICRON
VCORE_FET:REN685-0075 VCORE,FET,REN,J44
639-4878 BASE_BOM,CPU_HSW:2.4G,RAM_4G_HYNIX_H,CAMDRAM:HYNIX_HPCBA,MLB-4GB,2.4G,4GB-HYNIX,J44
639-4879 BASE_BOM,CPU_HSW:2.4G,RAM_4G_ELPIDA,CAMDRAM:ELPIDAPCBA,MLB-4GB,2.4G,4GB-ELPIDA,J44
639-4880
BASE_BOM,CPU_HSW:2.4G,RAM_4G_MICRON,CAMDRAM:MICRONPCBA,MLB-4GB,2.4G,4GB-MICRON,J44
SYNC_MASTER=J44
BOM Configuration
SYNC_DATE=01/03/2013
<BRANCH>
<SCH_NUM>
<E4LABEL>
3 OF 120
3 OF 78www.rosefix.com

Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
87 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
D
SIZEDRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
SH0435 & SH0436 removed.
POGO PINS (870-2451)
SSD STANDOFF (806-5375)
USB can Ground slot
Rubber Mount Standoffs (860-1448)
THERMAL MODULE STANDOFF (860-1645) FAN STANDOFF (806-5376)
SNOWMAN-SHAPED SLOT AT RIGHT OF MEMORY BANK
ABOVE GUMSTICK CARD IN MIDDLE OF BOARD
(862-0118)
(998-5879)
Upper TBT can Ground slot
Lower TBT can Ground slot
(862-0118)
(998-3975)
(998-3975)
USB can Ground slot
(998-5879)
SNOWMAN-SHAPED SLOT AT LEFT OF MEMORY BANK
Shield Cans
RIO FLEX BRACKET BOSSES (860-2354)
Mounting Holes & Slots
(998-1195)
USB Cage TBT Cage
2.9OD1.2ID-1.35H-SM
SH0466
1
2
2.9OD1.2ID-1.35H-SM
SH0461
1
2
2.9OD1.2ID-1.35H-SM
SH0465
1
2
2.9OD1.2ID-1.35H-SM
SH0463
1
2
2.9OD1.2ID-1.35H-SM
SH0467
1
2
POGO-2.3OD-5.5H-SM-LOW-FORCE
SM
SH0432
1
THERMAL-4.50-J44-SM
SH0426
1
THERMAL-4.50-J44-SM
SH0420
1
THERMAL-4.50-J44-SM
SH0421
1
THERMAL-4.50-J44-SM
SH0427
1
5.0OD2.0H-SM
SH0440
1
3.5OD2.0H-SM
SH0443
1
3.5OD2.0H-SM
SH0444
1
POGO-2.3OD-5.5H-SM-LOW-FORCE
SM
SH0433
1
OMIT
4P5R2P3-3P5B
ZT0411
1
SHLD-J44-MLB
SM
SH0451
1
SM
SHLD-J44-MLB-T29
SH0450
1
STDOFF-4.5OD1.73H-SM-1.33-3.2
SH0441
1
OMIT
6.19X4.60-SNOWMAN
ZT0413
1
OMIT
6.19X4.60-SNOWMAN
ZT0414
1
SL-1.1X0.45-1.4x0.75
TH-NSP
TH0405
1
SL-1.1X0.45-1.4x0.75
TH-NSP
TH0404
1
SL-1.1X0.5-1.4x0.8
TH-NSP
TH0403
1
TH-NSP
SL-1.1X0.5-1.4x0.8
TH0400
1
2.9OD1.2ID-1.35H-SM
SH0460
1
2
2.9OD1.2ID-1.35H-SM
SH0462
1
2
2.9OD1.2ID-1.35H-SM
SH0464
1
2
SYNC_DATE=08/12/2013SYNC_MASTER=J44
PD Parts
<BRANCH>
<SCH_NUM>
<E4LABEL>
4 OF 120
4 OF 78www.rosefix.com

OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
BI
BI
EDP_TXN0
EDP_TXP1
EDP_TXN1
EDP_TXP0
DDI1_TXP2
DDI1_TXN2
DDI2_TXP3
DDI2_TXN3
DDI2_TXP2
DDI2_TXN2
DDI2_TXP1
DDI2_TXN1
DDI2_TXP0
DDI1_TXP1
DDI1_TXN1
DDI1_TXP0
DDI1_TXN0
DDI2_TXN0
DDI1_TXP3
DDI1_TXN3
EDP_RCOMP
EDP_DISP_UTIL
EDP_AUXN
EDP_AUXP
EDP_TXP3
EDP_TXN3
EDP_TXP2
EDP_TXN2
DDI
EDP
SYM 1 OF 19
SYM 17 OF 19
DAISY_CHAIN_NCTF
DAISY_CHAIN_NCTF
DAISY_CHAIN_NCTF
DAISY_CHAIN_NCTF
DAISY_CHAIN_NCTF
DAISY_CHAIN_NCTF
DAISY_CHAIN_NCTF
DAISY_CHAIN_NCTF
DAISY_CHAIN_NCTF
DAISY_CHAIN_NCTF
DAISY_CHAIN_NCTF
DAISY_CHAIN_NCTF
DAISY_CHAIN_NCTF
DAISY_CHAIN_NCTF
DAISY_CHAIN_NCTF
DAISY_CHAIN_NCTF
DAISY_CHAIN_NCTF
DAISY_CHAIN_NCTF
DAISY_CHAIN_NCTF
DAISY_CHAIN_NCTF
DAISY_CHAIN_NCTF
DAISY_CHAIN_NCTF
DAISY_CHAIN_NCTF
DAISY_CHAIN_NCTF
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
SPARE
SYM 18 OF 19
TP
TP
TP
TP
TP
TP
TP
TP
NC NC
NCNC
NCNC
NCNC
NCNC
NCNC
NCNC
NC
NC
NC
NC
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
87 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
D
SIZEDRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
(MUXed with HDMI
TBT Sink 1
TBT Sink 0
DDI Port Assignments:
Internal panel eDP Port Assignment:
exist between both TP’s on each corner.
daisy-chain fashion. Continuity should
NO_TEST NO_TEST
Each corner of CPU has two testpoints.
MCP Daisy-Chain Strategy:
Other corner test signals connected in
if necessary)
66
66
62 74
62 74
62 74
62 74
62 74
62 74
62 74
62 74
62 74
62 74
CRITICAL
HASWELL-ULT
BGA-TSP
OMIT_TABLE
2C+GT2
U0500
C54
B58
B55
A57
C55
C58
A55
B57
C51
C53
C49
A53
C50
B54
B50
B53
A45
B45
A43
D20
C45
A47
C47
A49
B46
B47
C46
B49
2C+GT2
HASWELL-ULT
BGA-TSP
OMIT_TABLE
CRITICAL
U0500
A3
A4
A60
A61
A62
AV1
AW1
AW2
AW3
AW61
AW62
AW63
AY2
AY3
AY60
AY61
AY62
B2
B3
B61
B62
B63
C1
C2
HASWELL-ULT
OMIT_TABLE
CRITICAL
2C+GT2
BGA-TSP
U0500
AL1
AM11
AP7
AT2
AU10
AU15
AU44
AV44
AW14
AY14
D15
F22
H22
J21
N23
R23
T23
U10
TP-P6
TP0531
1 TP-P6
TP0500
1
TP-P6
TP0510
1
TP-P6
TP0501
1 TP-P6
TP0511
1
TP-P6
TP0520
1
TP-P6
TP0521
1
TP-P6
TP0530
1
24.9
1%
MF
201
1/20W
R0530
1
2
23 74
23 74
23 74
23 74
23 74
23 74
23 74
23 74
66
66
66
66
66
66
SYNC_DATE=08/12/2013SYNC_MASTER=J44
CPU GFX/NCTF/RSVD
MCP_DC_AW3_AY3TRUE
TRUE
MCP_DC_AW3_AY3
TRUEMCP_DC_AW2_AY2
MCP_DC_AW61_AY61 TRUE
MCP_DC_B62_B63 TRUE
MCP_DC_A3_B3 TRUE
TRUE
MCP_DC_A61_B61
MCP_DC_AW62_AY62 TRUE
TRUE
MCP_DC_AW62_AY62
MCP_DC_AW61_AY61
TRUE
TRUE
MCP_DC_AW2_AY2
TRUE MCP_DC_A61_B61
MCP_DC_A3_B3TRUE
DP_INT_ML_C_P<3>
MCP_EDP_RCOMP
DP_INT_ML_C_P<1>
=DP_TBTSNK1_ML_C_N<2>
=DP_TBTSNK1_ML_C_P<2>
=DP_TBTSNK1_ML_C_N<3>
=DP_TBTSNK1_ML_C_P<1>
DP_TBTSNK0_ML_C_P<3>
DP_TBTSNK0_ML_C_N<0>
DP_TBTSNK0_ML_C_P<2>
DP_TBTSNK0_ML_C_P<1>
DP_TBTSNK0_ML_C_N<1>
DP_TBTSNK0_ML_C_P<0>
=DP_TBTSNK1_ML_C_N<0>
=DP_TBTSNK1_ML_C_P<0>
=DP_TBTSNK1_ML_C_N<1>
=DP_TBTSNK1_ML_C_P<3>
DP_TBTSNK0_ML_C_N<2>
DP_TBTSNK0_ML_C_N<3>
PPVCOMP_S0_CPU
TP_EDP_DISP_UTIL
DP_INT_ML_C_N<0>
DP_INT_ML_C_P<0>
DP_INT_ML_C_N<1>
DP_INT_ML_C_N<2>
DP_INT_ML_C_P<2>
DP_INT_ML_C_N<3>
DP_INT_AUXCH_C_N
DP_INT_AUXCH_C_P
MCP_DC_A4
MCP_DC_A62
MCP_DC_AW1
MCP_DC_AY60
MCP_DC_B2
MCP_DC_A60
MCP_DC_AW63
MCP_DC_AV1
MCP_DC_C1_C2 TRUE
<BRANCH>
<SCH_NUM>
<E4LABEL>
5 OF 120
5 OF 78
5
5
5
5
5
5
5
5
5
5
5
5
70
8 www.rosefix.com

SM_PG_CNTL1
SM_DRAMRST*
SM_RCOMP1
SM_RCOMP2
SM_RCOMP0
PROCHOT*
PROCPWRGD
PECI
CATERR*
BPM7*
BPM6*
BPM5*
BPM4*
BPM3*
BPM2*
BPM1*
BPM0*
PROC_TDO
PROC_TDI
PROC_TRST*
PROC_TMS
PROC_TCK
PREQ*
PRDY*
PROC_DETECT*
SYM 2 OF 19
MISC
THERMAL
JTAG
DDR3
PWR
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
NC
NC
NC
BI
BI
OUT
NC
BI
BI
BI
BI
BI
BI
BI
BI
OUT
IN
IN
IN
IN
IN
OUT
OUT
OUT
VSS
VSS
RSVD
RSVD
CFG_RCOMP
RSVD
RSVD
RSVD
TD_IREF
CFG0
CFG1
CFG5
CFG4
CFG3
CFG2
CFG6
CFG10
CFG9
CFG8
CFG7
CFG11
CFG15
CFG14
CFG13
CFG12
CFG18
CFG16
CFG17
CFG19
RSVD
RSVD
RSVD_TP
RSVD_TP
RSVD_TP
RSVD_TP
EDP_SPARE
RSVD_TP
RSVD_TP
RSVD_TP
RSVD
RSVD
RSVD
PROC_OPI_COMP
RSVD
RSVD
RESERVED
SYM 19 OF 19
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
87 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
D
SIZEDRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
CFG<0> :RESET SEQUENCE STALL 1 = NORMAL OPERATION 0 = STALL AFTER PCU PLL LOCK
CFG<10>:SAFE MODE BOOT 1 = NORMAL OPERATION 0 = POWER FEATURES NOT ACTIVE
and are only for debug access
CFG<1> :PCH-LESS MODE 1 = NORMAL OPERATION 0 = PCH-LESS MODE
issue, but this locks CPU VR at 1.7V Vboot (CPU Sighting #4391569).
NOTE: Pre-ES2 CPUs have issue with Sx cycling, must set CFG<9> low to avoid
(IPU)
(IPU)
CFG<9> :NO SVID-CAPABLE VR 1 = VR SUPPORTS SVID 0 = VR DOES NOT SUPPORT SVID
(IPU)
(IPU)
(IPU)
(IPU)
(IPU)
(IPU)
(IPU)
(IPU)
(IPU)
(IPU)
CFG<4> :eDP ENABLE/DISABLE 1 = DISABLED 0 = ENABLED
CFG<8> :ALLOW NOA ON LOCKED UNITS 1 = NORMAL OPERATION 0 = NOA ALWAYS UNLOCKED
(IPU)
(IPU)
(IPU)
(IPU)
(IPU)
(IPU)
(IPU)
(IPU)
(IPU)
(IPU)
(IPU)
(IPU)
(IPU)
(IPU)
(IPU)
(IPU)
(IPU)
(IPU)
(IPU)
(IPU)
(IPD)
(IPU)
These can be placed close to J1800
BGA-TSP
2C+GT2
HASWELL-ULT
OMIT_TABLE
CRITICAL
U0500
J60
H60
H61
H62
K59
H63
K60
J61
K61
N62
J62
K62
D61
E60
F63
F62
E61
E59
K63
C61
AV15
AV61
AU60
AV60
AU61
NOSTUFF
1K
5%
201
1/20W
MF
R0640
1
2
HSW_PRE_ES2
1K
5%
201
1/20W
MF
R0639
1
2
MF
1/20W
201
5%
1K
NOSTUFF
R0638
1
2
MF
1/20W
201
5%
1K
NOSTUFF
R0631
1
2
1K
NOSTUFF
5%
201
1/20W
MF
R0630
1
2
6 16 70
6 16 70
16 70
16 70
16 70
6 16 70
16 70
16 70
6 16 70
6 16 70
16 70
6 16 70
16 70
16 70
16 70
16 70
16 70
16 70
16 70
16 70
36 37 53 70
5%
1/20W
MF
201
62
R0610
1
2
201
5%
MF
56
1/20W
R0611
12
37 70
36 70
PLACE_NEAR=U0500.C61:12.7mm
201
MF
1/20W
5%
10K
R0620
1
2
16 70
16 70
16 70
16 70
16 70
16 70
16 70
16 70
16 70
16 70
12 16 70
16 70
16 70
16 70
16 70
PLACE_NEAR=U0500.AU61:12.7mm
MF
1/20W
201
100
1%
R0652
1
2
MF
1/20W
201
1%
PLACE_NEAR=U0500.AV60:12.7mm
121
R0651
1
2
1%
200
201
1/20W
MF
PLACE_NEAR=U0500.AU60:12.7mm
R0650
1
2
22 66
17
1%
49.9
1/20W
201
MF
R0680
1
2
CRITICAL
OMIT_TABLE
HASWELL-ULT
2C+GT2
BGA-TSP
U0500
AC60
AC62
V60
U60
T63
T62
T61
T60
AA62
AA61
U63
U62
AC63
AA63
AA60
Y62
Y61
Y60
V62
V61
V63
B43
AY15
A5
AV62
D1
D58
E1
H18
J20
N60
P20
R20
A51
AU63
AV63
B51
C62
C63
L60
W23
Y22
B12
N21
P22
201
MF
1/20W
1%
49.9
R0690
1
2
1%
1/20W
201
MF
8.25K
R0685
1
2
EDP
MF
1/20W
201
5%
1K
R0634
1
2
CPU Misc/JTAG/CFG/RSVD
SYNC_MASTER=J44 SYNC_DATE=08/12/2013
CPU_CFG<18>
CPU_CFG<1>
CPU_CFG<8>
CPU_CFG<10>
CPU_CFG<0>
CPU_PROCHOT_L CPU_PROCHOT_R_L
CPU_PECI
CPU_MEMVTT_PWR_EN_LSVDDQ
MEM_RESET_HSW_L
CPU_SM_RCOMP<1>
CPU_PWRGD
CPU_CFG<12>
CPU_CFG_RCOMP
PCH_TD_IREF
TP_MCP_RSVD_L60
XDP_BPM_L<7>
XDP_BPM_L<6>
XDP_BPM_L<5>
XDP_BPM_L<4>
XDP_BPM_L<3>
XDP_BPM_L<2>
XDP_BPM_L<1>
XDP_BPM_L<0>
XDP_CPU_TDO
XDP_CPU_TDI
XDP_CPUPCH_TRST_L
XDP_CPU_TMS
XDP_CPU_TCK
XDP_CPU_PREQ_L
XDP_CPU_PRDY_L
CPU_OPI_RCOMP
TP_MCP_RSVD_A51
TP_MCP_RSVD_C62
TP_MCP_RSVD_C63
TP_MCP_RSVD_AU63
TP_MCP_RSVD_AV63
CPU_CFG<19>
CPU_CFG<17>
CPU_CFG<16>
CPU_CFG<13>
CPU_CFG<14>
CPU_CFG<15>
CPU_CFG<11>
CPU_CFG<7>
CPU_CFG<8>
CPU_CFG<10>
CPU_CFG<6>
CPU_CFG<2>
CPU_CFG<3>
CPU_CFG<4>
CPU_CFG<5>
CPU_CFG<1>
CPU_CFG<0>
TP_MCP_RSVD_B51CPU_CFG<9>
CPU_CATERR_L
CPU_SM_RCOMP<2>
PP1V05_S0
CPU_SM_RCOMP<0>
CPU_CFG<4>
CPU_CFG<9>
<BRANCH>
<SCH_NUM>
<E4LABEL>
6 OF 120
6 OF 78
6 16 70
6 16 70
6 16 70
6 16 70
70
70
70
70
8 11 15 16 17 37 53 57 60 61
65 68
70
6 16 70
6 16 70 www.rosefix.com

BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
BI
BI
BI
BI
BI
BI
BI
BI
SA_DQ63
SA_DQ62
SA_DQ61
SA_DQ60
SA_DQ59
SA_DQ58
SA_DQ57
SA_DQ55
SA_DQ56
SA_DQ54
SA_DQ53
SA_DQ52
SA_DQ51
SA_DQ50
SA_DQ49
SA_DQ48
SA_DQ47
SA_DQ45
SA_DQ46
SA_DQ42
SA_DQ43
SA_DQ44
SA_DQ40
SA_DQ41
SA_DQ39
SA_DQ37
SA_DQ38
SA_DQ34
SA_DQ36
SA_DQ32
SA_DQ33
SA_DQ29
SA_DQ30
SA_DQ31
SA_DQ27
SA_DQ28
SA_DQ24
SA_DQ25
SA_DQ22
SA_DQ23
SA_DQ21
SA_DQ19
SA_DQ20
SA_DQ17
SA_DQ18
SA_DQ16
SA_DQ14
SA_DQ15
SA_DQ11
SA_DQ13
SA_DQ10
SA_DQ9
SA_DQ7
SA_DQ8
SA_DQ6
SA_DQ4
SA_DQ5
SA_DQ3
SA_DQ1
SA_DQ0
SA_CLK1*
SA_CLK0
SA_CLK0*
SA_DQ12
SM_VREF_DQ1
SM_VREF_CA
SM_VREF_DQ0
SA_DQ35
SA_DQ26
SA_DQ2
SA_CLK1
SA_CS0*
SA_CS1*
SA_CKE0
SA_CKE1
SA_CKE2
SA_CKE3
SA_ODT0
SA_RAS*
SA_WE*
SA_CAS*
SA_MA0
SA_MA2
SA_MA1
SA_MA3
SA_MA4
SA_MA5
SA_MA7
SA_MA6
SA_MA8
SA_MA10
SA_MA9
SA_MA12
SA_MA11
SA_MA13
SA_MA14
SA_MA15
SA_BA2
SA_BA0
SA_BA1
SA_DQSP0
SA_DQSP2
SA_DQSP1
SA_DQSP3
SA_DQSP4
SA_DQSP5
SA_DQSP6
SA_DQSP7
SA_DQSN1
SA_DQSN0
SA_DQSN2
SA_DQSN4
SA_DQSN3
SA_DQSN5
SA_DQSN6
SA_DQSN7
SYM 3 OF 19
MEMORY CHANNEL A
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
SB_DQ0 SB_DQ1
SB_DQ2
SB_DQ3
SB_DQ4
SB_DQ5
SB_CKE0
SB_DQ6 SB_CKE1
SB_DQ7 SB_CKE2
SB_DQ8 SB_CKE3
SB_DQ9
SB_DQ10 SB_CS0*
SB_DQ11 SB_CS1*
SB_DQ12
SB_DQ13 SB_ODT0
SB_DQ14
SB_DQ15 SB_RAS*
SB_DQ16
SB_WE*
SB_DQ17 SB_CAS*
SB_DQ18
SB_DQ19
SB_BA0
SB_DQ20 SB_BA1
SB_DQ21 SB_BA2
SB_DQ22
SB_DQ23
SB_MA0
SB_DQ24 SB_MA1
SB_DQ25 SB_MA2
SB_DQ26 SB_MA3
SB_DQ27 SB_MA4
SB_DQ28 SB_MA5
SB_DQ29 SB_MA6
SB_DQ30 SB_MA7
SB_DQ31 SB_MA8
SB_DQ32 SB_MA9
SB_DQ33 SB_MA10
SB_DQ34 SB_MA11
SB_DQ35 SB_MA12
SB_MA13
SB_DQ37 SB_MA14
SB_DQ38 SB_MA15
SB_DQ39
SB_DQ40
SB_DQSN0
SB_DQ41 SB_DQSN1
SB_DQ42 SB_DQSN2
SB_DQ43 SB_DQSN3
SB_DQ44 SB_DQSN4
SB_DQ45 SB_DQSN5
SB_DQ46 SB_DQSN6
SB_DQ47 SB_DQSN7
SB_DQ48
SB_DQ49
SB_DQSP0
SB_DQ50 SB_DQSP1
SB_DQ51 SB_DQSP2
SB_DQ52 SB_DQSP3
SB_DQ53 SB_DQSP4
SB_DQ54 SB_DQSP5
SB_DQ55 SB_DQSP6
SB_DQ56 SB_DQSP7
SB_DQ57
SB_DQ58
SB_DQ59
SB_DQ60
SB_DQ61
SB_DQ62
SB_DQ63
SB_DQ36
SB_CK0*
SB_CK0
SB_CK1*
SB_CK1
SYM 4 OF 19
MEMORY CHANNEL B
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
124578
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D
87 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
D
SIZEDRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
RSVD4
RSVD3
CAA4
CAA2
CAA0
CAA8
CAA9
CAB0
CAA6
CAA7
CAB7
CAA1
CAA3
LPDDR3
CAB6
CAB4
CAB1
CAB2
CAB3
CAB5
CAB8
CAB9
CAA5
LPDDR3
CAB6
CAB4
CAB1
CAB2
CAB3
CAA4
CAA2
CAA0
RSVD2
RSVD1
CAB5
CAB8
CAB9
CAA5
CAA8
CAA9
CAB0
CAA6
CAA7
CAB7
CAA1
CAA3
67 68 73
67 68 73
67 68 73
67 68 73
67 68 73
67 68 73
67 68 73
67 68 73
67 68 73
67 68 73
67 68 73
67 68 73
67 68 73
67 68 73
67 68 73
67 68 73
67 68 73
67 68 73
67 68 73
67 68 73
67 68 73
67 68 73
67 68 73
67 68 73
67 68 73
67 68 73
67 68 73
67 68 73
67 68 73
67 68 73
67 68 73
67 68 73
20 67 68 73
67 68 73
67 68 73
67 68 73
67 68 73
67 68 73
67 68 73
67 68 73
67 68 73
67 68 73
67 68 73
67 68 73
67 68 73
67 68 73
67 68 73
67 68 73
67 68 73
67 68 73
67 68 73
67 68 73
67 68 73
67 68 73
67 68 73
67 68 73
67 68 73
67 68 73
67 68 73
67 68 73
67 68 73
67 68 73
67 68 73
67 68 73
67 73
67 73
20 67 73
67 73
67 73
67 73
67 73
67 73
22
66
22 66
20 22 73
22
22
66
66
20 22 73
20 22 73
20 22 73
66
20 22 66 73
66
20 22 66 73
20 22 66 73
20 22 66 73
66
66
66
66
66
66
20 22 66 73
66
66
66
66
66
66
66
67 73
67 73
67 73
67 73
67 73
20 67 73
67 73
67 73
2C+GT2
CRITICAL
OMIT_TABLE
BGA-TSP
HASWELL-ULT
U0500
AU35
AV35
AY41
AU34
AU43
AW43
AY42
AY43
AV37
AU37
AY36
AW36
AP33
AR32
AH63
AH62
AP63
AP62
AM61
AM60
AP61
AP60
AP58
AR58
AM57
AK57
AK63
AL58
AK58
AR57
AN57
AP55
AR55
AM54
AK54
AL55
AK55
AK62
AR54
AN54
AY58
AW58
AY56
AW56
AV58
AU58
AV56
AU56
AH61
AY54
AW54
AY52
AW52
AV54
AU54
AV52
AU52
AK40
AK42
AH60
AM43
AM45
AK45
AK43
AM40
AM42
AM46
AK46
AM49
AK49
AK61
AM48
AK48
AM51
AK51
AK60
AM63
AM62
AJ61
AN62
AM58
AM55
AV57
AV53
AL43
AL48
AJ62
AN61
AN58
AN55
AW57
AW53
AL42
AL49
AU36
AY37
AP35
AW41
AU41
AR35
AV42
AU42
AR38
AP36
AU39
AR36
AV40
AW39
AY39
AU40
AP32
AY34
AW34
AP49
AR51
AP51
66
66
19 73
19 73
19 73
21 22 73
21 22 73
66
66
21 22 73
22
66
66
21 22 73
22
22 66
21 22 66 73
21 22 66 73
21 22 66 73
66
21 22 66 73
66
66
66
66
66
66
66
21 22 66 73
66
66
66
66
66
66
66
66
22
67 73
67 73
67 73
67 73
67 73
67 73
21 67 73
67 73
67 73
67 73
67 73
67 73
67 73
21 67 73
67 73
67 73
67 68 73
67 68 73
67 68 73
67 68 73
67 68 73
67 68 73
67 68 73
67 68 73
67 68 73
67 68 73
67 68 73
67 68 73
67 68 73
67 68 73
67 68 73
67 68 73
67 68 73
67 68 73
67 68 73
67 68 73
OMIT_TABLE
CRITICAL
HASWELL-ULT
2C+GT2
BGA-TSP
U0500
AL35
AM36
AU49
AM33
AN38
AM38
AL38
AK38
AY49
AU50
AW49
AV50
AM32
AK32
AY31
AW31
AY25
AW25
AV27
AU27
AV25
AU25
AM29
AK29
AL28
AK28
AY29
AR29
AN29
AR28
AP28
AN26
AR26
AR25
AP25
AK26
AM26
AW29
AK25
AL25
AY23
AW23
AY21
AW21
AV23
AU23
AV21
AU21
AV31
AY19
AW19
AY17
AW17
AV19
AU19
AV17
AU17
AR21
AR22
AU31
AL21
AM22
AN22
AP21
AK21
AK22
AN20
AR20
AK18
AL18
AV29
AK20
AM20
AR18
AP18
AU29
AY27
AW27
AW30
AV26
AN28
AN25
AW22
AV18
AN21
AN18
AV30
AW26
AM28
AM25
AV22
AW18
AM21
AM18
AP40
AR40
AK36
AV47
AU47
AK33
AR46
AP46
AP42
AR42
AR45
AP45
AW46
AY46
AY47
AU46
AL32
AM35
AK35
67 68 73
67 68 73
67 68 73
67 68 73
67 68 73
67 68 73
67 68 73
67 68 73
67 68 73
67 68 73
67 68 73
67 68 73
21 67 68 73
67 68 73
67 68 73
67 68 73
67 68 73
67 68 73
67 68 73
67 68 73
67 68 73
67 68 73
67 68 73
67 68 73
67 68 73
67 68 73
67 68 73
67 68 73
67 68 73
67 68 73
67 68 73
67 68 73
67 68 73
67 68 73
67 68 73
67 68 73
67 68 73
67 68 73
67 68 73
67 68 73
67 68 73
67 68 73
67 68 73
67 68 73
SYNC_DATE=08/12/2013SYNC_MASTER=J44
CPU DDR3/LPDDR3 Interfaces
MEM_A_DQS_N<7>
MEM_A_DQS_P<7>
MEM_A_DQ<63>
MEM_A_DQ<62>
MEM_A_DQ<61>
MEM_A_DQ<60>
MEM_A_DQ<59>
MEM_A_DQ<58>
MEM_A_DQ<57>
MEM_A_DQ<55>
MEM_A_DQ<56>
MEM_A_DQ<54>
MEM_A_DQ<53>
MEM_A_DQ<52>
MEM_A_DQ<51>
MEM_A_DQ<50>
MEM_A_DQ<49>
MEM_A_DQ<48>
MEM_A_DQ<47>
MEM_A_DQ<45>
MEM_A_DQ<46>
MEM_A_DQ<42>
MEM_A_DQ<43>
MEM_A_DQ<44>
MEM_A_DQ<40>
MEM_A_DQ<41>
MEM_A_DQ<39>
MEM_A_DQ<37>
MEM_A_DQ<38>
MEM_A_DQ<34>
MEM_A_DQ<36>
MEM_A_DQ<32>
MEM_A_DQ<33>
MEM_A_DQ<29>
MEM_A_DQ<30>
MEM_A_DQ<31>
MEM_A_DQ<27>
MEM_A_DQ<28>
MEM_A_DQ<24>
MEM_A_DQ<25>
MEM_A_DQ<22>
MEM_A_DQ<23>
MEM_A_DQ<21>
MEM_A_DQ<35>
MEM_A_DQ<26>
MEM_A_DQ<19>
MEM_A_DQ<20>
MEM_A_DQ<17>
MEM_A_DQ<18>
MEM_A_DQ<16>
MEM_A_DQ<14>
MEM_A_DQ<15>
MEM_A_DQ<11>
MEM_A_DQ<13>
MEM_A_DQ<10>
MEM_A_DQ<9>
MEM_A_DQ<7>
MEM_A_DQ<8>
MEM_A_DQ<6>
MEM_A_DQ<4>
MEM_A_DQ<5>
MEM_A_DQ<3>
MEM_A_DQ<1>
MEM_A_DQ<0>
MEM_A_DQ<12>
MEM_A_DQ<2>
MEM_B_DQ<36>
MEM_B_DQ<63>
MEM_B_DQ<62>
MEM_B_DQ<61>
MEM_B_DQ<60>
MEM_B_DQ<59>
MEM_B_DQ<58>
MEM_B_DQ<57>
MEM_B_DQ<56>
MEM_B_DQ<55>
MEM_B_DQ<54>
MEM_B_DQ<53>
MEM_B_DQ<52>
MEM_B_DQ<51>
MEM_B_DQ<48>
MEM_B_DQ<47>
MEM_B_DQ<46>
MEM_B_DQ<45>
MEM_B_DQ<43>
MEM_B_DQ<42>
MEM_B_DQ<41>
MEM_B_DQ<40>
MEM_B_DQ<39>
MEM_B_DQ<38>
MEM_B_DQ<35>
MEM_B_DQ<34>
MEM_B_DQ<33>
MEM_B_DQ<32>
MEM_B_DQ<31>
MEM_B_DQ<27>
MEM_B_DQ<26>
MEM_B_DQ<25>
MEM_B_DQ<24>
MEM_B_DQ<23>
MEM_B_DQ<22>
MEM_B_DQ<21>
MEM_B_DQ<20>
MEM_B_DQ<19>
MEM_B_DQ<18>
MEM_B_DQ<16>
MEM_B_DQ<15>
MEM_B_DQ<14>
MEM_B_DQ<13>
MEM_B_DQ<12>
MEM_B_DQ<11>
MEM_B_DQ<10>
MEM_B_DQ<9>
MEM_B_DQ<8>
MEM_B_DQ<7>
MEM_B_DQ<6>
MEM_B_DQ<5>
MEM_B_DQ<4>
MEM_B_DQ<3>
MEM_B_DQ<2>
MEM_B_DQ<1>
MEM_B_DQ<0>
MEM_B_DQ<28>
MEM_B_DQ<29>
MEM_B_DQ<30>
MEM_B_DQ<44>
MEM_B_DQ<50>
MEM_B_DQ<49>
MEM_B_DQ<37>
MEM_B_DQ<17>
MEM_B_CLK_P<0>
MEM_B_CLK_N<0>
NC_MEM_B_CLKN<1>
MEM_B_CKE<0>
NC_MEM_B_CKE<3>
MEM_B_CS_L<0>
MEM_B_ODT_CPU0
MEM_B_WE_L
MEM_B_CAS_L
=MEM_B_BA<0>
MEM_B_BA<1>
=MEM_B_A<0>
=MEM_B_A<1>
=MEM_B_A<2>
=MEM_B_A<3>
=MEM_B_A<4>
=MEM_B_A<5>
MEM_B_A<6>
=MEM_B_A<7>
=MEM_B_A<9>
=MEM_B_A<8>
=MEM_B_A<10>
=MEM_B_A<11>
=MEM_B_A<12>
=MEM_B_A<13>
=MEM_B_A<14>
NC_MEM_B_A15
MEM_B_DQS_N<0>
MEM_B_DQS_N<2>
MEM_B_DQS_N<1>
MEM_B_DQS_N<3>
MEM_B_DQS_N<5>
MEM_B_DQS_N<4>
MEM_B_DQS_N<6>
MEM_B_DQS_N<7>
MEM_B_DQS_P<1>
MEM_B_DQS_P<4>
MEM_B_DQS_P<3>
MEM_B_DQS_P<6>
MEM_B_DQS_P<5>
MEM_B_DQS_P<7>
NC_MEM_A_CKE1
NC_MEM_A_CLKN<1>
NC_MEM_A_CLKP<1>
MEM_A_CLK_P<0>
MEM_A_CKE<0>
MEM_A_CLK_N<0>
MEM_A_CKE<2>
NC_MEM_A_CKE<3>
MEM_A_ODT_CPU0
MEM_A_CS_L<0>
NC_MEM_A_CS_L1
=MEM_A_BA<0>
MEM_A_CAS_L
MEM_A_WE_L
MEM_A_RAS_L
MEM_A_BA<1>
=MEM_A_BA<2>
=MEM_A_A<0>
=MEM_A_A<3>
=MEM_A_A<2>
=MEM_A_A<1>
=MEM_A_A<5>
=MEM_A_A<4>
MEM_A_A<6>
=MEM_A_A<7>
NC_MEM_A_A15
=MEM_A_A<14>
=MEM_A_A<8>
=MEM_A_A<10>
=MEM_A_A<9>
=MEM_A_A<11>
=MEM_A_A<12>
=MEM_A_A<13>
MEM_A_DQS_N<0>
MEM_A_DQS_P<0>
MEM_A_DQS_P<1>
MEM_A_DQS_N<1>
MEM_A_DQS_N<2>
MEM_A_DQS_N<3>
MEM_A_DQS_N<4>
MEM_A_DQS_N<6>
MEM_A_DQS_N<5>
MEM_A_DQS_P<5>
MEM_A_DQS_P<6>
MEM_A_DQS_P<3>
MEM_A_DQS_P<4>
MEM_A_DQS_P<2>
CPU_DIMM_VREFCA
CPU_DIMMA_VREFDQ
CPU_DIMMB_VREFDQ
MEM_B_CKE<2>
NC_MEM_B_CLKP<1>
NC_MEM_B_CKE1
NC_MEM_B_CS_L1
=MEM_B_BA<2>
MEM_B_DQS_P<0>
MEM_B_DQS_P<2>
MEM_B_RAS_L
<BRANCH>
<SCH_NUM>
<E4LABEL>
7 OF 120
7 OF 78www.rosefix.com

VCC
VCC
VCC
VCC
VCC
VCC
VCCST
VCCST
VCCST
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD_TP
RSVD_TP
RSVD_TP
RSVD_TP
VSS
PWR_DEBUG*
VSS
VCC_SENSE
RSVD
VCC
RSVD
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
RSVD
RSVD
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VDDQ
VCCIOA_OUT
RSVD
RSVD
VIDALERT*
RSVD
VIDSOUT
VIDSCLK
VR_EN
VCCST_PWRGD
VR_READY
VCCIO_OUT
RSVD
HSW ULT POWER
SYM 12 OF 19
OUT
IN
NC
NC
NC
NC
VCCHSIO
VCCHSIO
VCCHSIO
VCCIO
VCCIO
VCCUSB3PLL
VCCSATA3PLL
VCCAPLL
VCCAPLL
VCCAPLL
DCPSUS3
VCCHDA
DCPSUS2
VCCSUS3
VCCSUS3
VCC3
VCC3
VCCDSW3_3
VCC1P05
VCC1P05
VCCCLK
VCCCLK
VCCCLK
VCCCLK
VCCCLK
VCCCLK
VCCACLKPLL
VCCSUS3
VCCSUS3 VCCIO
VCCIO
VCCAPLL
DCPSUS4
VCCSUS3
VCCRTC
DCPRTC
VCCSPI
VCCASW
VCCASW
VCC1P05
VCC1P05
VCC1P05
VCC1P05
VCC1P05
DCPSUSBYP
DCPSUSBYP
VCCASW
VCCASW
VCCASW
DCPSUS1
DCPSUS1
VCC3
VCC3
VCCTS1_5
VCCSDIO
VCCSDIO
SUS OSCILLATOR
SERIAL IO
THERMAL SENSOR
SYM 13 OF 19
USB2
LPT LP POWER
CORE
SPI RTC
HSIO
OPI
USB3
AZALIA/HDA
VRM/USB2/AZALIA
GPIO/LCC
ICC
NC
NC
NC
NC
NC
NC
NC
NC
BI
NC
NC
IN
OUT
IN
NC
NC
NC
NC
NC
OUT
NC
NC
NC
NC
NC
NC
NC
IN
NC
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
87 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
D
SIZEDRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
R0810.2:
R0800.2:
R0802.2:
NOTE: Aliases not used on CPU supply outputs
473mA Max[1]
Powered in DeepSx
LPT-LP current estimates from Lynx Point-LP PCH EDS, doc #503118, v1.0.
Note [1] current numbers from clarification email, from Srini, dated 9/10/2012 2:11pm.
1499mA Max[1]57mA Max
1838mA Max
WF: RSVD on Sawtooth Peak rev 1.0
WF: RSVD on Sawtooth Peak rev 1.0
41mA Max
59mA Max[1]
0.3mA Max[1]
29mA Max[1]
185mA Max[1]
40mA Max[1]
1mA Max[1]
213mA Max[1]
HSW-ULT current estimates from Haswell Mobile ULT Processor EDS vol 1, doc #502406, v0.9.
1.1A Max (LPDDR3: 1.2V)
1.4A Max (DDR3: 1.5-1.35V)
32A Max
???mA Max
18mA Max
11mA Max
3mA Max
17mA Max
42mA Max
Max load: 300mA
Max load: 300mA
114mA Max
3.3mA Max[1]
WF: RSVD on Sawtooth Peak rev 1.0
VCCCLK: 200mA Max
31mA Max
VCCCLK: 200mA Max
to avoid any extraneous connections.
OMIT_TABLE
2C+GT2
HASWELL-ULT
BGA-TSP
CRITICAL
U0500
H59
AA23
AA59
AB23
AC58
AC59
AD23
AD59
AD60
AE59
AE60
AG58
J58
L59
N58
T59
N59
N61
P60
P61
U59
V59
F59
AB57
AD57
AG57
C24
C28
C32
C36
C40
C44
C48
C52
C56
E23
E25
E27
E29
E31
E33
E35
E37
E39
E41
E43
E45
E47
E49
E51
E53
E55
E57
F24
F28
F32
F36
F40
F44
F48
F52
F56
G23
G25
G27
G29
G31
G33
G35
G37
G39
G41
G43
G45
G47
G49
G51
G53
G55
G57
H23
J23
K23
K57
L22
M23
M57
P57
E63
U57
W57
A59
E20
AC22
AE22
AE23
B59
AH26
AJ31
AJ33
AJ37
AN33
AP43
AR48
AY35
AY40
AY44
AY50
L62
N63
L63
F60
C59
D63
P62
PLACE_NEAR=U0500.L63:2.54mm
1%
1/20W
130
MF
201
R0802
1
2
53 70
16
PLACE_NEAR=U0500.C50:50.8mm
100
MF
1/20W
201
5%
R0860
1
2
CRITICAL
OMIT_TABLE
HASWELL-ULT
2C+GT2
BGA-TSP
U0500
AE7
AD10
AD8
AH13
J13
AB8
AG19
AG20
AE8
AF22
H11
H15
J11
J18
K19
K14
K16
V8
W9
A20
AA21
AC20
W21
Y20
AE9
AF9
AG13
AG14
AG8
J17
K18
M20
R21
T21
V21
AH10
AH14
K9
L10
M9
AG16
AG17
N8
P9
AG10
B11
T9
U8
Y8
AA9
AC9
AE20
AE21
AH11
J15
B18
53 70
16 17 70
17 53
17 53
53 70
BYPASS=R0899:U0500:2.54mm
402
CERM
1UF
10%
6.3V
C0899
1
2
PLACE_NEAR=U0500.AG19:2.54mm
1%
MF-LF
5.11
1/20W
201
R0899
12
53 70
0.1UF
CERM
402
10V
20%
BYPASS=U0500.AE7:6.35mm
C0895
1
2
402
CERM
10V
20%
0.1UF
BYPASS=U0500.AG10:6.35mm
C0892
1
2
BYPASS=U0500.AG10:6.35mm
0.1UF
402
CERM
10V
20%
C0891
1
2
BYPASS=U0500.AG10:6.35mm
1UF
402
CERM
6.3V
10%
C0890
1
2
MF
1/20W
0201
0
5%
R0811
12
MF
1/20W
0201
0
5%
R0812
12
PLACE_NEAR=U0500.L62:38.1mm
1/20W
43
MF
201
5%
R0810
12
PLACE_NEAR=R0810.1:2.54mm
MF
1%
75
1/20W
201
R0800
1
2
CPU/PCH POWER
SYNC_MASTER=J44 SYNC_DATE=08/12/2013
PPVCOMP_S0_CPU
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=1.05V
MIN_LINE_WIDTH=0.4 mm
PP1V05_S0_PCH_VCCACLKPLL
PP1V05_S0
MIN_NECK_WIDTH=0.2 mm
MIN_LINE_WIDTH=0.2 mm
PPVOUT_S5_PCH_DCPSUSBYP_R
VOLTAGE=1.05V
PPVOUT_S5_PCH_DCPSUSBYP
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=1.05V
MIN_LINE_WIDTH=0.2 mm
PPVOUT_S0_PCH_DCPRTC
VOLTAGE=1.05V
MIN_NECK_WIDTH=0.2 mm
MIN_LINE_WIDTH=0.2 mm
PP3V3_SUS
PP3V3_SUS
PP3V3_SUS
PP3V3_S0
PP1V05_S0
PP3V3_S0
PP1V05_S0
PP1V5_S0
PP3V3_SUS
PP1V05_S0
PPVRTC_G3H
CPU_VIDSCLK
CPU_VIDSOUT
PP1V05_S0SW_PCH_VCCSATA3PLL
PP1V05_S0SW_PCH_VCCUSB3PLL
PP3V3_S0
PP1V5_S0SW_AUDIO_HDA
PP1V05_S0_PCH_VCCAPLL_OPI
PP1V05_S0SW_PCH_HSIO
PP3V3_S5
PP1V05_S0
PP1V05_S0_PCH_VCC_ICC
PP1V05_S0
PP1V05_S0
TP_CPU_RSVDN61
TP_CPU_RSVD_N59
TP_CPU_RSVDP61
TP_CPU_RSVD_P60
CPU_PWR_DEBUG
PPVCC_S0_CPU
PPVCC_S0_CPU
PP1V35_S3_CPUDDR
VOLTAGE=1.05V
MIN_NECK_WIDTH=0.2 mm
MIN_LINE_WIDTH=0.4 mm
TP_PPVCCIO_S0_CPU
CPU_VCCSENSE_P
CPU_VCCST_PWRGD
CPU_VR_READY
CPU_VR_EN
CPU_VIDSCLK_R
PP1V05_S0
CPU_VIDALERT_R_L
CPU_VIDSOUT_R
CPU_VIDALERT_L
<BRANCH>
8 OF 120
8 OF 78
<E4LABEL>
<SCH_NUM>
5
11 12
6 8 11 15 16 17 37 53 57
60 61 65 68
8 11 14 45 59 60 61 65
8 11 14 45 59 60 61 65
8 11 14 45 59 60 61 65
8 11 12 13 15 17 18 24 28 30 37
38 39 40 41 42 43 44 46 47 50
61 62 64 65 68 77
6 8 11 15 16 17 37 53 57 60 61
65 68
8 11 12 13 15 17 18 24 28 30 37
38 39 40 41 42 43 44 46 47 50
61 62 64 65 68 77
6 8 11 15 16 17 37 53 57 60 61
65 68
47 59 60 61 63 65 68
8 11 14 45 59 60 61 65
6 8 11 15 16 17 37 53 57
60 61 65 68
12 13 17 65
11 12
11 14
8 11 12 13 15 17 18 24 28
30 37 38 39 40 41 42 43 44
46 47 50 61 62 64 65 68 77
11 17 60
11
11 60 65
11 13 15 16 17 18 26 27 29 56
59 60 61 65 68 77
6 8 11 15 16 17 37 53 57
60 61 65 68
11
6 8 11 15 16 17 37 53 57 60 61
65 68
6 8 11 15 16 17 37 53 57 60
61 65 68
18
18
8 10 42 54 65 68
8 10 42 54 65 68
10 41 65 73
70
6 8 11 15 16 17 37 53 57 60
61 65 68
70
70 www.rosefix.com

SYM 14 OF 19
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
OUT
SYM 15 OF 19
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
SYM 16 OF 19
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS_SENSE
VSS
VSS
VSS
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
124578
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87 6 5 4 3
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NOTICE OF PROPRIETARY PROPERTY:
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A
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PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
D
SIZEDRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
2C+GT2
BGA-TSP
HASWELL-ULT
OMIT_TABLE
CRITICAL
U0500
A11
A14
A18
A24
A28
A32
A36
A40
A44
A48
A52
A56
AA1
AA58
AB10
AB20
AB22
AB7
AC61
AD21
AD3
AD63
AE10
AE5
AE58
AF11
AF12
AF14
AF15
AF17
AF18
AG1
AG11
AG21
AG23
AG60
AG61
AG62
AG63
AH17
AH19
AH20
AH22
AH24
AH28
AH30
AH32
AH34
AH36
AH38
AH40
AH42
AH44
AH49
AH51
AH53
AH55
AH57
AJ13
AJ14
AJ23
AJ25
AJ27
AJ29
AJ35
AJ39
AJ41
AJ43
AJ45
AJ47
AJ50
AJ52
AJ54
AJ56
AJ58
AJ60
AJ63
AK23
AK3
AK52
AL10
AL13
AL17
AL20
AL22
AL23
AL26
AL29
AL31
AL33
AL36
AL39
AL40
AL45
AL46
AL51
AL52
AL54
AL57
AL60
AL61
AM1
AM17
AM23
AM31
AM52
AN17
AN23
AN31
AN32
AN35
AN36
AN39
AN40
AN42
AN43
AN45
AN46
AN48
AN49
AN51
AN52
AN60
AN63
AN7
AP10
AP17
AP20
201
MF
1/20W
100
5% PLACE_NEAR=U0500.E62:50.8mm
R0960
1
2
53 70
2C+GT2
BGA-TSP
HASWELL-ULT
OMIT_TABLE
CRITICAL
U0500
AP22
AP23
AP26
AP29
AP3
AP31
AP38
AP39
AP48
AP52
AP54
AP57
AR11
AR15
AR17
AR23
AR31
AR33
AR39
AR43
AR49
AR5
AR52
AT13
AT35
AT37
AT40
AT42
AT43
AT46
AT49
AT61
AT62
AT63
AU1
AU16
AU18
AU20
AU22
AU24
AU26
AU28
AU30
AU33
AU51
AU53
AU55
AU57
AU59
AV14
AV16
AV20
AV24
AV28
AV33
AV34
AV36
AV39
AV41
AV43
AV46
AV49
AV51
AV55
AV59
AV8
AW16
AW24
AW33
AW35
AW37
AW4
AW40
AW42
AW44
AW47
AW50
AW51
AW59
AW60
AY11
AY16
AY18
AY22
AY24
AY26
AY30
AY33
AY4
AY51
AY53
AY57
AY59
AY6
B20
B24
B26
B28
B32
B36
B4
B40
B44
B48
B52
B56
B60
C11
C14
C18
C20
C25
C27
C38
C39
C57
D12
D14
D18
D2
D21
D23
D25
D26
D27
D29
D30
D31
2C+GT2
BGA-TSP
HASWELL-ULT
OMIT_TABLE
CRITICAL
U0500
AH16
AH46
D33
D34
D35
D37
D38
D39
D41
D42
D43
D45
D46
D47
D49
D5
D50
D51
D53
D54
D55
D57
D59
D62
D8
E11
E17
F20
F26
F30
F34
F38
F42
F46
F50
F54
F58
F61
G18
G22
G3
G5
G6
G8
H13
H17
H57
J10
J22
J59
J63
K1
K12
L13
L15
L17
L18
L20
L58
L61
L7
M22
N10
N3
P59
P63
R10
R22
R8
E62
T1
T58
U20
U22
U61
U9
V10
V23
V3
V58
V7
W20
W22
Y10
Y59
Y63
CPU/PCH GROUNDS
SYNC_MASTER=J44 SYNC_DATE=08/12/2013
CPU_VCCSENSE_N
9 OF 78
9 OF 120
<E4LABEL>
<SCH_NUM>
<BRANCH>www.rosefix.com

Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
87 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
D
SIZEDRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
Intel recommendation (Table 5-1): 23x 22uF 0805 stuff, 7x 22uF 0805 nostuff
Apple implementation : 18x 22uF 0603 stuff, 80x 22uF 0603 nostuff
All Intel recommendations from Intel doc #503160 Shark Bay Ultrabook Platform Power Delivery Design Guide Rev 0.9 unless stated otherwise
1x Bulk nostuff, Harris Beach has 2x nostuff
Added 2 extra 2.2uF per Harris Beach v0.9 schematic
CPU VDDQ DECOUPLING
Intel recommendation (Table 5-4): 2x 2.2uF 0402, 6x 10uF 0603
CPU VCC Decoupling
Apple implementation : 2x 2.2uF 0402, 6x 10uF 0402

CPU VCC Decoupling
CRITICAL
0402
X6S
4V
10UF
20%
C1000
1
2
20%
6.3V
CERM-X5R
0402-1
10UF
C1050
1
2
20%
6.3V
10UF
0402-1
CERM-X5R
C1051
1
2
CERM-X5R
20%
6.3V
10UF
0402-1
C1052
1
2
CERM-X5R
20%
6.3V
0402-1
10UF
C1053
1
2
20%
6.3V
CERM-X5R
0402-1
10UF
C1054
1
2
20%
6.3V
CERM-X5R
0402-1
10UF
C1055
1
2
20%
2.2UF
402-LF
CERM
6.3V
C1040
1
2
20%
2.2UF
CERM
6.3V
402-LF
C1041
1
2
2.2UF
20%
402-LF
CERM
6.3V
C1042
1
2
CERM
402-LF
2.2UF
20%
6.3V
C1043
1
2
TANT
2V
CASE-B2-SM
270UF
20%
C1060
1
2
TANT
2V
270UF
20%
CASE-B2-SM
NO STUFF
C1061
1
2
CRITICAL
NO STUFF
X6S
0402
4V
10UF
20%
C1001
1
2
NO STUFF
0402
10UF
CRITICAL
20%
X6S
4V
C1002
1
2
10UF
NO STUFF
20%
CRITICAL
X6S
4V
0402
C1003
1
2
CRITICAL
10UF
0402
20%
X6S
4V
C1004
1
2
X6S
20%
CRITICAL
4V
0402
10UF
C1008
1
2
NO STUFF
20%
4V
CRITICAL
10UF
X6S
0402
C1009
1
2
NO STUFF
X6S
20%
CRITICAL
4V
0402
10UF
C1010
1
2
X6S
4V
0402
20%
CRITICAL
10UF
NO STUFF
C1011
1
2
CRITICAL
10UF
X6S
4V
0402
20%
C1012
1
2
20%
CRITICAL
10UF
4V
NO STUFF
0402
X6S
C1014
1
2
CRITICAL
20%
4V
X6S
10UF
0402
C1018
1
2
CRITICAL
4V
0402
X6S
20%
10UF
C1019
1
2
CRITICAL
10UF
0402
4V
X6S
20%
C1020
1
2
4V
CRITICAL
20%
10UF
X6S
0402
NO STUFF
C1021
1
2
CRITICAL
10UF
20%
X6S
4V
0402
NO STUFF
C1084
1
2
CRITICAL
0402
10UF
20%
4V
X6S
NO STUFF
C1083
1
2
CRITICAL
0402
10UF
20%
X6S
4V
NO STUFF
C1082
1
2
CRITICAL
20%
0402
4V
X6S
NO STUFF
10UF
C1081
1
2
NO STUFF
CRITICAL
10UF
20%
4V
X6S
0402
C1077
1
2
20%
10UF
NO STUFF
CRITICAL
0402
X6S
4V
C1075
1
2
CRITICAL
10UF
20%
4V
X6S
0402
C1074
1
2
4V
10UF
20%
X6S
CRITICAL
NO STUFF
0402
C1073
1
2
0402
20%
4V
X6S
10UF
NO STUFF
CRITICAL
C1072
1
2
4V
X6S
CRITICAL
0402
10UF
20%
C1070
1
2
4V
X6S
20%
0402
CRITICAL
NO STUFF
10UF
C1097
1
2
CRITICAL
10UF
20%
X6S
4V
0402
NO STUFF
C1096
1
2
4V
X6S
20%
0402
NO STUFF
10UF
CRITICAL
C1095
1
2
CRITICAL
4V
X6S
10UF
20%
0402
NO STUFF
C1094
1
2
CRITICAL
4V
X6S
20%
0402
10UF
NO STUFF
C1093
1
2
4V
X6S
20%
10UF
0402
NO STUFF
CRITICAL
C1092
1
2
NO STUFF
10UF
X6S
20%
4V
0402
CRITICAL
C1091
1
2
CRITICAL
4V
X6S
10UF
20%
0402
NO STUFF
C1090
1
2
NO STUFF
CRITICAL
20%
0402
4V
X6S
10UF
C1089
1
2
20%
0402
4V
X6S
CRITICAL
10UF
NO STUFF
C1088
1
2
NO STUFF
4V
X6S
20%
0402
10UF
CRITICAL
C1087
1
2
NO STUFF
0402
10UF
X6S
4V
20%
CRITICAL
C1086
1
2
X6S
10UF
NO STUFF
0402
4V
20%
CRITICAL
C1085
1
2
X6S
4V
20%
10UF
0402
NO STUFF
C1038
1
2
NO STUFF
20%
10UF
X6S
4V
0402
C1037
1
2
NO STUFF
10UF
20%
X6S
0402
4V
C1036
1
2
NO STUFF
X6S
4V
10UF
20%
0402
C1035
1
2
CRITICAL
4V
20%
X6S
0402
10UF
C1034
1
2
NO STUFF
10UF
X6S
4V
20%
0402
C1033
1
2
NO STUFF
10UF
4V
X6S
20%
0402
C1032
1
2
NO STUFF
10UF
4V
20%
0402
X6S
C1029
1
2
X6S
4V
20%
10UF
0402
NO STUFF
C109A
1
2
4V
20%
10UF
X6S
0402
NO STUFF
C1099
1
2
10UF
20%
X6S
4V
0402
NO STUFF
C1098
1
2
0402
10UF
4V
X6S
20%
NO STUFF
C107B
1
2
NO STUFF
0402
X6S
10UF
4V
20%
C107A
1
2
0402
20%
4V
X6S
10UF
NO STUFF
C1069
1
2
NO STUFF
20%
10UF
4V
X6S
0402
C1068
1
2
10UF
0402
X6S
4V
20%
NO STUFF
C108F
1
2
10UF
20%
X6S
4V
0402
NO STUFF
C1067
1
2
0402
10UF
X6S
4V
20%
NO STUFF
C108E
1
2
20%
10UF
NO STUFF
X6S
4V
0402
C1066
1
2
NO STUFF
10UF
0402
20%
4V
X6S
C108D
1
2
0402
10UF
20%
4V
X6S
NO STUFF
C108C
1
2
10UF
X6S
4V
0402
CRITICAL
20%
C1065
1
2
NO STUFF
20%
X6S
4V
10UF
0402
C1028
1
2
NO STUFF
20%
X6S
4V
10UF
0402
C1027
1
2
20%
NO STUFF
10UF
4V
X6S
0402
C1049
1
2
NO STUFF
10UF
X6S
20%
4V
0402
C1048
1
2
20%
0402
X6S
CRITICAL
10UF
4V
C1026
1
2
NO STUFF
20%
10UF
X6S
0402
4V
C1047
1
2
NO STUFF
0402
X6S
4V
20%
10UF
C1025
1
2
NO STUFF
20%
X6S
4V
0402
10UF
C1024
1
2
NO STUFF
20%
4V
X6S
0402
10UF
C1046
1
2
NO STUFF
X6S
20%
4V
10UF
0402
C1045
1
2
NO STUFF
20%
4V
10UF
X6S
0402
C1023
1
2
4V
0402
10UF
20%
X6S
CRITICAL
C1022
1
2
NO STUFF
10UF
4V
X6S
20%
0402
C1044
1
2
20%
4V
X6S
10UF
0402
NO STUFF
C1039
1
2
10UF
4V
20%
0402
X6S
NO STUFF
C1064
1
2
NO STUFF
10UF
0402
4V
20%
X6S
C108B
1
2
NO STUFF
20%
10UF
4V
X6S
0402
C1063
1
2
NO STUFF
10UF
0402
4V
X6S
20%
C108A
1
2
X6S
4V
0402
20%
NO STUFF
10UF
C1062
1
2
NO STUFF
0402
20%
4V
10UF
X6S
C109F
1
2
NO STUFF
0402
10UF
20%
4V
X6S
C109E
1
2
NO STUFF
10UF
X6S
4V
20%
0402
C1059
1
2
NO STUFF
20%
X6S
4V
10UF
0402
C1058
1
2
NO STUFF
0402
X6S
4V
20%
10UF
C109D
1
2
4V
20%
10UF
X6S
NO STUFF
0402
C1057
1
2
0402
4V
10UF
NO STUFF
20%
X6S
C109C
1
2
NO STUFF
4V
0402
10UF
X6S
20%
C1056
1
2
NO STUFF
10UF
0402
20%
4V
X6S
C109B
1
2
470UF-0.0045OHM
CRITICAL
20%
POLY-TANT
2.5V
SM
C1031
1
23
20%
4V
CRITICAL
10UF
0402
X6S
NO STUFF
C1030
1
2
CRITICAL
0402
X6S
NO STUFF
4V
10UF
20%
C104E
1
2
20%
10UF
4V
CRITICAL
0402
X6S
C104F
1
2
20%
10UF
X6S
4V
CRITICAL
NO STUFF
0402
C106D
1
2
20%
10UF
4V
0402
NO STUFF
X6S
CRITICAL
C106E
1
2
CRITICAL
4V
X6S
0402
20%
10UF
C105A
1
2
CRITICAL
X6S
10UF
0402
4V
20%
NO STUFF
C105B
1
2
CRITICAL
0402
4V
20%
X6S
10UF
C105C
1
2
CRITICAL
0402
X6S
4V
20%
10UF
C105D
1
2
20%
X6S
4V
CRITICAL
10UF
NO STUFF
0402
C105E
1
2
10UF
0402
CRITICAL
20%
4V
X6S
C105F
1
2
SYNC_DATE=08/12/2013SYNC_MASTER=J44
CPU Decoupling
PP1V35_S3_CPUDDR
PPVCC_S0_CPU
10 OF 120
<BRANCH>
<SCH_NUM>
<E4LABEL>
10 OF 78
8 41 65 73
8 42 54 65 68 www.rosefix.com

Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
87 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
D
SIZEDRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
as well as from clarification email, from Srini, dated 9/10/2012 2:11pm.
LPT-LP current estimates from Lynx Point-LP PCH EDS, doc #503118, v1.0
PCH VCCSUSHDA BYPASS
(PCH 3.3V/1.8V SDIO PWR)
PCH VCCSDIO BYPASS
(PCH 3.3V/1.5V HDA PWR)
(PCH 3.3V SUSPEND RTC PWR)
(PCH 3.3V SPI PWR)
PCH VCCSPI BYPASS
(PCH 3.3V SUSPEND PWR)
PCH VCCSUS3_3 BYPASS
(PCH 3.3V DSW PWR)
(PCH 1.05V ACLK PLL PWR)
PCH VCCACLKPLL FILTER/BYPASS
PCH VCCCLK FILTER/BYPASS
(PCH 1.05V VCCCLK PWR)
PCH VCCIO BYPASS
(PCH 1.05V USB2 PWR)
(PCH 3.3V THERMAL PWR)
PCH VCC3_3 BYPASS
(PCH 3.3V GPIO/LPC PWR)
PCH VCC3_3 BYPASS
PCH VCCCLK BYPASS
(PCH 1.05V CLK PWR)
(PCH 1.05V OPI PLL PWR)
(PCH 1.05V ME CORE PWR)
PCH VCCASW BYPASS
(PCH 1.05V CORE PWR)
PCH VCC BYPASS
PCH VCCSUS3_3 BYPASS
PCH VCCDSW3_3 BYPASS
PCH VCCSATA3PLL FILTER/BYPASS
(PCH 1.05V SATA3 PLL PWR)
41mA Max
83mA Max 42mA Max
??mA Max
31mA Max
57mA Max
PCH OPI VCCAPLL FILTER/BYPASS
??mA Max
(PCH 1.05V USB3 PLL PWR)
PCH VCCUSB3PLL FILTER/BYPASS
(PCH 1.05V PCIe/SATA/USB3 PWR)
PCH VCCHSIO BYPASS
NO STUFF
10V
20%
0.1UF
402
CERM
BYPASS=U0500.Y8:6.35mm
C1202
1
2
NO STUFF
CRITICAL
2.2UH-240MA-0.221OHM
0603
L1280
12
1/16W
5%
402
MF-LF
0
R1280
12
BYPASS=U0500.B18:12.7mm
CERM-X5R
4V
20%
0805-1
47UF
C1295
1
2
BYPASS=U0500.B18:12.7mm
CERM-X5R
4V
20%
0805-1
47UF
NO STUFF
C1296
1
2
47UF
20%
BYPASS=U0500.B11:12.7mm
0805-1
CERM-X5R
4V
C1290
1
2
4V
20%
CERM-X5R
0805-1
BYPASS=U0500.B11:12.7mm
NO STUFF
47UF
C1291
1
2
NO STUFF
CERM-X5R
4V
20%
47UF
0805-1
BYPASS=U0500.AA21:12.7mm
C1280
1
2
NO STUFF
0805-1
47UF
20%
4V
CERM-X5R
BYPASS=U0500.AA21:12.7mm
C1281
1
2
CERM-X5R
0805-1
47UF
20%
4V
BYPASS=U0500.J18:12.7mm
C1275
1
2
BYPASS=U0500.J18:12.7mm
CERM-X5R
4V
20%
47UF
0805-1
C1276
1
2
4V
20%
47UF
0805-1
BYPASS=U0500.A20:12.7mm
CERM-X5R
C1270
1
2
BYPASS=U0500.A20:12.7mm
0805-1
47UF
20%
4V
CERM-X5R
C1271
1
2
NO STUFF
BYPASS=U0500.AH10:6.35mm
1UF
CERM
402
10%
6.3V
C1200
1
2
402
CERM
1UF
10%
BYPASS=U0500.AH14:6.35mm
6.3V
C1210
1
2
0.1UF
20%
10V
402
CERM
BYPASS=U0500.K14:6.35mm
C1214
1
2
10%
1UF
6.3V
CERM
402
BYPASS=U0500.AH11:6.35mm
C1206
1
2
6.3V
10%
1UF
BYPASS=U0500.AG16:6.35mm
CERM
402
C1264
1
2
BYPASS=U0500.L10:6.35mm
402
CERM
1UF
10%
6.3V
C1261
1
2
6.3V
BYPASS=U0500.M9:6.35mm
20%
10UF
0402-1
CERM-X5R
C1262
1
2
BYPASS=U0500.J17:6.35mm
10%
1UF
402
CERM
6.3V
C1266
1
2
10UF
X5R
603
20%
6.3V
BYPASS=U0500.J11:12.7mm
C1255
1
2
NO STUFF
603
22UF
20%
6.3V
X5R-CERM-1
BYPASS=U0500.AE9:12.7mm
C1250
1
2
CERM
1UF
10%
402
6.3V
BYPASS=U0500.J11:6.35mm
C1256
1
2
1UF
CERM
402
10%
6.3V
BYPASS=U0500.AE8:6.35mm
C1257
1
2
1UF
CERM
402
10%
6.3V
BYPASS=U0500.AE9:6.35mm
C1251
1
2
BYPASS=U0500.R21:6.35mm
10%
1UF
402
CERM
6.3V
C1267
1
2
BYPASS=U0500.AC9:12.7mm
603
22UF
20%
X5R-CERM-1
6.3V
C1204
1
2
603
BYPASS=U0500.V8:12.7mm
X5R-CERM-1
6.3V
20%
22UF
C1212
1
2
10%
1UF
6.3V
CERM
402
BYPASS=U0500.U8:6.35mm
C1208
1
2
CERM
6.3V
10%
402
BYPASS=U0500.K9:6.35mm
1UF
C1260
1
2
BYPASS=U0500.J18:6.35mm
1UF
X5R
402
10%
10V
C1277
1
2
CRITICAL
0603
2.2UH-240MA-0.221OHM
L1275
12
BYPASS=U0500.B18:6.35mm
1UF
X5R
402
10%
10V
C1297
1
2
0603
CRITICAL
2.2UH-240MA-0.221OHM
L1295
12
1UF
X5R
402
10%
10V
BYPASS=U0500.B11:6.35mm
C1292
1
2
0603
CRITICAL
2.2UH-240MA-0.221OHM
L1290
12
MF-LF
402
5%
0
1/16W
R1275
12
BYPASS=U0500.A20:6.35mm
10V
10%
402
X5R
1UF
C1272
1
2
2.2UH-240MA-0.221OHM
CRITICAL
0603
L1270
12
0
1/16W
MF-LF
402
5%
R1270
12
BYPASS=U0500.AA21:6.35mm
10V
10%
402
X5R
1UF
C1282
1
2
PCH Decoupling
SYNC_MASTER=J44 SYNC_DATE=08/12/2013
PP1V05_S0SW_PCH_HSIO
PP1V05_S0SW_PCH_HSIO
PP1V05_S0SW_PCH_VCCSATA3PLL
MIN_LINE_WIDTH=0.2 MM
VOLTAGE=1.05V
MIN_NECK_WIDTH=0.075 MM
PP1V05_S0_PCH_VCCACLKPLL_R
MIN_LINE_WIDTH=0.2 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.05V
MIN_LINE_WIDTH=0.2 MM
VOLTAGE=1.05V
MIN_NECK_WIDTH=0.075 MM
PP1V05_S0SW_PCH_VCCUSB3PLL
MIN_NECK_WIDTH=0.2 MM
PP1V05_S0_PCH_VCC_ICC_R
MIN_LINE_WIDTH=0.2 MM
VOLTAGE=1.05V
PP1V05_S0_PCH_VCCACLKPLL
MIN_LINE_WIDTH=0.2 MM
VOLTAGE=1.05V
MIN_NECK_WIDTH=0.075 MM
PP1V05_S0_PCH_VCC_ICC
MIN_LINE_WIDTH=0.2 MM
VOLTAGE=1.05V
MIN_NECK_WIDTH=0.075 MM
PP1V05_S0_PCH_VCCAPLL_OPI
MIN_NECK_WIDTH=0.075 MM
VOLTAGE=1.05V
MIN_LINE_WIDTH=0.2 MM
PP1V05_S0
PP1V05_S0
PP1V05_S0
PP1V05_S0
PP3V3_S0
PP3V3_S0
PP1V05_S0
PP3V3_SUS
PP3V3_SUSPP3V3_S5
PP1V5_S0SW_AUDIO_HDA
PP3V3_S0
PP3V3_SUS
11 OF 78
12 OF 120
<E4LABEL>
<SCH_NUM>
<BRANCH>
8 11 60 65
8 11 60 65 8 12
8 14
8 12
8
8
6 8
11 15 16 17 37 53 57 60
61 65 68
6 8 11 15 16 17 37 53 57 60
61 65 68
6 8 11 15 16 17 37 53 57 60
61 65 68
6 8 11 15 16 17 37 53 57 60
61 65 68
8 11 12 13 15 17 18 24 28 30
37 38 39 40 41 42 43 44 46 47
50 61 62 64 65 68 77
8 11 12 13 15 17 18 24 28 30
37 38 39 40 41 42 43 44 46 47
50 61 62 64 65 68 77 6 8 11 15 16 17 37 53 57 60
61 65 68
8 11 14 45 59 60 61 65
8 11 14 45 59 60 61 65
8 13 15 16 17 18 26 27 29 56
59 60 61 65 68 77
8 17 60
8 11 12 13 15 17 18 24 28 30
37 38 39 40 41 42 43 44 46 47
50 61 62 64 65 68 77
8 11 14 45 59 60 61 65 www.rosefix.com

IN IN
IN
IN
IN
IN
IN
OUT
BI
OUT
OUT
OUT
IN
IN
NC
NC
NC
IN
OUT
RSVD
RSVD
HDA_DOCK_EN*/I2S1_TXD
HDA_BCLK/I2S0_SCLK
RTCX1
RTCX2
RTCRST*
INTVRMEN
INTRUDER*
SRTCRST*
HDA_RST*/I2S_MCLK
HDA_SYNC/I2S0_SFRM
HDA_SDI0/I2S0_RXD
HDA_SDI1/I2S1_RXD
HDA_SDO/I2S0_TXD
HDA_DOCK_RST*/I2S1_SFRM
I2S1_SCLK
SATA_RN0/PERN6_L3
SATA_RP0/PERP6_L3
SATA_TN0/PETN6_L3
SATA_TP0/PETP6_L3
SATA_RN1/PERN6_L2
SATA_RP1/PERP6_L2
SATA_TN1/PETN6_L2
SATA_TP1/PETP6_L2
SATA_RN2/PERN6_L1
SATA_RP2/PERP6_L1
SATA_TN2/PETN6_L1
SATA_TP2/PETP6_L1
SATA_RN3/PERN6_L0
SATA_RP3/PERP6_L0
SATA_TN3/PETN6_L0
SATA_TP3/PETP6_L0
SATA0GP/GPIO34
SATA1GP/GPIO35
SATA2GP/GPIO36
SATA3GP/GPIO37
SATA_IREF
PCH_TRST*
PCH_TDI
PCH_TCK
PCH_TDO
RSVD
PCH_TMS
JTAGX
RSVD
RSVD SATALED*
SATA_RCOMP
AUDIO
SYM 5 OF 19
SATA
JTAG
RTC
OUT
IN
IN
OUT
OUT
IN
IN
NC
NC
OUT
CLKOUT_LPC_1
CLKOUT_LPC_0
CLKOUT_ITPXDP_N
CLKOUT_ITPXDP_P
PCIECLKRQ5*/GPIO23
PCIECLKRQ4*/GPIO22
CLKOUT_PCIE_N5
CLKOUT_PCIE_P5
PCIECLKRQ3*/GPIO21
CLKOUT_PCIE_P4
CLKOUT_PCIE_N4
PCIECLKRQ2*/GPIO20
CLKOUT_PCIE_P3
CLKOUT_PCIE_N3
PCIECLKRQ1*/GPIO19
CLKOUT_PCIE_P2
CLKOUT_PCIE_N2
PCIECLKRQ0*/GPIO18
CLKOUT_PCIE_P1
CLKOUT_PCIE_N1
CLKOUT_PCIE_N0
XTAL24_OUT
XTAL24_IN
CLKOUT_PCIE_P0
TESTLOW
TESTLOW
TESTLOW
TESTLOW
DIFFCLK_BIASREF
RSVD
RSVD
SYM 6 OF 19
CLOCK SIGNALS
OUT
OUT
OUT
IN
IN
IN
IN
IN
OUT
OUT
OUT
IN
OUT
OUT
OUT
OUT
IN
OUT
OUT
IN
NC
NC
OUT
OUT
OUT
IN
OUT
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
87 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
D
SIZEDRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
(IPU)
(IPU)
(IPD-PLTRST#)
SSD Lane 1
SATA Port assignments:
Reserved: ODD
Primary HDD/SSD
Unused
Secondary HDD/SSD
(IPD)
(IPU)
(IPD-PLTRST#)
(IPD-PWROK)
SSD Lane 3
PCIe Port assignments:
SSD Lane 2
SSD Lane 0
(IPD)16 70
100K
1/20W5% 201MF
R1345 12
2011/20W5% MF
100KR1375 12
16
16
16
16
100K
5% 201MF1/20W
R1343 12
16 70
16 70
16 70
16 70
47 72
47 72
47 72
PLACE_NEAR=U0500.AU8:1.27mm
1/20W5% MF
33
201
R1312 12
1/20W5%
33
MF
PLACE_NEAR=U0500.AV11:1.27mm
201
R1311 12
47 68 72
MF 2015% 1/20W
33
PLACE_NEAR=U0500.AW8:1.27mm
R1310 12
17 72 330K
1/20W
5%
201
MF
R1302
1
2
1/20W
5%
201
MF
1M
R1301
1
2
1UF
X5R
402
10%
10V
C1300
1
2
20K
MF
201
5%
1/20W
R1300
1
2
X5R
402
1UF
10%
10V
C1303
1
2
MF
1/20W
20K
201
5%
R1303
1
2
6 16 70
201
MF
3.01K
1/20W
1%
PLACE_NEAR=U0500.C12:2.54mm
R1370
1
2
30 68 70
CRITICAL
OMIT_TABLE
2C+GT2
HASWELL-ULT
BGA-TSP
U0500
AW8
AW10
AV10
AU8
AY10
AU12
AU11
AV11
AY8
AU6
AV7
AE63
AE62
AD61
AE61
AD62
AU62
AC4
AL11
AV2
K10
L11
AU7
AW5
AY5
V1
U1
V6
AC1
A12
C12
J5
J8
J6
F5
H5
H8
H6
E5
B15
A17
B14
C17
A15
B17
C15
D17
U3
AV6
30 68 70
30 68 70
30 68 70
30 68 70
30 68 70
30 68 70
30 68 70
30 68 70
OMIT_TABLE
CRITICAL
2C+GT2
HASWELL-ULT
BGA-TSP
U0500
B35
A35
AN15
AP15
C43
B41
C41
B38
A39
B37
C42
A41
B42
C37
B39
A37
C26
U2
Y5
AD1
N1
U5
T2
K21
M21
AK8
AL8
C34
C35
A25
B25
30 68 70
30 68 70
30 68 70
30 68 70
30 68 70
30 68 70
30 68 70
12 63
63 68 70
63 68 70
47 72
12 31
32 68 70
32 68 70
23 68 70
23 68 70
12 23
30 68 70
30 68 70
12 30
3.01K
MF
201
1%
PLACE_NEAR=U0500.C26:2.54mm
1/20W
R1380
1
2
17 72
17 72
2015% 1/20W MF
10KR1390 12
5%
10K
1/20W 201MF
R1391 12
5%
10K
1/20W MF 201
R1392 12
201MF1/20W
10K
5%
R1393 12
17 72
17 72
17
MF5%1/20W
33
PLACE_NEAR=U0500.AU11:1.27mm
201
R1313 12
1/20W
100K
MF 2015%
R1341 12
1/20W5% 201MF
100KR1344 12
100K
MF 2015% 1/20W
R1340 12
1/20W
100K
201MF5%
R1342 12
SYNC_MASTER=J44 SYNC_DATE=08/12/2013
PCH Audio/JTAG/SATA/CLK
SSD_CLKREQ_L
TBT_CLKREQ_L
FW_CLKREQ_L
XDP_SSD_PCIE1_SEL_L
XDP_SSD_PCIE2_SEL_L
XDP_SSD_PCIE3_SEL_L
PCIE_SSD_R2D_C_P<2>
PCIE_SSD_D2R_P<2>
PCIE_SSD_D2R_N<2>
PP1V05_S0SW_PCH_VCCSATA3PLL
PCIE_SSD_R2D_C_N<0>
PCH_JTAGX
XDP_PCH_TDI
XDP_PCH_TMS
XDP_PCH_TDO
PCH_SRTCRST_L
PCH_INTVRMEN
RTC_RESET_L
PPVRTC_G3H
PP1V05_S0_PCH_VCCACLKPLL
PCH_SATALED_L
PCH_DIFFCLK_BIASREF
LPC_CLK24M_LPCPLUS_R
PP3V3_S0
HDA_RST_R_L
HDA_SDOUT
PCH_TESTLOW_C35
PCIE_SSD_R2D_C_P<0>
HDA_SYNC
PCH_CLK32K_RTCX1
PCH_TESTLOW_AL8
PCH_TESTLOW_AK8
LPC_CLK24M_SMC_R
TP_ITPXDP_CLK100MP
TP_ITPXDP_CLK100MN
PCIE_SSD_R2D_C_N<1>
PCIE_SSD_R2D_C_P<1>
PCIE_SSD_D2R_N<1>
PCIE_SSD_D2R_P<1>
PCIE_SSD_D2R_N<3>
PCIE_SSD_D2R_P<3>
PCIE_SSD_R2D_C_P<3>
PCIE_SSD_R2D_C_N<3>
PCIE_SSD_R2D_C_N<2>
HDA_SDOUT_R
PCH_TESTLOW_C34
PCIE_SSD_D2R_N<0>
PCIE_SSD_D2R_P<0>
HDA_BIT_CLK
PCH_INTRUDER_L
XDP_SSD_PCIE0_SEL_L
NC_HDA_SDIN1
PCH_SATALED_L
ENETSD_CLKREQ_L
CAMERA_CLKREQ_L
AP_CLKREQ_L
HDA_RST_L
XDP_CPUPCH_TRST_L
TP_PCH_I2S1_SCLK
XDP_PCH_TCK
TP_PCH_I2S1_SFRM
TP_PCH_I2S1_TXD
NC_RTC_CLK32K_RTCX2
HDA_SDIN0
HDA_SYNC_R
HDA_BIT_CLK_R
PCH_CLK24M_XTALIN
PCH_CLK24M_XTALOUT
PCH_SATA_RCOMP
NC_PCIE_CLK100M_FWP
FW_CLKREQ_L
NC_PCIE_CLK100M_FWN
NC_PCIE_CLK100M_ENETSDN
NC_PCIE_CLK100M_ENETSDP
ENETSD_CLKREQ_L
PCIE_CLK100M_CAMERA_N
PCIE_CLK100M_CAMERA_P
CAMERA_CLKREQ_L
PCIE_CLK100M_AP_N
AP_CLKREQ_L
PCIE_CLK100M_AP_P
PCIE_CLK100M_TBT_N
PCIE_CLK100M_TBT_P
TBT_CLKREQ_L
PCIE_CLK100M_SSD_N
PCIE_CLK100M_SSD_P
SSD_CLKREQ_L
12 OF 78
<BRANCH>
<SCH_NUM>
<E4LABEL>
13 OF 120
12 30
12 23
12
8 11
72
72
72
8 13 17 65
8 11
12
8 11 13 15 17 18 24 28 30 37 38
39 40 41 42 43 44 46 47 50 61
62 64 65 68 77
72
17 72
72
66
12
12 68
12 31
12 63
72
72
72
66
12
66
66
66
12 68 www.rosefix.com

IN
OUT
IN
OUT
OUT
IN
IN
IN
IN
OUT
OUT
SLP_WLAN*/GPIO29
SLP_S0*
BATLOW*/GPIO72
ACPRESENT/GPIO31
PWRBTN*
SUSWARN*/SUSPWRDNACK/GPIO30
RSMRST*
PCH_PWROK
APWROK
SYS_RESET*
SUSACK*
PLTRST*
SYS_PWROK
DPWROK
DSWVRMEN
CLKRUN*/GPIO32
WAKE*
SLP_S5*/GPIO63
SUSCLK/GPIO62
SUS_STAT*/GPIO61
SLP_S4*
SLP_S3*
SLP_A*
SLP_SUS*
SLP_LAN*
SYSTEM POWER MANAGEMENT
SYM 8 OF 19
OUT
OUT
OUT
OUT
BI
IN
IN
OUT
OUT
GPIO53
GPIO51
GPIO54
GPIO52
GPIO55
PME*
PIRQC*/GPIO79
PIRQD*/GPIO80
PIRQA*/GPIO77
PIRQB*/GPIO78
EDP_BKLEN
EDP_BKLCTL
EDP_HPD
DDPC_HPD
DDPC_AUXP
DDPB_AUXP
DDPB_HPD
DDPB_AUXN
DDPC_AUXN
DDPC_CTRLCLK
DDPC_CTRLDATA
DDPB_CTRLCLK
DDPB_CTRLDATA
EDP_VDDEN
SIDEBAND
eDP
DISPLAY
PCI
SYM 9 OF 19
OUT
BI
BI
BI
BI
BI
BI
OUT
OUT
IN
IN
IN
IN
IN
IN
IN
OUT
OUT
OUT
OUT
IN
IN
OUT
IN
NC
08
NC
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
87 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
D
SIZEDRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
SLP_S0# Isolation
SLP_S0# can be driven high outside of S0
U1420 ensures signal will only be high in S0.
(IPD-PLTRST#)
(IPU)
(IPU)
(IPD-DeepSx)
(IPD-DeepSx)
(IPD-PLTRST#)
(IPU)
R1400 kept for debug purposes.
61 72
13 18 36
38
38
15 16 18
13 17 72
13 17 72
16 17 36 72
17 36 68 72
13 40 61
13 17 18 36 61 63 68
OMIT_TABLE
CRITICAL
HASWELL-ULT
2C+GT2
BGA-TSP
U0500
AJ8
AB5
AN4
V5
AV5
AW7
AY7
AG7
AL7
AW6
AL5
AJ7AF3
AT4
AJ6
AP5
AP4
AM5
AG4
AK2
AE6
AV4
AG2
AC3
AJ5
13 18 29 36 61 63
13 36 61
37
36 45 68
13 36 45 68
13 29 31 72
5%
201
1/20W
MF
100K
R1451
1
2
36 72
5%
201
1/20W
MF
330K
R1450
1
2
13 62
62 68
2C+GT2
BGA-TSP
CRITICAL
OMIT_TABLE
HASWELL-ULT
U0500
C5
B5
B9
C9
C8
B6
A6
D9
D11
A8
B8
A9
D6
C6
R5
L1
L4
L3
U7
U6
P4
N4
N2
AD4
13 62
23 74
64 66 74
64 66 74
23 74
28
64 66
64 66
28
23
64 66
62
5% 2011/20WMF
100KR1446 12
5% 201
1/20WMF
100KR1445 12
5% 201
1/20WMF
100KR1442 12
5% 201
1/20WMF
100KR1443 12
5% 201
1/20WMF
10KR1441 12
5%
0
0201
1/20W
MF
NO STUFF
R1400
1
2
5% 2011/20WMF
100KR1440 12
13 24
13 36
13 68
13 68
13 68
13 64 66
13 68
13 68
13 25 36
5% 2011/20W MF
10KR1455 12
5% 2011/20W MF
10KR1410 12
5% 2011/20WMF
100KR1447 12
5% 201
1/20WMF
100KR1448 12
5% 201
1/20WMF
100KR1449 12
5% 2011/20W MF
100KR1431 12
5% 2011/20W MF
100KR1430 12
36 37
13 61
5% 2011/20W MF
1KR1405 12
5% 2011/20W MF
10KR1452 12
5% 2011/20W MF
100KR1460 12
5% 2011/20W MF
100KR1461 12
5% 2011/20W MF
100KR1462 12
5% 2011/20W MF
100KR1464 12
5% 2011/20W MF
100KR1463 12
13 16 36 72
SOT891
74LVC1G08
CRITICAL
U1420
2
1
35
6
4
0.1UF
10V
10%
X5R-CERM
0201
C1420
1
2
SYNC_MASTER=J44 SYNC_DATE=08/12/2013
PCH PM/PCI/GFX
PCH_SUSWARN_L
PCH_SUSACK_L
DPMUX_HPD_OUT
DP_HDMI_TBT_AUX_P
NC_PM_SLP_A_L
DP_HDMI_TBT_AUX_N
DP_TBTSNK0_AUXCH_C_P
DP_TBTSNK0_AUXCH_C_N
DP_TBTSNK0_DDC_DATA
DP_HDMI_TBT_DDC_CLK
DP_TBTSNK0_HPD
DP_INT_HPD
PPVRTC_G3H
PM_SLP_S3_L
PM_SLP_S4_L
PM_CLK32K_SUSCLK_R
PM_SLP_S5_L
PCIE_WAKE_L
DP_HDMI_TBT_DDC_DATA
DP_TBTSNK0_DDC_CLK
TP_PCH_SLP_LAN_L
PM_SLP_SUS_L
NC_PCI_PME_L
TBT_PWR_REQ_L
SMC_RUNTIME_SCI_L
AUD_IP_PERIPHERAL_DET
AUD_I2C_INT_L
HDMITBTMUX_LATCH
ENET_LOW_PWR
AUD_IPHS_SWITCH_EN
AUD_PWR_EN
ODD_PWR_EN_L
PM_BATLOW_L
SMC_ADAPTER_EN
PM_PWRBTN_L
PM_RSMRST_L
PLT_RESET_L
PM_PCH_PWROK
PM_PCH_PWROK
PM_PCH_SYS_PWROK
PM_SYSRST_L
LPC_PWRDWN_L
PM_CLKRUN_L
PM_DSW_PWRGD
PCH_DSWVRMEN
EDP_PANEL_PWR
PCIE_WAKE_L
PM_CLKRUN_L
PM_SLP_S5_L
SMC_RUNTIME_SCI_L
TBT_PWR_REQ_L
AUD_I2C_INT_L
ODD_PWR_EN_L
HDMITBTMUX_LATCH
ENET_LOW_PWR
AUD_IPHS_SWITCH_EN
AUD_PWR_EN
PP3V3_S5
PM_PWRBTN_L
PM_BATLOW_L
TP_PCH_SLP_WLAN_L
EDP_BKLT_PWM
PP3V3_S0
PCH_PM_SLP_S0_L
PM_SLP_S0_L
EDP_BKLT_EN
PM_SLP_S4_L
PM_SLP_S3_L
PM_SLP_S0_L
AUD_IP_PERIPHERAL_DET
EDP_PANEL_PWR
EDP_BKLT_EN
PM_SLP_SUS_L
PP3V3_S0
13 OF 78
<BRANCH>
<SCH_NUM>
<E4LABEL>
14 OF 120
68
8 12 17 65
66
72
13 29 31 72
13 36 45 68
13 36 61
13 36
13 24
13 68
13 68
13 64 66
13 68
13 68
13 61
8 11 15 16 17 18 26 27 29 56 59
60 61 65 68 77
13 16 36 72
13 25 36
8 11 12 13 15 17 18 24 28 30
37 38 39 40 41 42 43 44 46 47
50 61 62 64 65 68 77
13 18 29 36 61 63
13 17 18 36 61 63 68
13 18 36
13 68
13 62
13 62
13 40 61
8 11 12 13 15 17 18 24 28 30 37
38 39 40 41 42 43 44 46 47 50
61 62 64 65 68
77 www.rosefix.com

SPI_IO3
SPI_MISO
SPI_IO2
SPI_CS2*
SPI_MOSI
SPI_CS0*
SPI_CS1*
LFRAME*
LAD2
LAD3
LAD1
SPI_CLK
LAD0 SMBALERT*/GPIO11
SMBCLK
SMBDATA
SML0ALERT*/GPIO60
SML0CLK
SML0DATA
SML1CLK_GPIO75
SML1ALERT*/PCHHOT*/GPIO73
SML1DATA/GPIO74
CL_CLK
CL_DATA
CL_RST*
SYM 7 OF 19
LPC
SMBUS
SPI
C-LINK
OUT
IN
IN
IN
OUT
IN
OUT
OUT
IN
IN
OUT
OUT
IN
IN
OUT
OUT
OUT
OUT
IN
IN
OUT
OUT
IN
IN
OUT
OUT
PCIE_RCOMP
PCIE_IREF
RSVD
RSVD
PETP1/USB3TP2
PETN1/USB3TN2
PERP1/USB3RP2
PERN1/USB3RN2
PETP4
PETN4
PERP4
PERN4
PETP3
PETN3
PERP3
PERN3
PETP5_L3
PETN5_L3
PETP5_L2
PETN5_L2
PERP5_L2
PERN5_L2
PETP5_L1
PETN5_L1
PERP5_L1
PERN5_L1
PERN2/USB3RN3
PERP2/USB3RP3
PETN2/USB3TN3
PETP2/USB3TP3
USB2P7
USB2N7
PERP5_L3
PERN5_L3
PETP5_L0
PETN5_L0
PERP5_L0
PERN5_L0
OC1*/GPIO41
OC0*/GPIO40
OC2*/GPIO42
OC3*/GPIO43
RSVD
RSVD
USBRBIAS*
USBRBIAS
USB3TP1
USB3TN1
USB3RP1
USB3RN1
USB3TP0
USB3TN0
USB3RP0
USB3RN0
USB2N0
USB2P0
USB2N1
USB2P1
USB2N2
USB2P2
USB2N3
USB2P3
USB2N4
USB2P4
USB2N5
USB2P5
USB2N6
USB2P6
USB
PCI-E
SYM 11 OF 19
IN
IN
NC
NC
OUT
OUT
IN
IN
OUT
IN
OUT
IN
IN
NC
NC
BI
BI
BI
IN
BI
BI
BI
BI
BI
OUT
BI
BI
OUT
BI
BI
BI
BI
OUT
OUT
OUT
OUT
IN
BI
BI
OUT
BI
OUT
BI
BI
IN
BI
BI
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
87 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
D
SIZEDRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
page, may be wire-ORed into other signals.
SML1ALERT# pull-up not provided on this
Unused
(& Ethernet if combo)
Thunderbolt lane 3
Thunderbolt lane 2
Thunderbolt lane 1
PCIe Port Assignments:
USB3 Port Assignments:
Thunderbolt lane 0
Reserved: FireWire
AirPort
Camera
Ext B (SS)
USB Port Assignments:
Ext A (LS/FS/HS)
Ext B (LS/FS/HS)
BT
IR
Reserved: SD (HS)
(IPU/IPD)
(IPU)
(IPU/IPD)
(IPU/IPD)
(IPU)
(IPU)
(IPU)
(IPU)
(IPU)
(IPU)
Trackpad
Reserved: Camera
(IPD)
SD Card Reader
Ext A (SS)
Otherwise, 100k pull-up to 3.3V SUS required.
(IPU)
CRITICAL
2C+GT2
BGA-TSP
OMIT_TABLE
HASWELL-ULT
U0500
AF2
AD2
AF4
AU14
AW12
AY12
AW11
AV12 AN2
AP2
AH1
AL2
AN1
AK1
AU4
AU3
AH3
AA3
Y7
Y4
AC2
Y6
AF1
AA4
AA2
23 68 70
100K
5% MF 1/20W 201
R1580 12
100K
5% 1/20W MF 201
R1581 12
14 16 33
14 16 63
14 16
38
14 16
23 68 70
14 68
23 68 70
23 68 70
23 68 70
23 68 70
23 68 70
23 68 70
23 68 70
23 68 70
63 71
63 71
63 68 71
63 68 71
32 70
32 70
32 68 70
32 68 70
63 68 70
63 68 70
OMIT_TABLE
2C+GT2
BGA-TSP
HASWELL-ULT
CRITICAL
U0500
AL3
AT1
AH2
AV3B27
A27
G17
F15
G11
F13
F10
F8
H10
E6
F17
G15
F11
G13
E10
E8
G10
F6
C30
B31
C29
B29
C23
B23
B21
B22
C31
A31
B30
A29
C22
A23
C21
A21
AM10
AN10
E13
E15
AN8
AR7
AR8
AR10
AM15
AM13
AP11
AR13
AM8
AT7
AP8
AT10
AL15
AN13
AN11
AP13
G20
E18
H20
F18
C33
B33
B34
A33
AJ11
AJ10
63 68 70
63 68 70
3.01K
201
MF
1%
PLACE_NEAR=U0500.A27:2.54mm
1/20W
R1500
1
2
63 68 71
63 68 71
63 68 71
63 68 71
33 68 71
23 68 70
33 68 71
33 68 71
33 68 71
22.6
201
1%
1/20W
MF
PLACE_NEAR=U0500.AJ10:2.54mm
R1570
1
2
34 71
34 71
66 71
23 68 70
66 71
29 71
29 71
63 71
63 71
23 68 70
33 71
33 71
36 45 68 72
36 45 68 72
36 45 68 72
36 45 68 72
36 45 68 72
1/20W5% 201MF
33R1543 12
2011/20W MF5%
33R1542 12
23 68 70
33
MF 2015% 1/20W
R1544 12
5% 1/20W 201MF
33R1540 12
1/20W5% 201MF
33R1541 12
45 72
45 72
32 36 39 43 68 72 76
23 68 70
32 36 39 43 68 72 76
39 72
39 72
16 19 39 63 68 72
16 19 39 63 68 72
45 72
45 72
23 68 70
14 45 72
14 45 72
2011/20W MF5%
100KR1591 12
1K
5% MF 1/20W 201
R1549 12
100K
5% 1/20W MF 201
R1590 12
1K
5% MF 1/20W 201
R1548 12
100K
5% 1/20W MF 201
R1582 12
100K
201MF5%1/20W
R1583 12
SYNC_DATE=08/12/2013SYNC_MASTER=J44
PCH PCIe/USB/LPC/SPI/SMBus
PP3V3_SUS
XDP_USB_EXTD_OC_L
XDP_USB_EXTC_OC_L
XDP_USB_EXTB_OC_L
XDP_USB_EXTA_OC_L
WOL_EN
LPC_AD_R<0>
LPC_AD<2>
PCH_SML1ALERT_L
PP1V05_S0SW_PCH_VCCUSB3PLL PCH_PCIE_RCOMP
USB_EXTA_P
USB_EXTB_P
USB_BT_N
NC_USB_IRP
USB_TPAD_N
USB_TPAD_P
TP_USB_5N
USB_BT_P
NC_PCIE_FW_R2D_CN
LPC_AD_R<2>
LPC_AD_R<1>
LPC_FRAME_L
NC_USB_IRN
USB3_EXTA_D2R_P
USB_EXTB_N
PCIE_TBT_D2R_P<0>
PCIE_TBT_R2D_C_N<0>
USB3_EXTB_R2D_C_P
PCIE_AP_D2R_N
PCH_SMBALERT_L
TP_USB_5P
NC_USB_CAMERAN
NC_USB_CAMERAP
NC_USB_SDP
NC_USB_SDN
USB_EXTA_N
USB3_EXTB_R2D_C_N
USB3_EXTB_D2R_P
USB3_EXTB_D2R_N
USB3_EXTA_R2D_C_N
USB3_EXTA_R2D_C_P
USB3_EXTA_D2R_N
USB3RPCIE_SD_R2D_C_N
USB3RPCIE_SD_D2R_P
USB3RPCIE_SD_D2R_N
NC_PCIE_FW_R2D_CP
NC_PCIE_FW_D2RP
PCIE_AP_R2D_C_N
PCIE_AP_D2R_P
PCIE_TBT_R2D_C_P<3>
PCIE_TBT_R2D_C_N<3>
PCIE_TBT_R2D_C_P<2>
PCIE_TBT_R2D_C_N<2>
PCIE_TBT_D2R_P<2>
PCIE_TBT_D2R_N<2>
PCIE_TBT_R2D_C_P<1>
PCIE_TBT_R2D_C_N<1>
PCIE_TBT_D2R_P<1>
PCIE_TBT_D2R_N<1>
PCIE_CAMERA_D2R_N
PCIE_CAMERA_D2R_P
PCIE_CAMERA_R2D_C_N
PCIE_TBT_D2R_P<3>
PCIE_TBT_D2R_N<3>
PCIE_TBT_R2D_C_P<0>
PCIE_AP_R2D_C_P
NC_PCIE_FW_D2RN
USB3RPCIE_SD_R2D_C_P
SPI_CLK_R
LPC_AD<0>
LPC_AD<1>
LPC_AD<3>
SML_PCH_0_CLK
SMBUS_PCH_DATA
SMBUS_PCH_CLK
NC_CLINK_DATA
NC_CLINK_RESET_L
NC_CLINK_CLK
PCIE_TBT_D2R_N<0>
PCH_USB_RBIAS
TP_SPI_CS2_L
TP_SPI_CS1_L
SPI_CS0_R_L
PCIE_CAMERA_R2D_C_P
LPC_FRAME_R_L
LPC_AD_R<3>
SPI_MOSI_R
SPI_MISO
SPI_IO<3>
SPI_IO<2>
XDP_USB_EXTA_OC_L
XDP_USB_EXTB_OC_L
XDP_USB_EXTC_OC_L
XDP_USB_EXTD_OC_L
SMBUS_SMC_1_S0_SDA
SMBUS_SMC_1_S0_SCL
SML_PCH_0_DATA
PP3V3_SUS
SPI_IO<2>
SPI_IO<3>
PCH_SMBALERT_L
WOL_EN
14 OF 78
15 OF 120
<E4LABEL>
<SCH_NUM>
<BRANCH>
8 11 14 45 59 60 61 65
14 16
14 16
14 16 63
14 16 33
8 11 72
71
66
14
71
66 71
66 71
66 71
66 71
66
66
66
66
66
66
71
8 11 14 45 59 60 61 65
14 45 72
14 45 72
14
14 68 www.rosefix.com

IN
OUT
BI
BI
OUT
IN
IN
IN
IN
OUT
OUT
SERIRQ
THRMTRIP*
RCIN*/GPIO82
PCH_OPI_COMP
RSVD
RSVD
GSPI0_CS*/GPIO83
GSPI0_MISO/GPIO85
GSPI0_CLK/GPIO84
GSPI1_CLK/GPIO88
GSPI1_CS*/GPIO87
GSPI0_MOSI/GPIO86
GSPI_MOSI/GPIO90
GSPI1_MISO/GPIO89
UART0_RXD/GPIO91
UART0_TXD/GPIO92
UART1_RXD/GPIO0
UART0_CTS*/GPIO94
UART0_RTS*/GPIO93
UART1_CTS*/GPIO3
UART1_RST*/GPIO2
UART1_TXD/GPIO1
I2C0_SCL/GPIO5
I2C1_SDA/GPIO6
I2C0_SDA/GPIO4
I2C1_SCL/GPIO7
SDIO_CMD/GPIO65
SDIO_CLK/GPIO64
SDIO_D1/GPIO67
SDIO_D2/GPIO68
SDIO_D0/GPIO66
SDIO_D3/GPIO69
BMBUSY*/GPIO76
GPIO8
LAN_PHY_PWR_CTRL/GPIO12
GPIO15
GPIO17
GPIO16
GPIO24
GPIO28
GPIO27
GPIO26
GPIO56
GPIO57
GPIO58
GPIO59
GPIO47
GPIO44
GPIO48
GPIO49
GPIO50
HSIOPC/GPIO71
GPIO13
GPIO25
GPIO14
GPIO45
GPIO46
GPIO9
GPIO10
DEVSLP0*/GPIO33
DEVSLP1*/GPIO38
SDIO_POWER_EN/GPIO70
DEVSLP2*/GPIO39
SPKR/GPIO81
SYM 10 OF 19
CPU/MISC
GPIO
LPIO
OUT
IN
IN
IN
IN
BI
BI
BI
NC
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
NC
OUT
BI
OUT
OUT
OUT
OUT
OUT
IN
OUT
OUT
IN
BI
BI
BI
IN
BI
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
87 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
D
SIZEDRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
BOM OPTIONSBOM GROUP
TABLE_BOMGROUP_HEAD
TABLE_BOMGROUP_ITEM
RR/FR: DPHDMIMUX_SEL_TBT, requires 100k pull-up to TBTLC
CR: TBT_GO2SX_BIDIR, requires 100k pull-up to SUS
Requires connection to SMC via 1K series R
platform does not use SD card
R1616 should also be stuffed if
(IPD-PLTRST#)
(IPD-PLTRST#)
GPIO12:
Redwood Ridge: Alias to TBT_CIO_PLUG_EVENT_L, requires pull-up (S0).
Cactus Ridge: Alias to TBT_CIO_PLUG_EVENT, requires pull-down.
Pull-up/down on chipset support page (depends on TBT controller)
(IPD-PLTRST#)
(IPD-DeepSx)
(IPD-RSMRST#)
(IPD)
(IPD)
TBTLC for CR, S0 for RR
Pull-up on TBT page
1/20W5% 201MF
10KR1652 12
MF5%
1/20W
100K
201
R1668 12
MF 2015%
1/20W
100KR1669 12
MF 2015%
100K
1/20W
R1672 12
MF 2015%
1/20W
100KR1674 12
MF 2015%
100K
1/20W
R1673 12
MF 2015%
1/20W
100KR1675 12
MF 2015%
1/20W
100KR1676 12
100K
1/20W5% 201MF
R1678 12
MF 2015%
1/20W
100KR1677 12
100K
1/20W5% 201MF
R1679 12
5%
1/20W
MF
201
100K
R1639
1
2
1/20WMF
1K
2015%
R1641 12
1/20WMF
100K
2015%
R1629 12
201
MF
5%
100K
1/20W
R1621
1
2
13 15 16 18
18 23
23 64 66
15 36 45 68
63
15 29
MF
1/20W
100K
5%
201
R1671
1
2
13 15 16 18
15 64
15 18
100K
MF 2015%1/20W
R1670 12
RAMCFG3:H
1/20W
5%
201
MF
100K
R1631
1
2
1/20W
5%
201
MF
100K
RAMCFG2:H
R1636
1
2
RAMCFG1:H
1/20W
5%
MF
201
100K
R1635
1
2
RAMCFG0:H
100K
1/20W
MF
201
5%
R1611
1
2
24
15 68
2C+GT2
HASWELL-ULT
BGA-TSP
CRITICAL
OMIT_TABLE
U0500
P1
P2
L2
N5
AM2
AT3
AH4
AD6
Y1
T3
AD5
AM4
AN3
AN5
AD7
AK4
AG5
AG3
AB6
U4
Y3
P3
AG6
AP1
AL4
AT5
AU2
AM3
L6
R6
N6
L8
L5
R7
N7
K2
Y2
F3
F2
F1
G4
AM7
AW15
V4
AB21
AF20
E3
F4
D3
E4
C3
E2
C4
T4
V2
D60
G1
J2
J1
K3
J4
J3
K4
G2
15 62
15 68
15 62 68
38
15 68
15 16
15 16 18
15 16 45 68
55
15 30 60 61
15 68
15 63
15 23
15 16
15 16
15 18
15 60
15 45 68 72
15 18
15 68
15 30
15 29
30
15 36
15 63
37 72
15 16
15 16 18
15 16 18
15 16 18
18 23 72
15 16 18
201
MF
1/20W
1K
5%
R1650
1
2
100K
1/20W5% MF 201
R1610 12
100K
5% 2011/20WMF
R1614 12
100K
1/20W 201MF5%
R1615 12
SD_ON_MLB
1/20WMF 2015%
100KR1616 12
201MF5%
1/20W
100KR1617 12
MF 2015%
1/20W
100KR1618 12
5% MF 201
1/20W
100KR1619 12
MF
1/20W 2015%
100KR1620 12
MF 201
1/20W5%
100KR1622 12
MF
100K
5% 2011/20W
R1623 12
100K
1/20W 201MF5%
R1624 12
201
100K
1/20WMF5%
R1625 12
1/20W
100K
201MF5%
R1626 12
201MF
1/20W
100K
5%
R1627 12
100K
1/20W 2015% MF
R1628 12
MF
100K
2015%1/20W
R1630 12
MF 2015%
1/20W
100K
NO STUFFR1632 12
100K
1/20W 201MF5%
R1633 12
1/20W5% 201MF
100KR1634 12
5% MF
1/20W
100K
201
R1640 12
MF 2015%
100K
1/20W
R1637 12
MF 2015%
100K
1/20W
R1638 12
100K
MF 2015%1/20W
R1691 12
10K
MF 2015%1/20W
R1694 12
100K
1/20W5% 201MF
R1693 12
PLACE_NEAR=U0500.AW15:2.54mm
49.9
201
1%
1/20W
MF
R1655
1
2
100K
MF5%1/20W 201
R1695 12
MF 2015%
1/20W
100KR1660 12
100K
MF 2015%1/20W
R1661 12
100K
1/20W5% 201MF
R1662 12
MF 2015%
1/20W
100KR1663 12
MF 2015%
1/20W
47KR1664 12
2015%
1/20W
47K
MF
R1665 12
1/20W5% 201MF
47KR1666 12
MF 2015%
1/20W
47KR1667 12
RAMCFG3:H,RAMCFG2:H,RAMCFG1:H,RAMCFG0:HRAMCFG_SLOT
PCH GPIO/MISC/LPIO
SYNC_MASTER=J44 SYNC_DATE=08/12/2013
SPIROM_USE_MLB
XDP_SDCONN_STATE_CHANGE_L
PP3V3_S3RS0_CAMERA
TPAD_SPI_IF_EN
JTAG_TBT_TMS_PCH
CAMERA_PWR_EN_PCH
SD_PWR_EN
XDP_JTAG_ISP_TDI
PCH_HSIO_PWR_EN
XDP_JTAG_ISP_TCK
FW_PWR_EN
SSD_DEVSLP
AP_S0IX_WAKE_SEL
PP3V3_S3
PP3V3_S0
PP3V3_S3
PP3V3_S0
PP3V3_S3
HDMITBTMUX_FLAG_L
TPAD_SPI_CS_L
PCH_GSPI0_MOSI
PCH_GSPI0_MISO
PCH_GSPI0_CLK
PCH_GSPI0_CS_L
PCH_UART1_CTS_L
PCH_I2C1_SDA
PCH_I2C0_SCL
PCH_I2C0_SDA
PCH_UART1_RTS_L
PCH_UART1_RXD
PCH_UART1_TXD
TPAD_SPI_CS_L
TPAD_SPI_MOSI
AP_S0IX_WAKE_L
HDMITBTMUX_FLAG_L
JTAG_ISP_TDO
AP_RESET_L
XDP_PCH_GPIO76
XDP_LPCPLUS_GPIO
XDP_PCH_GPIO17
TBT_PWR_EN
XDP_MLB_RAMCFG1
XDP_MLB_RAMCFG3
PP3V3_S0
HDMITBTMUX_SEL_TBT
XDP_JTAG_ISP_TDI
SD_RESET_L
XDP_MLB_RAMCFG1
XDP_MLB_RAMCFG0
XDP_MLB_RAMCFG2
PP1V05_S0
PM_THRMTRIP_L
LPC_SERIRQ
TBT_CIO_PLUG_EVENT_L
PCH_GSPI0_CS_L
PCH_GSPI0_MISO
TPAD_SPI_MISO
PCH_UART1_CTS_L
PCH_UART1_RTS_L
PCH_I2C0_SDA
PCH_HSIO_PWR_EN
FW_PWR_EN
XDP_PCH_GPIO76
MEM_VDD_SEL_1V5_L
XDP_MLB_RAMCFG0
XDP_LPCPLUS_GPIO
JTAG_TBT_TMS_PCH
TPAD_SPI_IF_EN
XDP_MLB_RAMCFG3
CAMERA_PWR_EN_PCH
PCH_STRP_TOPBLK_SWP_L
LCD_PSR_EN
LCD_IRQ_L
ENET_MEDIA_SENSE
PCH_UART1_RXD
PCH_I2C1_SCL
PCH_I2C1_SDA
PCH_I2C0_SCL
PLT_RESET_L
TPAD_SPI_CLK
PCH_OPI_COMP
BT_PWRRST_L
ENET_MEDIA_SENSE
LCD_IRQ_L
PCH_UART1_TXD
PCH_GSPI0_MOSI
PCH_GSPI0_CLKXDP_PCH_GPIO17
TPAD_SPI_INT_L
SD_RESET_L
SMC_WAKE_SCI_L
SSD_PWR_EN
TPAD_USB_IF_EN
TPAD_SPI_INT_L
FW_PME_L
LPC_SERIRQ
JTAG_ISP_TDO
AP_S0IX_WAKE_SEL
FW_PME_L
SSD_RESET_L
HDD_PWR_EN
PP3V3_S5
LCD_PSR_EN
PCH_I2C1_SCL
TPAD_SPI_CLK
AP_S0IX_WAKE_L
TPAD_SPI_MISO
PP3V3_S0
TPAD_SPI_MOSI
XDP_JTAG_ISP_TCK
PLT_RESET_L
BT_PWRRST_L
TBT_POC_RESET_L
TBT_PWR_EN
SD_PWR_EN
XDP_SDCONN_STATE_CHANGE_L
HDD_PWR_EN
PCH_TBT_PCIE_RESET_L
SSD_PWR_EN
TPAD_USB_IF_EN
SMC_WAKE_SCI_L
PP3V3_S0
SPIROM_USE_MLB
PCH_TCO_TIMER_DISABLE
XDP_MLB_RAMCFG2
SSD_DEVSLP
16 OF 120
<E4LABEL>
<SCH_NUM>
<BRANCH>
15 OF 78
15 45 68 72
15 16 18
31 42
15
15 18
15 18
15 63
15 16
15 60
15 16
15 68
15 30
15 29
15 18 19 39 42 60 65 68
8 11 12 13 15 17 18 24 28 30 37
38 39 40 41 42 43 44 46 47 50
61 62 64 65 68 77
15 18 19 39 42 60 65 68
8 11 12 13 15 17 18 24 28 30 37
38 39 40 41
42 43 44 46 47 50 61 62 64 65
68
77
15 18 19 39 42 60 65 68
15 64
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15 16
15 16 45 68
15 16
15 23
15 16 18
8 11 12 13 15 17 18 24 28 30 37
38 39 40 41 42 43 44 46 47 50
61 62 64 65 68 77
15 16 18
15 16 18
15 16 18
6 8 11 16 17 37 53 57 60 61
65 68
15
15
15
15
15
15
15
15
15
15
15
15
72
15 68
15 68
15 62 68
15
15
15
15
15 63
15 36
15 30 60 61
15
15
15 68
15 36 45 68
15 18
15 68
8 11 13 16 17 18 26 27 29 56 59
60 61 65 68 77
15 62
15
15
15 29
15
8 11 12 13 15 17 18 24 28 30
37 38 39 40 41 42 43 44 46 47
50 61 62 64 65 68 77
15
15
8 11 12 13 15 17 18 24 28 30
37 38 39 40 41 42 43 44 46 47
50 61 62 64 65 68 77 www.rosefix.com

IN
IN
IN
IN
IN
IN
IN
IN
OUT
OUT
IN
OUT
IN
OUT
OUT
IN
NC
NC
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
TP
TP
TP
TP
TP
TP
OUT
OUT
OUT
G
D
S
G
D S
G
D S
G
D S
OUT
OUT
OUT
IN
OUT
IN
OUT
IN
IN
TP
OUT IN
BI
OUT
TP
TPBI
TPBI
TPBI
OUT
BI
IN OUT
OUT
OUT
OUT
BI
IN
BI
IN
OUT
IN OUT
BI
TP
IN
OUT
GND
VCC
NCNC
YA
NC
IN
NC
IN
TP
IN
TP
IN
IN
BI
IN
OUT
IN
IN
IN
IN
IN
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
87 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
D
SIZEDRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
NOTE: Should force PCH GPIO47 high to ensure TBT router powered to avoid leakage/clamping of signals.
These signals do not connect to XDP connector in this architecture, only accessible
via Top-Side Probe. Nets are listed here to show XDP associations and to make clear
what restrictions exist on PCH GPIOs when Top-Side Probe is used for PCH debug.
PCH/XDP Signals
USB Overcurrents are aliased, do not cause USB OC# events during PCH debug.
SDCONN_STATE_CHANGE_L is aliased, do not plug/unplug SD Cards during PCH debug.
PCH XDP Signals
VCC_OBS_AB
SSD_PCIEx_SEL_L straps are connected via 1K to common net.
LPCPLUS_GPIO is aliased, do not attempt use during PCH debug.
Unused & MLB_RAMCFGx GPIOs have TPs.
NOTE: Must not short XDP pins together!
Non-XDP Signals
NOTE: XDP_DBRESET_L pulled-up to 3.3V on PCH Support Page
TDI and TMS are terminated in CPU.
HOOK2
TDO
TRSTn
Merged (CPU/PCH) Micro2-XDP
OBSFN_D0
SCL
OBSDATA_D2
OBSDATA_A1
Use with 921-0133 Adapter Flex to
NOTE: This is not the standard XDP pinout.
TCK0
TCK1
SDA
HOOK1
HOOK3
OBSDATA_B3
OBSDATA_B2
PWRGD/HOOK0
OBSDATA_B1
OBSDATA_B0
OBSFN_B0
OBSDATA_A2
OBSDATA_A3
OBSFN_B1
OBSDATA_A0
TDI
TMS
ITPCLK/HOOK4
XDP_PRESENT#
DBR#/HOOK7
OBSDATA_D3
ITPCLK#/HOOK5
OBSFN_D1
OBSDATA_D1
OBSDATA_D0
OBSDATA_C2
OBSDATA_C3
OBSDATA_C1
OBSFN_C1
OBSDATA_C0
OBSFN_C0
518S0847
support chipset debug.
Extra BPM Testpoints
RESET#/HOOK6
VCC_OBS_CD
OBSFN_A1
OBSFN_A0
CPU JTAG Isolation
JTAG_ISP (non-TMS) nets are aliased, do not attempt bit-banged JTAG during PCH debug.
6 70
13 15 18
6 70
6 70
6 70
6 70
6 70
6 70
13 36 72
13 17 36 72
12 16 70
17 72
6 70
12 16 70
12 16 70
5% 2011/20WMF
XDP
1K
PLACE_NEAR=U0500.AG7:2.54mm
R1805 12
5% 201
1/20WMF
XDP
51
PLACE_NEAR=U0500.E60:28mm
R1813 21
5%
0
402MF-LF
XDP
1/16W
R1804 12
5%
0
02011/20W MF
XDP
PLACE_NEAR=U5000.J3:2.54mm
R1802 12
5% 201
1/20W MF
1K
XDP
PLACE_NEAR=U0500.C61:2.54mm
R1800 12
6 70
M-ST-SM1
CRITICAL
DF40RC-60DP-0.4V
XDP_CONN
J1800
1
10
1112
1314
1516
1718
19
2
20
2122
2324
2526
2728
29
3
30
3132
3334
3536
3738
39
4
40
4142
4344
4546
4748
49
5
50
5152
5354
5556
5758
59
6
60
6162
6364
78
9
6 70
6 70
6 70
6 70
6 70
6 70
6 70
6 70
6 70
6 70
TP-P6
TP1806
1
TP-P6
TP1807
1
TP-P6
TP1805
1
TP-P6
TP1804
1
TP-P6
TP1803
1
TP-P6
TP1802
1
8
5%
150
402
MF-LF
1/16W
R1830
1
2
5% 201
1/20WMF
51
XDP
PLACE_NEAR=U0500.F62:28mm
R1810 12
12 16 70
5%
XDP
MF-LF
402
1/16W
1K
R1831
1
2
5% 201
1/20WMF
51
PLACE_NEAR=U0500.AE62:28mm
NO STUFF
R1896 21
5% 2011/20WMF
51
XDP
PLACE_NEAR=U0500.AD62:28mm
R1892 21
5% 2011/20WMF
51
XDP
PLACE_NEAR=U0500.AD61:28mm
R1891 21
5% 2011/20WMF
XDP
51
PLACE_NEAR=U0500.AE61:28mm
R1890 21
5% 2011/20WMF
1K
PLACE_NEAR=U0500.AE63:28mm
NO STUFF
R1899 21
5%
0
02011/20W MF
XDP
PLACE_NEAR=J1800.58:28mm
R1835 12
12 16 70
PLACE_NEAR=J1800.57:28mm
XDP
SOT-563
DMN5L06VK-7
CRITICAL
Q1842
6
2
1
XDP
SOT-563
DMN5L06VK-7
CRITICAL
PLACE_NEAR=J1800.51:28mm
Q1840
3
5
4
PLACE_NEAR=J1800.55:28mm
CRITICAL
XDP
DMN5L06VK-7
SOT-563
Q1842
3
5
4
CRITICAL
XDP
DMN5L06VK-7
SOT-563
PLACE_NEAR=J1800.53:28mm
Q1840
6
2
1
6 12 16 70
6 70
6 70
6 16 70
XDP
CERM-X5R
0201
6.3V
0.1UF
10%
C1801
1
2
15 16 18
14
14 16 63
6 70
14 16 63
TP-P6
TP1870
1
14 16 33 14 16 33
15 18
14
TP-P6
TP1874
1
XDP
CERM-X5R
0201
6.3V
0.1UF
10%
C1800
1
2
TP-P6
TP1876
115 18
TP-P6
TP1877
115 18
TP-P6
TP1878
115 18
12
15
15 18 23
12
12
12
5% 2011/20WMF
1KR1881 12
5% 201
1/20WMF
1KR1882 12
6 70
5% 2011/20WMF
1KR1883 12
5% 201
1/20WMF
1KR1884 12
30
15 16 45 68
6 70
15
15 18 23
15 16 45 68
TP-P6
TP1887
1
XDP
CERM-X5R
0201
6.3V
0.1UF
10%
C1804
1
2
XDP
CERM-X5R
0201
6.3V
0.1UF
10%
C1806
1
2
6 70
6 12 16 70
5% 2011/20WMFPLACE_NEAR=U0500.AU62:28mm
NO STUFF
51R1897 21
74LVC1G07GF
SOT891
U1845
2
3
1 5
6
4
16V
0201
X5R-CERM
0.1UF
10%
C1845
1
2
6 70
5%
201
1/20W
MF
330K
R1845
1
2
17 36 61
TP-P6
TP1873
1
15 16 18
TP-P6
TP1886
1
6 70
6 70
14 19 39 63 68 72
14 19 39 63 68 72
6 16 70
6 70
8 17 70
6 70
6 70
6 70
SYNC_MASTER=J44
CPU/PCH Merged XDP
SYNC_DATE=08/12/2013
CPU_PWR_DEBUG
CPU_CFG<4>
XDP_SYS_PWROK
PP3V3_S5
ALL_SYS_PWRGD
PP5V_S0
XDP_PCH_TMS
XDP_PCH_TMS
XDP_CPUPCH_TRST_L
CPU_CFG<1>
XDP_PCH_TDO
XDP_PCH_TDI
XDP_CPU_PRESENT_L
MAKE_BASE=TRUE
XDP_CPUPCH_TRST_L
XDP_CPU_TCK
XDP_BPM_L<6>
XDP_BPM_L<7>
XDP_BPM_L<5>
XDP_BPM_L<4>
XDP_BPM_L<3>
XDP_BPM_L<2>
PP1V05_SUS
PCH_JTAGX
XDP_PCH_TDI
XDP_CPU_TDO
XDP_PCH_TDO
PP1V05_S0
XDP_CPU_PRDY_L
XDP_CPU_PREQ_L
CPU_CFG<0>
CPU_CFG<2>
XDP_BPM_L<1>
XDP_BPM_L<0>
CPU_CFG<5>
CPU_CFG<6>
CPU_CFG<7>
SMBUS_PCH_CLK
XDP_PCH_TCK
CPU_VCCST_PWRGD
XDP_CPU_PWRBTN_L
PP1V05_S0
CPU_CFG<3>
PM_PWRBTN_L
PCH_JTAGX
PM_PCH_SYS_PWROK
CPU_CFG<17>
CPU_CFG<16>
CPU_CFG<8>
CPU_CFG<9>
CPU_CFG<18>
CPU_CFG<12>
CPU_CFG<13>
CPU_CFG<14>
CPU_CFG<15>
XDP_CPURST_L PLT_RESET_L
XDP_CPU_TDO
XDP_CPUPCH_TRST_L
XDP_CPUPCH_TRST_L
XDP_CPU_TDI
XDP_CPU_TMS
CPU_CFG<10>
CPU_CFG<11>
CPU_CFG<19>
XDP_PCH_TCK
XDP_TRST_L
XDP_DBRESET_L
XDP_JTAG_CPU_ISOL_L
XDP_CPU_VCCST_PWRGD
XDP_CPU_TCK
SSD_PCIE_SEL_L
XDP_USB_EXTA_OC_L
XDP_USB_EXTB_OC_L
XDP_SDCONN_STATE_CHANGE_L
JTAG_ISP_TCK
XDP_LPCPLUS_GPIO
XDP_MLB_RAMCFG0
XDP_USB_EXTA_OC_L
MAKE_BASE=TRUE
XDP_USB_EXTB_OC_L
MAKE_BASE=TRUE
XDP_USB_EXTC_OC_L
MAKE_BASE=TRUE
XDP_SDCONN_STATE_CHANGE_L
XDP_USB_EXTD_OC_L
XDP_MLB_RAMCFG1
MAKE_BASE=TRUE
XDP_JTAG_ISP_TCK
XDP_SSD_PCIE1_SEL_L
XDP_PCH_GPIO76
MAKE_BASE=TRUE
XDP_JTAG_ISP_TDI
SMBUS_PCH_DATA
JTAG_ISP_TDI
MAKE_BASE=TRUE
XDP_LPCPLUS_GPIO
XDP_SSD_PCIE0_SEL_L
XDP_SSD_PCIE2_SEL_L
XDP_PCH_GPIO17
XDP_SSD_PCIE3_SEL_L
XDP_MLB_RAMCFG3
XDP_MLB_RAMCFG2
18 OF 120
<E4LABEL>
<SCH_NUM>
<BRANCH>
16 OF 78
72
8 11 13 15 17 18 26 27 29 56
59 60 61 65 68 77
17 32 41 44 45 53 54 58 60 61
65 68
12 16 70
6 12 16 70
6 12 16 70
6 16 70
59 65
12 16 70
12 16 70
6 16 70
12 16 70
6 8 11 15 16 17 37 53 57 60
61 65 68
72 6 8 11 15 16 17 37 53 57 60
61 65 68
12 16 70
70
70 www.rosefix.com

OUT
OUT
OUT
OUT
IN
IN
BIIN
OUT
IN
S
D
G
S
D
G
OUT
NC
NC
NC
OUT
IN
IN
NC
OUT
IN
NC
AY
NC NC
VCC
GND
NC
IN
OUT
IN
IN
Y
A
B
08
Y
A
B
08
OUT
OUT
OUT
IN
OUT
IN
YA
B
NC
GND
VCC
32.768K
GND
THRM
VOUT
X2
X1
25M_A
25M_B
25M_C
VIOE_25M_A
VIOE_25M_B
VIOE_25M_C
VG3HOT
NC
VDD
PAD
NC
NC
NC
NC
DESCRIPTION REFERENCE DES BOM OPTIONQTYPART NUMBER CRITICAL
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
87 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
D
SIZEDRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
NOTE: 30 PPM or better required for RTC accuracy
PCH 24MHz Crystal
System RTC Power Source & 32kHz / 25MHz Clock Generator
Chipset uses 24MHz crystal, GreenCLK kept to save 1x 25MHz crystal & 1x 32kHz crystal
Must be powered if any VDDIO is powered.
This looks a little ugly to support
PCH ME Disable Strap
For SB RTC Power
to reduce VBAT draw.
+V3.3A should be first
create VDD_RTC_OUT.
internally ORed to
VBAT and +V3.3A are
Coin-Cell: VBAT (300-ohm & 10uF RC)
No Coin-Cell: 3.42V G3Hot (no RC)
Coin-Cell & G3Hot: 3.42V G3Hot
GreenCLK 25MHz Power
TBT XTAL Power
Coin-Cell & No G3Hot: 3.3V S5
No Coin-Cell: 3.3V S5
No bypass necessary
PCH 24MHz Outputs
CAM XTAL Power
If high, ME is disabled. This allows for full re-flashing of SPI ROM.
Q1920 & 5V pull-up allows circuit to work regardless of HDA voltage.
PCH Reset Button
PCH uses HDA_SDO as a power-up strap. If low, ME functions normally.
IPD = 9-50k
VCCST (1.05V S0) PWRGD
SMC controls strap enable to allow in-field control of strap setting.
Memory VTT Enable Level-Shifter
CPU output is on VDDQ rail (1.2V), TPS51916 has 1.8V Vih(min).
33uW when driven-low
Vih(min) = 1.8V
TPS51916 I(leak) = +/- 1uA,
WF: Do we need this?
available ~3.3V power
PCH PWROK Generation
pin 5 must receive S5 power (Stuff R2042)
new and old parts. With GreenCLK Rev C
12 72
23 71
6.3V
20%
0201
1UF
X5R
C1902
1
2
X5R
1UF
20%
6.3V
0201
C1910
1
2
12PF
5% 25V0201
NP0-C0G-CERM
C1905
12
25V
12PF
NP0-C0G-CERM
0201
5%
C1906
12
17 36 68 72
45 68 72
22
PLACE_NEAR=U0500.AN15:5.1mm
MF
1/20W
201
5%
R1927
12
22
PLACE_NEAR=U0500.AP15:5.1mm
MF
1/20W
201
5%
R1926
12
12 72
12 72
13 36 68 72 16 72
10%
16V
X5R-CERM
0201
0.1UF
C1924
1
2
MF
1/20W
0201
0
5%
R1905
12
1M
MF
1/20W
201
5%
NO STUFF
R1906
1
2
XDP
MF
1/20W
0201
0
5%
R1996
12
402
NO STUFF
SILK_PART=SYS RESET
MF-LF
1/16W
0
5%
R1997
1
2
10K
MF
1/20W
201
5%
R1995
1
2
100K
MF
1/20W
201
5%
R1920
1
2
1K
MF
1/20W
201
5%
R1921
1
2
12 72
36
SOT-563
DMN5L06VK-7
Q1920
3
5
4
DMN5L06VK-7
SOT-563
Q1920
6
2
1
X5R-CERM
0201
16V
10%
0.1UF
C1922
1
2
32 71
1M
MF
1/20W
201
5%
R1916
1
2
MF
1/20W
0
5%
0201
R1915
12
25V
+/-0.1PF
0201
6.8PF
C0G
C1915
12
25V
+/-0.1PF
C0G
0201
6.8PF
C1916
12
12 72
12 72
12 17
8 16 70
10K
MF
1/20W
201
5%
R1931
1
2
0.1UF
10%
X5R-CERM
16V
0201
C1930
1
2
13 18 36 61 63 68
330K
MF
1/20W
201
5%
R1970
1
2
74AUP1G07GF
SOT891
U1970
2
3
1 5
6
4
X5R-CERM
0201
16V
10%
0.1UF
C1970
1
2
6
17 55
24 25 36 37 72
16 17 36 61
SOT833
74LVC2G08GT/S505
U1950
1
2
4
8
7
0.1UF
16V
0201
10%
X5R-CERM
BYPASS=U1950:5MM
C1950
1
2
CKPLUS_WAIVE=UNCONNECTED_PINS
SOT833
CKPLUS_WAIVE=UNCONNECTED_PINS
74LVC2G08GT/S505
U1950
5
6
4
8
3
MF
1/20W
0201
0
5%
R1963
2
1
NO STUFF
MF
1/20W
0201
0
5%
R1960
2
1
1K
MF
201
5%
1/20W
R1962
12
13 16 36 72
13 17 72
13 17 72
NO STUFF
MF
1/20W
0201
0
5%
R1951
12
10K
MF
1/20W
201
5%
R1950
1
2
10K
MF
1/20W
201
5%
R1955
1
2
8 53
8 17 53
8 17 53
100K
NO STUFF
MF
1/20W
201
5%
R1961
1
2
CRITICAL
SOT891
74AUP1G09
U1930
2
1
3
5
6
4
CKPLUS_WAIVE=PwrTerm2Gnd
TQFN
CRITICAL
SLG3NB148CV
U1900
9
8
15
12
7
10
16
2
17
5
13
11
6
14
1
4
3
24.000MHZ-20PPM-6PF
3.20X2.50MM-SM1
CRITICAL
Y1915
24
13
SM-3.2X2.5MM
25.000MHZ-12PF-20PPM
CRITICAL
OMIT
Y1905
24
13
SYNC_MASTER=J44 SYNC_DATE=08/12/2013
Chipset Support
1 Y1905197S0480 XTAL,25MHZ,20PPM,12PF,3.2X2.5X.6MM,85C
PP1V2_CAM_XTALPCIEVDD
PP3V3_S5RS3RS0_SYSCLKGEN
MAKE_BASE=TRUE
PM_PCH_PWROK
SYSCLK_CLK25M_TBT
SYSCLK_CLK25M_CAMERA
SYSCLK_CLK25M_X2_R
PPVRTC_G3H
MAKE_BASE=TRUE
LPC_CLK24M_SMC
LPC_CLK24M_SMC
NC_RTC_CLK32K_RTCX2
MAKE_BASE=TRUE NO_TEST=TRUE
PP3V3_S0
CPUVR_PGOOD_R
PM_PCH_PWROK
PM_S0_PGOOD
PM_PCH_SYS_PWROK
MEMVTT_PWR_EN
PP3V3_S0
MAKE_BASE=TRUE
MEMVTT_PWR_EN
PP1V35_S3
CPU_MEMVTT_PWR_EN_LSVDDQ
SPI_DESCRIPTOR_OVERRIDE_LS5V
PP5V_S0
SYS_PWROK_R
LPC_CLK24M_LPCPLUS_R
LPC_CLK24M_SMC_R
PCH_CLK24M_XTALOUT
LPC_CLK24M_LPCPLUS
HDA_SDOUT_R
SPI_DESCRIPTOR_OVERRIDE
SPI_DESCRIPTOR_OVERRIDE_L
PP1V5_S0SW_AUDIO_HDA
PP3V3_S0
PM_SYSRST_LXDP_DBRESET_L
PP3V42_G3H
CPU_VR_READY
CPU_VR_EN
CPU_VR_READY
MAKE_BASE=TRUE
ALL_SYS_PWRGD
SMC_DELAYED_PWRGD
PP1V05_S0
CPU_VCCST_PWRGD
PP3V3_S5
ALL_SYS_PWRGD
PCH_CLK24M_XTALOUT_R
PP3V42_G3H
PP3V3_TBTLC
PCH_CLK32K_RTCX1
NC_RTC_CLK32K_RTCX2
PP3V3_S5
PM_SLP_S3_L
SYSCLK_CLK25M_X2
SYSCLK_CLK25M_X1
PCH_CLK24M_XTALIN
<BRANCH>
<SCH_NUM>
<E4LABEL>
19 OF 120
17 OF 78
31
18
71
8 12 13 65
17 36 68 72
12 17
8 11 12 13 15 17 18 24 28 30
37 38 39 40 41 42 43 44 46 47
50 61 62 64 65 68 77
72
8 11 12 13 15 17 18 24 28 30 37
38 39 40 41 42 43 44 46 47 50
61 62 64 65 68 77
17 55
19 20 21 22 41 55 65 73
16 32 41 44 45 53 54 58 60 61
65 68
72
8 11 60
8 11 12 13 15 17 18 24 28 30
37 38 39 40 41 42 43 44 46 47
50 61 62 64 65 68 77
17 30 33 34 36 37 38 39 45 51
52 61 65 68
6 8 11 15 16 37 53 57 60 61 65
68
8 11 13 15 16 17 18 26 27 29
56 59 60 61 65 68 77
16 17 36 61
72
17 30 33 34 36 37 38 39 45 51
52 61 65 68
18 23 24 65
8 11 13 15
16 17 18 26 27 29 56 59 60
61 65 68 77
71
71 www.rosefix.com

S
D
G S D
G
OUT
OUT
OUT
OUT
IN
IN
IN
IN
S D
G
S D
G
IN
OUT
OUT
OUT
OUT IN
OUT
IN
OUT YA
B
NC
GND
VCC
NC
G
D
S
G
D
S
IN
OUT
IN
IN
NC
NC
08
OUT
IN
IN OUT
OUT
VCC
1A 1Y
2A 2Y
GND
IN
IN
OUT
OUT
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
87 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
D
SIZEDRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
Renaming the pins N61 and P61 to remove automatic diffpari property
Pin N61 needs a TP for Power to perform iFDIM test
S0 pull-up on PCH page
NOTE: Solution shown is for LPT-LP. Other PCH’s may require isolation on TCK
and TDI as well for PCH glitch-prevention.
NOTE: This reference schematic assumes PCH JTAG GPIOs are only used for
Thunderbolt. If other ASIC JTAG signals are wired into these GPIOs
different isolation techniques will likely be necessary.
Multi-router designs also require different circuitry.
RAM Configuration Straps
Pull-downs for chip-down RAM systems
To RR
To SMC
To PCH
Scrub for Layout Optimization
Unbuffered
R2041/2 should be stuffed for
Buffered
REDWOOD RIDGE PLUG_EVENT IS ACTIVE-LOW, ALWAYS DRIVEN (PULL-UP)
THUNDERBOLT PULL-UP
Power State Debug LEDs
(For development only)
MAKE_BASE
Platform Reset Connections
GreekCLK A or B depending on S2 rail
To PCH
From PCH
S0 pull-up on PCH page
SDCONN_STATE_CHANGE Isolation TBTLC can be on when S0 is off, and vice-versa
Redwood Ridge JTAG Isolation
Isolation ensures no leakage to RR or PCH
From RR
GreenCLK 25MHz Power
R2042 should be stuffed for GreenCLK C
RAMCFG3:L
10K
MF
1/20W
201
5%
R2050
1
2
10K
RAMCFG2:L
MF
1/20W
201
5%
R2051
1
2
RAMCFG1:L
10K
MF
1/20W
201
5%
R2052
1
2
RAMCFG0:L
10K
MF
1/20W
201
5%
R2053
1
2
SOT-563
DMN5L06VK-7
DBGLED
Q2090
6
2
1
SOT-563
DBGLED
DMN5L06VK-7
Q2090
3
5
4
PLACE_SIDE=BOTTOM
DBGLED
SILK_PART=S5_ON
LTQH9G-SM
GREEN-56MCD-2MA-2.65V
D2090
A
K
PLACE_SIDE=BOTTOM
DBGLED
SILK_PART=STBY_ON
LTQH9G-SM
GREEN-56MCD-2MA-2.65V
D2091
A
K
20K
DBGLED
MF
5%
201
1/20W
R2090
1
2
DBGLED
PLACE_SIDE=BOTTOM
1/16W
MF-LF
402
0
5%
R2094
12
20K
MF
1/20W
201
5%
DBGLED
R2091
1
2
DBGLED
PLACE_SIDE=BOTTOM
SILK_PART=S3_ON
LTQH9G-SM
GREEN-56MCD-2MA-2.65V
D2092
A
K
20K
DBGLED
MF
1/20W
201
5%
R2092
1
2
DBGLED
SILK_PART=S0I3_ON
PLACE_SIDE=BOTTOM
LTQH9G-SM
GREEN-56MCD-2MA-2.65V
D2093
A
K
20K
DBGLED
MF
1/20W
201
5%
R2093
1
2
15 16
15 16
15 16
15 16
26 27 60 61
13 18 29 36 61 63
13 17 36 61 63 68
20K
DBGLED
MF
1/20W
201
5%
R2095
1
2
SILK_PART=S0_ON
DBGLED
PLACE_SIDE=BOTTOM
LTQH9G-SM
GREEN-56MCD-2MA-2.65V
D2095
A
K
13 36
DMN5L06VK-7
SOT-563
DBGLED
Q2091
6
2
1
DMN5L06VK-7
SOT-563
DBGLED
Q2091
3
5
4
10%
0.1UF
16V
0201
X5R-CERM
C2071
1
2
CRITICAL
MC74VHC1G08
SC70-HF
U2071
3
2
1
4
5
100K
MF
1/20W
201
5%
R2070
1
2
MF
1/20W
0201
0
5%
R2072
12
13 15 16
MF
1/20W
0201
0
5%
R2071
12
33
MF
1/20W
201
5%
R2081
12
36
19
45 68
15 18 23 72
100K
MF
1/20W
201
5%
R2015
1
2
15 18 23 72
MF
1/20W
0201
0
5%
R2089
12
31
15 18 23
15 16
10%
0.1UF
6.3V
0201
CERM-X5R
BYPASS=U2030.5:5MM
C2031
1
2
SOT891
74AUP1G09
CRITICAL
U2031
2
1
3
5
6
4
SOT-563
DMN5L06VK-7
Q2030
3
5
4
DMN5L06VK-7
SOT-563
Q2030
6
2
1
470K
MF
1/20W
201
5%
R2031
1
2
470K
MF
1/20W
201
5%
R2032
1
2
63
15 18 23
MF
1/20W
0201
0
5%
R2030
12
13 18 29 36 61 63
15
SOT891
CRITICAL
NOSTUFF
74LVC1G08
U2030
2
1
35
6
4
10%
0.1UF
10V
0201
X5R-CERM
NOSTUFF
BYPASS=U2030:3mm
C2030
1
2
31
MF
1/20W
0201
0
5%
R2042
12
NO STUFF
MF
1/20W
0201
0
5%
R2040
12
I1608
NO STUFF
MF
1/20W
0201
0
5%
R2041
12
23
15
100K
MF
1/20W
201
5%
R2061
1
2
0.1UF
20%
10V
CERM
402
C2060
1
2
100K
MF
1/20W
201
5%
R2062
1
2
23
15
74LVC2G07
SOT891
U2060
1 6
3 4
25
16 18 23
16 18 23
16 18 23
16 18 23
SYNC_MASTER=J44 SYNC_DATE=08/12/2013
Project Chipset Support
VOLTAGE=3.3V
MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.25 MM
PP3V3_S5_DBGLED
DBGLED_S4DBGLED_S5
DBGLED_S4_D
PCH_TBT_PCIE_RESET_L
PLT_RST_BUF_L
JTAG_TBT_TMS
JTAG_TBT_TDOJTAG_TBT_TMS_PCH
PP3V3_TBTLC
JTAG_ISP_TDO
PP3V3_S4
DBGLED_S0
CAMERA_PWR_EN_PCH
PM_SLP_S4_L
SMC_PME_S4_DARK_L
PP3V3_S5
PP3V3_S3
PP3V3_S3
PP3V3_S0
PLT_RESET_L
PCA9557D_RESET_L
DBGLED_S3
PM_SLP_S4_L
PM_SLP_S3_L
LPCPLUS_RESET_L
DBGLED_S0_DDBGLED_S0I3_DDBGLED_S3_D
PP3V3_S5
S4_PWR_EN
PM_SLP_S0_L
DBGLED_S0I3
PP3V3_S0
TRUE TBT_CIO_PLUG_EVENT_L
PP3V3_S0
TBT_CIO_PLUG_EVENT_L
PP3V3_S5
PP3V3_S5RS3RS0_SYSCLKGEN
PP3V3_S5RS3RS0_SYSCLKGEN
MIN_NECK_WIDTH=0.2 MM
MAKE_BASE=TRUE
VOLTAGE=3.3V
MIN_LINE_WIDTH=0.5 MM
PCH_TBT_PCIE_RESET_L
MAKE_BASE=TRUE
CAM_PCIE_RESET_L
SMC_LRESET_L
SMC_PME_S4_DARK_L
XDP_SDCONN_STATE_CHANGE_L
SMC_PME_SDCONN
JTAG_ISP_TCK
SDCONN_STATE_CHANGE_RIO
XDP_MLB_RAMCFG1
XDP_MLB_RAMCFG0
XDP_MLB_RAMCFG3
XDP_MLB_RAMCFG2
JTAG_ISP_TDI
MAKE_BASE=TRUE
JTAG_ISP_TDI
JTAG_ISP_TCK
MAKE_BASE=TRUE
MAKE_BASE=TRUE
TP_CPU_RSVDN61
TP_CPU_RSVDP61
TP_CPU_RSVDN61
MAKE_BASE=TRUE
TP_CPU_RSVDP61
CAMERA_PWR_EN
<BRANCH>
<SCH_NUM>
<E4LABEL>
20 OF 120
18 OF 78
17 23 24 65
29 34 37 38 42 60 63 64 65 68
18 23 36 37
8 11 13 15 16 17 18 26 27 29
56 59 60 61 65 68 77
15 18 19 39 42 60 65 68
15 18 19 39 42 60 65 68
8 11 12 13 15 17 18 24 28 30
37 38 39 40 41 42 43 44 46 47
50 61 62 64 65 68 77
8 11 13
15 16 17
18 26 27
29 56 59
60 61 65
68 77
8 11 12 13 15 17 18 24 28 30
37 38 39 40 41 42 43 44 46 47
50 61 62 64 65 68 77
8 11 12 13
15 17 18 24
28 30 37 38
39 40 41 42
43 44 46 47
50 61 62 64
65 68 77
8 11 13 15 16 17 18 26 27 29
56 59 60 61 65 68 77
17 18
17 18
18 23 36 37
8 18
8 18
8 18
8 18 www.rosefix.com

OUT
V-
V+
V-
V+
IN
IN
IN
IN
G
D
S
G
D S
G
D S
G
D S
G
D S
G
D S
G
D S
G
D S
RESET*
A0
A1
A2
SCL
SDA
P0
P1
P2
P5
P6
P7
P3
P4
THRM
VCC
GND
PAD
NC
IN
BI
VDD
VOUTD
VOUTC
VOUTB
VOUTA
SCL
SDA
A0
A1
GND
IN
BI
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
87 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
D
SIZEDRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
FETs for CPU isolation during DAC margining
VREFCA. Split into two
DAC margining VREFCA ensure
NOTE: MEMVREG and SPARE share a
soft-resets and sleep/wake cycles.
NOTE: Margining will be disabled across all
watchdog will disable margining.
RST* on ’platform reset’ so that system
- =I2C_VREFDACS_SDA
3.53mV / step @ output
CPU-Based Margining
Addr=0x98(WR)/0x99(RD)
NOTE: CPU DAC output step sizes:
DDR3 (1.5V) 7.70mV per step
- DDRVREF_DAC - Stuffs DAC margining circuit.
BOM options provided by this page:
May not be necessary due to C22x0
EN RC’s to avoid drain glitches
to remove short due to CPU.
4.28mV / step @ output
Addr=0x30(WR)/0x31(RD)
+25uA - -25uA (- = sourced)
1.343V (DAC: 0x68)
0.972V - 1.714V (+/- 371mV)
DDR3L (1.35V)
0.000V - 2.694V (0x00 - 0xD1)
DDR3L assumes TPS51916 supply with 19.6k/57.6k divider
Always used, regardless
NOTE: LPDDR3 assumes TPS51916 supply with 28.7k/57.6k divider
+21uA - -21uA (- = sourced)
1.200V (DAC: 0x5D)
5
D
MEM VREG
0.000V - 2.397V (0x00 - 0xBA)
LPDDR3 (1.2V)
0.800V - 1.600V (+/- 400mV)
LPDDR3 (1.2V)
DAC Channel:
PCA9557D Pin:
MEM A VREF DQ 1
A
MEM B VREF DQ
B
2
MEM A VREF CA
C
3
MEM B VREF CA
DDR3L (1.35V)
C
4
6.36mV / step @ output 6.36mV / step @ output
+82uA - -82uA (- = sourced)
0.337V - 1.013V (+/- 337.5mV)
DAC output, cannot enable
+73uA - -73uA (- = sourced)
0.000V - 1.354V (0x00 - 0x69)
0.675V (DAC: 0x34)
0.000V - 1.199V (0x00 - 0x5D)
- =I2C_PCA9557D_SDA
- =I2C_PCA9557D_SCL
Power aliases required by this page:
Pins B1 & B4:
both at the same time!
(OD)
VREFMRGN_CPU_EN is low
- =I2C_VREFDACS_SCL
DAC range:
Nominal value
VRef current:
DAC step size:
- =PP3V3_S3_VREFMRGN
- =PPDDR_S3_MEMVREF
VRef Dividers
of margining option.
DAC sets voltage level, PCA9557 & FETs enable outputs
and disables margining after platform reset.
margining support. When
signals for independent DAC
NOTE: CPU has single output for
LPDDR3 (1.2V) ?.??mV per step
DDR3L (1.35V) 6.99mV per step
Signal aliases required by this page:
Page Notes
R22x6 pin 2:
(All 4 R’s)
0.600V (DAC: 0x2E.5)
0.300V - 0.900V (+/- 300mV)Margined target:
DAC-Based Margining
55
10%
6.3V
DDRVREF_DAC
CERM-X5R
0201
0.1UF
C2202
1
2
PLACE_NEAR=R7415.2:1mm1%
DDRVREF_DAC
1/20W
MF
33.2K
201
R2214
12
201
DDRVREF_DAC
MF
1/20W
100K
5%
R2213
1
2
201
DDRVREF_DAC
MF
1/20W
100K
5%
R2212
1
2
DDRVREF_DAC
CRITICAL
UCSP
MAX4253
CKPLUS_WAIVE=unconnected_pinsCKPLUS_WAIVE=unconnected_pins
U2204
A3
A2
A1
A4
B1
B4
CRITICAL
MAX4253
DDRVREF_DAC
UCSP
U2204
C3
C2
C1
C4
B1
B4
402
OMIT
NONE
NONE
NONE
SHORT
R2218
12
18
7 73
7 73
201
DDRVREF_DAC
100K
MF
5%
1/20W
R2202
1
2
7 73
201
DDRVREF_DAC
MF
1/20W
5%
100K
R2201
1
2
201
100K
5%
DDRVREF_DAC
1/20W
MF
R2225
12
10%
6.3V
DDRVREF_DAC
CERM-X5R
0201
0.1UF
C2225
1
2
10%
6.3V
DDRVREF_DAC
CERM-X5R
0201
0.1UF
C2245
1
2
201
1/20W
100K
5%
DDRVREF_DAC
MF
R2245
12
201
DDRVREF_DAC
100K
5%
1/20W
MF
R2265
12
10%
6.3V
DDRVREF_DAC
CERM-X5R
0201
0.1UF
C2265
1
2
10%
6.3V
CERM-X5R
0201
DDRVREF_DAC
0.1UF
C2285
1
2
201
DDRVREF_DAC
MF
1/20W
5%
100K
R2215
1
2
201
DDRVREF_DAC
100K
5%
1/20W
MF
R2285
12
201
DDRVREF_DAC
MF
1/20W
5%
100K
R2207
1
2
2011% 1/20W MF
DDRVREF_DAC
332
PLACE_NEAR=Q2225.1:2.54mm
R2226 12
2011% 1/20W MF
DDRVREF_DAC
332
PLACE_NEAR=Q2265.4:2.54mm
R2246 12
2011% 1/20W MF
DDRVREF_DAC
332
PLACE_NEAR=Q2265.1:2.54mmR2266 12
2011% 1/20W MF
DDRVREF_DAC
332
PLACE_NEAR=Q2225.4:2.54mm
R2286 12
201
1M
DDRVREF_DAC
5%
1/20W
MF
R2217
1
2
201
MF
1/20W
5%
100K
R2200
1
2
201
MF
1%
1/20W
PLACE_NEAR=Q2220.6:4mm
1K
R2221
1
2
201
24.9
1%
1/20W
MF
R2280
12
PLACE_NEAR=Q2220.3:2mm
6.3V
X5R-CERM
0201
0.022UF
10%
C2280
1
2
201
MF
1/20W
2
5%
R2283
12
201
PLACE_NEAR=Q2220.3:4mm
1%
1/20W
MF
1K
R2281
1
2
201
PLACE_NEAR=R2281.2:1mm
1K
1%
1/20W
MF
R2282
1
2
201
PLACE_NEAR=R2261.2:1mm
1%
1/20W
MF
1K
R2262
1
2
201
24.9
1%
1/20W
MF
R2260
12
201
2
1/20W
MF
5%
R2263
12
PLACE_NEAR=Q2260.6:2mm
10%
0.022UF
6.3V
0201
X5R-CERM
C2260
1
2
201
1%
1/20W
MF
PLACE_NEAR=Q2260.6:4mm
1K
R2261
1
2
201
PLACE_NEAR=R2241.2:1mm
1%
1/20W
MF
1K
R2242
1
2
201
1%
1/20W
MF
24.9
R2240
12
201
1/20W
MF
2
5%
R2243
12
10%
0.022UF
6.3V
PLACE_NEAR=Q2260.3:2mm
0201
X5R-CERM
C2240
1
2
201
1%
1/20W
MF
PLACE_NEAR=Q2260.3:4mm
1K
R2241
1
2
201
MF
1/20W
2
5%
R2223
12
201
PLACE_NEAR=R2221.2:1mm
1%
MF
1/20W
1K
R2222
1
2
201
24.9
1%
1/20W
MF
R2220
12
10%
0.022UF
6.3V
0201
X5R-CERM
PLACE_NEAR=Q2220.6:2mm
C2220
1
2
PLACE_NEAR=Q2220.6:2.54mm
CRITICAL
DMN5L06VK-7
DDRVREF_DAC
SOT-563
Q2225
6
2
1
PLACE_NEAR=Q2260.6:2.54mm
DMN5L06VK-7
SOT-563
CRITICAL
DDRVREF_DAC
Q2265
6
2
1
DMN5L06VK-7
DDRVREF_DAC
CRITICAL
SOT-563
Q2225
3
5
4
DDRVREF_DAC
CRITICAL
DMN5L06VK-7
SOT-563
Q2265
3
5
4
CRITICAL
DMN5L06VK-7
SOT-563
Q2220
6
2
1
DMN5L06VK-7
CRITICAL
SOT-563
Q2260
6
2
1
CRITICAL
DMN5L06VK-7
SOT-563
Q2220
3
5
4
CRITICAL
DMN5L06VK-7
SOT-563
Q2260
3
5
4
DDRVREF_DAC
PCA9557
QFN
CRITICAL
U2201
3
4
5
8
6
7
9
10
11
12
13
14
15
1
2
17
16
14 16 19 39 63 68 72
14 16 19 39 63 68 72
MSOP
DAC5574
CRITICAL
DDRVREF_DAC
U2200
9
10
3
6
7
8
1
2
4
5
14 16 19 39 63
68 72
14 16 19 39 63
68 72
10%
6.3V
DDRVREF_DAC
CERM-X5R
0201
0.1UF
C2201
1
2
6.3V
402-LF
DDRVREF_DAC
2.2UF
CERM
20%
C2200
1
2
10%
6.3V
DDRVREF_DAC
CERM-X5R
0201
0.1UF
C2205
1
2
SYNC_MASTER=J44
DDR3 VREF MARGINING
SYNC_DATE=08/12/2013
VREFMRGN_MEMVREG_BUF
MEM_VREFCA_B_RC
CPU_DIMM_VREFCA_B_ISOL
VREFMRGN_DQ_A_RDIV
VREFMRGN_CA_A_RDIV
VREFMRGN_CA_A_EN
PP0V675_S3_MEM_VREFDQ_A
MIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.2 mm
MIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.2 mm
PP0V675_S3_MEM_VREFDQ_B
VREFMRGN_DQ_A
VREFMRGN_CA_AB
PP3V3_S3
PP3V3_S3
VREFMRGN_SPARE_EN
VREFMRGN_MEMVREG_EN
VREFMRGN_SPARE_BUF
MEM_VREFDQ_B_RC
SMBUS_PCH_CLK
SMBUS_PCH_DATA
SMBUS_PCH_CLK
SMBUS_PCH_DATA
DDRREG_FB
VREFMRGN_DQ_B
VREFMRGN_MEMVREG
PCA9557D_RESET_L
MIN_NECK_WIDTH=0.2 mm
MIN_LINE_WIDTH=0.3 mm
PP0V675_S3_MEM_VREFCA_A
VREFMRGN_CA_B_EN_RC
CPU_DIMMB_VREFDQ
CPU_DIMM_VREFCA
VREFMRGN_CA_A_EN_RC
VREFMRGN_DQ_B_EN
VREFMRGN_DQ_B_EN_RC
MIN_NECK_WIDTH=0.2 mm
MIN_LINE_WIDTH=0.3 mm
PP3V3_S3_VREFMRGN_DAC
VOLTAGE=3.3V
MEM_VREFCA_A_RC
VREFMRGN_CA_B_RDIV
VREFMRGN_DQ_B_RDIV
VREFMRGN_CA_B_EN
VREFMRGN_DQ_A_EN
PP1V35_S3
MIN_NECK_WIDTH=0.2 mm
MIN_LINE_WIDTH=0.3 mm
PP0V675_S3_MEM_VREFCA_B
VREFMRGN_CPU_EN
CPU_DIMMA_VREFDQ
CPU_DIMMA_VREFDQ_A_ISOL
VREFMRGN_DQ_A_EN_RC
MEM_VREFDQ_A_RC
CPU_DIMMB_VREFDQ_B_ISOL
CPU_DIMM_VREFCA_A_ISOL
19 OF 78
<SCH_NUM>
22 OF 120
<E4LABEL>
<BRANCH>
73
20 65 73
21 65 73
15 18 19 39 42 60 65 68
15 18 19 39 42
60 65 68
20 65 73
17 20 21 22 41 55 65 73
21 65 73
73
73
73 www.rosefix.com

UDQS
UDQS*
LDQS*
LDQS
DQ15
DQ14
DQ13
DQ10
DQ12
DQ11
DQ9
DQ8
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
UDM
LDM
A14
VDD
A2
A3
A1
A0
NC
A6
ODT
RESET*
VSSQ
VSS
CAS*
RAS*
BA2
BA0
BA1
ZQ
CS*
CKE
A13
A11
A10/AP
A8
A4
A5
A9
CK
VREFCA
VREFDQ
CK*
WE*
A12/BC*
A7
VDDQ
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
UDQS
UDQS* LDQS*
LDQS
DQ15
DQ14
DQ13
DQ10
DQ12
DQ11
DQ9
DQ8
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
UDM
LDM
A14
VDD
A2
A3
A1
A0
NC
A6
ODT
RESET*
VSSQ
VSS
CAS*
RAS*
BA2
BA0
BA1
ZQ
CS*
CKE
A13
A11
A10/AP
A8
A4
A5
A9
CK
VREFCA
VREFDQ
CK*
WE*
A12/BC*
A7
VDDQ
UDQS
UDQS* LDQS*
LDQS
DQ15
DQ14
DQ13
DQ10
DQ12
DQ11
DQ9
DQ8
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
UDM
LDM
A14
VDD
A2
A3
A1
A0
NC
A6
ODT
RESET*
VSSQ
VSS
CAS*
RAS*
BA2
BA0
BA1
ZQ
CS*
CKE
A13
A11
A10/AP
A8
A4
A5
A9
CK
VREFCA
VREFDQ
CK*
WE*
A12/BC*
A7
VDDQ
NC
NC
NC
NC
NC
UDQS
UDQS* LDQS*
LDQS
DQ15
DQ14
DQ13
DQ10
DQ12
DQ11
DQ9
DQ8
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
UDM
LDM
A14
VDD
A2
A3
A1
A0
NC
A6
ODT
RESET*
VSSQ
VSS
CAS*
RAS*
BA2
BA0
BA1
ZQ
CS*
CKE
A13
A11
A10/AP
A8
A4
A5
A9
CK
VREFCA
VREFDQ
CK*
WE*
A12/BC*
A7
VDDQ
NC
NC
NC
NC
NC
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
87 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
D
SIZEDRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
SDRAM BYPASSING (NOTE: 4X 2.2UF AND 6X 0.1UF PER CHIP)
OMIT_TABLE
FBGA
MT41K256M16HA-125:E
4GB-DDR3L-1600-256MX16
U2300
N3
P7
L7
R7
N7
T3
T7
P3
N2
P8
P2
R8
R2
T8
R3
M2
N8
M3
K3
J7
K7
K9
L2
E3
F7
C8
C2
A7
A2
B8
A3
F2
F8
H3
H8
G2
H7
D7
C3
E7
F3
G3
J1
J9
L1
L9
M7
K1
J3
T2
D3
C7
B7
B2
D9
G7
K2
K8
N1
N9
R1
R9
A1
A8
C1
C9
D2
E9
F1
H2
H9
M8
H1
A9
B3
T1
T9
E1
G8
J2
J8
M1
M9
P1
P9
B1
B9
D1
D8
E2
E8
F9
G1
G9
L3
L8
1/20W
1%
MF
240
201
R2300
1 2
0.047UF
6.3V
X5R
201
10%
C2309
1
2
0.047UF
6.3V
X5R
201
10%
C2308
1
24V
20%
0.47UF
CERM-X5R-1
201
C2307
1
2
0.047UF
6.3V
X5R
201
10%
C2349
1
2
0.047UF
6.3V
X5R
201
10%
C2348
1
2
CERM-X5R-1
0.47UF
20%
4V
201
C2347
1
2
MT41K256M16HA-125:E
FBGA
OMIT_TABLE
4GB-DDR3L-1600-256MX16
U2340
N3
P7
L7
R7
N7
T3
T7
P3
N2
P8
P2
R8
R2
T8
R3
M2
N8
M3
K3
J7
K7
K9
L2
E3
F7
C8
C2
A7
A2
B8
A3
F2
F8
H3
H8
G2
H7
D7
C3
E7
F3
G3
J1
J9
L1
L9
M7
K1
J3
T2
D3
C7
B7
B2
D9
G7
K2
K8
N1
N9
R1
R9
A1
A8
C1
C9
D2
E9
F1
H2
H9
M8
H1
A9
B3
T1
T9
E1
G8
J2
J8
M1
M9
P1
P9
B1
B9
D1
D8
E2
E8
F9
G1
G9
L3
L8
OMIT_TABLE
FBGA
MT41K256M16HA-125:E
4GB-DDR3L-1600-256MX16
U2360
N3
P7
L7
R7
N7
T3
T7
P3
N2
P8
P2
R8
R2
T8
R3
M2
N8
M3
K3
J7
K7
K9
L2
E3
F7
C8
C2
A7
A2
B8
A3
F2
F8
H3
H8
G2
H7
D7
C3
E7
F3
G3
J1
J9
L1
L9
M7
K1
J3
T2
D3
C7
B7
B2
D9
G7
K2
K8
N1
N9
R1
R9
A1
A8
C1
C9
D2
E9
F1
H2
H9
M8
H1
A9
B3
T1
T9
E1
G8
J2
J8
M1
M9
P1
P9
B1
B9
D1
D8
E2
E8
F9
G1
G9
L3
L8
4V
20%
CERM-X5R-1
0.47UF
201
C2367
1
2
MT41K256M16HA-125:E
4GB-DDR3L-1600-256MX16
FBGA
OMIT_TABLE
U2320
N3
P7
L7
R7
N7
T3
T7
P3
N2
P8
P2
R8
R2
T8
R3
M2
N8
M3
K3
J7
K7
K9
L2
E3
F7
C8
C2
A7
A2
B8
A3
F2
F8
H3
H8
G2
H7
D7
C3
E7
F3
G3
J1
J9
L1
L9
M7
K1
J3
T2
D3
C7
B7
B2
D9
G7
K2
K8
N1
N9
R1
R9
A1
A8
C1
C9
D2
E9
F1
H2
H9
M8
H1
A9
B3
T1
T9
E1
G8
J2
J8
M1
M9
P1
P9
B1
B9
D1
D8
E2
E8
F9
G1
G9
L3
L8
0.047UF
6.3V
X5R
201
10%
C2368
1
2
0.047UF
6.3V
X5R
201
10%
C2369
1
2
CERM-X5R-1
0.47UF
20%
4V
201
C2327
1
2
0.047UF
6.3V
X5R
201
10%
C2328
1
2
0.047UF
6.3V
X5R
201
10%
C2329
1
2
10V
20%
402
X5R-CERM
2.2UF
C2331
1
2
10V
20%
402
X5R-CERM
2.2UF
C2330
1
2
10V
20%
402
X5R-CERM
2.2UF
C2321
1
2
10V
20%
402
X5R-CERM
2.2UF
C2320
1
2
10V
20%
402
X5R-CERM
2.2UF
C2311
1
2
10V
20%
402
X5R-CERM
2.2UF
C2310
1
2
10V
20%
402
X5R-CERM
2.2UF
C2301
1
2
10V
20%
2.2UF
X5R-CERM
402
C2300
1
2
10V
20%
402
X5R-CERM
2.2UF
C2371
1
2
10V
20%
402
X5R-CERM
2.2UF
C2370
1
2
10V
20%
402
X5R-CERM
2.2UF
C2361
1
2
10V
20%
402
X5R-CERM
2.2UF
C2360
1
2
10V
20%
402
X5R-CERM
2.2UF
C2351
1
2
10V
20%
402
2.2UF
X5R-CERM
C2350
1
2
10V
20%
402
X5R-CERM
2.2UF
C2341
1
2
10V
20%
402
X5R-CERM
2.2UF
C2340
1
2
6.3V
CERM-X5R
0201
0.1UF
10%
C2324
1
2
6.3V
CERM-X5R
0201
0.1UF
10%
C2323
1
2
6.3V
CERM-X5R
0201
0.1UF
10%
C2364
1
2
6.3V
CERM-X5R
0201
0.1UF
10%
C2363
1
2
6.3V
CERM-X5R
0201
0.1UF
10%
C2315
1
2
6.3V
CERM-X5R
0201
0.1UF
10%
C2314
1
2
6.3V
CERM-X5R
0201
0.1UF
10%
C2355
1
2
6.3V
CERM-X5R
0201
0.1UF
10%
C2354
1
2
6.3V
CERM-X5R
0201
0.1UF
10%
C2313
1
2
6.3V
CERM-X5R
0201
0.1UF
10%
C2353
1
2
6.3V
CERM-X5R
0201
0.1UF
10%
C2345
1
2
6.3V
CERM-X5R
0201
0.1UF
10%
C2305
1
2
6.3V
CERM-X5R
0201
0.1UF
10%
C2304
1
2
6.3V
CERM-X5R
0201
0.1UF
10%
C2344
1
2
6.3V
CERM-X5R
0201
0.1UF
10%
C2303
1
2
6.3V
CERM-X5R
0201
0.1UF
10%
C2343
1
2
6.3V
CERM-X5R
0201
0.1UF
10%
C2335
1
2
6.3V
CERM-X5R
0201
0.1UF
10%
C2375
1
2
6.3V
CERM-X5R
0201
0.1UF
10%
C2334
1
2
6.3V
CERM-X5R
0201
0.1UF
10%
C2333
1
2
6.3V
CERM-X5R
0201
0.1UF
10%
C2374
1
2
6.3V
CERM-X5R
0201
0.1UF
10%
C2373
1
2
6.3V
CERM-X5R
0201
0.1UF
10%
C2325
1
2
6.3V
CERM-X5R
0201
0.1UF
10%
C2365
1
2
240
MF
1%
1/20W
201
R2320
1 2
240
MF
1%
1/20W
201
R2340
1 2
240
MF
1%
1/20W
201
R2360
1 2
SYNC_DATE=MASTERSYNC_MASTER=MASTER
DDR3 SDRAM Bank A (Rank 0)
PP1V35_S3
=MEM_A_DQS_N<3>
MEM_RESET_L
MEM_A_ZQ<3>
MEM_RESET_L
MEM_A_ZQ<2>
MEM_RESET_L
MEM_A_ZQ<1>MEM_A_ZQ<0>
MEM_RESET_L
PP1V35_S3
=MEM_A_DQ<13>
=MEM_A_DQS_N<1>
MEM_A_A<3>
MEM_A_A<5>
MEM_A_A<6>
MEM_A_A<9>
MEM_A_A<12>
=MEM_A_DQ<0>
MEM_A_A<5>
MEM_A_A<4>
MEM_A_CLK_N<0>
MEM_A_CKE<0>
MEM_A_CS_L<0>
MEM_A_BA<2>
=MEM_A_DQ<30>
PP0V675_S3_MEM_VREFCA_A
PP0V675_S3_MEM_VREFDQ_APP1V35_S3
PP0V675_S3_MEM_VREFCA_A
PP0V675_S3_MEM_VREFDQ_APP1V35_S3
=MEM_A_DQS_P<3>
=MEM_A_DQS_N<2>
=MEM_A_DQS_P<2>
=MEM_A_DQ<31>
=MEM_A_DQ<29>
=MEM_A_DQ<26>
MEM_A_DQ<32>
=MEM_A_DQ<27>
=MEM_A_DQ<25>
=MEM_A_DQ<24>
=MEM_A_DQ<23>
=MEM_A_DQ<22>
=MEM_A_DQ<21>
=MEM_A_DQ<20>
=MEM_A_DQ<19>
=MEM_A_DQ<18>
=MEM_A_DQ<17>
=MEM_A_DQ<16>
MEM_A_A<14>
MEM_A_A<2>
MEM_A_A<3>
MEM_A_A<1>
MEM_A_A<0>
MEM_A_A<6>
MEM_A_ODT<0>
MEM_A_CAS_L
MEM_A_RAS_L
MEM_A_BA<2>
MEM_A_BA<0>
MEM_A_BA<1>
MEM_A_CS_L<0>
MEM_A_CKE<0>
MEM_A_A<13>
MEM_A_A<11>
MEM_A_A<10>
MEM_A_A<8>
MEM_A_A<9>
MEM_A_CLK_P<0>
MEM_A_CLK_N<0>
MEM_A_WE_L
MEM_A_A<12>
MEM_A_A<7>
=MEM_A_DQS_P<7>
=MEM_A_DQS_N<7>
MEM_A_DQS_N<6>
MEM_A_DQS_P<6>
=MEM_A_DQ<63>
=MEM_A_DQ<62>
=MEM_A_DQ<61>
=MEM_A_DQ<58>
=MEM_A_DQ<60>
=MEM_A_DQ<59>
=MEM_A_DQ<57>
=MEM_A_DQ<56>
=MEM_A_DQ<55>
=MEM_A_DQ<54>
=MEM_A_DQ<53>
=MEM_A_DQ<52>
=MEM_A_DQ<51>
=MEM_A_DQ<50>
=MEM_A_DQ<49>
=MEM_A_DQ<48>
MEM_A_A<14>
MEM_A_A<2>
MEM_A_A<3>
MEM_A_A<1>
MEM_A_A<0>
MEM_A_A<6>
MEM_A_ODT<0>
MEM_A_CAS_L
MEM_A_RAS_L
MEM_A_BA<2>
MEM_A_BA<0>
MEM_A_BA<1>
MEM_A_A<13>
MEM_A_A<11>
MEM_A_A<10>
MEM_A_A<8>
MEM_A_A<4>
MEM_A_A<5>
MEM_A_A<9>
MEM_A_CLK_P<0>
MEM_A_WE_L
MEM_A_A<12>
MEM_A_A<7>MEM_A_A<7>
MEM_A_A<12>
MEM_A_WE_L
MEM_A_CLK_N<0>
MEM_A_CLK_P<0>
MEM_A_A<9>
MEM_A_A<5>
MEM_A_A<4>
MEM_A_A<8>
MEM_A_A<10>
MEM_A_A<11>
MEM_A_A<13>
MEM_A_CKE<0>
MEM_A_CS_L<0>
MEM_A_BA<1>
MEM_A_BA<0>
MEM_A_RAS_L
MEM_A_CAS_L
MEM_A_ODT<0>
MEM_A_A<6>
MEM_A_A<0>
MEM_A_A<1>
MEM_A_A<3>
MEM_A_A<2>
MEM_A_A<14>
=MEM_A_DQ<32>
=MEM_A_DQ<33>
=MEM_A_DQ<34>
=MEM_A_DQ<35>
=MEM_A_DQ<36>
=MEM_A_DQ<37>
=MEM_A_DQ<38>
=MEM_A_DQ<39>
=MEM_A_DQ<40>
=MEM_A_DQ<41>
=MEM_A_DQ<43>
=MEM_A_DQ<44>
=MEM_A_DQ<42>
=MEM_A_DQ<45>
=MEM_A_DQ<46>
=MEM_A_DQ<47>
=MEM_A_DQS_P<4>
=MEM_A_DQS_N<4>
=MEM_A_DQS_N<5>
=MEM_A_DQS_P<5>
MEM_A_A<7>
MEM_A_WE_L
MEM_A_CLK_N<0>
MEM_A_CLK_P<0>
MEM_A_A<4>
MEM_A_A<8>
MEM_A_A<10>
MEM_A_A<11>
MEM_A_A<13>
MEM_A_CKE<0>
MEM_A_CS_L<0>
MEM_A_BA<1>
MEM_A_BA<0>
MEM_A_BA<2>
MEM_A_RAS_L
MEM_A_CAS_L
MEM_A_ODT<0>
MEM_A_A<0>
MEM_A_A<1>
MEM_A_A<2>
MEM_A_A<14>
=MEM_A_DQ<1>
=MEM_A_DQ<2>
=MEM_A_DQ<3>
=MEM_A_DQ<4>
=MEM_A_DQ<5>
=MEM_A_DQ<6>
=MEM_A_DQ<7>
=MEM_A_DQ<8>
=MEM_A_DQ<9>
=MEM_A_DQ<11>
=MEM_A_DQ<12>
=MEM_A_DQ<10>
=MEM_A_DQ<14>
=MEM_A_DQ<15>
=MEM_A_DQS_P<0>
=MEM_A_DQS_N<0>
=MEM_A_DQS_P<1>
PP0V675_S3_MEM_VREFDQ_A
PP0V675_S3_MEM_VREFCA_A
PP1V35_S3
PP0V675_S3_MEM_VREFDQ_A
PP0V675_S3_MEM_VREFCA_A
<BRANCH>
<SCH_NUM>
<E4LABEL>
23 OF 120
20 OF 78
17 19 20 21 22 41 55 65 73
67
20 21 22
70
20 21 22
70
20 21 22
70
20 21 22
70
17 19 20 21 22 41 55 65 73
67
67
20 22 66 73
20 22 66 73
7 20 22 66 73
20 22 66 73
20 22 66 73
67
20 22 66 73
20 22 66 73
7 20 22 73
7 20 22 73
7 20 22 73
20 22 66 73
67
19 20 65 73
19 20 65 73
17 19 20 21 22 41 55 65 73
19 20 65 73
19 20 65 73
17 19 20 21 22 41 55 65 73
67
67
67
67
67
67
7 67 68 73
67
67
67
67
67
67
67
67
67
67
67
20 22 66 73
20 22 66 73
20 22 66 73
20 22 66 73
20 22 66 73
7 20 22 66 73
20 22 73
7 20 22 66 73
7 20 22 66 73
20 22 66 73
20 22 66 73
7 20 22 66 73
7 20 22 73
7 20 22 73
20 22 66 73
20 22 66 73
20 22 66 73
20 22 66 73
20 22 66 73
7 20 22 73
7 20 22 73
7 20 22 66 73
20 22 66 73
20 22 66 73
67
67
7 67 73
7 67 73
67
67
67
67
67
67
67
67
67
67
67
67
67
67
67
67
20 22 66 73
20 22 66 73
20 22 66 73
20 22 66 73
20 22 66 73
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20 22 73
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7 20 22 66 73
20 22 66 73
20 22 66 73
7 20 22 66 73
20 22 66 73
20 22 66 73
20 22 66 73
20 22 66 73
20 22 66 73
20 22 66 73
20 22 66 73
7 20 22 73
7 20 22 66 73
20 22 66 73
20 22 66 73 20 22 66 73
20 22 66 73
7 20 22 66 73
7 20 22 73
7 20 22 73
20 22 66 73
20 22 66 73
20 22 66 73
20 22 66 73
20 22 66 73
20 22 66 73
20 22 66 73
7 20 22 73
7 20 22 73
7 20 22 66 73
20 22 66 73
7 20 22 66 73
7 20 22 66 73
20 22 73
7 20 22 66 73
20 22 66 73
20 22 66 73
20 22 66 73
20 22 66 73
20 22 66 73
67
67
67
67
67
67
67
67
67
67
67
67
67
67
67
67
67
67
67
67
20 22 66 73
7 20 22 66 73
7 20 22 73
7 20 22 73
20 22 66 73
20 22 66 73
20 22 66 73
20 22 66 73
20 22 66 73
7 20 22 73
7 20 22 73
7 20 22 66 73
20 22 66 73
20 22 66 73
7 20 22 66 73
7 20 22 66 73
20 22 73
20 22 66 73
20 22 66 73
20 22 66 73
20 22 66 73
67
67
67
67
67
67
67
67
67
67
67
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67
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67
19 20 65 73
19 20 65 73
17 19 20 21 22 41 55 65 73
19 20 65 73
19 20 65 73 www.rosefix.com

NC
NC
NC
NC
UDQS
UDQS*
LDQS*
LDQS
DQ15
DQ14
DQ13
DQ10
DQ12
DQ11
DQ9
DQ8
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
UDM
LDM
A14
VDD
A2
A3
A1
A0
NC
A6
ODT
RESET*
VSSQ VSS
CAS*
RAS*
BA2
BA0
BA1
ZQ
CS*
CKE
A13
A11
A10/AP
A8
A4
A5
A9
CK
VREFCA
VREFDQ
CK*
WE*
A12/BC*
A7
VDDQ
NC
NC
NC
NC
NC
UDQS
UDQS*
LDQS*
LDQS
DQ15
DQ14
DQ13
DQ10
DQ12
DQ11
DQ9
DQ8
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
UDM
LDM
A14
VDD
A2
A3
A1
A0
NC
A6
ODT
RESET*
VSSQ VSS
CAS*
RAS*
BA2
BA0
BA1
ZQ
CS*
CKE
A13
A11
A10/AP
A8
A4
A5
A9
CK
VREFCA
VREFDQ
CK*
WE*
A12/BC*
A7
VDDQ
UDQS
UDQS*
LDQS*
LDQS
DQ15
DQ14
DQ13
DQ10
DQ12
DQ11
DQ9
DQ8
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
UDM
LDM
A14
VDD
A2
A3
A1
A0
NC
A6
ODT
RESET*
VSSQ VSS
CAS*
RAS*
BA2
BA0
BA1
ZQ
CS*
CKE
A13
A11
A10/AP
A8
A4
A5
A9
CK
VREFCA
VREFDQ
CK*
WE*
A12/BC*
A7
VDDQ
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
UDQS
UDQS*
LDQS*
LDQS
DQ15
DQ14
DQ13
DQ10
DQ12
DQ11
DQ9
DQ8
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
UDM
LDM
A14
VDD
A2
A3
A1
A0
NC
A6
ODT
RESET*
VSSQ VSS
CAS*
RAS*
BA2
BA0
BA1
ZQ
CS*
CKE
A13
A11
A10/AP
A8
A4
A5
A9
CK
VREFCA
VREFDQ
CK*
WE*
A12/BC*
A7
VDDQ
NC
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
87 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
D
SIZEDRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
SDRAM BYPASSING (NOTE: 4X 2.2UF AND 6X 0.1UF PER CHIP)
1/20W
1%
MF
240
201
R2540
1 2
0.047UF
6.3V
X5R
201
10%
C2548
1
2
0.047UF
6.3V
X5R
201
10%
C2549
1
2
0.47UF
CERM-X5R-1
4V
20%
201
C2567
1
2
4GB-DDR3L-1600-256MX16
MT41K256M16HA-125:E
FBGA
OMIT_TABLE
U2540
N3
P7
L7
R7
N7
T3
T7
P3
N2
P8
P2
R8
R2
T8
R3
M2
N8
M3
K3
J7
K7
K9
L2
E3
F7
C8
C2
A7
A2
B8
A3
F2
F8
H3
H8
G2
H7
D7
C3
E7
F3
G3
J1
J9
L1
L9
M7
K1
J3
T2
D3
C7
B7
B2
D9
G7
K2
K8
N1
N9
R1
R9
A1
A8
C1
C9
D2
E9
F1
H2
H9
M8
H1
A9
B3
T1
T9
E1
G8
J2
J8
M1
M9
P1
P9
B1
B9
D1
D8
E2
E8
F9
G1
G9
L3
L8
MF
1%
1/20W
240
201
R2520
1 2
CERM-X5R-1
4V
20%
0.47UF
201
C2507
1
2
0.047UF
6.3V
X5R
201
10%
C2508
1
2
0.047UF
6.3V
X5R
201
10%
C2509
1
2
0.47UF
CERM-X5R-1
4V
20%
201
C2527
1
2
OMIT_TABLE
FBGA
MT41K256M16HA-125:E
4GB-DDR3L-1600-256MX16
U2560
N3
P7
L7
R7
N7
T3
T7
P3
N2
P8
P2
R8
R2
T8
R3
M2
N8
M3
K3
J7
K7
K9
L2
E3
F7
C8
C2
A7
A2
B8
A3
F2
F8
H3
H8
G2
H7
D7
C3
E7
F3
G3
J1
J9
L1
L9
M7
K1
J3
T2
D3
C7
B7
B2
D9
G7
K2
K8
N1
N9
R1
R9
A1
A8
C1
C9
D2
E9
F1
H2
H9
M8
H1
A9
B3
T1
T9
E1
G8
J2
J8
M1
M9
P1
P9
B1
B9
D1
D8
E2
E8
F9
G1
G9
L3
L8
OMIT_TABLE
MT41K256M16HA-125:E
FBGA
4GB-DDR3L-1600-256MX16
U2520
N3
P7
L7
R7
N7
T3
T7
P3
N2
P8
P2
R8
R2
T8
R3
M2
N8
M3
K3
J7
K7
K9
L2
E3
F7
C8
C2
A7
A2
B8
A3
F2
F8
H3
H8
G2
H7
D7
C3
E7
F3
G3
J1
J9
L1
L9
M7
K1
J3
T2
D3
C7
B7
B2
D9
G7
K2
K8
N1
N9
R1
R9
A1
A8
C1
C9
D2
E9
F1
H2
H9
M8
H1
A9
B3
T1
T9
E1
G8
J2
J8
M1
M9
P1
P9
B1
B9
D1
D8
E2
E8
F9
G1
G9
L3
L8
CERM-X5R-1
0.47UF
20%
4V
201
C2547
1
2
0.047UF
6.3V
X5R
201
10%
C2568
1
2
0.047UF
6.3V
X5R
201
10%
C2569
1
2
CERM-X5R
0201
6.3V
0.1UF
10%
C2565
1
2
CERM-X5R
0201
6.3V
0.1UF
10%
C2525
1
2
CERM-X5R
0201
6.3V
0.1UF
10%
C2543
1
2
CERM-X5R
0201
6.3V
0.1UF
10%
C2503
1
2
1/20W
MF
1%
240
201
R2500
1 2
0.047UF
6.3V
X5R
201
10%
C2528
1
2
0.047UF
6.3V
X5R
201
10%
C2529
1
2
10V
20%
402
X5R-CERM
2.2UF
C2540
1
2
10V
20%
2.2UF
X5R-CERM
402
C2500
1
2
CERM-X5R
0201
6.3V
0.1UF
10%
C2573
1
2
MT41K256M16HA-125:E
4GB-DDR3L-1600-256MX16
OMIT_TABLE
FBGA
U2500
N3
P7
L7
R7
N7
T3
T7
P3
N2
P8
P2
R8
R2
T8
R3
M2
N8
M3
K3
J7
K7
K9
L2
E3
F7
C8
C2
A7
A2
B8
A3
F2
F8
H3
H8
G2
H7
D7
C3
E7
F3
G3
J1
J9
L1
L9
M7
K1
J3
T2
D3
C7
B7
B2
D9
G7
K2
K8
N1
N9
R1
R9
A1
A8
C1
C9
D2
E9
F1
H2
H9
M8
H1
A9
B3
T1
T9
E1
G8
J2
J8
M1
M9
P1
P9
B1
B9
D1
D8
E2
E8
F9
G1
G9
L3
L8
CERM-X5R
0201
6.3V
0.1UF
10%
C2533
1
2
CERM-X5R
0201
6.3V
0.1UF
10%
C2544
1
2
CERM-X5R
0201
6.3V
0.1UF
10%
C2504
1
2
CERM-X5R
0201
6.3V
0.1UF
10%
C2574
1
2
CERM-X5R
0201
6.3V
0.1UF
10%
C2575
1
2
CERM-X5R
0201
6.3V
0.1UF
10%
C2534
1
2
CERM-X5R
0201
6.3V
0.1UF
10%
C2545
1
2
CERM-X5R
0201
6.3V
0.1UF
10%
C2535
1
2
CERM-X5R
0201
6.3V
0.1UF
10%
C2553
1
2
CERM-X5R
0201
6.3V
0.1UF
10%
C2505
1
2
CERM-X5R
0201
6.3V
0.1UF
10%
C2513
1
2
CERM-X5R
0201
6.3V
0.1UF
10%
C2554
1
2
CERM-X5R
0201
6.3V
0.1UF
10%
C2514
1
2
10V
20%
402
X5R-CERM
2.2UF
C2541
1
2
10V
20%
402
X5R-CERM
2.2UF
C2501
1
2
2.2UF
X5R-CERM
402
20%
10V
C2550
1
2
X5R-CERM
2.2UF
402
20%
10V
C2510
1
2
X5R-CERM
2.2UF
402
20%
10V
C2551
1
2
X5R-CERM
2.2UF
402
20%
10V
C2511
1
2
2.2UF
X5R-CERM
402
20%
10V
C2560
1
2
1/20W
1%
MF
240
201
R2560
1 2
2.2UF
X5R-CERM
402
20%
10V
C2520
1
2
CERM-X5R
0201
6.3V
0.1UF
10%
C2555
1
2
CERM-X5R
0201
6.3V
0.1UF
10%
C2515
1
2
10V
20%
402
X5R-CERM
2.2UF
C2561
1
2
10V
20%
402
X5R-CERM
2.2UF
C2521
1
2
CERM-X5R
0201
6.3V
0.1UF
10%
C2563
1
2
CERM-X5R
0201
6.3V
0.1UF
10%
C2523
1
2
CERM-X5R
0201
6.3V
0.1UF
10%
C2564
1
2
CERM-X5R
0201
6.3V
0.1UF
10%
C2524
1
2
10V
20%
402
X5R-CERM
2.2UF
C2570
1
2
10V
20%
402
X5R-CERM
2.2UF
C2530
1
2
X5R-CERM
2.2UF
10V
402
20%
C2571
1
2
X5R-CERM
2.2UF
402
10V
20%
C2531
1
2
SYNC_MASTER=MASTER SYNC_DATE=MASTER
DDR3 SDRAM BANK B (RANK 0)
MEM_B_CLK_N<0>
MEM_B_ODT<0>
MEM_B_CS_L<0>
MEM_B_CKE<0>
MEM_RESET_L
MEM_B_ZQ<2>
MEM_B_A<14>
MEM_B_A<6>
MEM_B_CAS_L
MEM_B_RAS_L
MEM_B_BA<0>
MEM_B_BA<1>
MEM_B_A<13>
MEM_B_A<11>
MEM_B_A<10>
MEM_B_A<8>
MEM_B_A<5>
MEM_B_A<9>
MEM_B_CLK_P<0>
MEM_B_WE_L
MEM_B_A<12>
MEM_B_A<7>
MEM_B_BA<2>
MEM_B_A<2>
MEM_B_A<3>
MEM_B_A<1>
MEM_B_A<0>
MEM_B_A<4>
MEM_B_ODT<0>
MEM_B_CAS_L
MEM_B_RAS_L
MEM_B_BA<2>
MEM_B_BA<0>
MEM_B_BA<1>
MEM_B_CS_L<0>
MEM_B_CKE<0>
MEM_B_CLK_P<0>
MEM_B_CLK_N<0>
MEM_B_WE_L
MEM_RESET_L
MEM_B_ZQ<0>
=MEM_B_DQS_P<5>
=MEM_B_DQS_N<5>
MEM_B_DQS_N<6>
MEM_B_DQS_P<6>
=MEM_B_DQ<47>
=MEM_B_DQ<46>
=MEM_B_DQ<45>
=MEM_B_DQ<42>
MEM_B_DQ<32>
=MEM_B_DQ<43>
=MEM_B_DQ<41>
=MEM_B_DQ<40>
=MEM_B_DQ<39>
=MEM_B_DQ<38>
=MEM_B_DQ<37>
=MEM_B_DQ<36>
=MEM_B_DQ<35>
=MEM_B_DQ<34>
=MEM_B_DQ<33>
=MEM_B_DQ<32>
PP1V35_S3
=MEM_B_DQS_P<1>
=MEM_B_DQS_N<0>
=MEM_B_DQS_P<0>
=MEM_B_DQ<15>
=MEM_B_DQ<14>
=MEM_B_DQ<10>
=MEM_B_DQ<12>
=MEM_B_DQ<11>
=MEM_B_DQ<9>
=MEM_B_DQS_N<1>
=MEM_B_DQ<13>
PP0V675_S3_MEM_VREFDQ_B
PP0V675_S3_MEM_VREFCA_B
MEM_B_A<14>
MEM_B_A<2>
MEM_B_A<1>
MEM_B_A<0>
MEM_B_A<13>
MEM_B_A<11>
MEM_B_A<10>
MEM_B_A<8>
MEM_B_A<4>
MEM_B_A<7>
MEM_B_A<12>
MEM_B_A<9>
MEM_B_A<6>
MEM_B_A<5>
MEM_B_A<3>
PP1V35_S3
=MEM_B_DQ<8>
=MEM_B_DQ<7>
=MEM_B_DQ<6>
=MEM_B_DQ<5>
=MEM_B_DQ<4>
=MEM_B_DQ<3>
=MEM_B_DQ<2>
=MEM_B_DQ<1>
=MEM_B_DQ<0>
PP0V675_S3_MEM_VREFDQ_B
PP0V675_S3_MEM_VREFCA_B
MEM_B_A<7>
MEM_B_A<12>
MEM_B_WE_L
MEM_B_CLK_P<0>
MEM_B_A<9>
MEM_B_A<5>
MEM_B_A<4>
MEM_B_A<8>
MEM_B_A<10>
MEM_B_A<11>
MEM_B_A<13>
MEM_B_BA<1>
MEM_B_BA<0>
MEM_B_BA<2>
MEM_B_RAS_L
MEM_B_CAS_L
MEM_B_ODT<0>
MEM_B_A<6>
MEM_B_A<0>
MEM_B_A<1>
MEM_B_A<3>
MEM_B_A<2>
MEM_B_A<14>
MEM_B_A<7>
MEM_B_A<12>
MEM_B_WE_L
MEM_B_CLK_N<0>
MEM_B_CLK_P<0>
MEM_B_A<9>
MEM_B_A<8>
MEM_B_A<10>
MEM_B_A<11>
MEM_B_A<13>
MEM_B_CKE<0>
MEM_B_CS_L<0>
MEM_B_BA<1>
MEM_B_BA<0>
MEM_B_BA<2>
MEM_B_RAS_L
MEM_B_CAS_L
MEM_B_ODT<0>
MEM_B_A<6>
MEM_B_A<0>
MEM_B_A<1>
MEM_B_A<3>
MEM_B_A<2>
MEM_B_A<14>
MEM_B_CS_L<0>
MEM_B_CKE<0>
MEM_B_CLK_N<0>
MEM_B_A<4>
MEM_B_A<5>
MEM_RESET_L
MEM_RESET_L
MEM_B_ZQ<1>
MEM_B_ZQ<3>
=MEM_B_DQS_N<7>
=MEM_B_DQS_P<7>
=MEM_B_DQ<48>
=MEM_B_DQ<49>
=MEM_B_DQ<50>
=MEM_B_DQ<51>
=MEM_B_DQ<52>
=MEM_B_DQ<53>
=MEM_B_DQ<54>
=MEM_B_DQ<55>
=MEM_B_DQ<56>
=MEM_B_DQ<57>
=MEM_B_DQ<59>
=MEM_B_DQ<60>
=MEM_B_DQ<58>
=MEM_B_DQ<61>
=MEM_B_DQ<62>
=MEM_B_DQ<63>
=MEM_B_DQS_P<6>
=MEM_B_DQS_N<6>
PP1V35_S3
PP0V675_S3_MEM_VREFDQ_B
PP0V675_S3_MEM_VREFCA_B
=MEM_B_DQ<25>
=MEM_B_DQ<27>
=MEM_B_DQ<28>
=MEM_B_DQ<26>
=MEM_B_DQ<29>
=MEM_B_DQ<31>
=MEM_B_DQS_P<2>
=MEM_B_DQS_N<2>
=MEM_B_DQS_N<3>
=MEM_B_DQS_P<3>
=MEM_B_DQ<30>
PP1V35_S3
=MEM_B_DQ<16>
=MEM_B_DQ<17>
=MEM_B_DQ<18>
=MEM_B_DQ<19>
=MEM_B_DQ<20>
=MEM_B_DQ<21>
=MEM_B_DQ<22>
=MEM_B_DQ<23>
=MEM_B_DQ<24>
PP0V675_S3_MEM_VREFDQ_B
PP0V675_S3_MEM_VREFCA_B
PP1V35_S3
<BRANCH>
<SCH_NUM>
<E4LABEL>
25 OF 120
21 OF 78
7 21 22 73
21 22 73
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20 21 22
70
21 22 66 73
7 21 22 66 73
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7 21 22 66 73
21 22 66 73
21 22 66 73
21 22 66 73
21 22 66 73
21 22 66 73
21 22 66 73
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21 22 66 73
21 22 66 73
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21 22 66 73
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21 22 66 73
21 22 66 73
21 22 73
7 21 22 66 73
7 21 22 66 73
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7 21 22 66 73
7 21 22 73
7 21 22 73
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7 21 22 66 73
20 21 22
70
67
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7 67 73
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17 19 20 21 22 41 55 65 73
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17 19 20 21 22 41 55 65 73
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19 21 65 73
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17 19 20 21 22 41 55 65 73 www.rosefix.com

IN
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Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
87 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
D
SIZEDRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
MEM_ODT:PU disconnect ODT from CPU, ODT pins on DRAM pulled up to 1.35V VDDQ.
Memory ODT Option
MEMORY RPACK SPARES
(Connects to DRAM)
(Connects to DRAM)
(Connects to CPU)
(Connects to CPU)
Memory CMD/CTL Termination - Channel B
Memory CMD/CTL Termination - Channel A
Memory Clock
Far-End Termination
Place RC end termination after last DRAMPlace Source C termination before first DRAM
Near-End Termination
Memory Reset Pull Up
Reset is an open drain in Haswell ULT and needs pull up
Memory Clock
MEM_ODT:CPU drives ODT from CPU, terminated to 0.675V VTT.
201
4V
0.47UF
20%
CERM-X5R-1
C2704
1
2
201
4V
0.47UF
CERM-X5R-1
20%
C2702
1
2
201
20%
0.47UF
4V
CERM-X5R-1
C2700
1
2
201
0.47UF
CERM-X5R-1
20%
4V
C2723
1
2
201
0.47UF
CERM-X5R-1
20%
4V
C2727
1
2
201
0.47UF
CERM-X5R-1
20%
4V
C2725
1
2
201
0.47UF
CERM-X5R-1
20%
4V
C2707
1
2
201
20%
0.47UF
CERM-X5R-1
4V
C2703
1
2
201
0.47UF
CERM-X5R-1
20%
4V
C2705
1
2
201
0.47UF
20%
4V
CERM-X5R-1
C2730
1
2
201
0.47UF
CERM-X5R-1
20%
4V
C2728
1
2
201
0.47UF
CERM-X5R-1
20%
4V
C2726
1
2
MEM_ODT:CPU
0.00
MF
0201
PLACE_NEAR=U0500.AP32:8MM
1%
1/20W
R2780
12
7 66
201
5%
36
MF
1/20W
MEM_ODT:CPU
R2781
12
20 73
201
MEM_ODT:PU
5%
36
1/20W
MF
R2782
12
201
36
MEM_ODT:PU
MF
1/20W
5%
R2792
12
201
MF
36
5%
MEM_ODT:CPU
1/20W
R2791
12
MF
0201
1/20W
1%
0.00
MEM_ODT:CPU
PLACE_NEAR=U0500.AL32:8MM
R2790
12
21 73
7 66
36
5%
4X0201
1/32W
RP2701
18
36
4X02011/32W5%
RP2701 27
5%1/32W 4X0201
36
RP2720 36
36
5%
1/32W
4X0201
RP2728
27
20 66 73
20 66 73
20 66 73
20 66 73
20 66 73
20 66 73
20 66 73
20 66 73
20 66 73
20 66 73
7 20 66 73
20 66 73
7 20 73
20 66 73
20 66 73
7 20 66 73
20 66 73
20 66 73
20 66 73
7 20 66 73
7 20 73
7 20 66 73
7 20 66 73
4X0201
36
5%1/32W
RP2701
45
1/32W
36
4X02015%
RP2705
18
5% 4X02011/32W
36RP2702
27
5%1/32W
36
4X0201
RP2706
27
5% 4X02011/32W
36RP2703
18
5%
36
1/32W 4X0201
RP2702
18
1/32W5% 4X0201
36RP2703
27
1/32W
36
4X02015%
RP2705
27
1/32W5% 4X0201
36RP2706
18
4X02015%
36
1/32W
RP2707
36
4X0201
1/32W
5%
36
RP2705
36
4X02011/32W5%
36RP2706
45
1/32W5% 4X0201
36RP2702
36
5% 4X0201
36
1/32W
RP2703
45
1/32W
36
5%
4X0201
RP2704
36
1/32W5%
36
4X0201
RP2707
27
36
5%
1/32W
4X0201
RP2704
18
1/32W5%
36
4X0201
RP2702
45
5%
36
1/32W 4X0201
RP2707
18
36
1/32W5% 4X0201
RP2703
36
1/32W
36
4X02015%
RP2705
45
1/32W5% 4X0201
36RP2707
45
4X0201
36
5%1/32W
RP2701
36
1/32W5% 4X0201
36RP2704
45
1/32W
5%
36
4X0201
RP2704
27
36
5%1/32W 4X0201
RP2706
36
7 21 66 73
21 66 73
21 66 73
7 21 66 73
21 66 73
21 66 73
21 66 73
21 66 73
21 66 73
21 66 73
21 66 73
21 66 73
21 66 73
21 66 73
7 21 73
7 21 66 73
7 21 66 73
7 21 73
1/32W5% 4X0201
36RP2722
27
1/32W5% 4X0201
36RP2728
18
1/32W5% 4X0201
36RP2725
18
36
1/32W5% 4X0201
RP2725
27
1/32W5% 4X0201
36RP2720
27
36
4X0201
1/32W
5%
RP2725
36
1/32W5% 4X0201
36RP2730
27
1/32W5% 4X0201
36RP2726
45
1/32W5% 4X0201
36RP2730
18
1/32W5% 4X0201
36RP2730
36
1/32W5% 4X0201
36RP2726
27
1/32W5% 4X0201
36RP2724
45
1/32W5% 4X0201
36RP2724
18
1/32W5% 4X0201
36RP2726
36
1/32W5% 4X0201
36RP2722
36
1/32W5% 4X0201
36RP2730
45
1/32W5% 4X0201
36RP2726
18
1/32W5% 4X0201
36RP2724
36
36
4X02015%1/32W
RP2725
45
1/32W5% 4X0201
36RP2724
27
36
5%
1/32W
4X0201
RP2720
45
1/32W5% 4X0201
36RP2722
18
1/32W5% 4X0201
36RP2720
18
36
4X0201
1/32W
5%
RP2728
45
5%
1/32W
4X0201
36
RP2728
36
1/32W5% 4X0201
36RP2722
45
21 66 73
21 66 73
21 66 73
7 21 66 73
21 66 73
7 22
7 22
7 22
7 22
7 22
7 22
7 21 22 73
7 21 22 73
7 20 22 73
7 20 22 73
5%
201
CERM
3.3PF
25V
C2760
1
2
5%
201
3.3PF
CERM
25V
C2750
1
2
7 21 22 73
7 21 22 73
7 20 22 73
7 20 22 73
30
MF
1/20W
201
5%
R2761
12
30
MF
1/20W
201
5%
R2760
12
30
MF
1/20W
201
5%
R2751
12
30
MF
1/20W
201
5%
R2750
12
MF
0201
1/20W
5%
0
R2711
12
201
4V
CERM-X5R-1
20%
0.47UF
NO STUFF
C2711
1
2
470
1%
1/20W
MF
201
R2710
1
2
10%
0.1UF
0201
CERM-X5R
6.3V
C2761
12
10%
0.1UF
0201
CERM-X5R
6.3V
C2751
12
CERM-X5R-1
201
0.47UF
20%
4V
C2724
1
2
201
0.47UF
CERM-X5R-1
20%
4V
C2722
1
2
201
4V
20%
CERM-X5R-1
0.47UF
C2720
1
2
201
0.47UF
CERM-X5R-1
20%
4V
C2710
1
2
201
0.47UF
CERM-X5R-1
20%
4V
C2708
1
2
201
CERM-X5R-1
20%
4V
0.47UF
C2706
1
2
SYNC_DATE=04/02/2013SYNC_MASTER=J44_YONAS-4GB
DDR3 Termination
PP0V675_S0_DDRVTT
MEM_B_CLK_N<0>
MEM_B_CLK_P<0>
MEM_A_CLK_N<0>
MEM_A_CLK_P<0>
MEM_B_CLK_P<0>
MEM_B_CLK_N<0>
MEM_A_CLK_P<0>
MEM_A_CLK_N<0> MEM_B_CLK0_TERM_R
MEM_RESET_HSW_L MEM_RESET_L
MEM_A_CLK0_TERM_R
PP1V35_S3
NO_TEST=TRUEMAKE_BASE=TRUE
NC_MEM_B_A15NC_MEM_B_A15
NO_TEST=TRUEMAKE_BASE=TRUE
NC_MEM_A_A15NC_MEM_A_A15
PP0V675_S0_DDRVTT
PP0V675_S0_DDRVTT
NO_TEST=TRUEMAKE_BASE=TRUE
NC_MEM_B_CS_L1
NC_MEM_B_CKE1
NC_MEM_B_CS_L1
NO_TEST=TRUEMAKE_BASE=TRUE
NC_MEM_B_CKE1
NC_MEM_A_CKE1
MEM_B_A<10>
MEM_B_A<12>
MEM_B_BA<1>
MEM_B_A<8>
MEM_B_A<6>
MEM_B_A<4>
MEM_B_A<11>
MEM_B_CKE<0>
MEM_B_A<7>
MEM_B_A<5>
MEM_B_A<3>
MEM_B_BA<0>
MEM_B_CS_L<0>
MEM_B_A<14>
MEM_B_A<1>
MEM_B_A<13>
MEM_B_A<9>
MEM_B_A<2>
MEM_B_A<0>
MEM_B_BA<2>
MEM_B_WE_L
MEM_B_CAS_L
MEM_B_RAS_L
PP1V35_S3
MEM_A_ODT<0>
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MEM_B_ODT<0>
MEM_A_ODT_CPU0
MEM_B_ODT_CPU0
MEM_A_RAS_L
MEM_A_CAS_L
MEM_A_WE_L
MEM_A_BA<2>
MEM_A_A<2>
MEM_A_A<9>
MEM_A_A<13>
MEM_A_BA<1>
MEM_A_A<4>
MEM_A_A<6>
MEM_A_A<1>
MEM_A_A<11>
MEM_A_CS_L<0>
MEM_A_BA<0>
MEM_A_A<3>
MEM_A_A<5>
MEM_A_CKE<0>
MEM_A_A<0>
MEM_A_A<14>
MEM_A_A<12>
MEM_A_A<10>
MEM_A_A<8>
NC_MEM_A_CKE1
NO_TEST=TRUEMAKE_BASE=TRUE
NO_TEST=TRUE
NC_MEM_A_CS_L1
MAKE_BASE=TRUE
NC_MEM_A_CS_L1
MEM_A_A<7>
<BRANCH>
<SCH_NUM>
<E4LABEL>
27 OF 120
22 OF 78
22 55 65 68 73
6 66 20 21 70
17 19 20 21 22 41 55 65 73
7 22
7 22
22 55 65 68 73
22 55 65 68 73
7 22
7 22
17 19 20 21 22 41 55 65 73
7 22
7 22 www.rosefix.com

OUT
OUT
IN
IN
IN
IN
OUT
OUT
OUT
IN
OUT
IN
IN
OUT
OUT
IN
IN
IN
OUT
IN
IN
OUT
OUT
OUT
BI
BI
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
BI
BI
OUT
IN
OUT
IN
IN
OUT
OUT
OUT
OUT
BI
BI
IN
IN
IN
IN
OUT
OUT
OUT
BI
BI
IN
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
IN
IN
IN
IN
IN
OUT
OUT
PORTS
MISC
(1 OF 2)
PCIE GEN2
DISPLAY PORT
DPSNK1_2_N
DPSNK1_2_P
DPSNK1_3_P
PERP_2
PERN_2
PETN_3
PETP_3
PETN_1
PETP_1
PETP_0
PETN_0
XTAL_25_OUT
XTAL_25_IN
EE_CS_N
DPSNK0_0_N
DPSNK0_0_P
DPSNK0_1_N
DPSNK0_1_P
DPSNK0_2_N
DPSNK0_2_P
DPSNK0_AUX_N
DPSNK0_AUX_P
DPSNK0_HPD
DPSNK1_0_N
DPSNK1_0_P
DPSNK1_1_N
DPSNK1_1_P
DPSNK1_3_N
DPSNK1_AUX_N
DPSNK1_AUX_P
DPSNK1_HPD
DPSRC_0_N
DPSRC_0_P
DPSRC_1_N
DPSRC_1_P
DPSRC_2_N
DPSRC_2_P
DPSRC_3_N
DPSRC_3_P
DPSRC_AUX_N
DPSRC_AUX_P
DPSRC_HPD_OD
EE_CLK
EE_DI
EE_DO
GPIO_0/PA_HV_EN/BYP0 GPIO_1/PB_HV_EN/BYP0
GPIO_10/PA_CIO_SEL/BYP1 GPIO_11/PB_CIO_SEL/BYP1
GPIO_12/PA_DP_PWRDN/BYP2 GPIO_13/PB_DP_PWRDN/BYP2
GPIO_14
GPIO_15
GPIO_2/TMU_CLK_IN/AC_PRESENT
GPIO_3/FORCE_PWR
GPIO_4/WAKE_OD_N
GPIO_5/CIO_PLUG_EVENT_N/HV_OK_OD
GPIO_6_OD/CIO_SDA_OD
GPIO_7_OD/CIO_SCL_OD
GPIO_8/EN_CIO_PWR_OD*
GPIO_9/SX_CTRL_OD*
MONDC0
MONOBSN
MONOBSP
PA_AUX_N
PA_AUX_P
PA_CIO0_RX_N
PA_CIO0_RX_P
PA_CIO0_TX_N/DPSRC_0_N
PA_CIO0_TX_P/DPSRC_0_P
PA_CIO1_RX_N
PA_CIO1_RX_P
PA_CIO1_TX_N/DPSRC_2_N
PA_CIO1_TX_P/DPSRC_2_P
PA_CONFIG1/CIO_0_LSEO
PA_CONFIG2/CIO_0_LSOE
PA_DPSRC_1_N
PA_DPSRC_1_P
PA_DPSRC_3_N
PA_DPSRC_3_P
PA_DPSRC_HPD
PA_LSRX/CIO_1_LSOE
PA_LSTX/CIO_1_LSEO
PB_AUX_N
PB_AUX_P
PB_CIO2_RX_N
PB_CIO2_RX_P
PB_CIO2_TX_N/DPSRC_0_N
PB_CIO2_TX_P/DPSRC_0_P
PB_CIO3_RX_N
PB_CIO3_RX_P
PB_CIO3_TX_N/DPSRC_2_N
PB_CIO3_TX_P/DPSRC_2_P
PB_CONFIG1/CIO_2_LSEO
PB_CONFIG2/CIO_2_LSOE
PB_DPSRC_1_N
PB_DPSRC_1_P
PB_DPSRC_3_N
PB_DPSRC_3_P
PB_DPSRC_HPD
PB_LSRX/CIO_3_LSOE
PB_LSTX/CIO_3_LSEO
PCIE_CLKREQ_OD_N
PCIE_RST_0_N
PCIE_RST_1_N
PCIE_RST_2_N
PCIE_RST_3_N
PERN_0
PERN_1
PERN_3
PERP_0
PERP_1
PERP_3
PERST_OD_N
PETN_2
PETP_2
PWR_ON_POC_RSTN
RBIAS
REFCLK_100_IN_N
REFCLK_100_IN_P
RSENSE
RSVD
TCK
TDI
TDO
TEST_EN
THERMDA
TMS
TMU_CLK_OUT
MONDC1
TEST_PWR_GOOD
DPSNK0_3_P
DPSNK0_3_N
VCC
DO/IO1
GNDTHRM_PAD
CS*
CLK
WP*
HOLD*
DI/IO0
IN
OUT
IN
IN
IN
IN
IN
IN
IN
IN
IN
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
87 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
D
SIZEDRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
DEBUG: For monitoring current/voltage
SNK0 AC Coupling
SNK1 AC Coupling
(TBT_SPI_MISO)(TBT_SPI_MOSI)
(TBT_SPI_CLK)
Used for straps in host mode
depends on the code in the flash.
bit in the flash, so the active-level
Security strap setting is XORed with
If strap != bit then security is enabled?
(TBT_SPI_CS_L)
Use AA8 GND ball for THERM_DN
DEBUG: For monitoring clock
Divides 3.3V to 1.8V
NOTE: The following pins require testpoints:
8 - GPIO_15
9 - GPIO_11
15 - PB_LSRX
14 - PB_LSTX
13 - GPIO_10
12 - GPIO_12
10 - GPIO_14
11 - GPIO_0
5 - PCIE_RST_1_N
0 - GPIO_13
3 - GPIO_3
2 - GPIO_2
4 - GPIO_5
1 - GPIO_1
7 - PCIE_RST_3_N
6 - PCIE_RST_2_N
For unused port, pull CONFIG1, CONFIG2, LSRX, HPD and CIO_SEL low (10k). All other port signals can be NC.
5%
3.3K
201
1/20W
MF
R2890
1
2
13
64
201
1/20W
MF
5%
100
R2825
1
2
26
26 68 74
26 68 74
26
26 68 74
26 68 74
26 68 74
26 68 74
26 68 74
26 68 74
27
27 68 74
27 68 74
27
27 68 74
27 68 74
27 68 74
27 68 74
27 68 74
27 68 74
5%
100K
201
1/20W
MF
R2830
1
2
5%
100K
201
1/20W
MF
R2831
1
2
26 74
26 74
5%
3.3K
201
1/20W
MF
R2893
1
2
10% 16V
X5R-CERM0.1UF
0201
C2829
12
13 74
13 74
5 74
5 74
5 74
5 74
5 74
5 74
5 74
5 74
16V10%
X5R-CERM0.1UF
0201
C2828
12
10% 16V
X5R-CERM0.1UF
0201
C2827
12
16V10%
X5R-CERM0.1UF
0201
C2826
12
10% 16V
X5R-CERM0.1UF
0201
C2825
12
16V10%
0.1UF X5R-CERM
0201
C2824
12
10% 16V
X5R-CERM0.1UF
0201
C2823
12
16V10%
X5R-CERM0.1UF
0201
C2822
12
MF
1/20W
201
1K
1%
R2855
1
2
10% 16V
X5R-CERM0.1UF
0201
C2821
12
10% 16V
X5R-CERM0.1UF
0201
C2820
12
10% 16V
X5R-CERM0.1UF
0201
C2830
12
10% 16V
X5R-CERM0.1UF
0201
C2831
12
10% 16V
X5R-CERM0.1UF
0201
C2832
12
10% 16V
X5R-CERM0.1UF
0201
C2833
12
10% 16V
0.1UF X5R-CERM
0201
C2834
12
10% 16V
X5R-CERM0.1UF
0201
C2835
12
10% 16V
X5R-CERM0.1UF
0201
C2836
12
10% 16V
X5R-CERM0.1UF
0201
C2837
12
10% 16V
X5R-CERM0.1UF
0201
C2838
12
10% 16V
0.1UF X5R-CERM
0201
C2839
12
64 74
64 74
64 74
64 74
64 74
64 74
64 74
64 74
402
CERM
6.3V
10%
1UF
BYPASS=U2890:2mm
C2890
1
2
64 74
64 74
26
26
27
27
15 18
27 74
27 74
27 74
27 74
27 74
27 74
27
16 18
18
16 18
18
26 74
26 74
26 74
26 74
26
23 25 26
26
23 26
23 27 28
27
23 27
23 24
18 36 37
12
17 71
806
1%
1/20W
MF
201
R2895
12
5%
1K
201
MF
1/20W
R2896
1
2
201
10K
NO STUFF
1/20W
5%
MF
R2899
1
2
12 68 70
12 68 70
24
0201
OMIT
NONE
NONE
NOSTUFF
NONE
R2815
1
2
MF
1/20W
201
10K
5%
R2888
1
2
5%
1/20W
MF
201
10K
R2887
1
2
10K
MF
1/20W
201
5%
NO STUFF
R2886
1
2
MF
1/20W
201
10K
5%
NO STUFF
R2885
1
2
5%
201
1/20W
MF
100K
R2880
1
2
15
23 28
15 18 72
100K
MF
1/20W
201
5%
R2883
1
2
OMIT_TABLE
CRITICAL
REDWOOD-RIDGE
FCBGA
U2800
D19
E20
D17
E18
D15
E16
D13
E14
G2
G4
AB5
D11
E12
D9
E10
D7
E8
D5
E6
H1
H3
U4
B9
A8
B11
A10
B13
A12
B15
A14
J2
J4
AC2
U8
T5
AA2
Y3
R8
N2 R2
P3 F3
T1
T3
F1
U2
L6
H5
Y7
Y1
T7
V7
M7
AD23
AC24
W16
W18
L2
L4
E22
G22
E24
G24
J22
L22
J24
L24
P1
K5
B17
A16
B19
A18
M3
J6
N8
K1
K3
N22
R22
N24
R24
U22
W22
U24
W24
D3
M1
B21
A20
B23
A22
N6
P7
M5
V3
W6
AB3
AD3
V1
AA10
AB13
AA16
AB19
AB9
AA12
AB15
AA18
P5
AD7
AD11
AD15
AD19
AD5
AD9
AD13
AD17
R4
W20
AD21
AB21
U20
AD1
L8
AA6
W2
U6
R6
W8
AB7
AB1
AA4
AA24
AB23
CRITICAL
OMIT_TABLE
W25X40CLXIG
4MBIT
USON
U2890
6
1
52
4
7
9
8
3
23 25
23 26 27
MF
1/20W
201
10K
5%
R2861
1
2
5%
10K
201
1/20W
MF
R2863
1
2
NO STUFF
5%
10K
201
1/20W
MF
R2867
1
2
5%
10K
201
1/20W
MF
R2862
1
2
100K
5%
201
1/20W
MF
R2881
1
2
5%
MF
1/20W
201
10K
R2829
1
2
5%
201
1/20W
MF
100K
R2884
1
2
100K
5%
201
1/20W
MF
R2882
1
2
15 23 64 66
5%
201
1/20W
MF
100K
R2878
1
2
100K
MF
1/20W
201
5%
R2879
1
2
100K
MF
1/20W
201
5%
R2832
1
2
X5R-CERM
16V
10%
0201
0.1UF
C2801
12
X5R-CERM
16V
0.1UF
10% 0201
C2800
12
X5R-CERM
16V
0.1UF
10% 0201
C2802
12
0.1UF
X5R-CERM
16V
10%
0201
C2803
12
5%
3.3K
201
1/20W
MF
R2892
1
2
16V
0201X5R-CERM10%
0.1UF
C2804
12
X5R-CERM
16V
10%
0.1UF
0201
C2805
12
X5R-CERM
16V
0.1UF
10% 0201
C2806
12
X5R-CERM
16V
0.1UF
10% 0201
C2807
12
0201
0.1UF
X5R-CERM10% 16V
C2840
12
0201
0.1UF
X5R-CERM10% 16V
C2841
12
0201
0.1UF
X5R-CERM10% 16V
C2842
12
5%
3.3K
201
1/20W
MF
R2891
1
2
0201
0.1UF
X5R-CERM10% 16V
C2843
12
0201
0.1UF
X5R-CERM10% 16V
C2845
12
0201X5R-CERM
0.1UF
10% 16V
C2844
12
0201X5R-CERM
0.1UF
16V10%
C2846
12
0201X5R-CERM
0.1UF
16V10%
C2847
12
14 68 70
14 68 70
14 68 70
14 68 70
14 68 70
14 68 70
14 68 70
14 68 70
14 68 70
14 68 70
14 68 70
14 68 70
14 68 70
14 68 70
14 68 70
14 68 70
Thunderbolt Host (1 of 2)
SYNC_MASTER=J44 SYNC_DATE=08/12/2013
TBT_B_CONFIG1_BUFTBT_A_CONFIG1_BUF
TBT_A_LSRX
DP_TBTPA_ML_C_P<3>
DP_TBTPA_ML_C_N<3>
DP_TBTPA_AUXCH_C_P
DP_TBTPA_AUXCH_C_N
DP_TBTPA_HPD
TBT_A_HV_EN
TBT_A_DP_PWRDN
PP3V3_TBTLC
TBT_GPIO2
TBT_GPIO7
DP_TBTSRC_HPD
DP_TBTSRC_HPD
PP3V3_S4_TBT
TBT_EN_CIO_PWR_L
HDMITBTMUX_SEL_TBT
TBT_DDC_XBAR_EN_L
TBTDP_AUXIO_EN
PP3V3_S4_TBT
TBT_BATLOW_L
TBT_B_HV_EN
TBT_A_DP_PWRDN
TBT_ROM_SECURITY_XOR
SMC_PME_S4_DARK_L
HDMITBTMUX_SEL_TBT
TBT_CIO_PLUG_EVENT_L
TBT_PWR_EN
TP_DP_TBTSRC_AUXCH_CP
JTAG_TBT_TMS
JTAG_ISP_TCK
JTAG_TBT_TDO
TBT_TEST_EN
TBT_TEST_PWR_GOOD
TBT_SPI_MOSI
TBT_SPI_CS_L
TBT_SPI_CLK
TBT_SPI_MISO
TBT_MONOBSP
TBT_MONOBSN
TP_TBT_MONDC1
PCIE_TBT_R2D_N<1>
DP_TBTSNK0_ML_P<1>
DP_TBTSNK0_ML_N<1>
TP_DP_TBTSRC_ML_CN<1>
TBT_A_R2D_C_P<0>
PP3V3_TBTLC
PCIE_TBT_R2D_P<2>
TBT_DFT_STRAP_1
TBT_DFT_STRAP_3
TBTDP_AUXIO_EN
TBT_BATLOW_L
TBTROM_WP_L
TBTROM_HOLD_L
DP_TBTSNK1_ML_N<2>
DP_TBTSNK1_ML_P<2>
DP_TBTSNK1_ML_P<3>
PCIE_TBT_R2D_N<2>
PCIE_TBT_D2R_C_N<3>
PCIE_TBT_D2R_C_P<3>
PCIE_TBT_D2R_C_N<1>
PCIE_TBT_D2R_C_P<1>
PCIE_TBT_D2R_C_P<0>
PCIE_TBT_D2R_C_N<0>
TP_TBT_XTAL25OUT
DP_TBTSNK0_ML_N<0>
DP_TBTSNK0_ML_P<0>
DP_TBTSNK0_ML_N<2>
DP_TBTSNK0_ML_P<2>
DP_TBTSNK0_AUXCH_N
DP_TBTSNK0_AUXCH_P
DP_TBTSNK0_HPD
DP_TBTSNK1_ML_N<0>
DP_TBTSNK1_ML_P<0>
DP_TBTSNK1_ML_N<1>
DP_TBTSNK1_ML_P<1>
DP_TBTSNK1_ML_N<3>
DP_TBTSNK1_AUXCH_N
DP_TBTSNK1_AUXCH_P
DP_TBTSNK1_HPD
TP_DP_TBTSRC_ML_CP<0>
TP_DP_TBTSRC_ML_CP<2>
TBT_B_HV_EN
TBT_A_CIO_SEL TBT_B_CIO_SEL
TBT_B_DP_PWRDN
TP_TBT_MONDC0
TBT_A_D2R_N<0>
TBT_A_D2R_P<0>
TBT_A_R2D_C_N<0>
TBT_A_D2R_N<1>
TBT_A_D2R_P<1>
TBT_A_R2D_C_N<1>
TBT_A_R2D_C_P<1>
TBT_A_CONFIG2_RC
DP_TBTPA_ML_C_N<1>
DP_TBTPA_ML_C_P<1>
TBT_A_LSTX
DP_TBTPB_AUXCH_C_N
DP_TBTPB_AUXCH_C_P
TBT_B_D2R_N<0>
TBT_B_D2R_P<0>
TBT_B_R2D_C_P<0>
TBT_B_D2R_N<1>
TBT_B_D2R_P<1>
TBT_B_R2D_C_N<1>
TBT_B_R2D_C_P<1>
TBT_B_CONFIG2_RC
DP_TBTPB_ML_C_N<1>
DP_TBTPB_ML_C_P<1>
DP_TBTPB_ML_C_N<3>
DP_TBTPB_ML_C_P<3>
DP_TBTPB_HPD
TBT_B_LSRX
TBT_B_LSTX
TP_TBT_PCIE_RESET0_L
PCIE_TBT_R2D_N<3>
PCIE_TBT_R2D_P<0>
PCIE_TBT_R2D_P<3>
PCIE_TBT_D2R_C_N<2>
PCIE_TBT_D2R_C_P<2>
TBT_RBIAS
PCIE_CLK100M_TBT_N
TBT_RSENSE
JTAG_ISP_TDI
TBTTHMSNS_D1_P
DP_TBTSNK0_ML_P<3>
DP_TBTSNK0_ML_N<3>
PCIE_TBT_D2R_P<2>
DP_TBTSNK0_AUXCH_C_P
DP_TBTSNK0_AUXCH_N
DP_TBTSNK0_ML_C_N<3> DP_TBTSNK0_ML_N<3>
DP_TBTSNK1_ML_C_P<3>
PCIE_TBT_D2R_P<3>
PCIE_TBT_R2D_C_P<1>
PCIE_TBT_R2D_C_N<1>
PCIE_TBT_R2D_C_N<2>
PCIE_TBT_R2D_C_P<2>
PCIE_TBT_R2D_C_P<0>
DP_TBTSNK1_ML_N<2>
DP_TBTSNK1_AUXCH_P
DP_TBTSNK1_ML_N<3>
DP_TBTSNK1_ML_P<3>
DP_TBTSNK1_ML_P<2>
DP_TBTSNK1_ML_P<1>
DP_TBTSNK0_ML_P<2>
DP_TBTSNK0_ML_N<2>
DP_TBTSNK0_ML_P<0>
DP_TBTSNK0_ML_N<0>
DP_TBTSNK0_ML_P<1>
DP_TBTSNK0_ML_N<1>
DP_TBTSNK1_AUXCH_C_N
DP_TBTSNK1_AUXCH_C_P
DP_TBTSNK1_ML_C_N<3>
DP_TBTSNK1_ML_C_P<2>
DP_TBTSNK1_ML_C_P<1>
DP_TBTSNK1_ML_C_N<0>
DP_TBTSNK1_ML_C_P<0>
DP_TBTSNK0_ML_C_P<3>
DP_TBTSNK0_ML_C_N<2>
DP_TBTSNK0_ML_C_P<2>
DP_TBTSNK0_ML_C_N<0>
PCIE_TBT_D2R_N<1>
PCIE_TBT_D2R_P<1>
PCIE_TBT_D2R_N<0>
PCIE_TBT_D2R_P<0>
DP_TBTSNK1_ML_N<1>
DP_TBTSNK1_ML_C_N<2>
DP_TBTSNK0_AUXCH_P
DP_TBTSNK1_AUXCH_N
PCIE_TBT_R2D_C_N<3>
DP_TBTSNK1_ML_P<0>
DP_TBTSNK0_ML_C_N<1>
DP_TBTSNK0_ML_C_P<1>
DP_TBTSNK0_AUXCH_C_N
DP_TBTSNK1_ML_C_N<1>
DP_TBTSNK1_ML_N<0>
DP_TBTSNK0_ML_P<3>
PCIE_TBT_R2D_C_P<3>
PCIE_TBT_D2R_N<2>
PCIE_TBT_D2R_N<3>
DP_TBTSNK0_ML_C_P<0>
PP3V3_TBTLC
SYSCLK_CLK25M_TBT
PCIE_TBT_R2D_N<0>
PCIE_TBT_R2D_P<1>
TBT_EN_CIO_PWR_L
TBT_B_R2D_C_N<0>
TBT_DDC_XBAR_EN_L
PCIE_TBT_R2D_C_N<0>
TP_DP_TBTSRC_ML_CP<1>
TP_DP_TBTSRC_ML_CN<2>
TP_DP_TBTSRC_ML_CN<3>
TP_DP_TBTSRC_ML_CP<3>
TBT_TMU_CLK_OUT
PCH_TBT_PCIE_RESET_L
TBT_PWR_ON_POC_RST_L
PCIE_CLK100M_TBT_P
SYSCLK_CLK25M_TBT_R
TBT_A_HV_EN
TBT_B_DP_PWRDN
TP_DP_TBTSRC_AUXCH_CN
TP_DP_TBTSRC_ML_CN<0>
PP3V3_TBTLC
TBT_CLKREQ_L
23 OF 78
28 OF 120
<E4LABEL>
<SCH_NUM>
<BRANCH>
17 18 23 24 65
23
23
23 24 25 42 65
23 24
15 23 64 66
23 28
23 26 27
23 24 25 42 65
23 25
23 27 28
23 26
74
74
74
74
68 70
23 74
23 74
17 18 23 24 65
68
70
23 74
23 74
23 74
68 70
68
70
68
70
68
70
68 70
70
70
23 74
23 74
23 74
23 74
23 74
23 74
23 74
23 74
23 74
23 74
23 74
23 74
23 74
68 70
68
70
68
70
68
70
68
70
43 77
23 74
23 74
23 74
23 74
23 74
23 74
23 74
23 74
23 74
23 74
23 74
23 74
23 74
23 74
23 74
23 74
23 74
23 74
23 74
23 74
23 74
23 74
17 18 23 24 65
68 70
68
70
71
23 25 26
23 27
17 18 23 24 65 www.rosefix.com

GND
VCC
(2 OF 2)
VSSVSS
VCC3P3_RDV_DECAP
VCC3P3_LC
VCC3P3
VCC1P0_RDV_DECAP
VCC1P0_CIO
SVR_VCC1P0
SVR_AMON
SVR_IND0
NC
S
D
G
VOUT
GND
ON
VIN
IN
OUTIN
IN
D
SYM_VER_3
SG
G
D
S
OUT
GND
SENSE
ENABLE SENSE_OUT
CT
VCC
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
87 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
D
SIZEDRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
U2950
TPS22920
Push-pull output
Isolated to reduce noise from SVR
Part
Type
R(on)
@ 1.05V
Max Current = 4A (85C)
8 mOhm Typ
11.5 mOhm Max
Load Switch
Pull-up (S0) on PCH page
1.05V TBT "CIO" Switch
EDP: 1.25 A
25 mA EDP
1200 mA EDP700 mA EDP
1900 mA EDP
SVR input to RR - 1100 mA EDP
POC input to RR - 150 mA EDP
2.4 W (Single-Port)
3.1 W (Dual-Port)
100 mA EDP
Internal switch not functional on RR.
Delay = 4.04ms nominal
TBT "POC" Power-up Reset
Vth = 2.508V nominal
EDP current / power consumption figures copied from R68 schematic (Rev 2, dated October 28, 2012, not available on IBL).
20%
1.0UF
X5R
6.3V
0201-1
C2906
1
2
FCBGA
REDWOOD-RIDGE
OMIT_TABLE
CRITICAL
U2800
B5
A4
A6
B3
J8
K9
L14
M15
M17
P17
V19
J10
J12
R14
T11
T15
U10
U14
V11
K11
L10
M11
N10
N14
P11
P15
R10
G10
G12
K19
K7
L16
M19
P19
T19
U18
V15
V17
W12
G14
W14
G16
G18
H19
H9
J18
K15
K17
D1
E2
H11
N4
V5
W4
Y5
H13
H15
H17
H7
L18
N18
R18
W10
A2
A24
AC14
AC16
AC18
AC20
AC22
AC4
AC6
AC8
B1
B7
AA14
C10
C12
C14
C16
C18
C2
C20
C22
C24
C4
AA20
C6
C8
D21
D23
E4
F11
F13
F15
F17
F19
AA22
F21
F23
F5
F7
F9
G20
G6
G8
H21
H23
AA8 J14
J16
J20
K13
K21
K23
L12
L20
M13
M21
AB11
M23
M9
N12
N16
N20
P13
P21
P23
P9
R12
AB17
R16
R20
T13
T17
T21
T23
T9
U12
U16
V13
AC10
V21
V23
V9
Y11
Y13
Y15
Y17
Y19
Y21
Y23
AC12
Y9
20%
1.0UF
X5R
6.3V
0201-1
C2911
1
2
0201-1
X5R
6.3V
1.0UF
20%
C2910
1
2
SM
680NH-30%-3.6A-35MOHM
CRITICAL
L2920
12
6.3V
CERM-X5R
0402-1
10UF
20%
C2922
1
2
6.3V
CERM-X5R
0402-1
10UF
20%
C2923
1
2
NSR1020MW2T1G
SOD-323
CRITICAL
D2920
A
K
DMN5L06VK-7
SOT-563
Q2945
6
2
1
100K
201
MF
1/20W
5%
R2945
1
2
CSP
TPS22920
CRITICAL
U2940
D1
D2
A2
B2
C2
A1
B1
C1
20%
X5R
6.3V
0201-1
1.0UF
C2940
1
2
20%
1.0UF
X5R
6.3V
0201-1
C2981
1
2
20%
1.0UF
X5R
6.3V
0201-1
C2980
1
2
0201-1
6.3V
X5R
20%
1.0UF
C2970
1
2
23
0201-1
6.3V
X5R
1.0UF
20%
C2960
1
2
20%
1.0UF
X5R
6.3V
0201-1
C2961
1
2
20%
10UF
0402-1
CERM-X5R
6.3V
C2953
1
2
6.3V
CERM-X5R
0402-1
10UF
20%
C2952
1
2
6.3V
CERM-X5R
0402-1
10UF
20%
C2951
1
2
6.3V
CERM-X5R
0402-1
10UF
20%
C2950
1
2
PLACE_NEAR=C2953.1:1mm
SM
XW2960
1
2
23
X7R-CERM
0201
10%
330PF
16V
C2995
1
2
1/20W
MF
201
24.9K
1%
R2991
1
2
X5R
10%
0.1UF
25V
402
C2990
1
2
15
MF
201
100K
1/20W
5%
R2995
1
2
17 25 36 37 72
100K
1/20W
MF
201
5%
R2990
1
2
DFN1006H4-3
DMN32D2LFB4
Q2995
3
1
2
X7R-CERM
10%
50V
0.001UF
0402
C2991
1
2
SOT-563
DMN5L06VK-7
Q2945
3
5
4
13
TPS3895ADRY
USON
CRITICAL
U2990
5
1
2
3
4
6
1/20W
100K
201
MF
5%
R2992
1
2
0201-1
6.3V
X5R
1.0UF
20%
C2903
1
2
20%
10UF
0402-1
CERM-X5R
6.3V
C2920
1
2
6.3V
CERM-X5R
0402-1
10UF
20%
C2921
1
2
20%
6.3V
X5R
0201-1
1.0UF
C2904
1
2
20%
1.0UF
X5R
6.3V
0201-1
C2905
1
2
0201-1
6.3V
X5R
1.0UF
20%
C2900
1
2
1.0UF
X5R
6.3V
20%
0201-1
C2901
1
2
0201-1
6.3V
X5R
1.0UF
20%
C2902
1
2
20%
1.0UF
X5R
6.3V
0201-1
C2932
1
2
20%
1.0UF
X5R
6.3V
0201-1
C2931
1
2
20%
1.0UF
X5R
6.3V
0201-1
C2930
1
2
Thunderbolt Host (2 of 2)
SYNC_MASTER=J44 SYNC_DATE=08/12/2013
TBT_POC_RESET_L TBTPOCRST_MR_L
SMC_DELAYED_PWRGD
PP3V3_S0
PP3V3_S4_TBT
TBTPOCRST_SENSE
TBT_PWR_REQ_L
PP3V3_S0
PP1V05_TBT
MIN_NECK_WIDTH=0.20 MM
MIN_LINE_WIDTH=0.50 MM
VOLTAGE=1.05V
PP3V3_S4_TBT
PP3V3_S4_TBT_F
VOLTAGE=3.3V
MIN_NECK_WIDTH=0.20 MM
MIN_LINE_WIDTH=0.38 MM
PP1V05_TBTCIO
VOLTAGE=1.05V
MIN_NECK_WIDTH=0.2 mm
MIN_LINE_WIDTH=0.4 mm
MIN_LINE_WIDTH=0.50 MM
SWITCH_NODE=TRUE
DIDT=TRUE
MIN_NECK_WIDTH=0.20 MM
P1V05TBT_SW
MIN_LINE_WIDTH=0.38 MM
MIN_NECK_WIDTH=0.20 MM
PP3V3_TBTRDV
VOLTAGE=3.3V
PP1V05_TBTRDV
MIN_LINE_WIDTH=0.38 MM
VOLTAGE=1.05V
MIN_NECK_WIDTH=0.20 MM
PP1V05_TBT
TBT_EN_CIO_PWR
TBT_EN_CIO_PWR_L
TBTPOCRST_CT
TBT_PWR_ON_POC_RST_L
MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=3.3V
PP3V3_TBTLC
PP3V3_TBTLC
<BRANCH>
<SCH_NUM>
<E4LABEL>
29 OF 120
24 OF 78
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37 38 39 40 41 42 43 44 46 47
50 61 62 64 65 68 77
24
23 24 25 42 65
24
17 18 23 24 65
17 18 23 24 65 www.rosefix.com

IN
S
G
D
NC
VIN
FBX
EN/UVLO
INTVCC
VC
RT
SS
SYNC
SW
SGND GND
NC
SNS1
SNS2
IN
SYM_VER_2
GS
D
S
D
G
S D
G
OUT
D
SYM_VER_3
SG
IN
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
87 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
D
SIZEDRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
UVLO(rising) = UVLO(falling) + (2uA * R1)
UVLO(falling) = 1.22 * (R1 + R2) / R2
Thunderbolt 15V Boost Regulator
Vgs(th): -1.4V
Vgs(max): +/-12V
Vds(max): -30V
SI8409DB:
FREQ = 480KHZ
Max Current = 2A?
Vout = 15.47V
<R1>
Id(max): 3.7A @ 70C
<Ra>
<Rb>
Vout = 1.6V * (1 + Ra / Rb)
no XW necessary.
GND inside package,
SGND shorted to
Max Vgs: 10V
UVLO = 4.55V (falling), 4.95 (rising)
Changes required
for 2S.
8-13V Input
<R2>
Second FET needed for
dual-port designs.
Signal aliases required by this page:
Power aliases required by this page:
- =PPVIN_SW_TBTBST (8-13V Boost Input)
Page Notes
BOM options provided by this page:
add property on another page.
Voltage not specified here,
Rds(on): 46mOhm @ 4.5V Vgs
Pull-up on RR page
- =PP15V_TBT_REG (15V Boost Output)
(NONE)
(NONE)
BATLOW# Isolation
402
330K
1/16W
MF-LF
5%
R3081
1
2
402
470K
MF-LF
1/16W
5%
R3080
1
2
402
25V
10%
0.1UF
X5R
C3080
1
2
402
MF-LF
73.2K
1%
1/16W
R3092
1
2
402
1/16W
MF-LF
330K
5%
R3087
1
2
402
26.7K
1/16W
MF-LF
1%
R3094
1
2
402
10%
6.3V
CERM-X5R
0.33UF
C3094
1
2
402
330K
MF-LF
1/16W
5%
R3088
1
2
17 24 36 37 72
402
NO STUFF
100PF
CERM
50V
5%
C3089
1
2
402
1%
1/16W
MF-LF
15.8K
R3096
1
2
25V
CASE-D3L
20%
POLY-TANT
33UF-0.06OHM
C3095
1
2
25V
10%
X5R
1206-2
10UF
C3096
1
2
25V
10%
X5R
10UF
805
NO STUFF
C3097
1
2
50V
COG-CERM
0402
68PF
5%
C3087
1
2
402
20%
10V
2.2UF
X5R-CERM
C3085
1
2
SI8409DB
CRITICAL
BGA
Q3080
23
1
4
402
1%
49.9K
MF-LF
1/16W
R3093
1
2
402
1%
200K
MF-LF
1/16W
R3091
1
2
25V
10UF
X5R-CERM
0603
20%
C3090
1
2
25V
10UF
X5R-CERM
0603
20%
C3091
1
2
PIMB063T-SM
3.3UH-6.5A
CRITICAL
L3095
12
0402
C0G-CERM
10PF
50V
5%
C3088
1
2
CRITICAL
LT3957
QFN
U3090
25
31
12
13
14
15
16
17
28
1
2
10
35
36
33
6
3
4 23
24
37
32
8
9
20
21
38
34
30
27
402
1%
MF-LF
1/16W
137K
R3095
1
2
PLACE_NEAR=C3095.1:2 mm
SM
XW3095
12
MF
1/20W
0201
0
5%
R3089
1
2
10%
0402
X7R-CERM
0.001UF
50V
C3099
1
2
10%
0.0033UF
X7R-CERM
50V
0402
C3093
1
2
402
2.2UF
10V
20%
X5R-CERM
C3092
1
2
402
10V
X5R-CERM
2.2UF
20%
C3086
1
2
CRITICAL
PDS540XF
PWRDI5
D3095
1
2
3
23 26
DFN1006H4-3
DMN32D2LFB4
Q3005 3
1
2
SOT-563
DMN5L06VK-7
Q3088
6
2
1
SOT-563
DMN5L06VK-7
Q3088
3
5
4
23 25
DMN32D2LFB4
DFN1006H4-3
Q3000
3
1
2
13 36
SYNC_MASTER=J44 SYNC_DATE=08/12/2013
Thunderbolt Mobile Support
PP3V3_S4_TBT
TBT_BATLOW_L
SMC_DELAYED_PWRGD
TBTBST_SHDN_DIV
TBTBST_FBX
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm
SWITCH_NODE=TRUE
DIDT=TRUE
TBTBST_BOOST
TBTBST_VSNS
TBTBST_SNS1
TBT_BATLOW_L
MAKE_BASE=TRUE
PM_BATLOW_L
PP15V_TBT
TBT_A_HV_EN
PPBUS_G3H
TBTBST_VC_RC
TBTBST_PWREN_L
TBTBST_PWREN_DIV_L
TBTBST_VC
TBTBST_RT
TBTBST_SS
TBTBST_SNS2
PPVIN_SW_TBTBST
MIN_NECK_WIDTH=0.25 mm
MIN_LINE_WIDTH=0.5 mm
TBTBST_INTVCC
TBTBST_EN_UVLO
MIN_LINE_WIDTH=0.5 mm
GND_TBTBST_SGND
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=0V
<BRANCH>
<SCH_NUM>
<E4LABEL>
30 OF 120
25 OF 78
23 24 42 65
23 25
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40 51 52 58 65 68
28
65 www.rosefix.com

IN
IN
OUT
IN
IN
IN
IN
IN
OUT
BI
IN
IN
OUT
OUT
OUT
OUT
OUT
IN
IN
BI
BI
IN
IN
OUT
ML_LANE1P
GND1
ML_LANE0N
GND0
ML_LANE0P
ML_LANE1N
ML_LANE2N
RETURN
HPD
CONFIG1
CONFIG2
GND2
ML_LANE3P
ML_LANE3N
GND4
DP_PWR
AUX_CHP
AUX_CHN
ML_LANE2P
GND3
SHIELD PINS
SHIELD PINS
PORT B
TB+
LSRX
AUX+
CA_DET
DPMLO+
DPMLO-
HPD
THMPADGND
DP+
LSTX
DP-
HPDOUT
AUX-
VDD
DP_PD
AUXIO_EN
TB_ENATB-
AUXIO+
AUXIO-
CA_DETOUT
DDC_CLK
DDC_DAT
IN
IN
IN
V3P3
ISET_V3P3
OUT
THRMGND
HV_EN
S0
EN
ISET_S0
V3P3OUT
ISET_S3
ENHVU
VHV
FAULTZ
PAD
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
87 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
D
SIZEDRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
DESCRIPTION REFERENCE DES BOM OPTIONQTYPART NUMBER CRITICAL
Sink HPD range:
15.75V Max
3.3V/HV Power MUX
ISET_Sx with CD3210.
TBT: RX_1
TBT: RX_0
TBT: TX_1
For 12V systems:
<RHVS3> <RHVS0>
12V: See
Single R on ISET_V3P3 OK.
requires two R’s per HV
below
Single-fault protection
Nominal Min Max
<RV3P3>
IHVS3 890mA 830mA 930mA (assumes 3S, 9-12.6V, 7.5-11.7W)
(IPU)
(IPD)
(IPD)
(IPU)
TBT: RX_1
TBT: LSX_A_R2P/P2R (P/N)
High: 2.0 - 5.0V
Low: 0 - 0.8V
DP Source must pull
down HPD input with
greater than or equal
to 100K (DPv1.1a).
TBT: LSX_R2P/P2R (P/N)
(Both C’s)
DP Dir
(0-18.9V)
TBT: TX_0
TBT Dir
(Both C’s)
on AC-coupled signals.
(Both C’s)
TBT Dir DP Dir
(Both C’s)
TBT: Unused
ILIM = 40000 / RISET
wake from Thunderbolt devices.
Nominal Min Max
IHVS0/S3 1120mA 1090mA 1170mA (12W minimum)
V3P3 must be S4 to support
IV3P3 1100mA 1030mA 1200mA
IHVS0 890mA 830mA 930mA (assumes 15V, 12W minimum)
514-0876
(0-18.9V)
470k R’s for ESD protection
Thunderbolt Connector A
0.01UF
X7R-CERM
0402
10%
50V
C3200
1
2
23 68 74
23 68 74
0.01UF
X5R-CERM
10%
16V
0201
C3202
1
2
MF
1/20W
201
5%
12
R3201
12
0.01UF
X7R-CERM
0402
10%
50V
C3201
1
2
5%
NO_XNET_CONNECTION=TRUE
GND_VOID=TRUE
1/20W
MF
201
1K
R3294
1
2
5%
1K
MF
201
1/20W
GND_VOID=TRUE
NO_XNET_CONNECTION=TRUE
R3295
1
2
5%
100K
MF
201
1/20W
R3241
1
2
10UF
CERM-X5R
0402
20%
6.3V
C3286
1
2
0.1UF
0201
10%
16V
X5R-CERM
C3285
1
2
X5R-CERM
0201
10%
16V
0.1UF
C3281
1
2
X5R-CERM-1
603
6.3V
20%
22UF
C3280
1
2
CRITICAL
POLY-TANT
CASE-B2-SM
20%
6.3V
100UF
C3287
1
2
5%
1M
MF
201
1/20W
R3252
1
2
5%
1M
MF
201
1/20W
R3251
1
2
330PF
X7R-CERM
0201
10%
16V
C3294
1
2
330PF
X7R-CERM
0201
10%
16V
C3295
1
2
CRITICAL
FERR-120-OHM-3A
0603
L3200
12
23
402
25V
X5R
10%
0.1UF
C3210
1
2
5%
GND_VOID=TRUE
1/20W
201
MF
470K
R3270
1
2
5%
GND_VOID=TRUE
1/20W
201
MF
470K
R3271
1
2
GND_VOID=TRUE
6.3V20%
0201X5R0.22UF
C3271
12
GND_VOID=TRUE
6.3V20%
0201X5R0.22UF
C3270
12
23 68 74
23 68 74
GND_VOID=TRUE
6.3V20%
0201X5R0.22UF
C3272
12
GND_VOID=TRUE
6.3V20%
0201X5R0.22UF
C3273
12
5%
GND_VOID=TRUE
1/20W
201
MF
470K
R3273
1
2
5%
GND_VOID=TRUE
1/20W
201
MF
470K
R3272
1
2
23 25
18 27 60 61
27 46 61
36.5K
MF
201
1%
1/20W
R3212
1
2
402
25V
X5R
10%
0.1UF
C3211
1
2
X5R-CERM
16V
10%
0201
0.1UF
C3220
1
2
23
28
28
23
23
23 68 74
23 68 74
23 68 74
23 68 74
X5R 0201
20% 6.3V
0.22UF
C3232
12
X5R 0201
20% 6.3V
0.22UF
C3233
12
23 74
23 74
0201
X5R-CERM
16V10%
0.1UF
C3230
12
16V10%
X5R-CERM0.1UF
0201
C3231
12
23 74
23 74
X5R 0201
20% 6.3V
0.22UF
C3278
12
X5R 0201
20% 6.3V
0.22UF
C3279
12
23 74
23 74
TBTHV:P15V
22.6K
MF
201
1%
1/20W
R3211
1
2
TBTHV:P15V
22.6K
MF
201
1%
1/20W
R3210
1
2
1/20W
1%
201
MF
22.6K
TBTHV:P15V
R3214
1
2
1/20W
1%
201
MF
22.6K
TBTHV:P15V
R3213
1
2
25V
4.7UF
X5R-CERM
0603
10%
C3215
1
2
25V
GND_VOID=TRUE
10%
0201
X5R-CERM
0.01UF
C3205
1
2
25V
0.01UF
X5R-CERM
0201
10%
GND_VOID=TRUE
C3206
1
2
23
CRITICAL
MDP-J44
F-RT-TH
J3200
B18
B16
B4
B6
B20
B1
B7B8
B13B14
B2
B5
B3
B11
B9
B17
B15
B12
B10
B19
S12
S13
S14
S15
S16
S17
S18
S19
S20
S21
S22
S24
20%
0.47UF CERM-X5R-1
201
GND_VOID=TRUE
4V
C3274
12
20%
0.47UF CERM-X5R-1
GND_VOID=TRUE
4V201
C3275
12
CRITICAL
CBTL05024
SIGNAL_MODEL=TBT_MUX
HVQFN24-COMBO
U3220
1
2
24
23
22
1816
5
4
10
11
6
20
19
9
21
1712
13
14
15
7
8
25
3
23 27
23
23
5%
470K
MF
201
1/20W
R3279
1
2
5%
470K
MF
201
1/20W
R3278
1
2
CERM-X5R-1
GND_VOID=TRUE
20%
0.47UF
4V201
C3277
12
CERM-X5R-1
GND_VOID=TRUE
20%
0.47UF
4V201
C3276
12
CRITICAL
CD3211A0RGPR
QFN
U3210
5
16 4
1
2
3
13
15
11 10
9
8
12
14
17
21
19
20
18
6
7
R3211,R3214118S0145 TBTHV:P12V2 RES,MTL FILM,1/20W,17.8K,1,0201,SMD,LF
2 R3210,R3213 TBTHV:P12V118S0145 RES,MTL FILM,1/20W,17.8K,1,0201,SMD,LF
Thunderbolt Connector A
SYNC_MASTER=J44 SYNC_DATE=08/12/2013
VOLTAGE=18V
MIN_NECK_WIDTH=0.20 MM
MIN_LINE_WIDTH=0.38 MM
TBTACONN_20_RC
MIN_LINE_WIDTH=0.38 MM
PP3V3RHV_S4_TBTAPWR_F
MIN_NECK_WIDTH=0.20 MM
VOLTAGE=15V
VOLTAGE=18.9V
MIN_NECK_WIDTH=0.20 MM
TBTACONN_1_C
MIN_LINE_WIDTH=0.38 MM
TBT_A_R2D_P<0>
TBT_A_R2D_P<1>
TBT_A_R2D_N<0>
TBT_A_D2R_C_N<0>
TBT_A_D2R_C_P<0>
PP3V3_S5
TBTAPWRSW_ISET_V3P3
MIN_NECK_WIDTH=0.20 MM
MIN_LINE_WIDTH=0.38 MM
PP3V3RHV_S4_TBTAPWR
VOLTAGE=15V
TBT_A_HV_EN
PM_SLP_S3_BUF_L
S4_PWR_EN
TBTAPWRSW_ISET_S0
VOLTAGE=3.3V
MIN_LINE_WIDTH=0.38 MM
MIN_NECK_WIDTH=0.20 MM
PP3V3_S4_TBTAPWR
TBTAPWRSW_ISET_S3
PP15V_TBT
TBT_A_CIO_SEL
TBTDP_AUXIO_EN
TBT_A_DP_PWRDN
TBT_A_D2R1_AUXDDC_P
DP_A_LSX_ML_P<1>
VOLTAGE=18.9V
MIN_LINE_WIDTH=0.38 MM
MIN_NECK_WIDTH=0.20 MM
TBTACONN_7_C
DP_A_LSX_ML_N<1>
TBT_A_R2D_N<1>
TBT_A_HPD
DP_TBTPA_ML_P<3>
DP_TBTPA_ML_N<3>
TBT_A_D2R1_AUXDDC_P
TBT_A_D2R1_AUXDDC_N
DP_TBTPA_ML_C_P<1>
DP_TBTPA_ML_C_N<1>
DP_TBTPA_AUXCH_C_P
TBT_A_D2R_P<0>
TBT_A_D2R_N<0>
DP_TBTPA_ML_C_P<3>
DP_TBTPA_ML_C_N<3>
TBT_A_R2D_C_P<0>
TBT_A_R2D_C_P<1>
TBT_A_R2D_C_N<1>
TBT_A_R2D_C_N<0>
TBT_A_CONFIG2_RC
TBT_A_CONFIG1_RC
PP3V3_S4_TBTAPWR
TBT_A_CONFIG1_RC
DP_A_LSX_ML_P<1>
DP_A_LSX_ML_N<1>
TBT_A_HPD
DP_TBTPA_ML_P<1>
DP_TBTPA_ML_N<1>
DP_TBTPA_AUXCH_N
TBT_A_D2R1_AUXDDC_N
TBT_A_CONFIG1_BUF
DP_TBTPA_DDC_CLK
DP_TBTPA_DDC_DATA
TBT_A_LSTX
TBT_A_LSRX
DP_TBTPA_HPD
TBTAPWRSW_ISET_S0_R
TBTAPWRSW_ISET_S3_R
DP_TBTPA_AUXCH_P
DP_TBTPA_AUXCH_C_N
TBT_A_D2R_C_N<1>
TBT_A_D2R_N<1>
TBT_A_D2R_C_P<1>
TBT_A_D2R_P<1>
<BRANCH>
<SCH_NUM>
<E4LABEL>
32 OF 120
26 OF 78
68 74
68 74
68 74
68 74
68 74
8 11 13 15 16 17 18 27 29
56 59 60 61 65 68 77
68
68
26
68
25 27 65
26 74
26 74
26 74
68 74
26
74
74
26 74
26 74
26
26
26
26 74
26 74
26
74
74
74
26 74
68
74
68 74
68 74 www.rosefix.com

IN
IN
OUT
IN
IN
IN
IN
IN
OUT
BI
IN
IN
OUT
OUT
OUT
OUT
OUT
IN
IN
BI
BI
IN
IN
OUT
ML_LANE1P
GND3
GND4
HPD
CONFIG2
GND2
RETURN
AUX_CHN
CONFIG1
ML_LANE3N
ML_LANE3P
AUX_CHP
GND0
DP_PWR
ML_LANE0P
GND1
ML_LANE0N
ML_LANE1N
ML_LANE2N
ML_LANE2P
PORT A
SHIELD PINS
SHIELD PINS
TB+
LSRX
AUX+
CA_DET
DPMLO+
DPMLO-
HPD
THMPADGND
DP+
LSTX
DP-
HPDOUT
AUX-
VDD
DP_PD
AUXIO_EN
TB_ENATB-
AUXIO+
AUXIO-
CA_DETOUT
DDC_CLK
DDC_DAT
IN
IN
IN
V3P3
ISET_V3P3
OUT
THRMGND
HV_EN
S0
EN
ISET_S0
V3P3OUT
ISET_S3
ENHVU
VHV
FAULTZ
PAD
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
87 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
D
SIZEDRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
DESCRIPTION REFERENCE DES BOM OPTIONQTYPART NUMBER CRITICAL
15.75V Max
to 100K (DPv1.1a).
(Both C’s)
TBT Dir
(Both C’s)
on AC-coupled signals.
470k R’s for ESD protection
(Both C’s)
TBT Dir
(0-18.9V)
TBT: TX_0
(0-18.9V)
DP Dir
(Both C’s)
TBT: LSX_R2P/P2R (P/N)
Thunderbolt Connector B
DP Source must pull
Low: 0 - 0.8V
High: 2.0 - 5.0V
Sink HPD range:
TBT: LSX_A_R2P/P2R (P/N)
TBT: RX_1
(IPU)
(IPD)
(IPD)
(IPU)
IHVS3 890mA 830mA 930mA (assumes 3S, 9-12.6V, 7.5-11.7W)
IV3P3 1100mA 1030mA 1200mA
ISET_Sx with CD3210.
requires two R’s per HV
Single R on ISET_V3P3 OK.
12V: See
<RHVS0><RHVS3>
IHVS0/S3 1120mA 1090mA 1170mA (12W minimum)
Nominal Min Max
For 12V systems:
TBT: TX_1
TBT: RX_1
TBT: Unused
DP Dir
TBT: RX_0
down HPD input with
greater than or equal
ILIM = 40000 / RISET
IHVS0 890mA 830mA 930mA (assumes 15V, 12W minimum)
Nominal Min Max
3.3V/HV Power MUX
<RV3P3>
below
V3P3 must be S4 to support
wake from Thunderbolt devices.
Single-fault protection
514-0876
50V
10%
0402
X7R-CERM
0.01UF
C3300
1
2
23 68 74
23 68 74
16V
10%
0201
X5R-CERM
0.01UF
C3302
1
2
5%
MF
1/20W
12
201
R3301
12
50V
10%
0402
X7R-CERM
0.01UF
C3301
1
2
5%
NO_XNET_CONNECTION=TRUE
GND_VOID=TRUE
1/20W
201
MF
1K
R3394
1
2
GND_VOID=TRUE
5%
NO_XNET_CONNECTION=TRUE
1/20W
201
MF
1K
R3395
1
2
5%
1/20W
201
MF
100K
R3341
1
2
6.3V
20%
0402
CERM-X5R
10UF
C3386
1
2
16V
10%
0201
X5R-CERM
0.1UF
C3385
1
2
16V
10%
0201
0.1UF
X5R-CERM
C3381
1
2
20%
6.3V
X5R-CERM-1
22UF
603
C3380
1
2
CRITICAL
6.3V
20%
CASE-B2-SM
POLY-TANT
100UF
C3387
1
2
5%
1/20W
201
MF
1M
R3352
1
2
5%
1/20W
201
MF
1M
R3351
1
2
16V
10%
0201
X7R-CERM
330PF
C3394
1
2
16V
10%
0201
X7R-CERM
330PF
C3395
1
2
CRITICAL
FERR-120-OHM-3A
0603
L3300
12
23
402
25V
10%
X5R
0.1UF
C3310
1
2
5%
470K
MF
201
1/20W
GND_VOID=TRUE
R3370
1
2
5%
470K
MF
201
1/20W
GND_VOID=TRUE
R3371
1
2
0.22UF X5R 0201
20% 6.3V
GND_VOID=TRUE
C3371
12
0.22UF X5R 0201
20% 6.3V
GND_VOID=TRUE
C3370
12
23 68 74
23 68 74
0.22UF X5R 0201
20% 6.3V
GND_VOID=TRUE
C3372
12
0.22UF X5R 0201
20% 6.3V
GND_VOID=TRUE
C3373
12
5%
470K
MF
201
1/20W
GND_VOID=TRUE
R3373
1
2
5%
470K
MF
201
1/20W
GND_VOID=TRUE
R3372
1
2
23 28
18 26 60 61
26 46 61
1/20W
1%
201
MF
36.5K
R3312
1
2
402
25V
10%
X5R
0.1UF
C3311
1
2
10%
16V
X5R-CERM
0201
0.1UF
C3320
1
2
23
28
28
23
23
23 68 74
23 68 74
23 68 74
23 68 74
X5R 0201
20% 6.3V
0.22UF
C3332
12
X5R 0201
20% 6.3V
0.22UF
C3333
12
23 74
23 74
X5R-CERM
16V10%
0.1UF
0201
C3330
12
16V10%
X5R-CERM0.1UF
0201
C3331
12
23 74
23 74
0.22UF
6.3V20%
0201X5R
C3378
12
0.22UF
6.3V20%
0201X5R
C3379
12
23 74
23 74
1%
201
MF
22.6K
TBTHV:P15V
1/20W
R3311
1
2
1/20W
1%
201
MF
22.6K
TBTHV:P15V
R3310
1
2
TBTHV:P15V
22.6K
MF
201
1%
1/20W
R3314
1
2
TBTHV:P15V
22.6K
MF
201
1%
1/20W
R3313
1
2
25V
10%
0603
4.7UF
X5R-CERM
C3315
1
2
25V
0.01UF
X5R-CERM
0201
10%
GND_VOID=TRUE
C3305
1
2
25V
GND_VOID=TRUE
10%
0201
X5R-CERM
0.01UF
C3306
1
2
23
CRITICAL
F-RT-TH
MDP-J44
J3200
A18
A16
A4
A6
A20
A1
A7A8
A13A14
A2
A5
A3
A11
A9
A17
A15
A12
A10
A19
S1
S10
S11
S2
S23
S3
S4
S5
S6
S7
S8
S9
4V
GND_VOID=TRUE
0.47UF
20%
CERM-X5R-1
201
C3374
12
2014V
GND_VOID=TRUE
0.47UF
20%
CERM-X5R-1
C3375
12
SIGNAL_MODEL=TBT_MUX
CRITICAL
HVQFN24-COMBO
CBTL05024
U3320
1
2
24
23
22
1816
5
4
10
11
6
20
19
9
21
1712
13
14
15
7
8
25
3
23 26
23
23
5%
1/20W
201
MF
470K
R3379
1
2
5%
1/20W
201
MF
470K
R3378
1
2
GND_VOID=TRUE
2014V
0.47UF
20%
CERM-X5R-1
C3376
12
GND_VOID=TRUE
2014V
0.47UF
20%
CERM-X5R-1
C3377
12
CD3211A0RGPR
CRITICAL
QFN
U3310
5
16 4
1
2
3
13
15
11 10
9
8
12
14
17
21
19
20
18
6
7
TBTHV:P12VR3310,R33132118S0145 RES,MTL FILM,1/20W,17.8K,1,0201,SMD,LF
118S0145 TBTHV:P12VR3311,R33142 RES,MTL FILM,1/20W,17.8K,1,0201,SMD,LF
Thunderbolt Connector B
SYNC_MASTER=J44 SYNC_DATE=08/12/2013
PP3V3RHV_S4_TBTBPWR_F
MIN_LINE_WIDTH=0.38 MM
MIN_NECK_WIDTH=0.20 MM
VOLTAGE=15V
MIN_NECK_WIDTH=0.20 MM
VOLTAGE=15V
MIN_LINE_WIDTH=0.38 MM
PP3V3RHV_S4_TBTBPWR
MIN_LINE_WIDTH=0.38 MM
MIN_NECK_WIDTH=0.20 MM
TBTBCONN_20_RC
VOLTAGE=18V
TBT_B_D2R_C_P<0>
TBT_B_D2R_C_N<0>
PP15V_TBT
MIN_NECK_WIDTH=0.20 MM
MIN_LINE_WIDTH=0.38 MM
VOLTAGE=3.3V
PP3V3_S4_TBTBPWR
TBTBPWRSW_ISET_S0_R
TBTBPWRSW_ISET_S3_R
PP3V3_S5
TBTBPWRSW_ISET_V3P3
TBT_B_HV_EN
PM_SLP_S3_BUF_L
S4_PWR_EN
TBTBPWRSW_ISET_S0
TBTBPWRSW_ISET_S3
TBT_B_R2D_N<1>
DP_TBTPB_ML_N<3>
TBT_B_D2R1_AUXDDC_N
DP_TBTPB_ML_P<3>
TBT_B_HPD
TBT_B_D2R1_AUXDDC_P
DP_B_LSX_ML_P<1>
MIN_NECK_WIDTH=0.20 MM
MIN_LINE_WIDTH=0.38 MM
TBTBCONN_1_C
VOLTAGE=18.9V
TBT_B_R2D_P<0>
MIN_NECK_WIDTH=0.20 MM
MIN_LINE_WIDTH=0.38 MM
VOLTAGE=18.9V
TBTBCONN_7_C
TBT_B_R2D_N<0>
DP_B_LSX_ML_N<1>
TBT_B_R2D_P<1>
TBT_B_D2R_N<0>
DP_TBTPB_HPD
TBT_B_LSRX
TBT_B_LSTX
DP_TBTPB_DDC_DATA
TBT_B_CONFIG1_BUF
TBT_B_D2R1_AUXDDC_N
TBT_B_D2R1_AUXDDC_P
DP_TBTPB_AUXCH_N
DP_TBTPB_ML_N<1>
DP_TBTPB_ML_P<1>
TBT_B_HPD
DP_B_LSX_ML_N<1>
DP_B_LSX_ML_P<1>
TBT_B_CONFIG1_RC
DP_TBTPB_AUXCH_P
PP3V3_S4_TBTBPWR
TBT_B_CONFIG1_RC
TBT_B_CONFIG2_RC
TBT_B_R2D_C_N<0>
TBT_B_R2D_C_N<1>
TBT_B_R2D_C_P<1>
TBT_B_R2D_C_P<0>
DP_TBTPB_ML_C_N<3>
DP_TBTPB_ML_C_P<3>
TBT_B_D2R_P<0>
DP_TBTPB_AUXCH_C_N
DP_TBTPB_AUXCH_C_P
DP_TBTPB_ML_C_N<1>
DP_TBTPB_ML_C_P<1>
TBT_B_D2R_N<1>
TBT_B_D2R_P<1>
TBT_B_D2R_C_P<1>
TBT_B_D2R_C_N<1>
DP_TBTPB_DDC_CLK
TBT_B_DP_PWRDN
TBTDP_AUXIO_EN
TBT_B_CIO_SEL
<BRANCH>
<SCH_NUM>
<E4LABEL>
33 OF 120
27 OF 78
68 74
68 74
25 26 65
27
68
8 11 13 15 16 17 18 26 29
56 59 60 61 65 68 77
68
68
68 74
74
27 74
74
27
27 74
27 74
68 74
68 74
27 74
68 74
27 74
27 74
74
74
74
27
27 74
27 74
27
74
27
27
68 74
68 74 www.rosefix.com

BI
OUT
BI
OUT
SBI
INB+
VCC
OUTA1+
OUTA1-
OUTA0+
OUTA0-
SAO
OUTB1+
OUTB1-
OUTB0-
OUTB0+
SBO
ENA
INA-
INA+
SAI
INB-
GND THRM
ENB
PAD
BI
IN
BI
IN
IN
OUT
S
D
G
IN
S
D
G
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
87 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
D
SIZEDRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
Second FET needed for
dual-port designs.
CONNECTS TO TBTBTS_PWREN_L ON PAGE 30.
Only necessary on dual-port hosts.
to indicate active display interface.
NOTE: Only DDC_DATA is sensed, so DDC_CLK
DDC Pull-Ups
pull-ups are unstuffed.
2.2k pull-ups are required by PCH
DP++ spec violation, should remove!
On single-port hosts alias TBTPA_DDC to TBTSNK0_DDC.
DDC Crossbar
NEVER SEND AUXCH THROUGH CROSSBAR!
SAI/SBI = 1: INA == OUTA0, INB == OUTB0
SAI/SBI = 0: INA == OUTB0, INB == OUTA0
27
27
26
26
TS3DS10224
QFN
CRITICAL
U3400
16
10
5
2
1
4
3
17
18
19
20
9
8
7
6
14 15
12 11
21
13
64
64
13
13
0.1UF
20%
10V
402
CERM
C3480
1
2
MF
201
2.2K
1%
1/20W
R3451
1
2
201
2.2K
MF
1%
1/20W
R3452
1
2
2.2K
MF
1%
1/20W
201
R3453
1
2
MF
201
1%
1/20W
2.2K
R3454
1
2
23 27
25
SOT-563
DMN5L06VK-7
Q3485
6
2
1
23
MF
100K
1/20W
201
5%
R3485
1
2
DMN5L06VK-7
SOT-563
Q3485
3
5
4
SYNC_MASTER=J44 SYNC_DATE=08/12/2013
DDC Crossbar
DP_TBTSNK0_DDC_DATA
DP_TBTSNK1_DDC_CLK
DP_TBTPA_DDC_CLK
DP_TBTPA_DDC_DATA
PP3V3_S0
TBT_DDC_XBAR_EN
DP_TBTPB_DDC_DATA
DP_TBTPB_DDC_CLK
DP_TBTSNK0_DDC_CLK
DP_TBTSNK1_DDC_DATA
TBT_DDC_XBAR_EN_L
TBT_B_HV_EN
TBTBST_PWREN_L
<BRANCH>
<SCH_NUM>
<E4LABEL>
34 OF 120
28 OF 78
8 11 12 13 15 17 18 24 30 37
38 39 40 41 42 43 44 46 47 50
61 62 64 65 68 77 www.rosefix.com

NC
BI
BI
VDD
GND
DM
DP
OE*
S
DP_1
DM_1
DM_2
DP_2
OUT
SYM_VER_2
GS
D
IN
GND
VCC
A
B0
B1
S
VER-3
OUT
OUT
IN
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
87 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
D
SIZEDRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
H USB_BT (2)
SEL OUTPUT
BLUETOOTH
H AP_S0IX_WAKE_L (B1)
L PCIE_WAKE_L (B0)
SEL OUTPUT
PCIe Wake Muxing
L BT_WAKE (1)
CERM-X5R
0201
6.3V
0.1UF
10%
C3510
1
2
14 71
14 71
DFN
USB3740
SIGNAL_MODEL=BT_MUX
CRITICAL
U3510
9
1
7
10
2
6
8
3
4
5
34 36 38
201
1/20W
MF
1%
15K
R3512
1
2
DMN32D2LFB4
NO_XNET_CONNECTION=TRUE
DFN1006H4-3
Q3510 3
1
2
13 18 36 61 63
5%
201
1/20W
MF
100K
R3561
1
2
CRITICAL
SC70
NC7SB3157P6XG
U3560
4
3
1
2
6
5
CERM-X5R
0201
6.3V
0.1UF
10%
C3560
1
2
5%
0
0201
1/20W
MF
NOSTUFF
R3560
12
15
13 31 72
15
WIRELESS SUPPORT
SYNC_DATE=08/12/2013SYNC_MASTER=J44
PP3V3_S5
AP_S0IX_WAKE_L
AP_S0IX_WAKE_SEL
AP_PCIE_WAKE_L
PCIE_WAKE_L
USB_BT_CONN_N
USB_BT_CONN_P
PM_SLP_S4_L
USB_BT_N
USB_BT_P
SMC_PME_S4_WAKE_L
BT_WAKE
PP3V3_S4
<BRANCH>
<SCH_NUM>
<E4LABEL>
35 OF 120
29 OF 78
8 11 13 15 16 17 18 26 27 56
59 60 61 65 68 77
63 72
63 71
63 71
18 34 37 38 42 60 63 64 65 68 www.rosefix.com

OUT
OUT
IN
IN
NC
08
NC
RESET*
OUT
EN
MR*
GND
THRM
IN
VDD
SENSE
+
-
PAD
(OD)
0.7V
DLY
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
IN
IN
IN
OUT
NC
08
IN
NC
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
87 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
D
SIZEDRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
Delay = 55ms
514S0449
Supervisor & CLKREQ# Isolation
Per Intel PDG, use PCIe style decoupling, when muxing PCIe & SATA
GND_VOID
OOB Isolation
Gumstick3 Connector
SMC_PWRFAIL_WARN_L:
There is 10k pullup on the SSD, its OPEN drain on SMC.
GND_VOID
36
10%
0.1UF
0201
10V
PLACE_NEAR=L3700.1:1mm
X5R-CERM
C3702
1
2
CRITICAL
PLACE_NEAR=J3700.1:3mm
FERR-26-OHM-6A
0603
L3700
12
10%
0.1UF
X5R-CERM
0201
10V
PLACE_NEAR=L3700.1:1mm
C3701
1
2
201
1/20W
100K
1%
MF
R3742
1
2
201
5%
MF
1/20W
100K
R3740
1
2
232K
1/20W
1%
201
MF
R3741
1
2
12
10%
0.1UF
6.3V
0201
CERM-X5R
C3740
1
2
15
15 30 60 61
BYPASS=U3711:5 mm
CRITICAL
74LVC1G08
SOT891
U3711
2
1
35
6
4
10%
0.1UF
10V
X5R-CERM
0201
C3719
1
2
CRITICAL
SLG4AP016V
TDFN
U3740
6
5
7
3
8
4
2
9
1
12 68 70
12 68 70
12 68 70
12 68 70
12 68 70
12 68 70
12 68 70
12 68 70
10%
0.1UF
X5R-CERM
GND_VOID=TRUE
020116V
C3716
12
10%
0.1UF
GND_VOID=TRUE
X5R-CERM 020116V
C3717
12
10%
0.1UF
X5R-CERM
GND_VOID=TRUE
020116V
C3713
12
10%
0.1UF
X5R-CERM 020116V
GND_VOID=TRUEC3712
12
10%
0.1UF
X5R-CERM 0201
GND_VOID=TRUE
16V
C3715
12
10%
0.1UF
020116V X5R-CERM
GND_VOID=TRUEC3714
12
10%
0.1UF
GND_VOID=TRUE
0201X5R-CERM16V
C3711
12
10%
0.1UF
GND_VOID=TRUE
X5R-CERM 020116V
C3710
12
12 68 70
12 68 70
12 68 70
12 68 70
12 68 70
12 68 70
12 68 70
12 68 70
12 68 70
12 68 70
15 30 60 61
36
15
16
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
F-RT-SM
CRITICAL
SSD-GS3
J3700
1
10
11
12
13
14
15
16
17
18
19
2
20
21
22
23
24
25
26
27
28 29
3
30
31
32
33
34
35
36
37
38
39
4
40
41
42
43
44
45
46
47
48
49
5 50
51
52
53
54
55
56
57
58
59
6
60
61
62
63
7
8
9
201
1/20W
MF
100K
1%
R3700
1
2
SOT891
CRITICAL
74LVC1G08
U3710
2
1
35
6
4
36
10%
0.1UF
BYPASS=U3710:5 mm
X5R-CERM
0201
10V
C3718
1
2
201
100K
1/20W
MF
1%
R3701
1
2
SSD Connector
SYNC_MASTER=J44 SYNC_DATE=08/12/2013
SSD_RESET_CONN_L
SSD_CLKREQ_CONN_L
SSD_DEVSLP
SSD_PCIE_SEL_L
SMC_PWRFAIL_WARN_L
SSD_PWR_EN
PP3V3_S0SW_SSD_FLT
MIN_LINE_WIDTH=0.6mm
VOLTAGE=3.3V
MIN_NECK_WIDTH=0.15mm
PP3V3_S0
NC_SSD_MFG_RSVD
PP3V3_S0
SMC_OOB1_R2D_L
PP3V3_S0SW_SSD
PP3V3_S0
PP3V3_S0SW_SSD
PP3V3_S0SW_SSD
SMC_OOB1_D2R_L
PCIE_SSD_D2R_N<1>
PCIE_CLK100M_SSD_P
PCIE_CLK100M_SSD_N
PCIE_SSD_D2R_P<0>
PCIE_SSD_D2R_N<0>
PCIE_SSD_D2R_P<3>
PCIE_SSD_D2R_N<2>
PCIE_SSD_D2R_P<2>
PCIE_SSD_D2R_P<1>
PCIE_SSD_D2R_N<3>
PCIE_SSD_R2D_P<0>
PCIE_SSD_R2D_N<1>
PCIE_SSD_R2D_P<2>
PCIE_SSD_R2D_N<3>
PCIE_SSD_R2D_P<1>
PCIE_SSD_R2D_N<0>
PCIE_SSD_R2D_C_N<3>
PCIE_SSD_R2D_C_P<3>
PCIE_SSD_R2D_C_N<2>
PCIE_SSD_R2D_C_P<2>
PCIE_SSD_R2D_C_N<1>
PCIE_SSD_R2D_C_P<1>
PCIE_SSD_R2D_C_N<0>
PCIE_SSD_R2D_C_P<0>
PCIE_SSD_R2D_N<2>
PCIE_SSD_R2D_P<3>
SMC_OOB1_R2D_CONN_L
SMC_OOB1_D2R_CONN_L
SSD_RESET_L
SSD_PWR_EN
SSD_CLKREQ_L
P3V3SSD_VMON
PP3V42_G3H
<BRANCH>
<SCH_NUM>
<E4LABEL>
37 OF 120
30 OF 78
8 11 12 13 15 17 18 24 28 30
37 38 39 40 41 42 43 44 46 47
50 61 62 64 65 68 77
8 11 12 13 15 17 18 24 28 30
37 38 39 40 41 42 43 44 46 47
50 61 62 64 65 68 77
30 41 65
8 11 12 13 15 17 18
24 28 30 37 38 39 40
41 42 43 44 46 47 50
61 62 64 65 68 77
30 41 65
30 41 65
68 70
68 70
68 70
68 70
68 70
68 70
68 70
68 70
17 33 34 36 37 38 39 45 51 52
61 65 68 www.rosefix.com

NC
NC
NC
NC
OUT
IN
OUT
BI
IN
IN
IN
OUT
IN
IN
OUT
OUT
IN
IN
SYM 1 OF 3
DEBUG_15
DEBUG_14
DDR_PWR_SEL
SENSOR_WAKE*
PCIE_WAKE*
PCIE_CLKREQ*
JTAG_SRST*
JTAG_TRST*
JTAG_TMS
JTAG_TDO
PCIE_REFCLKN
DEBUG_03
DEBUG_04
DEBUG_05
DEBUG_09PCIE_RDP0
DEBUG_06
DEBUG_00
DEBUG_01
DEBUG_02
DEBUG_07
DEBUG_08
DEBUG_10
DEBUG_11
DEBUG_12
DEBUG_13
DEBUG_16
GPIO_00
GPIO_01
GPIO_02
GPIO_03
GPIO_04
GPIO_05
GPIO_06
GPIO_07
I2C_CLK_DBG
I2C_CLK_SENSOR
I2C_DATA_DBG
I2C_DATA_SENSOR
JTAG_TCK
JTAG_TDI
MIPI_CP_CLK
PCIE_RDN0
PCIE_REFCLKP
PCIE_RST*
PCIE_TDN0
RESET*
SHUTDOWN*
UARTCTS
UARTRTS
UARTRXD
UARTTXD
XTAL_N
XTAL_P
MIPI_DM0
MIPI_DP0
MIPI_CM_CLK
PCIE_TDP0
PCIE_TESTN
MIPI_DP1
MIPI_DM1
STRAP_XTAL_FREQ
STRAP_XTAL_SEL
TEST_OUT
TEST_MODE
PCIE_TESTP
SYM 2 OF 3
DDR_CK_N0
DDR_CK_P0
DDR_CAS*
DDR_RAS*
DDR_CKE
DDR_AD00
DDR_AD01
DDR_AD02
DDR_AD03
DDR_AD04
DDR_AD05
DDR_AD06
DDR_AD07
DDR_AD08
DDR_AD09
DDR_AD10
DDR_AD11
DDR_AD12
DDR_AD13
DDR_AD14
DDR_BA0
DDR_BA1
DDR_BA2
DDR_CS*
DDR_DM0
DDR_DM1
DDR_DQ00
DDR_DQ01
DDR_DQ02
DDR_DQ03
DDR_DQ04
DDR_DQ05
DDR_DQ06
DDR_DQ07
DDR_DQ08
DDR_DQ09
DDR_DQ10
DDR_DQ11
DDR_DQ12
DDR_DQ13
DDR_DQ14
DDR_DQ15
DDR_DQS_N0
DDR_DQS_N1
DDR_DQS_P0
DDR_DQS_P1
DDR_RESET*
DDR_WE*
DDR_ZQ
SR_VLXD_O
VDD_1P35A
PCIE_GND
XTAL_AVDD1P2
VDDC
VDD1P8_O
SR_VLXC_O
SR_VDD_3P3D
SR_VDD_3P3C
SR_PVSSD
SR_PVSSC
PMU_AVSS
OTP_VDD3P3
DDR_VDDIO_CK
MIPI_AGND
VDD_3P3A
DDR_VREF_O
VSSC
XTAL_AVSS
DDR_VDDIO
PCIE_VDD1P2
VSENSE_D
VSENSE_C
PCIE_PVDD1P2
DDR_AVDD1P8
MIPI_AVDD1P8
PLL_VDD1P8
VDD1P2_O
VDDO18
SYM 3 OF 3
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
IN
BI
BI
BI
BI
BI
BI
BI
OUT
OUT
OUT
IN
OUT
IN
IN
OUT
OUT
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
87 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
D
SIZEDRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
L3901:1
L3902:1
A1 SILICON BUG
PU = 25MHz
(=PP3V3_S3RS0_CAMERA)
PD = 1.35V
PU on PCH page
(=PP3V3_S3RS0_CAMERA)
12
32
32 68
32 68
100K
NOSTUFF
MF
1/20W
5%
201
R3930
1
2
5%
NOSTUFF
100K
1/20W
MF
201
R3932
1
2
18
18
10%
0.1UF
6.3V
0201
CERM-X5R
C3900
1
2
CERM-X5R
0201
0.1UF
10%
6.3V
C3924
1
2
6.3V
X5R
0201-1
1.0UF
20%
C3923
1
2
CERM-X5R
6.3V
0201
0.1UF
10%
C3922
1
2
6.3V
20%
X5R
0201-1
1.0UF
C3921
1
2
10%
0.1UF
6.3V
0201
CERM-X5R
BYPASS=U3900.D6:2.54MM
C3910
1
2
10%
0.1UF
6.3V
0201
CERM-X5R
BYPASS=U3900.D6:2.54MM
C3951
1
2
100K
MF
1/20W
201
5%
R3901
1
2
32 71
32 71
32 70
32 70
32 70
32 70
32 70
32 70
CAM_XTAL:YES
100K
MF
1/20W
201
5%
R3906
1
2
CAM_XTAL:NO
100K
MF
1/20W
201
5%
R3907
1
2
100K
MF
1/20W
201
5%
R3904
1
2
PLACE_NEAR=U3900.M13:4MM
1.0UH-1.6A-55MOHM
1008
L3901
12
PLACE_NEAR=U3900.K13:4MM
1008
1.0UH-1.6A-55MOHM
L3902
12
402
4.7UF
20%
X5R
6.3V
BYPASS=U3900.K13:2.54MM
C3912
1
2
PLACE_NEAR=U3900.M13:2.54MM
X5R
6.3V
4.7UF
20%
402
C3915
1
2
22NH
0402
L3906
12
BYPASS=U3900.L7:2.54MM
10%
0.1UF
6.3V
0201
CERM-X5R
C3916
1
2
X5R
6.3V
402
20%
4.7UF
C3928
1
2
PLACE_NEAR=U3900.M14:2.54MM
X5R
6.3V
402
20%
4.7UF
C3926
1
2
6.3V
CERM-X5R
0201
BYPASS=U3900.J1:2.54MM
10%
0.1UF
C3919
1
2
10%
0.1UF
6.3V
0201
CERM-X5R
BYPASS=U3900:5mm
C3937
1
2
BYPASS=U3900:5mm
10%
0.1UF
6.3V
0201
CERM-X5R
C3935
1
2
0201
CERM-X5R
6.3V
10%
0.1UF
BYPASS=U3900:5mm
C3940
1
2
X5R
6.3V
BYPASS=U3900:7mm
4.7UF
402
20%
C3942
1
2
6.3V
BYPASS=U3900.F15:2.54MM
2.2UF
20%
402-LF
CERM
C3941
1
2
10%
X5R
BYPASS=U3900.G15:2.54MM
1UF
10V
402
C3939
1
2
10%
0.1UF
6.3V
0201
CERM-X5R
C3960
1
2
FBGA
OMIT_TABLE
BCM15700
CRITICAL
U3900
G12
B11
C14
B14
A15
E11
E10
F11
F10
G11
G10
H11
H10
J10
K11
K10
L11
L10
R12
P12
P11
P10
P9
N11
N10
N9
D15
R10
C15
R9
C11
F13
E12
F12
D12
D11
R7
P7
R8
R6
P8
P6
P13
A7
B7
A10
B10
R14
B8
A8
C9
B9
N12
E15
R13
H12
C13
C12
M10
J12
D13
D14
E13
E14
A12
A13
BCM15700
CRITICAL
FBGA
OMIT_TABLE
U3900
L3
M4
N3
M3
M1
M2
P4
N2
P3
P2
J4
R2
L1
P1
R4
K3
L2
K2
H4
G2
H2
J3
L4
C1
C4
C2
E3
E4
D3
F3
F1
F4
F2
B5
C3
B1
B4
A5
C5
B2
B3
D2
A3
E2
A2
H3
R3
J2
G3
CRITICAL
BCM15700
FBGA
OMIT_TABLE
U3900
J1
A4
D4
G4
K4
N4
G5
N5
N7
N8
N6
L7
D7
C10
C7
D9
C8
D6
G14
M12
N13
P14
P15
R15
K15
L12
L13
L14
L15
M14
M15
N15
H14
H15
J13
J14
J15
M13
N14
K13
K14
F15
G15
F14
J11
F6
F7
F8
F9
L6
L5
L8
L9
B15
R11
M11
K12
A1
A6
G9
H5
H6
H7
H8
H9
J5
J6
J7
J8
B6
J9
K1
K5
K6
K7
K8
K9
A14
M9
N1
D1
P5
R1
R5
E9
D5
E5
G1
G6
G7
G8
B13
B12
1000PF
X7R-CERM
10%
BYPASS=U3900.J1:2.54MM
16V
0201
C3918
1
2
10%
X7R-CERM
1000PF
16V
BYPASS=U3900:3mm
0201
C3934
1
2
BYPASS=U3900.L7:2.54MM
10%
16V
1000PF
X7R-CERM
0201
C3917
1
2
10%
0201
16V
1000PF
X7R-CERM
BYPASS=U3900:3mm
C3936
1
2
10%
0201
16V
1000PF
X7R-CERM
BYPASS=U3900.D7:2.54MM
C3938
1
2
32 75
32 75
32 75
32 75
32 75
32 75
32 75
32 75
32 75
32 75
32 75
32 75
32 75
32 75
32 75
32 75
32 75
32 75
32 75
32 75
32 75
32 75
32 75
32 75
32 75
32 75
32 75
32 75
32 75
32 75
32 75
32 75
32 75
32 75
32 75
32 75
32 68 75
32 75
32 75
32 75
32 75
32 75
32 75
32 75
32 75
32 75
32 75
32 68 75
32
NO STUFF
100K
MF
1/20W
201
5%
R3910
1
2
100K
MF
1/20W
201
5%
R3911
1
2
1%
240
MF
1/20W
201
R3912
12
1K
MF
1/20W
201
5%
R3913
1
2
1K
MF
1/20W
201
5%
R3914
1
2
32 68 75
SM
XW3900
12
SM
XW3901
12
100K
MF
1/20W
201
5%
R3990
1
2
10%
0.1UF
6.3V
0201
CERM-X5R
NOSTUFF
C3990
1
2
0.1UF
10%
6.3V
0201
CERM-X5R
C3927
1
2 1.0UF
20%
X5R
6.3V
0201-1
C3930
1
2
32 68 75
20%
1.0UF
X5R
6.3V
0201-1
C3932
1
2
0402-1
CERM-X5R
10UF
6.3V
20%
C3931
1
2
0402-1
10UF
6.3V
20%
CERM-X5R
C3933
1
2
CAM_A1
100K
MF
1/20W
201
5%
R3915
1
2
X5R
6.3V
402
20%
4.7UF
C3914
1
2
402
X5R
6.3V
4.7UF
20%
C3913
1
2
220-OHM-1.4A
0603
L3903
12
220-OHM-1.4A
0603
L3904
12
NOSTUFF
MF
1/20W
0201
0
5%
R3991
12
13 29 72
BYPASS=U3900.L9:2.54MM
10%
0.1UF
6.3V
0201
CERM-X5R
C3975
1
2
6.3V
10%
0.1UF
0201
CERM-X5R
BYPASS=U3900.L9:2.54MM
C3974
1
2
BYPASS=U3900.F9:2.54MM
1000PF
10%
16V
X7R-CERM
0201
C3973
1
2
BYPASS=U3900.F9:2.54MM
CERM-X5R
10%
0.1UF
6.3V
0201
C3972
1
2
BYPASS=U3900.F6:2.54MM
10%
0201
16V
1000PF
X7R-CERM
C3971
1
2
0.1UF
10%
6.3V
0201
CERM-X5R
BYPASS=U3900.F6:2.54MM
C3970
1
2
51K
MF
1/20W
201
5%
R3975
1
2
51K
MF
1/20W
201
5%
R3976
1
2
100K
1/20W
MF
201
5%
R3920
1
2
100K
MF
1/20W
201
5%
R3921
1
2
NOSTUFF
100K
MF
1/20W
201
5%
R3934
1
2
1/20W
201
MF
5%
330K
R3931
1
2
MF
1/20W
201
5%
330K
R3933
1
2
1/20W
MF
201
5%
330K
R3935
1
2
100K
NOSTUFF
MF
1/20W
201
5%
R3936
1
2
NOSTUFF
100K
MF
1/20W
201
5%
R3937
1
2
32 75
SYNC_MASTER=J44
Camera 1 of 2
SYNC_DATE=08/12/2013
PP1V2_CAM_PCIE_VDD_FLT
MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM
VOLTAGE=1.2V
PP1V2_CAM_PCIE_PVDD_FLT
MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM
VOLTAGE=1.2V
PP1V8_CAM
VOLTAGE=1.8V
MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM
GND_CAM_PVSSD
P1V35_CAM_SRVLXD_PHASE
PP1V2_CAM
PP1V8_CAM P1V2_CAM_SRVLXC_PHASE
PCIE_CAMERA_R2D_N
PCIE_CAMERA_D2R_C_N
PCIE_CLK100M_CAMERA_C_N
PP1V2_CAM_XTALPCIEVDD
VOLTAGE=1.35V
MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM
PP1V35_DDR_CLK
PP1V2_CAM_XTALPCIEVDD
PP3V3_S3RS0_CAMERA
TP_CAM_LV_JTAG_TMS
TP_CAM_LV_JTAG_TDO
TP_CAM_LV_JTAG_TDI
TP_CAM_LV_JTAG_TCK
TP_CAM_TEST_MODE2
TP_CAM_TEST_MODE1
TP_CAM_TEST_MODE0
TP_CAM_LV_JTAG_TRSTN
GND_CAM_PVSSC
MEM_CAM_A<14>
MEM_CAM_A<13>
PP1V2_CAM_XTALPCIEVDD
MEM_CAM_A<12>
MEM_CAM_BA<0>
PCIE_CLK100M_CAMERA_C_P
GND_CAM_PVSSD
PP1V8_CAM
CAM_GPIO3
PP1V8_CAM
CAM_RAMCFG0
CAM_XTAL_SEL
CAM_XTAL_FREQ
CAM_TEST_MODE
CAM_TEST_OUT
CAM_UARTCTS
TP_CAM_UARTRTS
CAM_UARTRXD
TP_CAM_UARTTXD
CAM_RAMCFG1
I2C_CAM_SMBDBG_DAT
I2C_CAM_SMBDBG_CLK
GND_CAM_PVSSC
PP1V2_CAM
VOLTAGE=1.2V
MIN_NECK_WIDTH=0.2MM
MIN_LINE_WIDTH=0.6MM
PP1V8_CAM
VOLTAGE=1.2V
MIN_LINE_WIDTH=0.6MM
MAKE_BASE=TRUE
PP1V2_CAM_XTALPCIEVDD
MIN_NECK_WIDTH=0.2MM
PP1V35_CAM
PP1V35_CAM
PP1V2_CAM
PP0V675_CAM_VREF
MIN_NECK_WIDTH=0.2MM
VOLTAGE=0.675V
MIN_LINE_WIDTH=0.6MM
MIN_LINE_WIDTH=0.6MM
P1V2_CAM_SRVLXC_PHASE
MIN_NECK_WIDTH=0.2MM
DIDT=TRUE
MEM_CAM_ZQ_S2
MEM_CAM_A<0>
MEM_CAM_A<1>
MEM_CAM_A<2>
MEM_CAM_A<3>
MEM_CAM_A<5>
MEM_CAM_A<4>
MEM_CAM_A<6>
MEM_CAM_A<7>
MEM_CAM_A<8>
MEM_CAM_A<10>
MEM_CAM_A<9>
MEM_CAM_A<11>
MEM_CAM_BA<1>
MEM_CAM_BA<2>
MEM_CAM_CLK_P
MEM_CAM_CLK_N
MEM_CAM_DM<0>
MEM_CAM_DM<1>
MEM_CAM_CKE
MEM_CAM_CS_L
MEM_CAM_DQ<15>
MEM_CAM_DQ<14>
MEM_CAM_DQ<13>
MEM_CAM_DQ<12>
MEM_CAM_DQ<11>
MEM_CAM_DQ<10>
MEM_CAM_DQ<9>
MEM_CAM_DQ<8>
MEM_CAM_DQ<7>
MEM_CAM_DQ<6>
MEM_CAM_DQ<5>
MEM_CAM_DQ<4>
MEM_CAM_DQ<3>
MEM_CAM_DQ<2>
MEM_CAM_DQ<1>
MEM_CAM_DQ<0>
CAM_JTAG_SRST_L
CAMERA_PWR_EN
CAM_SENSOR_WAKE_L
TP_CAM_JTAG_TMS
TP_CAM_JTAG_TDI
TP_CAM_JTAG_TDO
TP_CAM_JTAG_TRST_L
CAM_JTAG_SRST_L
TP_CAM_JTAG_TCK
I2C_CAM_SMBDBG_DAT
I2C_CAM_SMBDBG_CLK
MIPI_DATA_N
MIPI_DATA_P
PCIE_CAMERA_R2D_P
PCIE_CAMERA_D2R_C_P
PP1V8_CAM
PP1V8_CAM
CAM_DEBUG_RESET_L
CAM_PWR_SEL
CAM_XTAL_SEL
PP1V8_CAM
CAM_XTAL_FREQ
CAM_UARTCTS
CAM_UARTRXD
CLK25M_CAM_CLKP
CLK25M_CAM_CLKN
CAMERA_CLKREQ_L
MEM_CAM_DQS_P<0>
MEM_CAM_DQS_N<0>
MEM_CAM_DQS_P<1>
MEM_CAM_DQS_N<1>
MEM_CAM_RAS_L
MEM_CAM_WE_L
MEM_CAM_CAS_L
MEM_CAM_RESET_L
CAM_TEST_MODE
PP1V8_CAM
MIN_NECK_WIDTH=0.175MM
GND_CAM_PVSSD
VOLTAGE=0V
MIN_LINE_WIDTH=0.6MM
PCIE_WAKE_L
MIN_NECK_WIDTH=0.175MM
VOLTAGE=0V
MIN_LINE_WIDTH=0.6MM
GND_CAM_PVSSC
CAM_TEST_OUT
CAM_PCIE_RESET_L
CAM_PCIE_WAKE_L
CAM_RAMCFG2
I2C_CAM_SCK
I2C_CAM_SDA
P1V35_CAM_SRVLXD_PHASE
MIN_NECK_WIDTH=0.2MM
DIDT=TRUE
MIN_LINE_WIDTH=0.6MM
MIPI_CLK_N
MIPI_CLK_P
CAM_RAMCFG2
CAM_RAMCFG1
CAM_RAMCFG0
VOLTAGE=1.35V
PP1V35_CAM
MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM
<BRANCH>
<SCH_NUM>
<E4LABEL>
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31 OF 78
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31
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31
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31 32 75 www.rosefix.com

OUT
OUT
OUT
OUT
IN
IN
IN
IN
BI
IN
IN
IN
BI
BI
SYM_VER-1
SYM_VER-1
BI
IN
A4
A14
DQSL*
DQL1
VDD
A2
A3
A1
A0
NC
A6
ODT
RESET*
VSSQ VSS
CAS*
RAS*
BA2
BA0
BA1
DQL7
DQL4
DQL3
DQL2
DQL0
ZQ
DQU3
DQU2
DQU4
CS*
CKE DQU7
DQU6
DQSU*
DQU0
DQSL
A13
A11
A10/AP
A8
A5
A7
A9
CK
DML
DMU
DQL5
DQL6
DQSU
DQU1
DQU5
VREFCA
VREFDQ
CK*
WE*
VDDQ
A12/BC*
NC
NC
NC
NC
NC
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
IN
IN
BI
BI
BI
BI
BI
BI
BI
BI
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
NC
NC
OUT
IN
OUT
OUT
IN
IN
IN
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
87 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
D
SIZEDRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
NOTE: TBD PPM crystal required
518S0892
ALS
CAMERA SENSOR
96.2 mA peak
77.2 mA nominal max
31 70
31 70
14 68 70
14 68 70
10%
0.1UF
X5R-CERM 020116V
C403312
10%
0.1UF
X5R-CERM 020116V
C403212
10%
0.1UF
16V 0201X5R-CERM
C403112
10%
0.1UF
16V 0201X5R-CERM
C403012
14 70
14 70
31 70
31 70
5%
0
0201
1/20W
MF
CAM_XTAL:YES
R4009
12
5%
0
0201
1/20W
MF
CAM_XTAL:YES
R4010
12
5%
0
0201
1/20W
MF
CAM_XTAL:NO
R4008
12
5%
0
0201
1/20W
MF
CAM_XTAL:YES
R4007
12
5%
0
0201
1/20W
MF
R4000
12
0.47UF
20%
4V
CERM-X5R-1
201
BYPASS=U4000.H9:4mm
C4004
1
2
402
BYPASS=U4000.K2:4mm
X5R-CERM
20%
2.2UF
10V
C4008
1
2
402
2.2UF
10V
20%
BYPASS=U4000.D2:4mm
X5R-CERM
C4006
1
2
201
1/20W
MF
NOSTUFF
1M
1%
R4012
1
2
25V5%
CAM_XTAL:YES
12PF
NP0-C0G-CERM
0201
C4015
12
CAM_XTAL:YES
5%
25V
0201
NP0-C0G-CERM
12PF
C4014
12
10%
0.1UF
6.3V
0201
CERM-X5R
C4009
1
2
10%
0.1UF
6.3V
0201
CERM-X5R
BYPASS=U4000.R9:4mm
C4007
1
2
402
0.1uF
20%
CERM
10V
C4013
1
2
31 68
31 68
10%
0.1UF
6.3V
0201
CERM-X5R
C4005
1
2
31 68 75
31 68 75
31 68 75
31 68 75
FERR-120-OHM-1.5A
0402-LF
L4010
12
10UF
20%
BYPASS=U4000.B2:4mm
6.3V
CERM-X5R
0402-1
C4003
1
2
BYPASS=U4000.A1:4mm
10UF
20%
CERM-X5R
0402-1
6.3V
C4002
1
2
CRITICAL
90-OHM-50MA
TCM0605-1
PLACE_NEAR=J4002.2:2.54MM
L4009
1
23
4
PLACE_NEAR=J4002.5:2.54MM
90-OHM-50MA
TCM0605-1
CRITICAL
L4007
1
23
4
14 36 39 43 68 72 76
14 36 39 43 68 72 76
201
1/20W
MF
1K
1%
R4022
1
2
201
1/20W
MF
1K
1%
R4023
1
2
OMIT_TABLE
FBGA
CRITICAL
K4B4G1646B-HYK0
4GB-DDR3-256MX16
U4000
N3
P7
L7
R7
N7
T3
T7
P3
N2
P8
P2
R8
R2
T8
R3
M2
N8
M3
K3
J7
K7
K9
L2
E7
D3
E3
F7
F2
F8
H3
H8
G2
H7
F3
G3
C7
B7
D7
C3
C8
C2
A7
A2
B8
A3
J1
J9
L1
L9
M7
K1
J3
T2
B2
D9
G7
K2
K8
N1
N9
R1
R9
A1
A8
C1
C9
D2
E9
F1
H2
H9
M8
H1
A9
B3
T1
T9
E1
G8
J2
J8
M1
M9
P1
P9
B1
B9
D1
D8
E2
E8
F9
G1
G9
L3
L8
31 75
31 75
10%
0.1UF
6.3V
0201
CERM-X5R
C4011
1
2
31 75
31 75
31 75
31 75
31 75
31 75
31 75
31 75
31 75
31 75
10%
0.1UF
6.3V
0201
CERM-X5R
C4010
1
2
31 75
31 75
31 75
31 75
31 75
31 75
31 75
31 75
31 75
31 75
31
31 75
31 75
31 75
31 75
201
1/20W
MF
1%
84.5
R4020
1
2
31 75
31 75
31 75
31 75
31 75
31 75
31 75
31 75
31 75
31 75
31 75
31 75
31 75
31 75
31 75
31 75
31 75
31 75
31 75
201
1/20W
MF
NO STUFF
1%
82
R4021
1
2
31 75
5%
201
1/20W
MF
1K
R4002
1
2
5%
201
1/20W
MF
1K
NOSTUFF
R4003
1
2
201
1/20W
MF
1%
240
R4004
1
2
CAM_WAKE:YES
5%
0
0201
1/20W
MF
R4030
12
5%
25V
100PF
CAM_XTAL:NO
NP0-CERM
0201
C4016
1
2
5%
0
0201
1/20W
MF
CAM_WAKE:NO
R4031
1
2
CRITICAL
CCR20-AK7100-1
F-RT-SM
J4002
14
13
1
10
11
12
2
3
4
5
6
7
8
9
10%
0.1UF
X5R-CERM 020116V
C4061
12
10%
0.1UF
X5R-CERM 020116V
C406212
NOSTUFF
0402-LF
FERR-120-OHM-1.5A
L4011
12
5%
25V
NP0-CERM
0201
100PF
NO STUFF
R4006
1
2
31 75
CAM_XTAL:YES
CRITICAL
25.000MHZ-12PF-20PPM
SM-3.2X2.5MM
Y4000
24
13
31 71
31 71
31 70
31 70
12 68 70
12 68 70
5%
201
1/20W
MF
100K
R4005
1
2
17 71
SYNC_DATE=08/12/2013
Camera 2 of 2
SYNC_MASTER=J44
PP0V675_CAM_VREF
VOLTAGE=0.675V
MIN_NECK_WIDTH=0.2 mm
MIN_LINE_WIDTH=0.5 mm
PP0V675_MEM_CAM_VREFCA
PP1V35_CAM
MIPI_CLK_CONN_N
MIPI_DATA_N
MIPI_DATA_P
MIPI_CLK_P
MIPI_CLK_N
MEM_CAM_DQ<15>
MEM_CAM_RAS_L
MEM_CAM_CLK_P
MEM_CAM_CLK_N
MEM_CAM_DQ<0>
MEM_CAM_DQ<1>
MEM_CAM_BA<1>
MEM_CAM_A<14>
MEM_CAM_BA<0>
MEM_CAM_BA<2>
MEM_CAM_DM<1>
MEM_CAM_A<6>
MEM_CAM_A<11>
MEM_CAM_A<12>
MEM_CAM_A<13>
MEM_CAM_CKE_R
MEM_CAM_CKE
MEM_CAM_A<4>
PCIE_CLK100M_CAMERA_C_N
PCIE_CLK100M_CAMERA_C_PPCIE_CLK100M_CAMERA_N
PCIE_CAMERA_D2R_C_N
MEM_CAM_WE_L
MEM_CAM_CS_L
MEM_CAM_CAS_L
MEM_CAM_A<9>
MEM_CAM_A<10>
MEM_CAM_A<8>
MEM_CAM_A<7>
MEM_CAM_A<2>
MEM_CAM_DQ<13>
MEM_CAM_DQ<9>
MEM_CAM_DQS_P<1>
MEM_CAM_DQ<6>
MEM_CAM_DQ<5>
MEM_CAM_DQS_P<0>
MEM_CAM_DQS_N<1>
MEM_CAM_DQ<14>
MEM_CAM_DQ<12>
MEM_CAM_DQ<10>
MEM_CAM_DQ<11>
MEM_CAM_DQ<2>
MEM_CAM_DQ<3>
MEM_CAM_DQ<4>
MEM_CAM_DQ<7>
MEM_CAM_DQS_N<0>
CLK25M_CAM_CLKP
PCIE_CAMERA_R2D_C_N
PCIE_CAMERA_D2R_C_P PCIE_CAMERA_R2D_N
PCIE_CAMERA_D2R_N
PCIE_CAMERA_D2R_P
PCIE_CAMERA_R2D_P
SYSCLK_CLK25M_CAMERA
PCIE_CAMERA_R2D_C_P
MEM_CAM_DM<0>
CLK25M_CAM_XTALP_R
MEM_CAM_A<0>
PP1V8_CAM
MEM_CAM_A<3>
MEM_CAM_RESET_L
MEM_CAM_ZQ_DDR
PCIE_CLK100M_CAMERA_P
CLK25M_CAM_CLKN
CAM_SENSOR_WAKE_L
MEM_CAM_DQ<8>
PP5V_S0
PP5V_S4
CAM_SENSOR_WAKE_L_CONN
SMBUS_SMC_1_S0_SCL
I2C_CAM_SCK
I2C_CAM_SDA
MIPI_CLK_CONN_P
MEM_CAM_A<5>
MEM_CAM_A<1>
MEM_CAM_ODT
PP0V675_MEM_CAM_VREFDQ
MIN_LINE_WIDTH=0.5 mm
VOLTAGE=0.675V
MIN_NECK_WIDTH=0.2 mm
PP5V_S3RS0_ALSCAM_F
VOLTAGE=5V
MIN_NECK_WIDTH=0.2 mm
MIN_LINE_WIDTH=0.5 mm
MIPI_DATA_CONN_P
SMBUS_SMC_1_S0_SDA
MIPI_DATA_CONN_N
CAM_SENSOR_WAKE_L_CONN
CLK25M_CAM_XTALN
CLK25M_CAM_XTALP
<BRANCH>
<SCH_NUM>
<E4LABEL>
40 OF 120
32 OF 78
31 75
75
31 75
68 75
71
31
31
16 17 41 44 45 53 54 58 60 61
65 68
33 46 55 56 57 60 62 63 65 66
68
32 68
68 75
75
75
68
68 75
68 75
32 68
71
71 www.rosefix.com

SYM_VER-1
OUT
OUT
IN
IN
FAULT*
IN_1
IN_0
ILIM
OUT1
OUT2
EN
GND
THRM
PAD
VCC
GND
SELOE*
D+
D-
Y+
Y-
M+
M-
BI
BI
IN
OUT
IN
GND
VBUS
SSTX+
SSRX-
GND
SSTX-
D+
D-
GND
SXRX+
OUT
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
87 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
D
SIZEDRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
RIGHT USB PORT A
Current limit per port (R4600+R4601): 2.19A min / 2.76A max
USB Port Power Switch
THE PI3USB102E CAN CLAMP VOLTAGE IN THE INTERNAL USB PINS
Mojo SMC Debug Mux
H USB (D)
L SMC (M)
SEL OUTPUT
X5R-CERM
0201
0.01UF
16V
10%
C4605
1
2
90-OHM
CRITICAL
DLP0NS
L4600
12
34
14 68 71
14 68 71
14 68 71
14 68 71
GND_VOID=TRUE
6.3V
CERM-X5R 0201
0.1UF
10%
C4620
12
GND_VOID=TRUE
6.3V
CERM-X5R 0201
0.1UF
10%
C4621
12
CRITICAL
TSSLP-2-1
ESD0P2RF-02LS
GND_VOID=TRUE
D4610
1
2
GND_VOID=TRUE
CRITICAL
ESD0P2RF-02LS
TSSLP-2-1
D4620
1
2
ESD0P2RF-02LS
TSSLP-2-1
CRITICAL
GND_VOID=TRUE
D4611
1
2
ESD0P2RF-02LS
TSSLP-2-1
CRITICAL
GND_VOID=TRUE
D4621
1
2
MF
1/20W
22.1K
1%
201
R4601
1
2
SON
CRITICAL
TPS2557DRB
U4600
4
8
1
5
2
3
6
7
9
TQFN
CRITICAL
PI3USB102EZLE
SIGNAL_MODEL=MOJO_MUX_SMSC
U4650
6
7
3
4
5
8 10
9
2
1
BYPASS=U4650.9:3:5mm
10V
0201
X5R-CERM
0.1UF
10%
C4650
1
2
100K
201
MF
1/20W
5%
R4650
1
2
14 71
14 71
36 37 71
36 37 71
36
TSSLP-2-1
ESD0P2RF-02LS
CRITICAL
D4600
1
2
ESD0P2RF-02LS
CRITICAL
TSSLP-2-1
D4601
1
2
USB3.0-J44-ALT
CRITICAL
F-RT-TH
J4600
5
6
4
7
10
11
20
21
22
23
12
13
14
15
16
17
18
19
9
3
2
8
1
10UF
0402-2
CERM-X5R
20%
6.3V
C4695
1
2
0201
X5R-CERM
16V
0.1UF
10%
C4691
1
2
14 16
10UF
0402-2
CERM-X5R
20%
6.3V
C4690
1
2
22.1K
1%
1/20W
MF
201
R4600
1
2
20%
POLY-TANT
CRITICAL
220UF-35MOHM
CASE-B2-SM1
6.3V
C4696
1
2
0603
FERR-120-OHM-3A
CRITICAL
L4605
12
External A USB3 Connector
SYNC_MASTER=J44 SYNC_DATE=08/12/2013
USB2_EXTA_MUXED_N
SMC_DEBUGPRT_EN_L
USB2_EXTA_MUXED_P
PP3V42_G3H
USB_EXTA_P
USB_EXTA_N
SMC_DEBUGPRT_RX_L
SMC_DEBUGPRT_TX_L
USB_ILIM
USB_PWR_EN
PP5V_S4
XDP_USB_EXTA_OC_L
PP5V_S3_LTUSB_A_ILIM
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.15 mm
VOLTAGE=5V
USB_ILIM_L
USB3_EXTA_R2D_C_P
USB3_EXTA_R2D_C_N
USB3_EXTA_D2R_P
USB2_EXTA_MUXED_F_N
USB2_EXTA_MUXED_F_P
USB3_EXTA_R2D_N
USB3_EXTA_D2R_N
USB3_EXTA_R2D_P
PP5V_S3_LTUSB_A_F
VOLTAGE=5V
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.375 mm
<BRANCH>
<SCH_NUM>
<E4LABEL>
46 OF 120
33 OF 78
71
71
17 30 34 36 37 38 39 45 51 52
61 65 68
61
32 46 55 56 57 60 62 63 65 66
68
71
71
68 71
71
68 www.rosefix.com

NC
P2_4
P2_6
VDD
P0_4
P0_2
P2_0
P2_2
P0_0P2_3
P2_1
P4_7
P4_5
P4_3
P4_1
P3_7
P3_5
P3_3
P3_1
P5_7
P5_5
P5_3
P5_1
P1_1
P1_3
P1_5
P1_7
P7_7 VSS D+
D- VDD P7_0
P1_0
P1_2
P1_4
P1_6
P5_0
P5_2
P5_4
P5_6
P3_0
P3_2
P3_4
P4_0
P4_2
P4_4
P4_6
P3_6
P2_5
P2_7
P0_3
VSS
P0_5
P0_7
P0_6
PAD
THRML
(SYM-VER2)
P0_1
OUT
IN
S
D
G
S
D
G
NC NC
NC
OUT
OUT
VDD
OUT_1
GND
THRM
OE
OUT_ALL#
OUT_3
OUT_2
IN_1
IN_3
IN_2
(IPD)
(IPD)
(IPD)
(IPD)
PAD
IN
NC
NC
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
87 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
D
SIZEDRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
Spare MOSFET symbol
LID CLOSE => SMC_LID_LC < 0.50V
PSOC USB CONTROLLER
WHEN THE LID IS CLOSED
THIS ASSUMES THERE’S A PP3V42_G3H PULL UP ON MLB
LID OPEN => SMC_LID_LC ~ 3.42V
PLACE THESE COMPONENTS CLOSE TO J4800
THE TPAD BUTTONS WILL BE DISABLE
TPAD Buttons Disable
ISSP SDATA/I2C SDA
(PP3V3_S3_PSOC)
ISSP SCLK/I2C SCL
337S4426
Left shift, option & control keys combined with power button cause SMC RESET# assertion.
SMC Manual Reset & Isolation
No IPD on OE input pin PP3V3_S4 (symbol error).
Pull-up in U5110.
IPD Flex Connector
518S0848
- USB INTERFACES TO MLB
- SPI HOST TO Z2
518S0752
Keyboard Connector
Keys ANDed with PSoC power to isolate when PSoC is not powered.
PIN NAME
36E-3 W
16.32E-6 W
0.255E-6 W
POWERV_SNS
0.204 V
0.0255 V
0.6 V
75.2E-6 W
0.72E-3 W
96E-6 W
294E-6 W
0.012 V
0.012 V
0.021 V
0.0188 V
R_SNS
2.55 KOHM
0.2 OHM
1.5 OHM
10 OHM
4.7 OHM
60MA (MAX)
10UA
80UA
CURRENT
V+
VDD
IC
4MA (MAX)
14MA (MAX)
8MA (TYP)
60MA (MAX)
VDD
VIN
VOUT
18V BOOSTER
TMP102
3V3 LDO
PSOC
- TRACKPAD PICK BUTTONS
- KEYBOARD SCANNER
100PF
5%
25V
0201
NP0-CERM
BYPASS=U4801.22:19:5 mm
C4802
1
2
CERM-X5R
0.1UF
6.3V
10%
0201
BYPASS=U4801.22:19:8 mm
C4803
1
2
BYPASS=U4801.22:19:11 mm
4.7UF
6.3V
20%
X5R
402
C4801
1
2
CRITICAL
OMIT
CY8C24794
MLF-1
U4801
20
21
45
54
46
53
47
52
48
51
25
18
26
17
27
16
28
15
412
421
43
56
44
55
3310
349
358
367
376
385
394
403
2914
3013
3112
3211
24
23
57
2249
19
50
29 36 38
PLACE_SIDE=BOTTOM
402
5%
1/16W
MF-LF
1.5
R4804
21
201
5%
220K
MF
1/20W
R4803
1
2
5%
0201
NP0-CERM
25V
100PF
BYPASS=U4801.49:50:5 mm
C4804
1
2
BYPASS=U4801.49:50:8 mm
CERM-X5R
10%
6.3V
0201
0.1UF
C4805
1
2
4.7UF
X5R
402
20%
6.3V
BYPASS=U4801.49:50:11 mm
C4806
1
2
10%
X5R-CERM
10V
PLACE_NEAR=J4800.4:4MM
0.1UF
0201
C4807
1
2
0402-LF
FERR-120-OHM-1.5A
PLACE_NEAR=J4800.4:3MM
L4807
12
MF
0
1/20W
5%
0201
R4808
12
NOSTUFF
6.3V
CERM-X5R
10%
0.1UF
0201
C4808
1
2
51K
MF
201
1/20W
5%
R4800
1
2
36 37 38
SOT-563
DMN5L06VK-7
Q4801
6
2
1
CRITICAL
FF14-18C-R11DL
F-RT-SM
J4800
20
19
1
10
11
12
13
14
15
16
17
18
2
3
4
5
6
7
8
9
DMN5L06VK-7
SOT-563
Q4801
3
5
4
37
16V
0402
BYPASS=U4850.10:5:5 mm
X7R-CERM
0.1UF
10%
C4850
1
2
36 37 68
PLACE_NEAR=J4813.5:5MM
20%
10V
CERM
402
0.1UF
C4810
1
2
1K
5%
1/16W
402
MF-LF
R4810
12
5%
0
MF-LF
1/16W
402
R4815
12
1%
1/16W
402
MF-LF
113
R4814
12
FF14A-30C-R11DL-B-3H
CRITICAL
F-RT-SM
J4813
31
32
1
10
11
12
13
14
15
16
17
18
19
2
20
21
22
23
24
25
26
27
28
29
3
30
4
5
6
7
8
9
SLG4AP4103
TQFN
U4850
5
1
2
3
4
9
8
7
6
11
10
201
5%
MF
24
1/20W
R4802
12
201
5%
24
MF
1/20W
R4801
12
61
SYNC_MASTER=J44 SYNC_DATE=08/12/2013
KEYBOARD/TRACKPAD (1 OF 2)
Z2_KEY_ACT_L
Z2_HOST_INTN
SMBUS_SMC_2_S3_SCL
PP5V_S4_CUMULUS
MIN_NECK_WIDTH=0.20MM
MIN_LINE_WIDTH=0.50MM
VOLTAGE=5V
Z2_SCLK
Z2_CLKIN
PSOC_MOSI
WS_LEFT_SHIFT_KEY
WS_LEFT_OPTION_KEY
WS_CONTROL_KEY
MIN_NECK_WIDTH=0.20MM
MIN_LINE_WIDTH=0.50MM
PP3V3_S3_PSOC
VOLTAGE=3.3V
WS_KBD18
SMC_TPAD_RST_L
WS_KBD15_C
WS_LEFT_OPTION_KEY
PSOC_MISO
Z2_MISO
PSOC_F_CS_L
Z2_KEY_ACT_L
Z2_MOSI
WS_KBD17
WS_KBD11
WS_KBD10
WS_KBD8
WS_KBD7
WS_KBD1
WS_KBD2
WS_KBD3
WS_CONTROL_KEY
PSOC_MISO
PSOC_F_CS_L
PSOC_MOSI
PSOC_SCLK
Z2_MISO
Z2_CS_L
Z2_SCLK
Z2_MOSI
TPAD_VBUS_EN
USB_TPAD_P
USB_TPAD_N
PP3V42_G3H
PP3V3_S4
WS_LEFT_OPTION_KBD
PP3V3_S4
WS_KBD15_CAP
WS_KBD16_NUM
WS_KBD8
WS_KBD7
WS_CONTROL_KBD
WS_LEFT_OPTION_KBD
WS_LEFT_SHIFT_KBD
WS_KBD23
WS_KBD22
WS_KBD19
WS_KBD20
WS_KBD21
WS_KBD9
WS_KBD10
WS_KBD12
WS_KBD11
WS_KBD13
WS_KBD14
WS_KBD17
WS_KBD18
WS_KBD6
WS_KBD5
WS_KBD2
WS_KBD1
WS_KBD15_C
WS_KBD16N
SMC_ONOFF_L WS_KBD_ONOFF_L
WS_CONTROL_KBD
WS_KBD4
WS_KBD3
SMBUS_SMC_2_S3_SDA
WS_KBD16N
WS_KBD14
WS_LEFT_SHIFT_KEY
PP3V42_G3H
PP3V3_S4
PICKB_L
WS_LEFT_SHIFT_KBD
WS_KBD20
WS_KBD5
WS_KBD4
WS_KBD19
WS_KBD13
WS_KBD22
WS_KBD23
TP_ISSP_SDATA_P1_0
WS_KBD9
TP_PSOC_SCL
TP_PSOC_SDA
TP_ISSP_SCLK_P1_1
TP_PSOC_P1_3
Z2_HOST_INTN WS_KBD6
USB_TPAD_R_P
USB_TPAD_R_N TP_P7_7
Z2_CLKIN
WS_KBD21
WS_KBD12
SMC_PME_S4_WAKE_L
BUTTON_DISABLE
PICKB_L
Z2_CS_L
PSOC_SCLK
PP3V3_TPAD_CONN
MIN_NECK_WIDTH=0.20MM
MIN_LINE_WIDTH=0.50MM
VOLTAGE=3.3V
PP3V3_S4
PP5V_S5
BUTTON_DISABLE
SMC_LID
34 OF 78
<BRANCH>
<SCH_NUM>
<E4LABEL>
48 OF 120
34 68
34 68
36 39 68 76
68
34 68
34 68
34 68
34
34
34
34 68
34
34
34 68
34 68
34 68
34 68
34 68
34 68
34 68
34 68
34 68
34 68
34 68
34 68
34 68
34
34 68
34 68
34 68
34 68
34 68
34 68
34 68
34 68
14 71
14 71
17 30 33 34 36 37 38 39 45 51
52 61 65 68
18 29 34 37 38 42 60 63 64 65
68
34 68
18 29 34 37 38 42 60 63 64 65
68
68
68
34 68
34 68
34 68
34 68
34 68
34 68
34 68
34 68
34 68
34 68
34 68
34 68
34 68
34 68
34 68
34 68
34 68
34 68
34 68
34 68
34 68
34 68
34
34
68
34 68
34 68
34 68
36 39
68 76
34
34 68
34
17 30 33 34 36 37 38 39 45 51
52 61 65 68
18 29 34 37 38 42 60
63 64 65 68
34 68
34 68
34 68
34 68
34 68
34 68
34 68
34 68
34 68
34 68
34 68
34 68
71
71
34 68
34 68
34 68
34
34 68
34 68
34 68
68 18 29 34 37 38 42 60 63 64 65
68
56 65 68
34 www.rosefix.com

NC
OUT
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
87 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
D
SIZEDRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
Keyboard Backlight Connector
PIN 6 WAS USED KEYBOARD BKLT DETECTION
ON KEYBOARD BACKLIGHT FLEX
J4915 PIN 5 IS GROUNDED
NOT USED ANYMORE
516S0899
.
F-ST-SM
AA07A-S010-VA1
CRITICAL
J4915
11
12
13
14
1
10
2
34
56
78
9
SYNC_MASTER=J44 SYNC_DATE=08/12/2013
KEYBOARD/TRACKPAD (2 OF 2)
KBDLED_CATHODE1KBDLED_CATHODE2
PPVOUT_S0_KBDBKLT PPVOUT_S0_KBDBKLT
<BRANCH>
<SCH_NUM>
<E4LABEL>
49 OF 120
35 OF 78
58 68 58 68
35 58 68 35 58 68 www.rosefix.com

LPC0AD3
LPC0CLK
LPC0FRAME*
LPC0AD1
LPC0AD2
AIN08
AIN07LPC0CLKRUN*
LPC0PD*
AIN13
AIN14
PM7/FAN0TACH0
PM6/FAN0PWM0
AIN04
C1-
I2C2SDA
AIN05
AIN09
AIN11
AIN21
AIN23
PK7/FAN0TACH1
AIN15
AIN06
AIN10
AIN20
AIN22
T1CCP1/PJ1
PK5
LPC0AD0
AIN12
PECI0RX
PECI0TX
PK6/FAN0PWM1
LPC0RESET*
PQ0/IRQ124
PP6/IRQ122
PN3/FAN0TACH2
I2C0SDA
AIN01
AIN00
PQ1/IRQ125
I2C0SCL
U1TX/PB1
USB0DP
USB0DM
AIN03
AIN02
T0CCP1/PB7
T0CCP0/PB6
PQ2/IRQ126
U1RX/B0
LPC0SCI*
AIN17
AIN16
PN2/FAN0PWM2
WT4CCP1/PH7
AIN18
AIN19
WT4CCP0/PH6
WT3CCP1/PH5
WT5CCP1/PM3
LPC0SERIRQ
PH3/FAN0TACH5
WT3CCP0/PH4
PH2/FAN0PWM5
PP3/IRQ119
PP4/IRQ120
C0-
WT2CCP0/PH0
WT2CCP1/PH1
PQ5/IRQ129
PP7/IRQ123
WT0CCP0/PG4
I2C3SDA
SSI1FSS/PF3
PC5/C1+
U0RX
SSI0RX/PA4
PP5/IRQ121
PQ7/IRQ131
WT0CCP1/PG5
I2C3SCL
SSI1CLK/PF2
PN4/FAN0PWM3
PP1/IRQ117
U0TX
SSI0CLK/PA2
SSI0FSS/PA3
I2C1SCL
PP2/IRQ118
PQ6/IRQ130
I2C4SDA
SSI1RX/PF0
PN7/FAN0TACH4
PP0/IRQ116
SSI0TX/PA5
I2C1SDA
I2C5SDA
PQ3/IRQ127
PQ4/IRQ128
I2C4SCL
I2C2SCL
SSI1TX/PF1
PN6/FAN0PWM4
PN5/FAN0TACH3
I2C5SCL
T3CCP0/PJ4/C2+
T3CCP1/PJ5/C2-
PF4
PF5
T1CCP0/PJ0
T2CCP0/PJ2
T2CCP1/PJ3
C0+
(1 OF 2)
VDDC
VREFA-
SWO/TDO
TDI
RST*
HIB*
WAKE*
XOSC0
VREFA+
VDDA
GNDA
PK4/RTCCLK
GND
NC
OSC0
XOSC1
SWCLK/TCK
SWDIO/TMS
OSC1
VBAT
VDD
(2 OF 2)
IN
IN
BI
BI
BI
BI
IN
IN
IN
BI
OUT
IN
OUT
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
OUT
OUT
OUT
OUT
OUT
IN
OUT
OUT
OUT
OUT
IN
OUT
IN
IN
OUT
OUT
OUT
OUT
NC
OUT
BI
OUT
IN
OUT
OUT
IN
OUT
OUT
IN
OUT
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
OUT
OUT
BI
OUT
OUT
IN
OUT
IN
OUT
IN
IN
OUT
OUT
IN
IN
IN
IN
OUT
BI
OUT
BI
IN
OUT
IN
IN
OUT
OUT
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
87 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
D
SIZEDRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
those designated as inputs require pull-ups.
pins designed as outputs can be left floating,
Unused pins have "SMC_Pxx" names. Unused
NOTE:
(OD)
(OD)
SMS INTERRUPT IS NOT USED, PULL UP TO SMC RAIL.
NOTE:
(OD)
(OD)
(OD)
(OD)
(OD)
(OD)
(OD)
(OD)
(OD)
(OD)
(OD)
(OD)
(OD)
(OD)
(OD)
(OD)
(OD)
(OD)
(PL7)
(PL6)
BGA
LM4FSXAH5BB
OMIT_TABLE
U5000
E2
E1
F2
F1
B3
A3
B4
A4
B5
A5
B6
A6
C1
C2
B1
B2
G2
G1
H1
H2
B7
A7
B8
A8
K2
K1
L2
E10
D13
M4
N2
N8
M8
L8
K8
N7
M7
N4
N3
B13
A13
C12
D11
H12
G11
D12
F13
C13
F12
H13
L1
C4
C6
L9
K9
J4
J2
B12
C11
A12
H11
L13
G3
D10
L11
N12
N11
M11
M13
L12
M5
J12
J13
L5
D8
K6
D4
E4
F5
N5
N6
K5
M6
L6
M2
M3
L4
N1
L10
K10
M9
N9
F4
F3
C9
B9
A9
C8
D5
C5
L3
M1
F11
E11
E13
E12
K7
L7
K3
K4
J3
H4
H3
G4
H10
BGA
LM4FSXAH5BB
OMIT_TABLE
U5000
A1
C7
K11
D9
E5
F9
H5
H9
J5
J8
J11
C3
E3
M12
A2
G12
G13
B11
G10 C10
A10
A11
B10
K12
D7
E6
E8
E9
F10
J7
J9
J10
D3
J1
J6
K13
D6
D1
D2
N13
M10
N10
SM
PLACE_NEAR=U5000.A1:4MM
XW5000
12
37 38 45
52 68
37
1/20W
5%
201
MF
1M
R5002
1
2
10V
10%
0201
X5R-CERM
0.1UF
C5006
1
2
10V
10%
0201
X5R-CERM
0.1UF
C5005
1
2
10V
10%
0201
X5R-CERM
0.1UF
C5009
1
2
10V
10%
0201
X5R-CERM
0.1UF
C5008
1
2
10V
10%
0201
X5R-CERM
0.1UF
C5004
1
2
10V
10%
0201
X5R-CERM
0.1UF
C5003
1
2
10V
10%
0201
X5R-CERM
0.1UF
C5007
1
2
14 45 68 72
14 45 68 72
14 45 68 72
14 45 68 72
17 68 72
14 45 68 72
18
15 45 68
13 45 68
13 45 68
13
39 62 68 76
39 62 68 76
14 32 39 43 68 72 76
14 32 39 43 68 72 76
34 39 68 76
34 39 68 76
39 43 63 76
39 43 63 76
38
38
39 51 52 68 76
39 51 52 68 76
38 40
38 40
38 40
38 40
38 40
38 42
38 40
38 41
38 40
38 40
38 41
38
38 41
38
38 41
38
38 42
38 41
38 41
38 41
38 42
38 42
38 42
38 42
37 56 61
13 72
17 24 25 37 72
37
33 37 71
33 37 71
38
45 72
45 72
45 72
45 72
33
38
16 17 61
37
13 16 72
13 17 68 72
13 37
15
37 70
37 70
37 45 68
37 45 68
38
38
38
58
44
44
37
29 34 38
34 37 38
37
37 51 52
13 18
13 17 18 61 63 68
13 18 29 61 63
13 61
34 37 68
18 23 37
37 61
13 25
63
38
38
38
38
56 61
17
0402
30-OHM-1.7A
L5001
12
6 37 53 70
30
38
30
51
13 16 17 72
6 70
37
38 40 60
10V
10%
0201
X5R-CERM
0.1UF
PLACE_NEAR=U5000.K13:5MM
C5016
1
2
10V
10%
0201
X5R-CERM
0.1UF
PLACE_NEAR=U5000.K13:5MM
C5015
1
2
10V
10%
0201
X5R-CERM
0.1UF
PLACE_NEAR=U5000.J1:5MM
C5013
1
2
PLACE_NEAR=U5000.D6:5MM
6.3V
20%
0201-1
X5R
1.0UF
C5010
1
2
10V
10%
0201
X5R-CERM
0.1UF
C5001
1
2
6.3V
20%
0201
X5R
1UF
C5002
1
2
38
38
6.3V
20%
0201
X5R
1UF
BYPASS=U5000.D2:D1:1MM
C5021
1
2
10V
10%
0201
X5R-CERM
0.01UF
BYPASS=U5000.D2:D1:1MM
C5020
1
2
38
10V
10%
0201
X5R-CERM
0.1UF
PLACE_NEAR=U5000.J1:5MM
C5011
1
2
10V
10%
0201
X5R-CERM
0.1UF
PLACE_NEAR=U5000.J6:5MM
C5012
1
2
6.3V
20%
0201-1
X5R
1.0UF
PLACE_NEAR=U5000.J6:5MM
C5014
1
2
6.3V
20%
0201-1
X5R
1.0UF
PLACE_NEAR=U5000.D6:5MM
C5017
1
2
37 38
38 63
37
37
30
38
SMC
SYNC_MASTER=J44 SYNC_DATE=08/12/2013
SMC_DP_HPD_L
NC_SMC_BIL_BUTTON_L
SMC_PME_S4_WAKE_L
NC_SMC_T101_COM_1
SMC_PCH_SUSWARN_L
PM_SLP_S0_L
NC_SMC_ACTUATOR_DISABLE_L
NC_SMC_5VSW_PWR_EN
SMC_PCH_SUSACK_L
SMC_ONOFF_L
SMC_TX_L
SMC_ADAPTER_EN
PP3V42_G3H
SMC_FAN_0_TACH
PM_DSW_PWRGD
SMC_S5_PWRGD_VIN
SMC_PM_G2_EN
SMC_BOARDID
SMC_OOB1_D2R_L
SMC_CPU_VSENSE
SMC_OOB1_R2D_L
SMC_LCDPANEL_ISENSE
SMC_TBT_ISENSE
SMC_OTHER5V_HI_ISENSE
SMC_DCIN_VSENSE
NC_SMC_GFX_OVERTEMP
NC_BDV_BKL_PWM
PM_BATLOW_L
CPU_CATERR_L
SPI_SMC_MISO
SPI_SMC_CLK
SPI_DESCRIPTOR_OVERRIDE_L
LPC_CLK24M_SMC
SMC_CPU_ISENSE
SMC_LCDBKLT_ISENSE
SMC_PP5VS0_ISENSE
SMC_PP3V3S0_ISENSE
SMC_SSD_ISENSE
SMC_ADC12_PD
SMC_DDR_ISENSE
SMC_OTHER3V3_HI_ISENSE
SMC_DCIN_ISENSE
SMC_BMON_ISENSE
SMC_TMS
SMC_TCK
SMC_DEBUGPRT_EN_L
SMC_RUNTIME_SCI_L
NC_SMC_XOSC1
SMC_CPUDDR_ISENSE
SMC_PBUS_VSENSE
SMC_CPU_IMON_ISENSE
SMC_XTAL
WIFI_EVENT_L
SMC_WAKE_L
LPC_AD<2>
SMC_BMON_DISCRETE_ISENSE
NC_SMC_HIB_L
SMC_RESET_L
SMC_TDI
SMC_TDO
SPI_SMC_CS_L
LPC_AD<0> SMC_CPU_HI_ISENSE
SMC_CLK32K
SMC_PCH_ISENSE
SMC_EXTAL
GND_SMC_AVSS
PP3V3_S5_AVREF_SMC
SMC_CAMERA_ISENSE
SMC_ADC16_PD
SMC_PWRFAIL_WARN_L
SMC_WIFI_PWR_EN
MIN_NECK_WIDTH=0.1MM
MIN_LINE_WIDTH=0.25MM
VOLTAGE=3.3V
PP3V3_S5_SMC_VDDA
MIN_NECK_WIDTH=0.1MM
MIN_LINE_WIDTH=0.25MM
VOLTAGE=1.2V
PP1V2_S5_SMC_VDDC
SMC_FAN_0_CTL
NC_SMC_GFX_THROTTLE_L
SMC_DEBUGPRT_RX_L
SMC_DELAYED_PWRGD
SMC_PROCHOT
LPC_AD<3>
SMC_LRESET_L
SMC_DEBUGPRT_TX_L
SMC_ADC11_PD
NC_SMC_SYS_LED
SMC_LID
LPC_AD<1>
CPU_PROCHOT_L
PM_CLKRUN_L
LPC_PWRDWN_L
LPC_SERIRQ
LPC_FRAME_L
NC_MEM_EVENT_L
NC_SMC_FAN_1_TACH
NC_SMBUS_SMC_4_ASF_SCL
SMBUS_SMC_1_S0_SCL
SMC_WAKE_SCI_L
SMBUS_SMC_0_S0_SCL
SMBUS_SMC_0_S0_SDA
SMBUS_SMC_1_S0_SDA
SMBUS_SMC_2_S3_SCL
SMBUS_SMC_3_SDA
SMBUS_SMC_2_S3_SDA
SMBUS_SMC_3_SCL
SMBUS_SMC_5_G3_SCL
NC_SMC_FAN_1_CTL
NC_SMBUS_SMC_4_ASF_SDA
SMBUS_SMC_5_G3_SDA
SMC_SYS_KBDLED
PM_SLP_S5_L
PM_SLP_S4_L
PM_SLP_S3_L
SMC_BC_ACOK
SMS_INT_L
SMC_SENSOR_ALERT_L
SMC_S4_WAKESRC_EN
NC_SMC_FAN_5_CTL
SMC_SENSOR_PWR_EN
CPU_THRMTRIP_3V3
PM_SYSRST_L
PM_PWRBTN_L
SMC_PME_S4_DARK_L
SYS_ONEWIRE
CPU_PECI_R
SMC_RX_L
SMC_PECI_L
SMC_TOPBLK_SWP_L
SPI_SMC_MOSI
S5_PWRGD
PM_PCH_SYS_PWROK
ALL_SYS_PWRGD
SMC_THRMTRIP
SMC_VCCIO_CPU_DIV2
<BRANCH>
<SCH_NUM>
<E4LABEL>
50 OF 120
36 OF 78
38
38
17 30 33 34 37 38 39 45 51 52
61 65 68
37 45 68
37 45 68
37
37 45 68
37 45 68
37
37
38
40 41
42
37 68 www.rosefix.com

IN
OUT
BI
IN
IN
IN OUT
IN OUT
OUT
IN
BIOUT
IN
OUT
SYM_VER_2
GS
D
S
D
G
S D
G
NCNC
IN
SN0903049
PAD
REFOUT
MR1*
THRM
GND
RESET*
DELAY
MR2*
VINV+
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
87 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
D
SIZEDRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
SMC_DP_HD_L IS NOT USED ANY MORE
To SMC
SMC USB Clock require these crystal
SMC Crystal Circuit
SMC Reset "Button", Supervisor & AVREF Supply
SMC12 PECI Support
Debug Power "Buttons"
values:5,6,8,10,12,16,18,20,24,25 MHz
MR1* and MR2* must both be low to cause manual reset.
Used on mobiles to support SMC reset via keyboard.
NOTE: Internal pull-ups are to VIN, not V+.
Mobiles: 3.42V
(IPU)
(IPU)
From SMC
From/To CPU/PCH
Desktops: 5V
10K
MF1/20W 2015%
R5170 12
100K
MF1/20W 2015%
R5171 12
10K
MF1/20W 2015%
R5173 12
100K
MF1/20W 2015%
R5174 12
10K
MF1/20W 2015%
R5177 12
10K
MF1/20W 2015%
R5178 12
10K
MF1/20W 2015%
R5179 12
10K
MF1/20W 2015%
R5180 12
10K
MF1/20W 2015%
R5185 12
36 37
15 37 72
PLACE_SIDE=TOP
SILK_PART=PWR_BTN
OMIT
MF-LF
603
1/10W
0
5%
R5115
1
2
6 36 53 70
36
2.49K
1%
MF
1/20W
201
R5110
12
25V
12PF
NP0-C0G-CERM
0201
5%
C5111
1
2
100K
MF1/20W 2015%
R5187 12
PLACE_SIDE=BOTTOM
SILK_PART=PWR_BTN
OMIT
MF-LF
603
1/10W
0
5%
R5116
1
2
SILK_PART=SMC_RST
PLACE_SIDE=BOTTOM
OMIT
MF-LF
603
1/10W
0
5%
R5101
1
2
34 36 37 68
34
0.01UF
X5R-CERM
0201
10%
10V
C5101
1
2
402
0.47UF
CERM-X5R
10%
6.3V
C5120
1
2
0.01UF
X5R-CERM
0201
10%
10V
C5126
1
2
100K
MF
1/20W
201
5%
R5100
1
2
36 38 45 52 68
13
22
PLACE_NEAR=U0500.AE6:5.1mm MF1/20W 2015%
R5112
12
36
100K
MF1/20W 2015%
R5190 12
20K
MF1/20W 2015%
R5175 12
20K
MF1/20W 2015%
R5176 12
10K
MF1/20W 2015%
R5186 12
1K
MF
1/20W
201
5%
R5188
1
2
25V
12PF
NP0-C0G-CERM
0201
5%
C5110
1
2
1%
100K
MF
1/20W
201
R5197
1
2
100K
1%
MF
1/20W
201
R5196
1
2
34 36 37 68
36 70
NOSTUFF
1.6K
MF
1/20W
201
5%
R5153
1
2
MF
1/20W
0201
0
5%
R5152
12
330
MF
1/20W
201
5%
R5151
1
2
100K
MF1/20W 2015%
R5117 12
100K
MF1/20W 2015%
R5167 12
6
70
36 70
43
MF
1/20W
201
5%
R5134
12
15 37 72
CRITICAL
DFN1006-3
MMBT3904LP-7
Q5158
1
3
2
36 37
10UF
X5R-CERM
0402-1
20%
10V
C5125
1
2
3.3K
MF
1/20W
201
5%
R5158
12
100K
MF1/20W 2015%
R5191 12
3.2X2.5MM-SM
12.000MHZ-30PPM-10PF-85C
CRITICAL
Y5110
24
13
CRITICAL
DMN32D2LFB4
DFN1006H4-3
Q5150 3
1
2
DMN5L06VK-7
SOT-563
Q5159
6
2
1
DMN5L06VK-7
SOT-563
Q5159
3
5
4
402
NOSTUFF
4.7UF
X5R
20%
6.3V
C5127
1
2
402MF-LF
1/16W
0
5%
R5127
12
10K
MF1/20W 2015%
R5172 12
18 23 36 37
25V
PLACE_NEAR=Q5150.2:5MM
NOSTUFF
47PF
NP0-C0G-CERM
0201
5%
C5134
1
2
25V
PLACE_NEAR=Q5159.6:5MM
47PF
NP0-C0G-CERM
0201
5%
C5131
1
2
VREF-3.3V-VDET-3.0V
CRITICAL
DFN
U5110
4
2
6
7
8
5
9
1
3
100K
MF1/20W 2015%
R5198 12
100K
MF1/20W 2015%
R5192 12
10K
MF1/20W 2015%
R5193 12
100K
MF1/20W 2015%
R5168 12
SYNC_DATE=08/12/2013
SMC Shared Support
SYNC_MASTER=J44
SMC_DELAYED_PWRGD
SMC_ADAPTER_EN
SMC_THRMTRIP
SMC_VCCIO_CPU_DIV2
CPU_THRMTRIP_3V3
SMC_TPAD_RST_L
MIN_NECK_WIDTH=0.1 mm
GND_SMC_AVSS
VOLTAGE=0V
MIN_LINE_WIDTH=0.4 mm
PP3V42_G3H
SMC_CLK32K
SMC_PME_S4_DARK_L
SMC_EXTAL
SMC_XTAL_R
SMC_DEBUGPRT_RX_L
SMC_TDI
SMC_PM_G2_EN
SMC_S4_WAKESRC_EN
SMC_TMS
SMC_TDO
CPU_THRMTRIP_3V3
SMC_DEBUGPRT_TX_L
SMC_ROMBOOT
SMC_RESET_L
GND_SMC_AVSS
PM_CLK32K_SUSCLK_R
SMC_XTAL
PM_THRMTRIP_R_L
CPU_PECI
SMC_PECI_L_R
PP1V05_S0
SMC_PROCHOT
SMC_THRMTRIP
SMC_ONOFF_L
PM_THRMTRIP_L
SMC_PECI_L
CPU_PROCHOT_L
PM_THRMTRIP_L
SMC_BC_ACOK
SMC_PME_S4_DARK_L
MAKE_BASE=TRUE
SMC_BC_ACOK
MAKE_BASE=TRUE
PP3V3_S5_AVREF_SMC
VOLTAGE=3.3V
MIN_LINE_WIDTH=0.4 mm
MIN_NECK_WIDTH=0.1 mm
PP3V42_G3H PP3V42_G3H_SMC_SPVSR
VOLTAGE=3.42V
MIN_LINE_WIDTH=0.4 mm
MIN_NECK_WIDTH=0.1 mm
SMC_MANUAL_RST_L
SMC_ONOFF_L
CPU_PECI_R
PP3V42_G3H
PP1V05_S0
SMC_ONOFF_L
SMC_SENSOR_ALERT_L
SMC_PME_S4_DARK_L
SMC_DP_HPD_L
PP3V3_S0
PP3V3_S4
SMC_RX_L
SMC_TX_L
SMC_LID
SMS_INT_L
SMC_TCK
SMC_BC_ACOK
SMC_S5_PWRGD_VIN
<BRANCH>
<SCH_NUM>
<E4LABEL>
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36 www.rosefix.com

OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
IN
IN
OUT
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
OUT
IN
IN
IN
NC
NC
NC
NC
OUT
IN
IN
OUT
IN
IN
IN
IN OUT
IN
IN
IN
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
BOM OPTIONSBOM GROUP
TABLE_BOMGROUP_HEAD
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
87 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
D
SIZEDRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
TABLE_BOMGROUP_ITEM
DESCRIPTION REFERENCE DES BOM OPTIONQTYPART NUMBER CRITICAL
TABLE_BOMGROUP_ITEM
BOM OPTIONSBOM GROUP
TABLE_BOMGROUP_HEAD
TABLE_BOMGROUP_ITEM
Requires EMC1412-1 or EMC1412-2 instead of EMC1412-A, new APN needs to be created.
SMC12 ADC Assignments
S4 SMC Wake Sources
SMC12 Pin Assignments
APN: 998-4692
Hall Effect Pads
Specify one of these BOM GROUPs.
Specify one of these BOM GROUPs.
Top Block Swap
Thermal Alerts
639-4502 (J44 HALL EFFECT BOARD) REPORTS TO 677-0912
CPUTHRM_ALRT:SMC
100
MF
1/20W
201
5%
R5214
12
36 38 42
36 38 42
36 38 42
36 38 42
36 38 41
36 38 41
MF
1/20W
201
5%
100
NOSTUFF
R5215
12
36 38 41
36 38
36 38 41
36 38 42
36 38 41
36 38
36 38 40
36 38
36 38 41
36 38 40
5%
201
1/20W
MF
100
BMONHYS
R5213
12
36 38 41
36 38 40
36 38 42
36 38 40
36 38 40
36 38 40
36 38 40
36 38 40
36 38 40
36 38 40
36 37
36 38 40
36 38 40
36 38 42
36 38 42
36 38 41
36 38 42
36 38 41
36 38 41
36
36 38 40
36 38 41
36 38 40
36 38 40
36 38 41
36 38 42
36 38 40
5%
201
1/20W
MF
1K
R5283
12
CPUTHRM_THRM:SMC
100
MF
1/20W
201
5%
R5216
12
TBTTHRM_THRM:SMC
100
MF
1/20W
201
5%
R5220
12
43
5%
201
1/20W
MF
1K
R5296
1
2
43
16V
10%
0201
X7R-CERM
1000PF
NOSTUFF
C5270
1
2
36 38 41
15
36 38 41
36 38 42
36 38 42
SM
HALL-EFFECT-SENSOR-MLB-D1
OMIT_TABLE
J5250
1
2
3
45
6
7
8
5%
0
1/16W
402
MF-LF
R5250
12
50V
10%
0402
X7R-CERM
0.001UF
C5250
1
2
5% 201
1/20W MF
10K
NOSTUFF
R5295 12
5% 201
1/20W MF
10K
NOSTUFF
R5294 12
36
36
5%
0
0201
1/20W
MF
R5231
12
13
13
5%
0
0201
MF
1/20W
R5230
12
100
MF
1/20W
201
5%
CPUHYS
R5217
12
41
SMCBOARDID:8
5%
10K
201
1/20W
MF
R5233
1
2
MF
10K
5%
1/20W
SMCBOARDID:16
201
R5232
1
2
5%
201
1/20W
MF
NOSTUFF
100K
R5284
1
2
100K
NOSTUFF
MF
1/20W
201
5%
R5285
1
2
100K
NOSTUFF
MF
1/20W
201
5%
R5286
1
2
43
29 34 36 38
29 34 36 38
100K
MF
1/20W
201
5%
R5282
1
2
29 34 36 38
43
42
14
100
MF
1/20W
201
5%
TBTTHRM_ALRT:SMC
R5210
12
CPUTHRM_THRM:PU,CPUTHRM_ALRT:PUCPUTHRM:NONE
TBTTHRM:BOTH
TBTTHRM_THRM:SMC,TBTTHRM_ALRT:SMC
SUBASSY,PCBA HALL EFFECT,J44 CRITICALJ52501677-0912
CPUTHRM_THRM:SMC,CPUTHRM_ALRT:SMCCPUTHRM:BOTH
SMC Project Support
CPUTHRM_THRM:SMC,CPUTHRM_ALRT:PUCPUTHRM:THRM
CPUTHRM_THRM:PU,CPUTHRM_ALRT:SMCCPUTHRM:ALRT
TBTTHRM_THRM:SMC,TBTTHRM_ALRT:PUTBTTHRM:THRM
TBTTHRM:ALRT
TBTTHRM_THRM:PU,TBTTHRM_ALRT:SMC
TBTTHRM_THRM:PU,TBTTHRM_ALRT:PUTBTTHRM:NONE
TBTTHRM:GONE
GND_SMC_AVSS
SMC_OTHER3V3_HI_ISENSE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
SMC_ADC11_PD
TBTTHMSNS_ALERT_L
TBTTHMSNS_THM_L
CPUTHMSNS_ALERT_L
CPUTHMSNS_THM_L
PCH_SML1ALERT_L
PCH_SUSWARN_L
SMC_CPU_ISENSE
SMC_OTHER5V_HI_ISENSE
SMC_PCH_ISENSE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
SMC_ADC12_PD
SMC_LCDPANEL_ISENSE
MAKE_BASE=TRUE
SMC_CPU_IMON_ISENSE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
SMC_CPU_ISENSE
SMC_OTHER5V_HI_ISENSE
MAKE_BASE=TRUE
SMC_SENSOR_PWR_EN
SMC_PCH_SUSACK_L
MAKE_BASE=TRUE
SMC_SENSOR_PWR_EN
MAKE_BASE=TRUE
SMC_SENSOR_PWR_EN
SMC_WIFI_PWR_EN
MAKE_BASE=TRUE
SMC_CPU_VSENSE
SMC_PCH_ISENSE
SMC_SENSOR_PWR_EN
PCH_STRP_TOPBLK_SWP_LSMC_TOPBLK_SWP_L
PP3V3_S0
GND_SMC_AVSS
PP3V3_S4
SMC_RESET_L
SMC_LID_R
PP3V42_G3H
MAKE_BASE=TRUE
SMC_PBUS_VSENSE
SMC_CPU_HI_ISENSE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
SMC_BMON_ISENSE
SMC_DCIN_ISENSE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
SMC_DCIN_VSENSE
MAKE_BASE=TRUE
SMC_BMON_DISCRETE_ISENSE
SMC_CPU_HI_ISENSE
SMC_BMON_ISENSE
SMC_BMON_DISCRETE_ISENSE
SMC_DCIN_VSENSE
SMC_OTHER3V3_HI_ISENSE
SMC_LCDBKLT_ISENSE
SMC_DDR_ISENSE
MAKE_BASE=TRUE
SMC_SSD_ISENSE
MAKE_BASE=TRUE
SMC_PP3V3S0_ISENSE
MAKE_BASE=TRUE
SMC_CAMERA_ISENSE
MAKE_BASE=TRUE
SMC_ADC16_PD
MAKE_BASE=TRUE
SMC_CPUDDR_ISENSE
MAKE_BASE=TRUE
SMC_CPU_VSENSE
SMC_ADC11_PD
SMC_PP3V3S0_ISENSE
SMC_PP5VS0_ISENSE
SMC_ADC16_PD
SMC_LCDPANEL_ISENSE
PCH_SUSACK_L
SMC_WIFI_PWR_EN
MAKE_BASE=TRUE
SMC_PP5VS0_ISENSE
SMC_LID
SMC_CAMERA_ISENSE
MAKE_BASE=TRUE
SMC_PCH_SUSWARN_L
SMC_DDR_ISENSE
MAKE_BASE=TRUE
SMC_LCDBKLT_ISENSE
MAKE_BASE=TRUE
SMC_ADC12_PD
SMC_SSD_ISENSE
MAKE_BASE=TRUE
SMC_TBT_ISENSESMC_TBT_ISENSE
SMC_CPU_IMON_ISENSE
NC_SMBUS_SMC_4_ASF_SCL
MAKE_BASE=TRUE NO_TEST=TRUE
NC_SMBUS_SMC_4_ASF_SCL
NO_TEST=TRUE
NC_SMBUS_SMC_4_ASF_SDA
MAKE_BASE=TRUE
NC_SMBUS_SMC_4_ASF_SDA
NC_BDV_BKL_PWM
NO_TEST=TRUEMAKE_BASE=TRUE
NC_BDV_BKL_PWM
NC_SMC_SYS_LED
NO_TEST=TRUEMAKE_BASE=TRUE
NC_SMC_SYS_LED
NO_TEST=TRUEMAKE_BASE=TRUE
NC_SMC_GFX_THROTTLE_LNC_SMC_GFX_THROTTLE_L
NC_SMC_FAN_1_CTL
MAKE_BASE=TRUE NO_TEST=TRUE
MAKE_BASE=TRUE NO_TEST=TRUE
NC_SMC_GFX_OVERTEMP
MAKE_BASE=TRUE
NC_SMC_FAN_1_TACH
NO_TEST=TRUE
NO_TEST=TRUE
NC_SMC_5VSW_PWR_EN
MAKE_BASE=TRUE
NO_TEST=TRUEMAKE_BASE=TRUE
NC_SMC_FAN_5_CTL
NC_SMC_BIL_BUTTON_L
NO_TEST=TRUEMAKE_BASE=TRUE
NC_MEM_EVENT_L
NO_TEST=TRUEMAKE_BASE=TRUE
NC_SMC_GFX_OVERTEMP
NC_SMC_BIL_BUTTON_L
NC_SMC_5VSW_PWR_EN
NC_SMC_FAN_1_TACH
NC_SMC_FAN_5_CTL
NC_MEM_EVENT_L
NO_TEST=TRUEMAKE_BASE=TRUE
NC_SMC_T101_COM_1
NC_SMC_ACTUATOR_DISABLE_L
MAKE_BASE=TRUE NO_TEST=TRUE
NC_SMC_ACTUATOR_DISABLE_L
NC_SMC_T101_COM_1
SMC_WIFI_PWR_EN
PP3V42_G3H
SMC_BOARDID
PP3V3_S4
SMC_PME_S4_WAKE_L
MAKE_BASE=TRUE
SMC_PME_S4_WAKE_L
SMC_PME_S4_WAKE_L
SMC_BOARDID
MAKE_BASE=TRUE
SMC_ADC11_PD
SMC_ADC12_PD
SMC_ADC16_PD
SMC_DCIN_ISENSE
SMC_CPUDDR_ISENSE
SMC_PBUS_VSENSE
NC_SMC_FAN_1_CTL
SMC_BMON_COMP_ALERT_L
SMC_CPUHI_COMP_ALERT_L
SMC_SENSOR_ALERT_L
<BRANCH>
<SCH_NUM>
<E4LABEL>
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62 64 65 68 77
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18 29 34 37 38 42 60 63 64 65
68
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52 61 65 68
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34 36 37
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36 38 www.rosefix.com

Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
87 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
D
SIZEDRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
J4800
(Write: 0x90 Read: 0x91)
U5000
Parade T-con - (0x10-0x2F or 0x30-0x4F) Y Y
Internal DP
HDMI Redriver (on RIO)
LYNX POINT LP S0 "SMBus 0" Connections
SMC SMBus "1" S0 Connections
U5000
(MASTER)
J9510
LYNX POINT LP
XDP Connectors
(WRITE: 0xCC READ: 0xCD)
(Write: 0x30 Read: 0x31)
(Write: 0x98 Read: 0x99)
(Write: 0x98 Read: 0x99)
(Write: 0x12 Read: 0x13)
(Write: 0xD8 Read: 0xD9)
(Write: 0x92 Read: 0x93)
U0500
U0500
J4002
EMC1704-02: U5870
EMC1412: U5850
TMP105: J9510
J7050
ISL6259 - U7100U5000
J8300
U5000
J1800
U2201
U2200
U0500
Trackpad
(Write: 0x88 Read: 0x89)
(Write: 0x72 Read 0x73)
access PCH.
SMLink 1 is slave port to
LYNX POINT LP
(MASTER)
LYNX POINT LP
SMC
ALS Fixstack Prox
CPU, Mem, Airflow,
TBT & MLB Prox
X29 Temp (on RIO)
SMC
(See Table)
Battery
Battery Charger
(MASTER)
SMC
(See Table)
Internal DP
(MASTER)
SMC
(MASTER)
VRef DACs
(MASTER)
Margin Control
SMC SMBus "5" G3H ConnectionsSMC SMBus "0" S0 Connections
LYNX POINT LP S0 "SMLink 1" Connections
LYNX POINT LP S0 "SMLink 0" Connections
(MASTER)
SMC
Battery
Battery Manager - (Write: 0x16 Read: 0x17)
(MASTER)
U5000
SMC SMBus "3" S0 Connections
SMC SMBus "2" S3 Connections
Samsung LGD
J44
2.0K
1/20W
5%
201
MF
R5361
1
2
2.0K
1/20W
5%
201
MF
R5360
1
2
2.0K
MF
201
5%
1/20W
R5380
1
2
2.0K
MF
201
5%
1/20W
R5381
1
2
1K
MF
201
5%
1/20W
R5370
1
2
1K
201
MF
5%
1/20W
R5371
1
2
8.2K
MF
201
5%
1/20W
R5310
1
2
8.2K
MF
201
5%
1/20W
R5311
1
2
1/20W
1K
MF
201
5%
R5301
1
2
5%
1K
MF
201
1/20W
R5300
1
2
2.0K
MF
201
5%
1/20W
R5391
1
2
2.0K
MF
201
5%
1/20W
R5390
1
2
2.0K
1/20W
5%
201
MF
R5351
1
2
2.0K
1/20W
5%
201
MF
R5350
1
2
SYNC_MASTER=J44 SYNC_DATE=08/12/2013
SMBus Connections
MAKE_BASE=TRUE
SMBUS_SMC_0_S0_SDA
PP3V3_S3
MAKE_BASE=TRUE
SMBUS_SMC_2_S3_SCL
MAKE_BASE=TRUE
SMBUS_SMC_2_S3_SDA
SMBUS_SMC_1_S0_SCL
SMBUS_SMC_1_S0_SCL
SMBUS_SMC_1_S0_SCL
SMBUS_SMC_1_S0_SDA
SMBUS_SMC_1_S0_SDA
SMBUS_SMC_2_S3_SDA
SMBUS_SMC_2_S3_SCL
SMBUS_SMC_3_SCL
MAKE_BASE=TRUE
SMBUS_SMC_3_SDA
MAKE_BASE=TRUE
SMBUS_SMC_3_SCL
SMBUS_SMC_3_SDA
SMBUS_PCH_CLK
SMBUS_PCH_DATA
SMBUS_PCH_DATA
SMBUS_PCH_CLK
SMBUS_PCH_DATA
SMBUS_PCH_CLK
MAKE_BASE=TRUE
SMBUS_SMC_5_G3_SDASMBUS_PCH_DATA
SMBUS_SMC_3_SDA
SMBUS_SMC_3_SCL
MAKE_BASE=TRUE
SMBUS_SMC_5_G3_SCL
SMBUS_SMC_5_G3_SDA
SMBUS_SMC_5_G3_SCL
SMBUS_SMC_5_G3_SDA
SMBUS_SMC_5_G3_SCL
SMBUS_SMC_0_S0_SCL
PP3V3_S0
PP3V42_G3H
SML_PCH_0_DATA
MAKE_BASE=TRUE
SML_PCH_0_CLK
MAKE_BASE=TRUE
PP3V3_S0
SMBUS_SMC_0_S0_SDA
SMBUS_SMC_1_S0_SDA
SMBUS_PCH_CLK
MAKE_BASE=TRUE
SMBUS_PCH_DATA
MAKE_BASE=TRUE
SMBUS_PCH_CLK
PP3V3_S0
PP3V3_S0
SMBUS_SMC_1_S0_SCL
MAKE_BASE=TRUE
MAKE_BASE=TRUE
SMBUS_SMC_1_S0_SDA
MAKE_BASE=TRUE
SMBUS_SMC_0_S0_SCL
PP3V3_S0
<SCH_NUM>
<E4LABEL>
<BRANCH>
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39 43 68
72 76
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63 76
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14 16 19
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72
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39 63 68
72
14 16 19
39 63 68
72
36 39 51 52
68 76
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63 68 72
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63 76
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63 76
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68 76
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14 72
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37 38 39 40 41 42 43 44 46 47
50 61 62 64 65 68 77
36 39 62
68 76
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39 43 68
72 76
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63 68 72
14 16 19 39
63 68 72
14 16 19 39
63 68 72
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50 61 62 64 65 68 77
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43 68 72 76
14 32 36 39
43 68 72 76
36 39 62 68
76
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50 61 62 64 65 68 77 www.rosefix.com

IN
OUT
IN-
IN+REF
V+
GND
ININ
OUT
OUT
OUT
IN- IN+REF
V+
GND
IN
OUT
S
S
D
N-CHANNEL
G
D
G
P-CHANNEL
OUT
IN
S
S
D
N-CHANNEL
G
D
G
P-CHANNEL
OUTOUT
OUT
IN-
IN+REF
V+
GND
OUT
IN
V+
REF IN+
IN-
OUT
GND
OUT
OUT
DESCRIPTION
REFERENCE DES
BOM OPTION
QTY
PART NUMBER
CRITICAL
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.
1 2 4 5 7 8
B
D
87 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE1 2
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
D
SIZE
DRAWING NUMBER REVISION
BRANCH
63
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT
Rsense: 0.003 (R5410) or Rsense SHORT Vsense: 21 mV, Range: 11 A
Vnominal: 12.6 V, Range: 19.7 V
SMC ADC: 00 OTHER 3.3V High Side Current Sense (IO3R)Rsense: 0.003 (R5400)
Charger (BMON) Current Sense (IPBR)
CPU High Side Current Sense (IC0R)
100x
Rsense: 0.003 (R5440) or Rsense SHORT
(to CPU High Side Threshold
Gain: 200x, EDP: 5 A
DC In Voltage Sense & Enable (VD0R)
OTHER 5V High Side Current Sense (IO5R) LCD Backlight Current Sense (IBLC)Gain: 100x, EDP: 7 A
Short Rsense
Gain: 0.167x PBUS Voltage Sense & Enable (VP0R)
Vsense: 28.5 mV, Range: 11 A Gain: 100x, EDP: 9.5 A
Charger Gain: 36x, EDP: 8 A Rsense: 0.005 (R7150)
Alert circuit)
Rthevenin = 4573 Ohms
Rthevenin = 4573 Ohms
SMC ADC: 04 Vnominal: 16.5 V, Range: 22.29 V Gain: 0.148x
divider when in S0.
Enables PBUS VSense
divider when AC present. Enables DC-In VSense
SMC ADC: 03 Rsense: 0.020 (R7120) Charger Gain: 20x, EDP: 4.6 A
SMC AD: 10 Vsense: 22.5 mV, Range: 1.32 A Rsense: 0.025 (R7700) Gain: 100x. EDP: 0.9 A
SMC ADC: 01
100x
SMC ADC: 02
100x
200x
SMC ADC: 07 Vsense: 12 mV, Range: 5.5 A SMC ADC: 08
Short Rsense
DC-IN (AMON) Current Sense (ID0R)
52
3300PF X7R-CERM
020110%
10V
PLACE_NEAR=U5000.F2:5MM
C5429
1
2
SC70
PLACE_NEAR=U7700.2:10MM
PLACE_NEAR=U7700.1:10MM
INA214
CRITICAL LOADISNS
U5450
2
5
4
6
1
3
58 77
58 77
201
MF15K 1%
PLACE_NEAR=U5410.6:5MM
1/20W OTHERISNSR5415
1
2
PLACE_NEAR=U5440.6:5MM
1/20W 20115K 1%
MF OTHERISNSR5445
1
2
36 38
1%
PLACE_NEAR=U5450.6:5MM
1/20W 201
MF6.04K LOADISNSR5455
1
215K 1/20W5%
201
MF NOSTUFF PLACE_NEAR=U5400.6:5MM R5405
1
2
41
OMIT
1%
1w
PLACE_NEAR=U5410.5:10MM
0.003
PLACE_NEAR=U5410.4:10MM
CYN
0612-SHORTR5410
1
2
3
4
PLACE_NEAR=U5440.4:10MM
CYN
1w
1%
0612-SHORT
0.003
PLACE_NEAR=U5440.5:10MM
OMIT
R5440
1
2
3
4
INA214
SC70
CRITICAL OTHERISNS
U5410
2
5
4
6
1
3
BYPASS=U5410.3:5MM 0.1UF CERM20%
10V
402OTHERISNS C5411
1
2
PLACE_NEAR=U5000.A4:5MM
4.53K
MF
201
1%
1/20W
OTHERRC:YES R5419 12
0.22UF X5R
20%6.3V
0201 PLACE_NEAR=U5000.A4:5MM
OTHERRC:YES
C5419
1
2
52
402 BYPASS=U5400.3:5MM 0.1UF CERM20%
10VC5401
1
2
02010.22UF X5R
20%6.3V PLACE_NEAR=U5000.E2:5MM C5409
1
2
4.53K
MF
201
1%
1/20W
PLACE_NEAR=U5000.E2:5MM R5409 12
100K
402
1%
1/16W
MF-LF
R5491
1
2
36 38
100K MF-LF
402
1%
1/16W
R5481
1
2
PLACE_NEAR=U5000.B3:5MM
5.49K
MF-LF
402
1%
1/16W
R5499
1
2
31.6K
MF-LF
402
1%
1/16W
PLACE_NEAR=U5000.B3:5MM R5498
1
2
0.22UF X5R 020120% 6.3VPLACE_NEAR=U5000.B3:5MM C5499
1
2
CRITICAL NTUD3169CZ
SOT-963
Q5490
6
3
2
5
1
4
100K MF-LF
402
1%
1/16W
R5492
1
2
PLACE_NEAR=U5000.E1:5MM
MF-LF
5.49K
402
1%
1/16W
R5489
1
2
X5R
0.22UF 020120% 6.3VPLACE_NEAR=U5000.E1:5MM C5489
1
2
36 38
36 38 60
CRITICAL NTUD3169CZ
SOT-963
Q5480
6
3
2
5
1
4
100K MF-LF
402
1%
1/16W
R5482
1
2
27.4K
MF-LF
402
1%
1/16W
PLACE_NEAR=U5000.E1:5MM R5488
1
2
36 38
36 38
SM
PLACE_NEAR=R5400.1:10 MM
XW5480
12
INA214
SC70
CRITICAL
U5400
2
5
4
6
1
3
0.1UF CERM 402
20%
10VBYPASS=U5440.3:5MM OTHERISNS C5441
1
2
4.53K
1%
1/20W
201
MF
PLACE_NEAR=U5000.B5:5MM OTHERRC:YES R5449 12
0.22UF X5R 020120% 6.3V PLACE_NEAR=U5000.B5:5MM OTHERRC:YESC5449
1
2
36 38
13 61
45.3K
MF
201
1%
1/20W
PLACE_NEAR=U5000.F1:5MM
R5439 12
INA210
SC70
CRITICAL OTHERISNS
U5440
2
5
4
6
1
3
PLACE_NEAR=U5400.4:10MM
PLACE_NEAR=U5400.5:10MM
TFT
1W
1%
0612
0.003
CRITICAL
R5400
1
2
3
4
PLACE_NEAR=U5000.F1:5MM
2200PF X7R-CERM
020110%
10VC5439
1
2
BYPASS=U5450.3:5MM 0.1UF CERM 402
20%
10VLOADISNS C5450
1
2
PLACE_NEAR=U5000.B6:5MM
4.53K
MF
201
1%
1/20W
LOADRC:YES
R5459 12
0.22UF X5R 020120% 6.3V PLACE_NEAR=U5000.B6:5MM LOADRC:YESC5459
1
2
36 38
36 38
300K
MF
201
1/20W
PLACE_NEAR=U5000.F2:5MM
1%
R5429 12
RES,MTL FLIM,100K,1/16W,0201,SMD,LF
C5459
1
117S0008
LOADRC:NO
1
RES,MTL FLIM,100K,1/16W,0201,SMD,LF
117S0008
C5419,C5449
OTHERRC:NO
Power Sensors: High Side
SYNC_MASTER=J44SYNC_DATE=08/12/2013
PDCINVSENS_EN_L_DIV
PPBUS_S5_HS_OTHER3V3PPBUS_G3HPPBUS_S5_HS_OTHER5V
CHGR_BMON
PPDCIN_G3H_ISOL
SMC_SENSOR_PWR_EN
GND_SMC_AVSS
PP3V3_S4SW_SNS
SMC_BMON_ISENSE
CHGR_AMON
SMC_DCIN_ISENSE
GND_SMC_AVSS
PM_SLP_SUS_L
DCIN_S5_VSENSE
DCINVSENS_EN_L
GND_SMC_AVSSSMC_DCIN_VSENSE
PBUSVSENS_EN_L
PBUS_S0_VSENSE
SMC_PBUS_VSENSE
SMC_LCDBKLT_ISENSEGND_SMC_AVSS
PP3V3_S4SW_SNS
PP3V3_S4SW_SNS
ISNS_HS_COMPUTING_P
ISNS_LCDBKLT_P
ISNS_LCDBKLT_N
HS_OTHER3V3_IOUT
ISNS_LCDBKLT_IOUT
GND_SMC_AVSS
GND_SMC_AVSS
PPBUS_G3H
SMC_CPU_HI_ISENSE
HS_OTHER5V_IOUT
PPBUS_S5_HS_COMPUTING PPBUS_G3H
ISNS_HS_OTHER5V_P
ISNS_HS_OTHER5V_N ISNS_HS_OTHER3V3_P
PPBUS_G3H
PBUS_S0_VSENSE_IN
ISNS_HS_COMPUTING_N ISNS_HS_OTHER3V3_N
PP3V3_S0
CPUHI_IOUT
SMC_OTHER3V3_HI_ISENSE
PBUSVSENS_EN_L_DIV
GND_SMC_AVSS
GND_SMC_AVSS
SMC_OTHER5V_HI_ISENSE
<BRANCH>
<SCH_NUM>
<E4LABEL>
54 OF 120
40 OF 78
56 65
25 40 51 52 58
65 68
56 65
51 52 65
36 37 38 40 41 42
40 41 42 60 65
36 37 38 40 41 42
36 37 38 40 41 42
36 37 38 40 41 42
40 41 42 60 65
40 41 42 60 65
42
77
36 37 38 40 41 42
36 37 38 40 41 42
25 40 51 52 58 65 68
53 54 55 57 65
25 40 51 52 58
65 68
77
77
77
25 40 51 52 58
65 68
42
77
77
8
11 12 13 15 17 18 24
28 30 37 38 39 41 42 43
44 46 47 50 61 62 64 65
68 77
36 37 38 40 41 42
36 37 38 40 41 42 www.rosefix.com

V+
REFIN+
IN-
OUT
GND
OUT
OUT
OUT
OUT
OUT
V+
REFIN+
IN-
OUT
GND
IN
IN
OUTIN-
IN+ REF
V+
GND
SYM_VER_2
GS
D
OUT
IN
OUTIN- IN+ REF
V+
GND
V+
REFIN+
IN-
OUT
GND
V+
REFIN+
IN-
OUT
GND
IN
IN OUT
IN
IN
IN
IN
V+
V-
OUT
DESCRIPTION REFERENCE DES BOM OPTIONQTYPART NUMBER CRITICAL
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
87 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
D
SIZEDRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
Rsense: 0.005 (R5580)
Rsense: 0.005 (R5530) or Rsense SHORT
Rsense: 0.001 (R7640) or Rsense SHORT
Rsense: 0.005 (R5520) or Rsense SHORT
Rsense: 0.002 (R7450) or XW7450
CPU High Side Current (IC0R) Threshold Alert
Trip Target on CPU High current: 2.5 A
Vtl = 0.771 V -> 2.571 A on CPU High current
Vth = 0.616 V -> 2.054 A on CPU High current
Vref = 0.737 V
Hysteresis Circuit:
Hysteresis Margin = 0.518 A
Gain: 100x
Vsense: 23.5 mV, Range: 1.32 A
Vsense: 21.5 mV, Range: 1.32 A
Gain: 500x, EDP: 1.0 A
500x
500x
Gain: 100x, EDP: 9 A
SMC ADC: 13
Gain: 219.33x, EDP: 40 A
SMC ADC: 17
SMC ADC: 14
Vsense: 21 mV, Range: 16.5 A
SMC ADC: 09
SMC ADC: 19 SMC ADC: 06
Vsense: 15 mV, Range: 40.12 A
Rsense: 2x of 0.00075 (R7310, R7320), Rsum: 0.000375
5V S0 Rail Current Sense (IR5C)
3.3V S0 Rail Current Sense (IR3C)
CPU Fixed Current Sense (IC0C)
SSD Current Sense (ISDC)
100x
500x
107S0241
Gain: 100x, EDP: 5 A (16.5 W)
Vsense: 25 mV, Range: 6.6 A
100x
Vsense: 12.5 mV, Range: 6.6 A
200x
Gain: 200x, EDP: 2.5 A
DDR 1.35V S3 (CPU & Memory) Current Sense (IM0C)
Gain: 500x, EDP: 5 A
Rsense: 0.005 (R5510) or Rsense SHORT
CPU DDR 1.35V S3 (CPU Only) Current Sense (IM1C)
SMC ADC: 18
Short Rsense
Short Rsense
Gain: 500x, EDP: 1.0 A
PCH 1.05V Current Sense (IC1C)
Vsense: 5 mV, Range: 6.6 A
Short Rsense
Rsense: 0.003 (R5400)
CRITICAL
SC70
PLACE_NEAR=R7640.4:5MM
PLACE_NEAR=R7640.3:5MM
INA211
LOADISNS
U5560
2
5
4
6
1
3
1.05K
1%
MF
1/20W
201
LOADISNS
R5543
12
1.05K
1%
MF
1/20W
201
LOADISNS
R5542
12
36 38
X5R
6.3V
0.22UF
0201
20%
PLACE_NEAR=U5000.C2:5MM
C5589
1
2
4.53K
1%
PLACE_NEAR=U5000.C2:5MM
MF
1/20W
201
R5589
12
402
0.1uF
CERM
20%
10V
BYPASS=U5580.3:5MM
C5580
1
2
402
0.1UF
CERM
20%
10V
BYPASS=U5570.3:5MM
DDRISNS
C5570
1
2
PLACE_NEAR=U5000.A5:5MM
4.53K
1%
MF
1/20W
201
DDRRC:YES
R5579
12
6.3V
0201
20%
PLACE_NEAR=U5000.A5:5MM
X5R
0.22UF
DDRRC:YES
C5579
1
2
36 38
36 38
X5R
6.3V
0.22UF
0201
20%
PLACE_NEAR=U5000.H1:5MM
LOADRC:YES
C5519
1
2
4.53K
1%
PLACE_NEAR=U5000.H1:5MM
MF
1/20W
201
LOADRC:YES
R5519
12
402
0.1UF
CERM
20%
10V
BYPASS=U5510.3:5MM
LOADISNS
C5510
1
2
36 38
X5R
6.3V
0.22UF
0201
20%
PLACE_NEAR=U5000.B1:5MM
OMIT
C5529
1
2
4.53K
1%
PLACE_NEAR=U5000.B1:5MM
MF
201
1/20W
LOADRC:YES
R5529
12
402
0.1UF
CERM
20%
10V
BYPASS=U5520.3:5MM
LOADISNS
C5520
1
2
36 38
402
CERM
20%
10V
BYPASS=U5530.3:5MM
0.1UF
LOADISNS
C5530
1
2
X5R
6.3V
0.22UF
0201
20%
PLACE_NEAR=U5000.G1:5MM
LOADRC:YES
C5539
1
2
4.53K
1%
PLACE_NEAR=U5000.G1:5MM
MF
1/20W
201
LOADRC:YES
R5539
12
CRITICAL
SC70
INA210
LOADISNS
U5510
2
5
4
6
1
3
PLACE_NEAR=U5580.5:10MM
PLACE_NEAR=U5580.4:10MM
1W
1%
CRITICAL
0612-2
MF
0.005
R5580
1
2
3
4
55 77
55 77
PLACE_NEAR=U5560.6:5MM
NOSTUFF
20K
MF
1/20W
201
5%
R5565
1
2
NOSTUFF
20K
PLACE_NEAR=U5570.6:5MM
MF
5%
1/20W
201
R5575
1
2
NOSTUFF
20K
PLACE_NEAR=U5520.6:5MM
MF
1/20W
201
5%
R5525
1
2
51K
PLACE_NEAR=U5530.6:5MM
MF
1/20W
201
5%
LOADISNS
R5535
1
2
PLACE_NEAR=U5580.6:5MM
NOSTUFF
20K
MF
1/20W
201
5%
R5585
1
2
NOSTUFF
20K
PLACE_NEAR=U5540.4:5MM
MF
1/20W
201
5%
R5540
1
2
CRITICAL
SC70
INA214
PLACE_NEAR=XW7450.1:10MM
PLACE_NEAR=XW7450.2:10MM
DDRISNS
U5570
2
5
4
6
1
3
RB521ZS-30
SM-201
NOSTUFF
D5557
A
K
1/20W
0
5%
0201
NOSTUFF
MF
R5557
1
2
CPUHYS
201
1/20W
MF
1%
84.5K
R5555
1
2
CPUHYS
201
1/20W
MF
1%
294K
R5554
1
2
CPUHYS
MF
1/20W
0201
0
5%
R5552
1
2
402
25V
10%
X5R
NOSTUFF
0.1UF
C5552
1
2
CPUHYS
10%
0.1UF
6.3V
0201
BYPASS=U5551:3MM
CERM-X5R
C5551
1
2
CPUHYS
DMN32D2LFB4
DFN1006H4-3
U5552 3
1
2
38
CPUHYS
402
1/16W
1%
MF-LF
255K
R5553
12
X5R
6.3V
0.22UF
0201
20%
NOSTUFF
C5553
12
CPUHYS
MCP6541T
SC70-5
U5551
3
4
1
5
2
40
NOSTUFF
20K
PLACE_NEAR=U5510.6:5MM
MF
1/20W
201
5%
R5515
1
2
CPUHYS
201
MF
1%
12K
1/20W
R5556
12
CRITICAL
SC70
INA214
U5580
2
5
4
6
1
3
SC70
CRITICAL
INA211
LOADISNS
U5520
2
5
4
6
1
3
SC70
INA211
CRITICAL
LOADISNS
U5530
2
5
4
6
1
3
0612-SHORT
0
0
1 W
MF
PLACE_NEAR=U5510.4:10MM
PLACE_NEAR=U5510.5:10MM
OMIT
R5510
1
2
3
4
0612-SHORT
0
1 W
MF
OMIT
PLACE_NEAR=U5520.5:10MM
PLACE_NEAR=U5520.4:10MM
0
R5520
1
2
3
4
0612-SHORT
0
0
1 W
MF
OMIT
PLACE_NEAR=U5530.5:10MM
PLACE_NEAR=U5530.4:10MM
R5530
1
2
3
4
57 77
57 77
402
0.1uF
CERM
20%
10V
BYPASS=U5560.3:5MM
LOADISNS
C5560
1
2
1%
PLACE_NEAR=U5000.H2:5MM
MF
1/20W
201
4.53K
LOADRC:YES
R5569
12
X5R
6.3V
0201
20%
PLACE_NEAR=U5000.H2:5MM
0.22UF
LOADRC:YES
C5569
1
2
36 38
54 77
4.42K
0402
0.1%
1/16W
PLACE_NEAR=R7320.4:5MM
NO_XNET_CONNECTION=TRUE
MF
LOADISNS
R5548
12 402
715K
0.1%
1/16W
NO_XNET_CONNECTION=TRUE
MF
LOADISNS
R5544
1
2
402
NO_XNET_CONNECTION=TRUE
NO_XNET_CONNECTION=TRUE
715K
0.1%
1/16W
MFLOADISNS
R5541
12
54 77
54 77
54 77
4.42K
0402
0.1%
1/16W
PLACE_NEAR=R7310.3:5MM
MF
NO_XNET_CONNECTION=TRUE
LOADISNS
R5547
12
4.42K
0402
0.1%
1/16WNO_XNET_CONNECTION=TRUE
PLACE_NEAR=R7320.3:5MM
MF
LOADISNS
R5546
12
4.42K
0402
0.1%
1/16WNO_XNET_CONNECTION=TRUE
PLACE_NEAR=R7310.4:5MM
MF
LOADISNS
R5545
12
ISL28133
SC70-5
CRITICAL
LOADISNS
U5540
3
1
4
25
402
0.1UF
CERM
20%
10V
BYPASS=U5540.5:3MM
LOADISNS
C5540
1
2
X5R
6.3V
0.22UF
0201
20%
PLACE_NEAR=U5000.B4:5MM
LOADRC:YES
C5549
1
2
4.53K
1%
PLACE_NEAR=U5000.B4:5MM
MF
1/20W
201
LOADRC:YES
R5549
12
36 38
117S0008 1 RES,MTL FLIM,100K,1/16W,0201,SMD,LF C5579 DDRRC:NO
117S0008
3 RES,MTL FLIM,100K,1/16W,0201,SMD,LF C5529,C5539,C5549 LOADRC:NO
117S0008 2 RES,MTL FLIM,100K,1/16W,0201,SMD,LF C5569,C5519 LOADRC:NO
SYNC_MASTER=J44 SYNC_DATE=08/12/2013
Power Sensors: Load Side
SMC_DDR_ISENSE
CPUHI_COMP_OUT
ISNS_PP3V3S0_IOUT
PP5V_S0
CPUHI_IOUT_R
CPUHI_COMP_VREF
P1V05S0_IOUT
PP5V_S0_FET
ISNS_PP5VS0_N
ISNS_PP5VS0_P
PP3V3_S0_FET
PP3V3_S0
ISNS_PP3V3S0_N
ISNS_PP3V3S0_P
PP1V35_S3
PP1V35_S3_CPUDDR
ISNS_CPUDDR_N
ISNS_CPUDDR_P
PP3V3_S4SW_SNS
ISNS_S0_SSD_IOUT
ISNS_SSD_N
ISNS_SSD_P
PP3V3_S4SW_SNS
PP3V3_S0SW_SSD
CPUVR_ISNS_P
CPUHI_COMP_FB
CPUHI_IOUT
BMON_IOUT_D
SMC_SSD_ISENSE
PP3V3_S0SW_SSD_FET
GND_SMC_AVSS
CPUVR_ISNS2_N
CPUVR_ISNS1_N
CPUVR_ISNS2_P
CPUVR_ISNS_R_P
SMC_CPU_ISENSE
CPUVR_ISNS1_P
CPUVR_ISNS_N CPUVR_ISNS_R_N
CPUVR_ISUM_IOUT
PP3V3_S0
GND_SMC_AVSS
ISNS_DDR_IOUTNC_ISNS_DDR_S3N
NC_ISNS_DDR_S3P
ISNS_1V05_S0_N
GND_SMC_AVSS
SMC_PCH_ISENSE
PP3V3_S4SW_SNS
ISNS_1V05_S0_P
PP3V3_S4SW_SNS
GND_SMC_AVSS
SMC_PP5VS0_ISENSE
GND_SMC_AVSS
SMC_PP3V3S0_ISENSE
SMC_CPUDDR_ISENSE
GND_SMC_AVSS
GND_SMC_AVSS
ISNS_CPUDDR_IOUT
ISNS_PP5VS0_IOUT
PP3V3_S4SW_SNS
PP3V3_S4SW_SNS
PP3V3_S0
SMC_CPUHI_COMP_ALERT_L
<BRANCH>
<SCH_NUM>
<E4LABEL>
55 OF 120
41 OF 78
16 17 32
44 45 53
54 58 60
61 65 68
60 65
77
77
60 65
8 11 12
13 15 17
18 24 28
30 37 38
39 40 41
42 43 44
46 47 50
61 62 64
65 68 77
77
77
17 19 20
21 22 55
65 73
8 10 65
73
77
77
40 41 42
60 65
77
77
40 41 42 60 65
30 65
77
42
60 65
36 37 38 40 41 42
77
77 77
8 11 12 13 15 17 18 24 28 30
37 38 39 40 41 42 43 44 46 47
50 61 62 64 65 68 77
36 37 38 40 41 42
36 37 38 40 41 42
40 41 42 60 65
40 41
42 60
65
36 37 38 40 41 42
36 37 38 40 41 42
36 37 38 40 41 42
36 37 38 40 41 42
40 41 42 60
65
40 41 42
60 65
8 11 12 13 15 17 18 24 28 30
37 38 39 40 41 42 43 44 46 47
50 61 62 64 65 68 77 www.rosefix.com

OUT
IN
IN
V+
REFIN+
IN-
OUT
GND
IN
OUT
OUT
OUT
V+
REFIN+
IN-
OUT
GND
IN OUT
OUT
IN
OUT
IN
OUT
V+
REFIN+
IN-
OUT
GND
V+
REFIN+ IN-
OUT
GND
OUT
SYM_VER_2
GS
D
IN
IN
V+
REFIN+ IN-
OUT
GND
DESCRIPTION REFERENCE DES BOM OPTIONQTYPART NUMBER CRITICAL
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
87 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
D
SIZEDRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
Rsense: 0.005 (R5610) or XW5610
RSENSE: 0.005 (R8320) or Rsense SHORT
Rsense: 0.005 (R5640) or Rsense SHORT
LCD Panel Current Sense (ILDC)
present on IN+/- pins with INA output voltage decreasing
With 20uA sink: 0.125A - 2.1A -> 23mV - 92 mV
With 10uA sink: 0.125A - 2.1A -> 13mV - 83 mV
This deviation has been designed in our Peak Detection circuit.
SENSE+ pins of EMC1704 sink 10-20uA current.
Battery BMON Discrete Current Sense (IP0R) & Threshold Alert
Vref = 0.854 V
Trip Target on Battery current: 3.5 A
into system.
Hysteresis Circuit:
Hysteresis Margin = 0.518 A
200x
Gain: 200x. EDP: 2.8 A
Vsense: 14 mV, Range: 3.3 A
Vsense: 50 mV, Range: 13.2 A
500x
500x
50x
200x
Camera (S2 Controller) Current Sense (ICMC)
CPU Core IMON Current Sense (IC2C)
CPU Core Voltage Sense (VC0C)
CPU High Side (IC0R) Peak Detection Support
Gain: 50x. EDP: 8 A
SMC AD: 05
SMC ADC: 20
Gain: 1 A / 28.273 mV, Range: 40 A.
SMC ADC: 22
Gain: 500x. EDP: 0.82 A
SMC AD: 15
Vsense: 4.1 mV, Range: 1.32 A
Gain: 500x. EDP: 1 A
Vsense: 5 mV, Range: 1.32 A
SMC AD: 21
SMC AD: 23
In battery discharge scenario negative voltage will be
from 3.3V with increasing discharge current.
With R7210 (Ri) set to 316 Ohm,
R7230 set to 95.3 kOhm,
R7310 (Rsen) set to 0.75 mOhm,
Num Phases (N) is 2, and Io (ICCmax) is 40A,
then 1A of Io gives 28.273mV at the Vimon.
Rsense: 0.005 (R7150)
Vth = 0.758 V -> 3.031 A on Battery current
Vtl = 0.887 V -> 3.549 A on Battery current
to measure Battery discharge power
CHGR_CSO_R_P/N are swapped on purpose
Thunderbolt TBT Current/Voltage Sense (IHSC/VHSC)
Short Rsense
0.22UF
0201
20%
PLACE_NEAR=U5000.A3:5MM
6.3V
X5R
BMONRC:YES
C5679
1
2
PLACE_NEAR=U5000.A3:5MM
1%
4.53K
MF
1/20W
201
BMONRC:YES
R5679
12
36 38
5%
MF
0201
1/20W
0
BMONHYS
R5672
1
2
402
NOSTUFF
0.1UF
10%
25V
X5R
C5672
1
2
MCP6541T
SC70-5
BMONHYS
U5671
3
4
1
5
2
6.3V
0.1UF
0201
CERM-X5R
10%
BYPASS=U5671:3MM
BMONHYS
C5671
1
2
402
255K
MF-LF
1%
1/16W
BMONHYS
R5673
12
NOSTUFF
0.22UF
0201
20%
6.3V
X5R
C5673
12
201
16K
1/20W
MF
1%
R5661
1
2
201
1K
1/20W
MF
1%
R5662
1
2
NOSTUFF
0.22UF
0201
20%
6.3V
X5R
C5665
1
2
5%
0
0201
1/20W
MF
R5665
12
5%
201
1/20W
MF
47
R5660
12
40 42 77
40 42 77
BYPASS=U5660.3:5MM
CERM-X5R
0201
6.3V
0.1UF
10%
C5660
1
2
CRITICAL
INA210
SC70
PLACE_NEAR=R5400:10MM
CKPLUS_WAIVE=NdifPr_badTerm
CKPLUS_WAIVE=NdifPr_badTerm
U5660
2
5
4
6
1
3
62 77
SM
PLACE_NEAR=R7310.2:5 MM
XW5680
12
NOSTUFF
0.22UF
0201
20%
PLACE_NEAR=U5000.B8:5MM
6.3V
X5R
C5699
1
2
5%
0
0201
1/20W
MF
PLACE_NEAR=U5000.B8:5MM
R5699
12
0.22UF
0201
20%
PLACE_NEAR=U5000.B7:5MM
6.3V
X5R
C5689
1
2
201
1/20W
MF
4.53K
1%
PLACE_NEAR=U5000.B7:5MM
R5689
12
36 38
36 38
36 38
0.22UF
0201
20%
PLACE_NEAR=U5000.B2:5MM
6.3V
X5R
LOADRC:YES
C5619
1
2
201
1/20W
MF
4.53K
1%
PLACE_NEAR=U5000.B2:5MM
LOADRC:YES
R5619
12
CERM
20%
10V
BYPASS=U5630.3:5MM
0.1UF
402
LOADISNS
C5610
1
2
INA211
SC70
LOADISNS
U5610
2
5
4
6
1
3
5%
0
CAMERA_3V3:S0
MF-LF
1/16W
402
R5611
12
5%
0
CAMERA_3V3:S3
MF-LF
1/16W
402
R5612
12
62 77 36 38
0.22UF
0201
20%
PLACE_NEAR=U5000.A7:5MM
6.3V
X5R
LOADRC:YES
C5629
1
2
201
69.8K
MF
1/20W
1%
BMONHYS
R5675
1
2
201
200K
MF
1/20W
1%
BMONHYS
R5674
1
2
5%
201
1/20W
MF
NOSTUFF
PLACE_NEAR=U5640.6:5MM
20K
R5645
1
2
5%
201
1/20W
MF
51K
PLACE_NEAR=U5620.6:5MM
LOADISNS
R5625
1
2
5%
201
1/20W
MF
NOSTUFF
20K
PLACE_NEAR=U5610.6:5MM
R5615
1
2
PLACE_NEAR=U5660.6:5MM
NOSTUFF
MF
1/20W
201
5%
15K
R5664
1
2
MF
1/20W
201
5%
NOSTUFF
15K
PLACE_NEAR=U5670.6:5MM
R5671
1
2
201
10K
MF
1/20W
1%
BMONHYS
R5676
12
43 77
5%
0
0201
1/20W
MF
PLACE_NEAR=U5660.6:10MM
R5666
12
5%
0
0201
1/20W
MF
NOSTUFF
PLACE_NEAR=U5660.6:10MM
R5667
12
40 42 77
43 77
5%
0
0201
1/20W
MF
PLACE_NEAR=U5660.6:10MM
R5668
12
5%
0
0201
1/20W
MF
NOSTUFF
PLACE_NEAR=U5660.6:10MM
R5669
12
40 42 77
SM
XW5610
1
2
PLACE_NEAR=U5640.4:10MM
PLACE_NEAR=U5640.5:10MM
0612-SHORT
0
0
1 W
MF
OMIT
R5640
1
2
3
4
CERM
20%
10V
0.1UF
402
BYPASS=U5640.3:5MM
TBTISNS
C5640
1
2
201
1/20W
MF
4.53K
1%
PLACE_NEAR=U5000.A8:5MM
TBTRC:YES
R5649
12
0.22UF
0201
20%
6.3V
X5R
PLACE_NEAR=U5000.A8:5MM
TBTRC:YES
C5649
1
2
36 38
201
1/20W
MF
4.53K
1%
PLACE_NEAR=U5000.A7:5MM
LOADRC:YES
R5629
12
0.1UF
BYPASS=U5620.3:5MM
CERM
20%
10V
402
LOADISNS
C5620
1
2
INA211
SC70
LOADISNS
U5620
2
5
4
6
1
3
PLACE_NEAR=R5640.1:10 MM
SM
XW5640
12
5%
0
0201
1/20W
MF
PLACE_NEAR=XW5640.2:10MM
NOSTUFFR5648
12
5%
0
0201
1/20W
MF
PLACE_NEAR=XW5640.2:10MM
TBTISNS
R5647
12SC70
INA210
TBTISNS
U5640
2
5
4
6
1
3
38
DMN32D2LFB4
DFN1006H4-3
BMONHYS
U5672 3
1
2
52 77
52 77
CKPLUS_WAIVE=NdifPr_badTerm
CRITICAL
INA213
SC70
CKPLUS_WAIVE=NdifPr_badTerm
BMONISNS
U5670
2
5
4
6
1
3
CERM-X5R
0201
6.3V
0.1UF
10%
BYPASS=U5670:3MM
BMONISNS
C5670
1
2
NOSTUFF
RB521ZS-30
SM-201
D5677
A
K
NOSTUFF
0201
1/20W
MF
0
5%
R5677
1
2
Power Sensors: Extended
SYNC_MASTER=J44 SYNC_DATE=08/12/2013
117S0008 4 RES,MTL FILM,100K,1/16W,0201,SMD,LF C5619,C5629,C5649
C56791 RES,MTL FILM,100K,1/16W,0201,SMD,LF117S0008
SMC_TBT_ISENSE
PP3V3_S4
PP3V3_S4_TBT
ISNS_TBT_N
ISNS_TBT_P
ISNS_TBT_IVOUT
PP3V3_S0
BMON_COMP_FB
BMON_IOUT_R
ISNS_HS_COMPUTING_N
ISNS_HS_COMPUTING_P
CPUVSENSE_INPPVCC_S0_CPU SMC_CPU_VSENSE
GND_SMC_AVSS
CPUVR_IMON
ISNS_HS_COMPUTING_P
ISNS_LCDPANEL_IOUT
GND_SMC_AVSS
SMC_CPU_IMON_ISENSE
PP3V3_S0
CHGR_CSO_R_P
CHGR_CSO_R_N
GND_SMC_AVSS
ISNS_CPUHIGAIN_OUT
PP3V3_S3
PP3V3_S0
PP3V3_S3RS0_CAMERA
MAKE_BASE=TRUE
VOLTAGE=3.3V
MIN_LINE_WIDTH=0.5MM
MIN_NECK_WIDTH=0.175MM
PP3V3_S3RS0_CAMERA
ISNS_CAMERA_IOUT SMC_CAMERA_ISENSE
PP3V3_S4SW_SNS
GND_SMC_AVSS
ISNS_LCDPANEL_N
ISNS_LCDPANEL_P
ISNS_TBT_IOUT
SMC_LCDPANEL_ISENSE
PP3V3_S4SW_SNS
PP3V3_S4SW_SNS
GND_SMC_AVSS
GND_SMC_AVSS
BMON_IOUT_D
BMON_IOUT
SMC_BMON_COMP_ALERT_L
ISNS_CPUHIGAIN_OUT_R
ISNS_CPUHIGAIN_P
ISNS_CPUHIGAIN_N
ISNS_CPUHIGAIN_R_N
ISNS_HS_COMPUTING_N
BMON_COMP_VREF
SMC_BMON_DISCRETE_ISENSE
ISNS_CPUHIGAIN_R_P
PP3V3_S3RS0_CAMERA
PP3V3_S3RS0_CAMERA_R
MIN_LINE_WIDTH=0.5MM
MIN_NECK_WIDTH=0.2MM
VOLTAGE=3.3V
NC_ISNS_CAMERAN
NC_ISNS_CAMERAP
ISNS_TBT_IVIN
BMON_COMP_OUT
<BRANCH>
<SCH_NUM>
<E4LABEL>
56 OF 120
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34 37
38 60
63 64
65 68
23 24
25 65
77
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50 61 62 64 65 68 77
8 10 54 65 68
36 37 38 40 41 42
53
36 37 38 40 41 42
8 11 12 13 15 17 18 24 28 30
37 38 39 40 41 42 43 44 46 47
50 61 62 64 65 68 77
36 37 38 40 41 42
15 18
19 39
60 65
68
8 11
12 13
15 17
18 24
28 30
37 38
39 40
41 42
43 44
46 47
50 61
62 64
65 68
77
15 31 42
15 31
42
40 41 42 60 65
36 37 38 40 41 42
40 41 42 60 65
40 41 42 60 65
36 37 38 40 41 42
36 37 38 40 41 42
41
77
77
15 31
42
77
77 www.rosefix.com

BI
BI
OUT
OUT
OUT
NC
DUR_SEL
DP1
VDD THERM*
ALERT*
SMDATA
SMCLK
ADDR_SEL
GPIO
THRM_PAD
GND
TH_SEL
SENSE-
SENSE+
DN2/DP3
DP2/DN3
DN1
IN
IN
OUT
THERM*/ADDR
ALERT*
GND
VDD
DN
DP
SMDATA
SMCLK
THRM
PAD
BI
BI
BI
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
87 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
D
SIZEDRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
By setting R5851 to 15k, I2C address
on the TOP side.
Place U5870 at corner near Fan,
Placement Note:
Thermal Sensor A:
Thunderbolt Die, MLB Proximity
Thermal Sensor B & CPU High Peak Detection:
CPU Proximity, Memory Proximity, Airflow, Fin Stack Proximity
Thermal Diode: TBT Die (THSP)
Thermal Diode: MLB Proximity (TMLB)
Thermal Diode: Airflow (TA0P)
Thermal Diode: Memory Proximity (TM0P) Thermal Diode: CPU Proximity (TC0P)
Thermal Sensor: Fin Stack Proximity (Th1H)
Place U5850 on the TOP side, on the left portion
of the board, 1" to the right of USB connector.
Placement Note:
for U5850 is 0xD8/0xD9.
U5850 I2C Address:
Placement Note:
The P leg connects to THERMDA pin of the TBT
chip, the N leg connect to pin AA8.
Placement Note:
Place Q5872 between two rows of Memory devices,
between channel A and B, on the BOTTOM side.
Placement Note:
Place Q5871, Airflow thermal indicator, above
the SSD, on the BOTTOM side.
Placement Note:
Place Q5873 under the CPU,
on the BOTTOM side.
Note: Use GND pin AA8 on U2800 for N leg.
I2C Write: 0x98, I2C Read: 0x99
I2C Write: 0xD8, I2C Read: 0xD9
CRITICAL
BC846BLP
DFN1006H4-3
Q5871
1
3
2
47
MF-LF
402
1/16W
5%
R5870
12
0.0022uF
CERM
402
10%
50V
PLACE_NEAR=U5870.4:5MM
NO_XNET_CONNECTION=TRUE
PLACE_NEAR=U5870.5:5MM
C5872
1
2
0.0022uF
CERM
402
10%
50V
PLACE_NEAR=U5870.2:5MM
NO_XNET_CONNECTION=TRUE
PLACE_NEAR=U5870.3:5MM
C5871
1
2
0.1uF
CERM
402
20%
10V
C5870
1
2
14 32 36 39 68 72 76
14 32 36 39 68 72 76
0.1uF
CERM
402
20%
10V
TBTTHRM_SNS
C5850
1
2
47
MF-LF
402
1/16W
5%
R5850
12
CRITICAL
BC846BLPDFN1006H4-3
Q5872
1
3
2
CRITICAL
BC846BLP
DFN1006H4-3
Q5873
1
3
2
38
38
15K
1%
MF
1/20W
201
TBTTHRM_THRM:PU
R5851
1
2
TBTTHRM_ALRT:PU
100K
1%
MF
1/20W
201
R5852
1
2
CPUTHRM_ALRT:PU
100K
1%
MF
1/20W
201
R5872
1
2
100K
1%
CPUTHRM_THRM:PU
MF
1/20W
201
R5871
1
2
38
MF
1/20W
0201
0
5%
R5875
1
2
CRITICAL
EMC1704-2
QFN
U5870
6
103
5
2
4
13
8
7
15
16
12
11
14
9
17
1
42 77
42 77
NOSTUFF
10K
MF
1/20W
201
5%
R5874
1
2
NOSTUFF
10K
MF
1/20W
201
5%
R5873
1
2
38
EMC1412-A
TQFN
TBTTHRM_SNS
U5850
6
3
2
5
8
7
4
9
1
36 39 63 76
36 39 63 76
0.0022uF
CERM
402
10%
50V
PLACE_NEAR=U5850.3:5MM
PLACE_NEAR=U5850.2:5MM
NO_XNET_CONNECTION=TRUE
TBTTHRM_SNS
C5851
1
2
SM
PLACE_NEAR=U2800.AA8:2MM
XW5851
12
23 43 77
SYNC_MASTER=J44 SYNC_DATE=08/12/2013
Thermal Sensors
ISNS_CPUHIGAIN_N
ISNS_CPUHIGAIN_P
TBTTHMSNS_D1_P
MAKE_BASE=TRUE
TBTTHMSNS_D1_N
SMBUS_SMC_3_SCL
SMBUS_SMC_3_SDA
PP3V3_S0_CPUTHMSNS_R
VOLTAGE=3.3V
MIN_LINE_WIDTH=0.25 mm
MIN_NECK_WIDTH=0.2 mm
TBTTHMSNS_THM_L
TBTTHMSNS_ALERT_L
PP3V3_S0_TBTTHMSNS_R
VOLTAGE=3.3V
MIN_LINE_WIDTH=0.38 mm
MIN_NECK_WIDTH=0.2 mm
PP3V3_S0
CPUTHMSNS_ALERT_L
CPUTHMSNS_ADDR_SEL
SMBUS_SMC_1_S0_SDA
SMBUS_SMC_1_S0_SCL
PP3V3_S0
CPUTHMSNS_TH_SEL
CPUTHMSNS_DUR_SEL
TBTTHMSNS_D1_P
CPUTHMSNS_THM_L
CPUTHMSNS_D1_N
CPUTHMSNS_D2_N
CPUTHMSNS_D2_P
CPUTHMSNS_D1_P
<BRANCH>
<SCH_NUM>
<E4LABEL>
58 OF 120
43 OF 78
23
43 77
77
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37 38 39 40 41 42 43 44 46 47
50 61 62 64 65 68 77
8 11 12 13 15 17 18 24 28 30
37 38 39 40 41 42 43 44 46 47
50 61 62 64 65 68 77
77
77
77
77 www.rosefix.com

D
SYM_VER_3
SG
OUT
IN
NC
NC
NC
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
87 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
D
SIZEDRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
518S0769
KEEP THE 5 PIN CONNECTOR FROM D1
TACH
5V DC
GND
MOTOR CONTROL
FAN CONNECTOR
1/20W
5%
201
MF
47K
R6065
12
47K
201
MF
5%
1/20W
R6060
1
2
100K
1/20W
5%
201
MF
R60611
2
DFN1006H4-3
DMN32D2LFB4
Q6060
3
1
2
36
36
FF14A-5C-R11DL-B-3H
F-RT-SM
CRITICAL
J6050
7
6
1
2
3
4
5
SYNC_MASTER=J44 SYNC_DATE=08/12/2013
Fan
SMC_FAN_0_CTL
FAN_RT_TACHSMC_FAN_0_TACH
PP5V_S0
PP3V3_S0
FAN_RT_PWM
<BRANCH>
<SCH_NUM>
<E4LABEL>
60 OF 120
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65 68
8 11 12 13 15 17 18 24 28 30 37
38 39 40 41 42 43 46 47 50 61
62 64 65 68 77 www.rosefix.com

BIBI
IN
OUT
OUT
OUT
OUT
OUT
OUT
BI
IN
BI
BI
IN
BI
IN
BI
OUT
IN
BI
IN
IN
OUT
BI
IN
OUT
RST*/HOLD*
CE*
WP*
SCK
VSS
THRM_PAD
SI/SIO0
SO/SOI1
VDD
IN
IN
IN
OUT
BI
BI
IN
OUTIN
OUTIN
BIBI
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
87 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
D
SIZEDRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
CPU Master
is for experimentation only.
Matt card ROM override. Quad-IO support
support Quad-IO. Also not compatible with
NOTE: Not all ROM APNs currently used
SMC12 Master
(SPI_IO<1>)
(SPI_IO<0>)
SPI Bus Series Termination
SPI ROM Slave
Matt Card ROM Slave
SPI ROM
SPI Frequency: 50MHz for CPU, 20MHz for SMC.
Dual-IO Mode (Mode 0 & 3) supported.
(Matt Card Connector)
LPC+SPI Connector
516S1039
in normal and Dual-IO modes.
ROM will ignore SPI cycles
NOTE: If HOLD* is asserted
PLACE_NEAR=J6100.12:5MM
LPCPLUS
MF
1/20W
0201
0
5%
R6126
1
2
45 72
1%
33
PLACE_NEAR=U6100.5:12MM
MF
1/20W
201
R6122
12
PLACE_NEAR=U0500.AA2:50MM
MF
1/20W
0201
0
5%
R6112
12
14 72
PLACE_NEAR=J6100.15:5MM
LPCPLUS
MF
1/20W
0201
0
5%
R6127
1
2
LPCPLUS
PLACE_NEAR=J6100.2:5MM
MF
1/20W
0201
0
5%
R6128
1
2
36 37 68
36 37 68
36 37 68
36 37 68
37 68
36 37 38 52 68
36 37 68
15 16 68
18 68
14 36 68 72
14 36 68 72
45 72
14 36 68 72
17 68 72
14 36 68 72
36 37 68
13 36 68
15 36 68
45 72
45 72
13 36 68
15 45 68 72
14 36 68 72
45 72
LPCPLUS
CRITICAL
DF40C-30DP-0.4V
M-ST-SM
J6100
1
10
11 12
13 14
15 16
17 18
19
2
20
21 22
23 24
25 26
27 28
29
3
30
31 32
33 34
4
5 6
7 8
9
SPI:DUAL_IO
3.3K
MF
1/20W
201
5%
R6101
1
2
BYPASS=U6100:3mm
0.1UF
X5R-CERM
0201
10%
16V
C6100
1
2
OMIT_TABLE
64MBIT
CRITICAL
SST25VF064C
WSON
U6100
1
7
6 5
2
9
8 4
3
36 72
36 72
36 72
36 72
PLACE_NEAR=U5000.K10:12MM
MF
1/20W
0201
0
5%
R6117
12
PLACE_NEAR=U5000.N9:12MM
MF
1/20W
0201
0
5%
R6115
12
PLACE_NEAR=U5000.L10:12MM
MF
1/20W
0201
0
5%
R6116
12
PLACE_NEAR=U5000.M9:12MM
MF
1/20W
0201
0
5%
R6114
12
PLACE_NEAR=U0500.AA2:50MM
MF
1/20W
0201
0
5%
R6113
12
1%
33
PLACE_NEAR=U6100.3:12MM
SPI:QUAD_IO
MF
1/20W
201
R6130
12
33
1%
PLACE_NEAR=U6100.7:12MM
SPI:QUAD_IO
MF
1/20W
201
R6131
12
14 72
14 72
PLACE_NEAR=U6100.7:12MM
SPI:DUAL_IO
MF
1/20W
0201
0
5%
R6102
12
15 45 68
72
MF
1/20W
5%
100K
201
R6103
1
2
45 72
PLACE_NEAR=U0500.Y7:50MM
MF
1/20W
0201
0
5%
R6110
12
14 72
45 72
PLACE_NEAR=U0500.AA3:50MM
MF
1/20W
0201
0
5%
R6111
12
14 72
45 72
33
PLACE_NEAR=U6100.2:12MM
1%
MF
1/20W
201
R6123
12
14 72
1%
33
PLACE_NEAR=U6100.1:12MM
MF
1/20W
201
R6120
12
LPCPLUS
PLACE_NEAR=J6100.14:5MM
MF
1/20W
0201
0
5%
R6125
1
2
PLACE_NEAR=U6100.6:12MM
1%
33
MF
1/20W
201
R6121
12
SYNC_DATE=08/12/2013SYNC_MASTER=J44
LPC+SPI Debug Connector
PP3V3_SUS
SPIROM_USE_MLB
SPIROM_WP_L
SPIROM_HOLD_L
SPI_MOSI
SPI_CS0_L
PP5V_S0
PP3V42_G3H
SPI_ALT_MISO
LPC_FRAME_L
SPIROM_USE_MLB
PM_CLKRUN_L
SPI_ALT_CLK
SPI_ALT_CS_L
LPC_SERIRQ
LPC_PWRDWN_L
SMC_TDI
SMC_TCK
SMC_RESET_L
SMC_ROMBOOT
SMC_RX_L
SMC_TMS
NC_SMC_TRST_L
NC_SMC_MD1
LPC_CLK24M_LPCPLUS
LPC_AD<0>
LPC_AD<1>
LPC_AD<3>
SPI_ALT_MOSI
XDP_LPCPLUS_GPIO
LPCPLUS_RESET_L
SMC_TDO
SMC_TX_L
SPI_MLB_CS_L
SPI_MLB_CLK SPI_MLB_MOSI
SPI_MLB_MISO
SPI_ALT_CS_L
SPI_ALT_MOSI
SPI_ALT_CLK
SPI_ALT_MISO
SPI_CLK
SPI_MISO_R
SPI_MLB_CS_L
SPI_MLB_CLK
SPI_MLB_MOSI
SPI_MLB_MISO
SPIROM_WP_L
SPIROM_HOLD_L
SPI_SMC_MOSI
SPI_SMC_MISO
SPI_SMC_CS_L
SPI_SMC_CLK
SPI_CS0_R_L
SPI_CLK_R
SPI_MOSI_R
SPI_MISO
SPI_IO<2>
SPI_IO<3>
LPC_AD<2>
<BRANCH>
<SCH_NUM>
<E4LABEL>
61 OF 120
45 OF 78
8 11 14 59 60 61 65
45 72
45 72
72
72
16 17 32 41 44 53 54 58 60 61
65 68
17 30 33 34 36 37 38 39 51 52
61 65 68
66
66
45 72
45 72 45 72
45 72
45 72
45 72
45 72
45 72
72
72
45 72
45 72 www.rosefix.com

ANALOG
SYM 1 OF 2
AGND AGND AGND AGND HPGND HPGND HPGND HSGND PLLGND
VA_PLL
VA
VA_REF
VA_HP
SENSE_A1
SENSE_A2
HPOUT_L
HPOUT_R
HS3
HS4
HS4_REF
SENSE_B2
SENSE_B1
SENSE_D
SENSE_C
HS3_REF
HSIN+
HSIN-
LINEOUT1_L-
LINEOUT1_L+
LINEOUT1_R+
LINEOUT1_R-
LINEOUT2_L-
LINEOUT2_L+
LINEOUT2_R-
LINEOUT2_R+
LINEOUT3_R+
LINEOUT3_L+
LINEOUT3_R-
LINEOUT4_L+
LINEOUT4_L-
LINEOUT4_R+
LINEOUT4_R-
LINEOUT3_L-
VREF_ADC
VCOM
FLYN
FLYN
FLYP
VHP_FILT-
VREF_DAC
LINEIN_L+
LINEIN_R-
LINEIN_R+
LINEIN_L-
MICBIAS2_R
MICBIAS2_L
MICBIAS1_R
MICBIAS1_L
MICIN1_L+
MICIN2_L-
MICIN1_L-
MICIN1_R+
MICIN2_L+
MICIN2_R+
MICIN2_R-
HSBIAS_IN
HSBIAS
HSBIAS_REF
HSBIAS_FILT
MICIN1_R-
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
NR/FB
NC
IN
EN
GND
OUT
IN
IN
IN
IN
IN
IN
IN
IN
OUT
OUT
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
87 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
D
SIZEDRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
LFT. SPKR AMP. SIG. SOURCE
RT. SPKR AMP. SIG. SOURCE
LFT SUBWOOFER AMP. SIG. SOURCE
RT. SUBWOOFER AMP. SIG. SOURCE
APPLE P/N 353S2456
PLACE XW6200 BENEATH U6200, BETWEEN PINS 2 & 5
AUDIO CODEC, ANALOG BLOCKS
APPLE P/N 353S4080
4.5V POWER SUPPLY FOR CODEC
PLACE XW6201 NEAR 5V SOURCE
CS4208-CRZR
VFBGA
U6201
M11
L6
L9
L10
B10
B11
A8
A10
C8
C10
A12
A13
C13
B13
C12
B12
L13
N11
L12
M13
D13
M6
N6
M10
N10
M9
N9
E13
E12
F12
F11
G11
F13
G13
G12
J11
H11
J13
J12
K12
K11
L11
K13
L8
L7
L5
L4
M8
N8
M7
N7
M5
N5
M4
N4
A2
C11
D12
E11
D11
M3
L3
N13
A9
A1
H12
M12
A11
N12
H13
20%
0.1UF
X7R-CERM
10V
0402
C6200
1
2
X7R-CERM
16V
10%
0402
BYPASS=U6201.A1:A2:5 MM
0.1UF
C6212
1
2
16V
0.1UF
X7R-CERM
0402
10%
BYPASS=U6201.N13:M11:5 mm
C6216
1
2
0805-LLP-1
CRITICAL
10UF
TANT-POLY
20%
16V
BYPASS=U6201.H12:H13:5 mm
C6215
1
2
4V
20%
0402
X5R
15UF
CRITICAL
C6219
12
48 77
48 77
48 77
48 77
48 77
48 77
48 77
48 77
CRITICAL
20%
0603-LLP
TANT
1UF-10OHM
25V
C6210
1
2
0805-LLP-1
16V
TANT-POLY
CRITICAL
10UF
20%
C6211
1
2
4V
20%
0402
X5R
15UF
CRITICAL
BYPASS=U6201.A8:B10:5 mm
C6222
1
2
10V
20%
0402
X5R-CERM
4.7UF
C6221
1
2
X5R
1UF
10%
25V
402
C6220
12
1/20W
1%
201
MF
2.21K
R6206
12
10%
X5R
1UF
25V 402
C6224
12
10%
X5R
1UF
25V
402
C6225
12
SM
XW6201
12
NO STUFF
1/20W
MF
5%
2.2K
201
R6200
12
FERR-22-OHM-1A-0.065-OHM
0201
L6200
12
10V
10%
X5R
1UF
402
C6201
1
2
TPS71745
CRITICAL
SON
U6200
4
2
6
5
3
1
SM
XW6200
12
10V
20%
0201-1
X5R-CERM
1.0UF
CRITICAL
C6203
1
2
BYPASS=U6201.H12:L10:5 mm
16V
0.1UF
X7R-CERM
0402
10%
C6218
1
2
50
50
50
50 77
50 77
50 77
50 77
49 77
49 77
16V
20%
TANT-POLY
0805-LLP-1
10UF
C6217
1
2
50
50
10%
0201
X5R-CERM
CRITICAL
25V
0.01UF
C6202
1
2
10%
0.1UF
X7R-CERM
0402
16V
C6214
1
2
10V
0402-1
X5R-CERM
CRITICAL
20%
10UF
C6213
1
2
0402
120-OHM-25%-1.3A
CRITICAL
L6201
12
16V
10%
0201
X5R-CERM
0.1UF
C6226
12
MF-LF
1/16W
5%
402
22K
R6207
12
SYNC_MASTER=J44 SYNC_DATE=08/12/2013
AUDIO:CODEC, ANALOG
VOLTAGE=5V
PP5V_S4_AUDIO_XW
MIN_NECK_WIDTH=0.20MM
MIN_LINE_WIDTH=0.60MM
4V5_REG_EN
PM_SLP_S3_BUF_L
PP3V3_S0
PP5V_S4
MIN_NECK_WIDTH=0.15MM
MIN_LINE_WIDTH=0.5MM
VOLTAGE=0V
GND_AUDIO_CODEC
4V5_NR
GND_AUDIO_CODEC
MIN_NECK_WIDTH=0.1 mm
MIN_LINE_WIDTH=0.4 MM
VOLTAGE=3.3V
PP3V3_S0_AUDIO_ANALOG
GND_AUDIO_CODEC
NC_AUD_LO4_RN
NC_AUD_LO4_RP
AUD_TIPDET_2
MIN_NECK_WIDTH=0.07MM AUD_US_HS_GNDMIN_LINE_WIDTH=0.5MM
MIN_LINE_WIDTH=0.20MM
MIN_NECK_WIDTH=0.07MM
VHP_FILTN
PP4V5_AUDIO_ANALOG
AUD_HP_PORT_REFCHMIN_NECK_WIDTH=0.07MMMIN_LINE_WIDTH=0.4MM
MIN_NECK_WIDTH=0.07MM AUD_CH_HS_GNDMIN_LINE_WIDTH=0.5MM
AUD_TIPDET_1
MIN_LINE_WIDTH=0.20MM
MIN_NECK_WIDTH=0.15MM
VOLTAGE=5V
4V5_REG_IN
MIN_LINE_WIDTH=0.20MM
CODEC_FLYP
MIN_NECK_WIDTH=0.07MM
GND_AUDIO_CODEC
TP_AUD_CODEC_MICBIAS1_L
TP_AUD_CODEC_MICBIAS1_R
TP_AUD_CODEC_MICBIAS2_L
MIN_NECK_WIDTH=0.07MM
CODEC_FLYN
MIN_LINE_WIDTH=0.20MM
AUD_HSBIAS_REF
AUD_HSBIAS
CODEC_HS_MIC_N
MIN_NECK_WIDTH=0.06MM
MIN_LINE_WIDTH=0.3MM
TP_AUD_CODEC_MICBIAS2_R
NC_AUD_LO1_RN
AUD_LO2_L_P
AUD_LO2_R_P
CODEC_VREF_ADC
CODEC_MICIN2
GND_AUDIO_CODEC
GND_AUDIO_CODEC
AUD_LO3_L_N
PP3V3_S0
GND_AUDIO_CODEC
AUD_LO3_L_P
NC_AUD_LO4_LN
NC_AUD_LO1_LP
AUD_LO2_R_N
NC_AUD_LO4_LP
AUD_LO2_L_N
AUD_LO3_R_P
AUD_LO3_R_N
GND_AUDIO_CODEC
CODEC_VCOM
AUD_HP_PORT_REFUSMIN_NECK_WIDTH=0.07MMMIN_LINE_WIDTH=0.4MM
MIN_NECK_WIDTH=0.07MM
MIN_LINE_WIDTH=0.3MM
HS_MIC_P
CODEC_HS_MIC_P
MIN_NECK_WIDTH=0.06MM
MIN_LINE_WIDTH=0.3MM
MIN_LINE_WIDTH=0.3MM
AUD_HP_PORT_RMIN_NECK_WIDTH=0.07MM
VREF_DAC
MIN_NECK_WIDTH=0.07MM
MIN_LINE_WIDTH=0.20MM
HS_MIC_N
MIN_LINE_WIDTH=0.3MM
MIN_NECK_WIDTH=0.07MM
MIN_NECK_WIDTH=0.15MM
MIN_LINE_WIDTH=0.20MM
VOLTAGE=4.5V
PP4V5_AUDIO_ANALOG
MIN_LINE_WIDTH=0.3MM AUD_HP_PORT_LMIN_NECK_WIDTH=0.07MM
AUD_HSBIAS_FILT
AUD_TYPEDET
AUD_HSBIAS_IN
GND_AUDIO_CODEC
NC_AUD_LO1_RP
NC_AUD_LO1_LN
GND_AUDIO_CODEC
<BRANCH>
<SCH_NUM>
<E4LABEL>
62 OF 120
46 OF 78
26 27 61
8 11 12 13 15 17 18 24 28 30
37 38 39 40 41 42 43 44 46
47 50 61 62 64 65 68 77
32 33 55 56 57 60 62
63 65 66 68
46 50
46 50
46 50
46
46 50
77
46
50
46 50
8 11 12 13 15 17 18 24 28 30 37
38 39 40 41 42 43 44 46 47 50
61 62 64 65 68 77
46 50
46 50
77
46
46 50
46 50 www.rosefix.com

DIGITAL
SYM 2 OF 2
VD
VL_HD VL_IFVL_SP VL_DM
NC
NC
NC
NC
NC
NC
NC
NC
NC
DMIC_SCL3
DMIC_SDA3
DMIC_SCL2
DMIC_SDA2
DMIC_SCL1
DMIC_SDA1
DMIC_SCL0
DMIC_SDA0
SPDIF_OUT
SPDIF_IN
SCL
SDA
SDIN_B
SDOUT_B
LRCK_B
SCLK_B
MCLK_B
RST*
SDO3
SDO2
SDO1
SDO0
GPIO0
GPIO1
GPIO5
GPIO4
GPIO3
GPO0
SYNC
BCLK
SDI0
GPO1
SDI1
SCLK_A
MCLK_A
LRCK_A
SDOUT_A
SDIN_A
GPIO2
DGND LGNDLGNDLGND LGND LGND
OUT
IN
OUT
IN
IN
IN
OUT
OUT
IN
OUT
PP
PP
OUT
IN
IN
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
87 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
D
SIZEDRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AUDIO CODEC, DIGITAL BLOCKS
APPLE P/N 353S4080
CS4208-CRZR
VFBGA
U6201
F2
J1
N2
M1
L1
L2
N3
N1
M2
K2
H3
H2
H1
C4
C5
C7
C9
B9
F1
E3
F3
J3
K3
B4
B5
A5
A6
F6
F7
F8
G6
G7
G8
H6
H7
H8
D3
B7
B2
B6
C6
D1
C1
B3
A4
D2
C2
C3
B1
A3
B8
G3
G2
E2
J2
K1
E1
G1
A7
402
SHORT
OMIT
R6302
12
201
100K
MF
5%
1/20W
R6323
12
1/20W
5%
MF
100K
201
R6325
1
2
49
0201
FERR-22-OHM-1A-0.065-OHM
L6300
12
12 72
12 68 72
12 72
12 72
5%
MF
22
1/20W
201
R6331
12
10V
20%
0402-1
X5R-CERM
10UF
C6305
1
2
BYPASS=U6201.E1:F1:5 mm
16V
0402
X7R-CERM
0.1UF
10%
C6302
1
2
10V
20%
0402-1
X5R-CERM
10UF
C6306
1
2
BYPASS=U6201.A7:E3:5 mm
CERM-X5R
0201
6.3V
0.1UF
10%
C6307
1
2
BYPASS=U6201.G1:F1:5 mm
CERM-X5R
0201
6.3V
0.1UF
10%
C6303
1
2
4.7UF
4V
20%
X5R-1
402
C6300
1
2
BYPASS=U6201.K1:K3:5 mm
CERM-X5R
0201
6.3V
0.1UF
10%
C6304
1
2
12 47 72
1/16W
5%
402
MF-LF
33
R6330
12
50
1/16W
1%
402
MF-LF
75
R6332
12
50 68
47 50 68
BYPASS=U6201.J2:J1:5 mm
16V
0402
X7R-CERM
0.1UF
10%
C6301
1
2
48
1/20W
5%
MF
100K
201
R6324
1
2
NOSTUFF
1/20W
5%
MF
100K
201
R6322
12
PLACE_NEAR=U6201.N3:5 mm
SM
P3MM
PP6301
1
PLACE_NEAR=U6201.D2:5 mm
SM
P3MM
PP6304
1
49
50 68
50 68
AUDIO:CODEC, DIGITAL
SYNC_MASTER=J44 SYNC_DATE=08/12/2013
DMIC_SDA3
MIN_NECK_WIDTH=0.07MM
MIN_LINE_WIDTH=0.6 MM
PP1V5_S0_AUDIO_DIG
VOLTAGE=1.5V
NC_CS4208_SCLKB
DMIC_CLK3_R NC_DMIC_CLK1
NC_CS4208_MCLKB
NC_CS4208_SDOUTA
HDA_SDOUT
NC_CS4208_SCLKA
NC_CS4208_LRCLKA
NC_CS4208_LRCLKB
NC_CS4208_SDOUTB
GPIO0_SPKR_SHUTDOWN
NC_DMIC_CLK2
DMIC_CLK3
CS4208_SPDIF_IN
CS4208_HDA_SDOUT0_R
TP_CS4208_HDA_SDOUT1
HDA_SDOUT
SPDIF_OUT_JACK
HDA_RST_L
PP3V3_S0
DMIC_SDA3
CS4208_SPDIF_OUT
NC_DMIC_CLK0
SPKRCONN_L_ID
NC_CS4208_GPO1
HDA_SYNC
SPKRCONN_R_ID
DFET_OPENUS
NC_CS4208_GPO0
PP3V3_S0
PP3V3_S0
NC_CS4208_MCLKA
HDA_BIT_CLK
HDA_SDIN0
PP1V5_S0
PD_CS4208_GPIO1
DFET_OPENCH
<BRANCH>
<SCH_NUM>
<E4LABEL>
63 OF 120
47 OF 78
47 50 68
72
12 47 72
8 11 12 13 15 17 18 24 28 30
37 38 39 40 41 42 43 44 46 47
50 61 62 64 65 68 77
8 11 12 13 15 17 18 24 28 30 37
38 39 40 41 42 43 44 46 47 50
61 62 64 65 68 77
8 11 12 13 15 17 18 24 28 30 37
38 39 40 41 42 43 44 46 47 50
61 62 64 65 68 77
8 59 60 61 63 65
68 www.rosefix.com

VDD
EDGE
GND
GAINSD*
OUT+
OUT-
IN-
IN+
OUT
OUT
VDD
EDGE
GND
GAINSD*
OUT+
OUT-
IN-
IN+
OUT
OUT
IN
IN
OUT
IN
OUT
IN
IN
OUT
OUT
IN-
IN+
OUT+
OUT-
GAINSHDN*
PVDD
NC
PGND
IN-
IN+
OUT+
OUT-
GAINSHDN*
PVDD
NC
PGND
IN
IN
IN
IN
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
87 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
D
SIZEDRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
4X MONO SPEAKER AMPLIFIERS (MAX98300 & SSM2375)
1ST ORDER FC (SUB) = NOM 9 HZ
GAIN = +3 DB
1ST ORDER FC (L&R) = NOM 569 HZ
APN: 353S2888 & 353S2958
0402
FERR-1000-OHM
CRITICAL
L6430
12
16V
10%
402
CERM
0.22UF
CRITICAL
C6443
12
16V
10%
402
CERM
0.22UF
CRITICAL
C6444
12
CERM
10%
16V
402
0.22UF
CRITICAL
C6434
12
16V
10%
402
CERM
0.22UF
CRITICAL
C6433
12
WLCSP
SSM2375
CRITICAL
U6430
B2
A3
C1
A1
B1
B3
C3
A2
C2
50 68 77
50 68 77
BYPASS=U6430.C2:C1:5 mm
16V
10%
0201
X5R-CERM
0.1UF
C6431
1
2
WLCSP
SSM2375
CRITICAL
U6440
B2
A3
C1
A1
B1
B3
C3
A2
C2
50 68 77
50 68 77
6.3V
20%
CASE-A4
TANT-POLY
47UF
CRITICAL
C6422
1
2
6.3V
20%
CASE-AL1
TANT
100UF
CRITICAL
C6432
1
2
6.3V
20%
CASE-AL1
TANT
100UF
CRITICAL
C6442
1
2
50V
10%
0402
X7R-CERM
4700PF
C6436
1
2
50V
10%
0402
X7R-CERM
4700PF
C6446
1
2
10%
0.1UF
X5R-CERM
16V
BYPASS=U6440.C2:C1:5 mm
0201
C6441
1
2
10%
0.1UF
X5R-CERM
16V
BYPASS=U6410.A1:A2:5 mm
0201
C6411
1
2
5%
402
MF-LF
100K
1/16W
R6400
1
2
0402
FERR-1000-OHM
CRITICAL
L6401
12
46 77
47
0402
FERR-1000-OHM
CRITICAL
L6411
12
50 68 77
16V
10%
0201
X5R-CERM
0.1UF
BYPASS=U6420.A1:A2:5 mm
C6421
1
2
0402
FERR-1000-OHM
CRITICAL
L6421
12
46 77
50 68 77
6.3V
20%
CASE-A4
TANT-POLY
47UF
CRITICAL
C6412
1
2
0402
FERR-1000-OHM
CRITICAL
L6410
12
46 77
0402
FERR-1000-OHM
CRITICAL
L6420
12
46 77
50V
10%
0402
X7R-CERM
0.01UF
CRITICAL
C6423
12
50V
10%
0402
X7R-CERM
0.01UF
CRITICAL
C6424
12
50V
10%
0402
X7R-CERM
0.01UF
CRITICAL
C6414
12
50V
10%
0402
X7R-CERM
0.01UF
CRITICAL
C6413
12
50 68 77
50 68 77
WLP
MAX98300
CRITICAL
U6410
C3
B3
A3
B2
C1
B1
A2A1
C2
1/16W
5%
402
MF-LF
100K
R6410
1
2
WLP
MAX98300
CRITICAL
U6420
C3
B3
A3
B2
C1
B1
A2A1
C2
1/16W
5%
402
MF-LF
100K
R6420
1
2
46 77
46 77
CRITICAL
FERR-1000-OHM
0402
L6441
12
CRITICAL
0402
FERR-1000-OHM
L6440
12
46 77
0402
FERR-1000-OHM
CRITICAL
L6431
12
46 77
AUDIO: SPEAKER AMP
SYNC_DATE=08/12/2013SYNC_MASTER=J44
RSUBIN_N
NO_TEST=TRUE
AUD_LO3_L_N
AUD_LO3_L_P
AUD_LO3_R_N
AUD_LO3_R_P
SPKRCONN_SL_OUT_P
MIN_NECK_WIDTH=0.10 MM
MIN_LINE_WIDTH=0.40 MM
RSUBIN_P
NO_TEST=TRUE
SPKRCONN_R_OUT_N
MIN_NECK_WIDTH=0.10 MM
MIN_LINE_WIDTH=0.40 MM
SPKRCONN_R_OUT_P
MIN_NECK_WIDTH=0.10 MM
MIN_LINE_WIDTH=0.40 MM
SPKRAMP_RIN_N
NO_TEST=TRUE
SPKRAMP_LIN_P
NO_TEST=TRUE
AUD_SPKRAMP_RIN_N
NO_TEST=TRUE
AUD_SPKRAMP_RIN_P
NO_TEST=TRUE
SPKRAMP_LIN_N
NO_TEST=TRUE
NO_TEST=TRUE
AUD_SPKRAMP_RSUBIN_N
AUD_SPKRAMP_LSUBIN_N
NO_TEST=TRUE
AUD_SPKRAMP_LIN_N
NO_TEST=TRUE
AUD_SPKRAMP_LSUBIN_P
NO_TEST=TRUE
AUD_SPKRAMP_RSUBIN_P
NO_TEST=TRUE
SPKRAMP_RIN_P
NO_TEST=TRUE
LSUBIN_N
NO_TEST=TRUE
LSUBIN_P
NO_TEST=TRUE
AUD_LO2_L_N
AUD_LO2_R_P
AUD_LO2_R_N
SPKR_SHUTDOWN
AUD_LO2_L_P
SPKR_SHUTDOWN
SPKR_SHUTDOWN
GPIO0_SPKR_SHUTDOWN
SPKR_SHUTDOWN
SPKR_L_GAIN
RSUB_GAIN
LSUB_GAIN
SPKRCONN_SR_OUT_P
MIN_NECK_WIDTH=0.10 MM
MIN_LINE_WIDTH=0.40 MM
NO_TEST=TRUE
AUD_SPKRAMP_LIN_P
MIN_NECK_WIDTH=0.10 MM
MIN_LINE_WIDTH=0.40 MM
SPKRCONN_L_OUT_P
PP5V_S0_AUDIO_AMP_L
SPKRCONN_L_OUT_N
MIN_LINE_WIDTH=0.40 MM
MIN_NECK_WIDTH=0.10 MM
SPKR_R_GAIN
SPKRCONN_SR_OUT_N
MIN_NECK_WIDTH=0.10 MM
MIN_LINE_WIDTH=0.40 MM
SPKRCONN_SL_OUT_N MIN_NECK_WIDTH=0.10 MM
MIN_LINE_WIDTH=0.40 MM
PP5V_S0_AUDIO_AMP_L
PP5V_S0_AUDIO_AMP_R
PP5V_S0_AUDIO_AMP_R
<BRANCH>
<SCH_NUM>
<E4LABEL>
64 OF 120
48 OF 78
77
77
77
77
77
77
77
77
77
77
77
48
48
48
48
77
48 66
48 66
48 66
48 66 www.rosefix.com

OUT
OUT IN
IN
IN
OUT
OUT
OUT
OUT
IN
PSEL
CP
GND
OUT2
OUT1
VDD
PSEL
CP
GND
OUT2
OUT1
VDD
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
87 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
D
SIZEDRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
R/C6550 FILTER TO ADDRESS OUT-OF-BAND
NOISE ISSUE SEEN ON EARLY HEADSETS
(SEE RADAR # 6210118)
46 77
46 77
100K
5%
MF
201
1/20W
R6556
1
2
5%
402
2.2K
MF-LF
1/16W
R6550
12
5%
NP0-C0G
25V
CRITICAL
27PF
0201
C6558
1
2
5%
2.2K
1/16W
MF-LF
402
R6559
12
50 77
50 77
5%
1000PF
NP0-C0G
25V
0402
C6501
1
2
47
49 50 77
49 50 77
49 50 77
49 50 77
47
0402
25V
NP0-C0G
1000PF
5%
C6502
1
2
MF-LF
1/16W
10K
402
5%
R6520
1
2
BYPASS=U6501.B2:3MM
X5R-CERM
0201
16V
10%
0.1UF
C6542
1
2
CERM-X5R
0402
35V
10%
1.0UF
C6530
1
2
0201
CRITICAL
3300PF
X7R-CERM
10%
10V
C6550
1
2
BYPASS=U6501.B2:3MM
10V
10%
0201
X5R-CERM
0.01UF
C6543
1
2
WCSP
TAIC3027A0YFFR
U6500
C1
B1
A1
A2
C2
B2
TAIC3027A0YFFR
WCSP
U6501
C1
B1
A1
A2
C2
B2
5%
402
10K
1/16W
MF-LF
R6521
1
2
BYPASS=U6500.B2:3MM
0.01UF
X5R-CERM
0201
10%
10V
C6563
1
2
BYPASS=U6500.B2:3MM
0.1UF
10%
16V
0201
X5R-CERM
C6562
1
2
1.0UF
10%
35V
0402
CERM-X5R
C6560
1
2
SYNC_DATE=08/12/2013SYNC_MASTER=J44
AUDIO: JACK
DFET_CPO1 AUD_CONN_SLEEVE_XW
AUD_CONN_SLEEVE_XW
AUD_HS_MIC_P
MIN_LINE_WIDTH=0.2MM
MIN_NECK_WIDTH=0.06MM
HS_MIC_P
HS_MIC_N
DFET_CPO2 AUD_CONN_RING2_XW
AUD_CONN_RING2_XW
AUD_HS_MIC_N
MIN_LINE_WIDTH=0.2MM
MIN_NECK_WIDTH=0.06MM
DFET_OPENUS
DFET_OPENCH
<BRANCH>
<SCH_NUM>
<E4LABEL>
65 OF 120
49 OF 78www.rosefix.com

IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
OUT
OUT
OUT
IN
OUT
OUT
OUT
OUT
OUT
OUT
IN
OUT
OUT
IN
GND
VDD
AUDIO GND
SHELL
VIN
MIC
DET2
DET1
1RTN
2RTN
R.AUDIO
AUDIO GND
PINS
POF
OPERATING VOLTAGE 3.3
AUDIO
NC
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
87 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
D
SIZEDRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
2.7V
APN: 514-0875
FUNCTION
OTHER CODEC GPIO LINES
INPUT
INPUT
HP/HS OUT
TWEETERS
SUB 0X04 (4)
0X03 (3)
0X02 (2)
VOLUME CONVERTER
0X02 (2)
0X03 (3)
0X04 (4)
PIN COMPLEX
0X10 (16)
0X12 (18)
0X13 (19)
MUTE CONTROL
N/A
CODEC GPIO0
CODEC GPIO0
FUNCTION
DMIC 1
DMIC 2
HEADSET MIC
DFET CONTROL
LEFT SPEAKER ID
0X07 (7)
0X09 (9)
CONVERTER PIN COMPLEX
0X1C (28)
0X18 (24)
VREF
3.3V
3.3V
APN: 518S0818
HP=80HZ
APN: 518S0672
0X1C (28)
2-MIC CONNECTOR
SPEAKER CONNECTOR
RIGHT SPEAKER ID
GPIO2
HIGH = FG, LOW = MERRY
0X09 (9)
CODEC INPUT SIGNAL PATHS
N/A
CODEC OUTPUT SIGNAL PATHS
OUTPUT
N/A
0X21 (33)0X0E (14)SPDIF OUT
GPIO3
GPIO4
HIGH = FG, LOW = MERRY
HIGH = DFETs OPEN
CRITICAL
78171-6006
M-RT-SM
J6602
7
8
1
2
3
4
5
6
CRITICAL
78171-6006
M-RT-SM
J6603
7
8
1
2
3
4
5
6
48 68 77
48 68 77
48 68 77
47 68
48 68 77
47 68
48 68 77
48 68 77
48 68 77
48 68 77
47 68
47 68
F-RT-SM
FF14A-6C-R11DL-B-3H
CRITICAL
J6601
1
2
3
4
5
6
7
8
402
SHORT
OMIT
R6680
12
46
46
49 77
49 77
46
46
46 77
46 77
46
CRITICAL
0201
FERR-470-OHM
L6606
12
0402
CRITICAL
120-OHM-25%-1.3A
L6605
12
FERR-470-OHM
0201
CRITICAL
L6607
12
120-OHM-25%-1.3A
CRITICAL
0402
L6604
12
46 77
46 77
FERR-470-OHM
0201
CRITICAL
L6608
12
402-1
X5R
10%
10V
1UF
C6600
1
2
CERM-X5R
0201
6.3V
0.1UF
10%
C6601
1
2
5%
402
10K
1/16W
MF-LF
R6601
1
2
SM
PLACE_NEAR=J6600.5:5mm
XW6600
12
SM
PLACE_NEAR=J6600.6:5mm
XW6602
12
SM
XW6601
12
SM
XW6603
12
ESDALC5-1BM2
SOD882
CRITICAL
DZ6601
1
2
SOD882
ESDALC5-1BM2
CRITICAL
DZ6602
1
2
SOD882
ESDALC5-1BM2
CRITICAL
DZ6603
1
2
ESDALC5-1BM2
SOD882
CRITICAL
DZ6606
1
2
ESDALC5-1BM2
SOD882
CRITICAL
DZ6605
1
2
ESDALC5-1BM2
SOD882
CRITICAL
DZ6604
1
2
SOD882
ESDALC5-1BM2
CRITICAL
DZ6607
1
2
47
F-RT-TH
AUDIO-SPDIF-J44
J6600
1
10
11
12
13
14
15
2
3
4
5
6
7
8
9
100PF
NP0-CERM
0201
25V
5%
C6608
1
2
25V
100PF
NP0-CERM
0201
5%
C6607
1
2
100PF
NP0-CERM
0201
25V
5%
C6606
1
2
NP0-CERM
100PF
0201
25V
5%
C6605
1
2
100PF
NP0-CERM
0201
25V
5%
C6604
1
2
0201
NP0-CERM
25V
5%
100PF
C6603
1
2
0201
NP0-CERM
25V
5%
100PF
C6602
1
2
0402
CRITICAL
120-OHM-25%-1.3A
L6611
12
0402
120-OHM-25%-1.3A
CRITICAL
L6612
12
0402
CRITICAL
120-OHM-25%-1.3A
L6613
12
120-OHM-25%-1.3A
CRITICAL
0402
L6614
12
1/16W
MF-LF
5%
402
2.2K
R6602
1
2
MF-LF
5%
1/16W
402
2.2K
R6603
1
2
SYNC_MASTER=J44 SYNC_DATE=08/12/2013
AUDIO: JACK TRANSLATORS
AUD_CONN_SLEEVE
MIN_LINE_WIDTH=0.4MM
MIN_NECK_WIDTH=0.06MM
AUD_HS_MIC_N
SPKRCONN_R_OUT_P
SPKRCONN_SL_OUT_N
AUD_TIPDET_1
SPKRCONN_L_ID
SPKRCONN_L_OUT_P
SPKRCONN_SR_OUT_P
SPKRCONN_R_ID
SPKRCONN_R_OUT_N
SPKRCONN_L_OUT_N
AUD_HS_MIC_P
SPKRCONN_SR_OUT_N
SPKRCONN_SL_OUT_P
PP3V3_S0
DMIC_SDA3
DMIC_CLK3
DMIC_SDA2
MIN_NECK_WIDTH=0.06MM
MIN_LINE_WIDTH=0.3MM
AUD_CONN_HP_RIGHT
AUD_CONN_TYPEDET
AUD_CONN_TIPDET_1
AUD_CH_HS_GND
AUD_CONN_RING2_XW
MIN_NECK_WIDTH=0.1MM
MIN_LINE_WIDTH=0.5MM
AUD_CONN_SLEEVE_XW
MIN_LINE_WIDTH=0.5MM
MIN_NECK_WIDTH=0.1MM
AUD_CONN_TIPDET_2
AUD_CONN_HP_LEFT
MIN_LINE_WIDTH=0.3MM
MIN_NECK_WIDTH=0.06MM
MIN_LINE_WIDTH=0.4MM
AUD_CONN_RING2
MIN_NECK_WIDTH=0.06MM
AUD_US_HS_GND
AUD_HP_PORT_REFCH
GND_AUDIO_CODEC
AUD_TYPEDET
AUD_HP_PORT_R
SPDIF_OUT_JACK
PP3V3_S0
AUD_HP_PORT_REFUS
AUD_TIPDET_2
AUD_HP_PORT_L
<BRANCH>
<SCH_NUM>
<E4LABEL>
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68
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37 38 39 40 41 42 43 44 46 47
50 61 62 64 65 68 77 www.rosefix.com

VCC
EXT INT
NCGND
SW
BOOSTVIN
BIAS
SHDN*
GND
NC
FB
PAD
THRM
NC
BI
NC
G
D
S
GS
D
Y
B
A IN
G
D
S
NC
NC BI
BI
GND
SMBUSSDA
SMBUSSCL
PWR
PWR
SYSDETL
GND
GND
PWR
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
87 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
D
SIZEDRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
518-0394
MagSafe DC Power Jack
6.8V Zener
518S0508
Vout = 1.25V * (1 + Ra / Rb)
Vout = 3.425V
conduct and power charger and 3.42V reg
When input voltage is at 16V+, FET will
properly detected.
blocking the leakage path and 22.1K can be
When input voltage is 2V the FET will be off
for both MPM4 and MPM5.
sparkitecture requirements
Input impedance of 68K meets
<Rb>
<Ra>
connected.
send transients onto ADAPTER_SENSE when AC is
1-Wire OverVoltage Protection
The chassis ground will otherwise float and can
Supply needs to guarantee 3.31V delivered to SMC VRef generator
3.425V "G3Hot" Supply
300MA MAX OUTPUT
(Switcher limit)
0603
6AMP-32V-0.0095OHM
CRITICAL
F7005
12
50V
10%
603-1
X7R
0.1UF
NO STUFF
C7005
1
2
SC70-5
MAX9940
CRITICAL
U7000
5
2
4
3
1
DFN
LT3470AED
CRITICAL
U7090
2
3
1
5
7
84
9
6
5%
NP0-C0G-CERM
50V
0201
22PF
C7095
1
2
201
1/20W
MF
1%
200K
R7096
1
2
6.3V
20%
0603
X5R
22UF
CRITICAL
C7099
1
2
201
1/20W
MF
1%
348K
R7095
1
2
5%
805
MF-LF
10
1/8W
R7005
12
MF
1/3W
1%
805
47
R7020
12
SOT-323
SBR0330CW
CRITICAL
D7005
1
2
3
CRITICAL
2520
10UH-20%-0.85A-0.46OHM
L7095
12
10V
10%
CERM
0.22UF
402
C7094
1
2
10%
0603
X6S-CERM
4.7UF
25V
C7090
1
2
36
5%
1/16W
MF-LF
2.0K
402
R7029
1
2
POWERPAK
SI5419DU
Q7010
1
4
5
5A
5%
201
1/20W
MF
100K
R7010
1
2
GDZ-0201
GDZT2R6.8
D7010
A
K
201
1/20W
MF
1%
68K
R7012
1
2
10%
0603
X6S-CERM
4.7UF
25V
C7091
1
2
10%
0603
X6S-CERM
4.7UF
25V
C7092
1
2
201
1/20W
MF
1%
10K
R7011
12
10%
0402
X5R
0.047UF
25V
C7012
1
2
SOT23-HF1
2N7002
BLEEDER
Q7030
3
1
2
5%
1/16W
MF-LF
1K
BLEEDER
402
R7030
1
2
50V
10%
603-1
X7R
0.1UF
BLEEDER
C7020
1
2
SOT-323
SBR0330CW
CRITICAL
BLEEDER
D7020
1
2
3
5%
1/16W
MF-LF
10K
BLEEDER
402
R7021
1
2
10V
20%
CERM
0.1UF
402
C7000
1
2
SOT665
TC7SZ08FEAPE
CRITICAL
U7001
2
1
3
5
4
10V
20%
CERM
0.1UF
PLACE_NEAR=U7001.5:1MM
402
C7008
1
2
36 37 52
SOT23
AO3407A
BLEEDER
Q7020
3
1
2
5%
NO STUFF
CERM
0402
25V
1000PF
C7080
1
2
201
1/20W
MF
NO STUFF
1%
49.9K
R7081
1
2
5%
0
0201
1/20W
MF
R7080
1
2
10%
X5R
0.1UF
25V
402
C7050
1
2
10%
603-1
X5R
1UF
25V
C7060
1
2
SC-75
RCLAMP2402B
CRITICAL
D7050
3
1
2
5%
1/16W
MF-LF
10K
402
R7050
1
2
36 39 52 68 76
36 39 52 68 76
CRITICAL
WTB-PWR-M82
M-RT-SM
J7000
1
2
3
4
5
6
F-ST-TH
CRITICAL
BAT-J44
J7050
1 10
2 11
3 12
4 13
5 14
6 15
7 16
8 17
9 18
DC-In & Battery Connectors
SYNC_DATE=08/12/2013SYNC_MASTER=J44
PP3V42_G3H
VOLTAGE=18.5V
PPBUS_G3H_R
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.25 mm
P3V42G3H_SHDN_L
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=18.5V
MIN_LINE_WIDTH=0.4 mm
PPVIN_G3H_P3V42G3H
ADAPTER_SENSE
TP_TDM_ONEWIRE_MPM
PPVBAT_G3H_CONN
DCIN_ISOL_GATE_R
P3V42G3H_FB
DCIN_ISOL_GATE
PP3V42_G3H
SMC_BC_ACOK
PPDCIN_G3H
PPBUS_G3H
SYS_ONEWIRE
MIN_NECK_WIDTH=0.25 mm
MIN_LINE_WIDTH=0.5 mm
P3V42G3H_SW
DIDT=TRUE
SWITCH_NODE=TRUE
DCIN_ISOL_BLEEDER_R
MIN_NECK_WIDTH=0.20MM
MIN_LINE_WIDTH=0.6MM
DCIN_ISOL_BLEEDER_NGATE
MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.20MM
MIN_NECK_WIDTH=0.20MM
MIN_LINE_WIDTH=0.6MM
DCIN_ISOL_BLEEDER_PSRC
P3V42G3H_BOOST
NO_TEST=TRUE
SWITCH_NODE=TRUE
DIDT=TRUE
MIN_LINE_WIDTH=0.6 mm
VOLTAGE=18.5V
PP18V5_DCIN_CONN_R
MIN_NECK_WIDTH=0.25 mm
MIN_NECK_WIDTH=0.20MM
MIN_LINE_WIDTH=0.6MM
VOLTAGE=18.5V
PP18V5_DCIN_FUSE
SMC_BC_ACOK_VCC
SMBUS_SMC_5_G3_SDA
SYS_DETECT_L
SMBUS_SMC_5_G3_SCL
PPDCIN_G3H_ISOL
<BRANCH>
<SCH_NUM>
<E4LABEL>
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52 65 68
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68
68
40 52 65 www.rosefix.com

IN
SW
BOOSTVIN
BIAS
SHDN*
GND
NC
FB
PAD
THRM
NC
NC
IN
BI
IN
OUT
OUT
OUT
AMON
BMON
ACOK
LGATE
PHASE
BOOT
SGATE
AGATE
CSIP
CSIN
DCIN
VNEG
CSOP
CSON
THRM_PAD
PGND
VDDPVDD
BGATE
UGATE
ICOMP
VCOMP
ACIN
SDA
VFRQ
CELL
VHST
SCL
SMB_RST_N
G
D
SYM-VER-2
S
G
G
S
D
S
D
NCNCNC
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
87 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
D
SIZEDRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
FROM ADAPTER
ACIN pin threshold is 3.2V, +/- 50mV
Divider sets ACIN threshold at 13.55V
Inrush Limiter
(CHGR_AGATE)
TO/FROM BATTERY
250MA MAX OUTPUT
(Switcher limit)
Vout = 5.50V
353S2929
(OD)
(CHGR_CSO_P)
20V/V
<Ra>
<Rb>
(CHGR_CSO_N)
(GND)
36V/V
(PPVBAT_G3H_CHGR_R)
(AGND)
(P5V1_BIAS)
(CHGR_DCIN)
(PPVBAT_G3H_CHGR_R)
(CHGR_SGATE)
Float CELL for 1S
sparkitecture requirements
Input impedance of ~90K meets
(CHGR_BGATE)
TO SYSTEM
Max Current = 8.5A
f = 400 kHz
(L7130 limit)
Reverse-Current Protection
For Erp Lot6 spec
Vout = 1.25V * (1 + Ra / Rb)
30mA max load
10V
10%
0402
X5R-CERM
0.068UF
C7142
1
2
36
37
38
45
68
25V
20%
CASE-D2-SM
POLY-TANT
22UF
CRITICAL
C7132
1
2
25V
4.7UF
X6S-CERM
10%
0603
C7190
1
2
LT3470A
CRITICAL
DFN
U7190
2
3
1
5
7
8 4
9
6
5%
22PF
50V
NP0-C0G-CERM
0201
C7195
1
2
CRITICAL
33UH-20%-0.39A-0.435OHM
DP418C-SM
L7195
12
402
10V
10%
X5R
1UF
C7102
1
2
402
10V
10%
CERM
0.22UF
C7194
1
2
1%
201
MF
200K
1/20W
R7196
1
2
1/20W
1%
201
MF
681K
R7195
1
2
25V
CRITICAL
10UF
20%
0603
X5R-CERM
C7198
1
2
25V
CRITICAL
10UF
X5R-CERM
0603
20%
C7199
1
2
5%402
1/16W
MF-LF
0
R7191
12
5%402
1/16W
MF-LF
0
NOSTUFF
R7190
12
PIME103T-4R7MS
CRITICAL
4.7UH-20%-8.5A-18.3MOHM
L7130
12
5%402MF-LF
1/16W
0
R7192
12
X7R-CERM
16V
10%
0402
0.01UF
C7111
1
2
25V
4.7UF
10%
NOSTUFF
X6S-CERM
0603
C7180
1
2
10V
10%
402-1
X5R
1UF
C7100
1
2
PLACE_NEAR=U7100.22:1MM
PLACE_NEAR=U7100.29:1MM
SM
XW7100
12
50V
10%
0603-1
X5R-CERM
0.22UF
C7105
1
2
402
16V
10%
X5R
1UF
C7150
1
2
61
36 39 51
68 76
36 39 51
68 76
50V
10%
0402
CERM
470PF
C7116
1
2
5%
402
1/16W
MF-LF
0
R7100
12
5%
402
1/16W
MF-LF
100K
NO STUFF
R7102
1
2
5%
402
1/16W
MF-LF
4.7
R7101
12
5%
402
1/16W
MF-LF
20
R7105
12
402
10%
10V
X5R
1UF
C7101
1
2
CRITICAL
SOT-323
SBR0330CW
D7105
1
2
3
402
25V
10%
X5R
0.1UF
C7185
1
2
402
1/16W
1%
MF-LF
470K
R7185
1
2
402
1/16W
1%
MF-LF
332K
R7186
1
2
36 37 51
40
40
50V
10%
0402
X7R-CERM
0.001UF
C7126
1
2
5% 4021/16W MF-LF
2.2R7151 12
5% 4021/16W MF-LF
0R7152 12
402
1/16W
1%
MF-LF
21.5K
R7111
1
2
402
PLACE_NEAR=U7100.23:2MM
10V
10%
CERM
0.22UF
C7125
1
2
402
25V
10%
X5R
0.1UF
NO_XNET_CONNECTION=TRUE
C7122
1
2
10V
10%
0402
X5R-CERM
0.047UF
C7120
1
2
402
25V
10%
0.1UF
X5R
NO_XNET_CONNECTION=TRUE
C7121
1
2
5%
402
MF-LF
10
1/16W
R7122
12
5%
402
1/16W
MF-LF
10
R7121
12
402
25V
10%
X5R
1UF
C7155
1
2
402
25V
10%
X5R
0.1UF
C7156
1
2
0.01UF
X7R-CERM
50V
10%
0402
C7157
1
2
16V
20%
CASE-D2E-SM
POLY-TANT
68UF
CRITICAL
C7140
1
2
25V
20%
CASE-D2-SM
POLY-TANT
22UF
CRITICAL
C7130
1
2
25V
20%
CASE-D2-SM
POLY-TANT
22UF
CRITICAL
C7131
1
2
402
1/16W
1%
MF-LF
3.01K
R7116
1
2
50V
10%
0603
X5R
1.0UF
C7135
1
2
50V
10%
0402
X7R-CERM
0.001UF
C7145
1
2
1206
12AMP-32V
CRITICAL
F7140
12
PLACE_NEAR=Q7130.2:1MM
50V
10%
0603
X5R
1.0UF
C7136
1
2
PLACE_NEAR=C7136.1:3mm
50V
20%
0402
CERM
0.001UF
C7137
1
2
5%
402
1/16W
MF-LF
62K
R7181
1
2
5%
402
100K
MF-LF
1/16W
R7180
1
2
TQFN
ISL6259
CRITICAL
U7100
3
14
1
9
16
15
25
6
27
28
17
18
2
5
21
22
23
11
10
26
13
29
24
7
19
20
4
12
8
5%
402
1/16W
MF-LF
0
R7125
1
2
0.005
0612-2
1%
1W
MF
CRITICAL
R7150
12
34
402
1/16W
1%
MF-LF
68.1K
R7110
1
2
402
1/16W
1%
100K
MF-LF
R7115
1
2
5%
402
50V
COG
330PF
C7115
1
2
SO-8
SI7137DP
CRITICAL
Q7155
5
4
1
2
3
402
MF-LF
1/16W
1K
1%
R7142
1
2
402
1/16W
MF-LF
1%
1K
R7112
1
2
1W
0.5%
RL1632W
MF
CRITICAL
0.02
R7120
1
2
3
4
RJK03P0DPA
WPAK
CRITICAL
Q7130
2
1
6
7
34 5
DIRECTFET-MC
IRF9395TRPBF
CRITICAL
Q7180
8
7
910
6
3
4
1
5
2
PBus Supply & Battery Charger
SYNC_DATE=08/12/2013SYNC_MASTER=J44
VOLTAGE=5.1V
PP5V1_CHGR_VDDP
MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.2 mm
CHGR_CSI_R_N
P5V1_VIN
MIN_NECK_WIDTH=0.25 mm
MIN_LINE_WIDTH=0.5 mm
MIN_LINE_WIDTH=0.5 mm
CHGR_DCIN_D_R
MIN_NECK_WIDTH=0.25 mm
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm
P5V1_BIAS
CHGR_PHASE
MIN_NECK_WIDTH=0.2 mm
SWITCH_NODE=TRUE
DIDT=TRUE
MIN_LINE_WIDTH=0.6 mm
CHGR_ICOMP
CHGR_VCOMP
CHGR_VNEG
CHGR_CSO_P
CHGR_VCOMP_R
CHGR_DCIN
CHGR_CSO_N
MIN_NECK_WIDTH=0.2 mm
MIN_LINE_WIDTH=0.2 mm
VOLTAGE=0V
GND_CHGR_AGND
PPVBAT_G3H_CHGR_R
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=12.6V
MIN_LINE_WIDTH=0.6 mm
CHGR_BGATE
PPBUS_G3H
MIN_NECK_WIDTH=0.2 mm
PPVBAT_G3H_CHGR_REG
VOLTAGE=12.6V
MIN_LINE_WIDTH=0.6 mm
CHGR_CSI_N
CHGR_AGATE
CHGR_UGATE
MIN_NECK_WIDTH=0.2 mm
MIN_LINE_WIDTH=0.6 mm
GATE_NODE=TRUE
DIDT=TRUE
DIDT=TRUE
SWITCH_NODE=TRUECHGR_BOOT
MIN_NECK_WIDTH=0.2 mm
MIN_LINE_WIDTH=0.2 mm
PP3V42_G3H
PP5V1_CHGR_VDD
VOLTAGE=5.1V
MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.2 mm MIN_NECK_WIDTH=0.2 mm
MIN_LINE_WIDTH=0.6 mm
VOLTAGE=18.5V
PPDCIN_G3H_CHGR
CHGR_SGATE
CHGR_CELL
PPDCIN_G3H_ISOL
MIN_NECK_WIDTH=0.2 mm
CHGR_LGATE MIN_LINE_WIDTH=0.6 mm
GATE_NODE=TRUE
DIDT=TRUE
DIDT=TRUE
SWITCH_NODE=TRUE
P5V1_BOOST
NO_TEST=TRUE
P5V1_SW
MIN_NECK_WIDTH=0.25 mm
MIN_LINE_WIDTH=0.5 mm
DIDT=TRUE
SWITCH_NODE=TRUE
MIN_NECK_WIDTH=0.3 mm
MIN_LINE_WIDTH=0.3 mm
CHGR_AGATE_DIV
CHGR_BOOT_R
MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.2 mm
SWITCH_NODE=TRUE
DIDT=TRUE
MIN_NECK_WIDTH=0.2 mm
MIN_LINE_WIDTH=0.6 mm
VOLTAGE=12.6V
PPVBAT_G3H_CONN
GND_CHGR_AGND
CHGR_CSI_R_P
PP5V1_CHGR_VDDP
SMC_RESET_L
CHGR_ICOMP_RC
CHGR_DCIN
CHGR_VNEG_R
SMBUS_SMC_5_G3_SCL
CHGR_AMON
SMBUS_SMC_5_G3_SDA
CHGR_VFRQ
CHGR_RST_L
CHGR_DCIN_D_R
P5V1_FB
CHGR_ACIN
SMC_BC_ACOK
CHGR_BMON
CHGR_CSI_P
CHGR_SGATE_DIV
MIN_NECK_WIDTH=0.3 mm
MIN_LINE_WIDTH=0.3 mm
PPDCIN_G3H
VOLTAGE=18.5V
MIN_NECK_WIDTH=0.1 mm
MIN_LINE_WIDTH=0.1 mm
PPDCIN_G3H_INRUSH
CHGR_CSO_R_P
CHGR_CSO_R_N
<BRANCH>
<SCH_NUM>
<E4LABEL>
71 OF 120
52 OF 78
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52
77
52
77
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25 40 51 58 65 68
77
17 30 33 34 36 37 38 39 45 51
61 65 68
40 51 65
51 68
52
77
52
52
52
77
51 65 68
42 77
42 77 www.rosefix.com

BI
IN
OUT
IN
OUT
ISEN3
ISEN2
ISEN1
IMON
ISUMN
ISUMP
FB2
FB
RTN
COMP
SCLK
ALERT*
SDA
NTC
VINVDD
FCCM
PWM1
PWM2
PWM3
DRSEL
PGOOD
THRM
VR_ON
PROG3
NC
NC
NC
NC
PROG2
SLOPE
VR_HOT*
PROG1
PAD
OUT
OUT
NC
NC
OUT
OUT
IN
IN
IN
OUT
IN
IN
IN
NC
NC
NC
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
87 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
D
SIZEDRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
DESCRIPTION REFERENCE DES BOM OPTIONQTYPART NUMBER CRITICAL
(CPUVR_ISUMP)
FCCM = 1: Forced CCM
FCCM = FLOATING: PS4
(GND)
FCCM = 0: DCM
8 70
8 70
8 70
8 17
6 36 37 70
201
1/20W
MF
1%
54.9
PLACE_NEAR=U7200.32:2mm
R7279
1
2
201
1/20W
MF
1%
130
PLACE_NEAR=U7200.30:2mm
R7280
1
2
CRITICAL
ISL95826
LLP
OMIT_TABLE
U7200
31
6
25
7
8
18
3
12
11
10
14
15
9
19
21
24
5
2
28
27
26 20
22
23
13
32
30
29
33
16
17
4
1
8 17
54
54
54
5%
0
0201
1/20W
MF
R7224
12
5%
1/16W
MF-LF
10
402
R7202
12
0402
PLACE_NEAR=U7200.17:2mm
0.22UF
X7R
10%
25V
C7202
1
2
5%
1/16W
MF-LF
1
402
R7201
12
10%
PLACE_NEAR=U7200.16:2mm
402-1
1UF
10V
X5R
C7201
1
2
54
54
10V
X7R-CERM
0201
0.01UF
10%
C7210
1
2
0.01UF
X7R-CERM
0201
10V
10%
C7211
1
2
54
CERM-X5R
0201
6.3V
0.1UF
10%
C7213
1
2
201
1/20W
MF
1%
6.04K
R7220
1
2
201
1/20W
MF
34K
1%
R7221
1
2
42
1/20W
MF
1%
201
95.3K
R7230
1
2
0201
1500PF
10%
X7R
10V
C7230
1
2
54
201
X7R-CERM
NO_XNET_CONNECTION=TRUE
220PF
10%
25V
C7214
1
2
201
1/20W MF
1%
845
R7215
12
X7R-CERM
020110%
25V
820PF
C7215
12
25V
5%
NP0-C0G
22PF
201
C7216
12
8 70
9 70
0201
X7R-CERM
330PF
16V
10%
C7260
1
2
X7R-CERM
330PF
16V
0201
10%
C7261
1
2
CERM
10V
0201-1
1.2NF
+/-10%
C7240
1
2
5%
NO_XNET_CONNECTION=TRUE
NP0-CERM
0201
100PF
25V
C7242
12
25V
5%
NP0-C0G
39PF
NO_XNET_CONNECTION=TRUE
201
C7241
1
2
201
1/20W
MF
1%
75K
NO_XNET_CONNECTION=TRUE
R7240
1
2
201
1/20W
MF
1K
1%
R7242
12
5%
0
0201
1/20W
MF
NO_XNET_CONNECTION=TRUE
R7243
12
1%
MF
1/20W
201
7.5K
R7235
12
201
1/20W
MF
95.3K
1%
PLACE_NEAR=L7310.1:3MM
R7236
1
2
0201
100KOHM
PLACE_NEAR=Q7310.3:3MM
R7237
1
2
201
1/20W
MF
2K
1%
NOSTUFF
NO_XNET_CONNECTION=TRUE
R7250
12
330PF
16V
X7R-CERM
0201
NOSTUFF
10%
C7250
1
2
201
1/20W
MF
1%
1.69K
R7241
12
201
1/20W
MF
316
1%
R7210
12
201
1/20W
MF
1%
16.9K
R7223
1
2
201
1/20W
MF
1%
9.31K
R7222
1
2
NO_XNET_CONNECTION=TRUE
SM
XW7261
12
5%
0
0201
1/20W
MF
NOSTUFF
R7225
1
2
CERM-X5R
0201
10%
0.1UF
6.3V
PLACE_NEAR=R7279.1:3mm
C7278
1
2
1 CRITICALU7200353S4170 IC,ISL95826R6200,PWM,PGOOD,SCREN,32P,QFN
CPU VR12.6 VCC Regulator IC
SYNC_DATE=08/12/2013SYNC_MASTER=J44
PP5V_S0_CPUVR_VDD
MIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=5V
PP1V05_S0
CPUVR_FB_RC
CPUVR_SLOPE
CPUVR_PROG1
CPUVR_PWM1
CPU_VCCSENSE_P_RC
CPU_VCCSENSE_N
CPU_VCCSENSE_P
CPUVR_PWM2
CPU_VR_READY
PPBUS_S5_HS_COMPUTINGPP5V_S0
CPUVR_COMP_RC
CPU_VCCSENSE_P_R
CPUVR_FCCMCPU_PROCHOT_L
CPUVR_ISUMN_RC
CPUVR_NTC_R
CPUVR_PROG2
CPUVR_ISUMN
CPUVR_NTC
VOLTAGE=12.9V
MIN_NECK_WIDTH=0.2 mm
MIN_LINE_WIDTH=0.3 mm
PPVIN_S0_CPUVR_VIN
CPU_RTN
CPU_VIDSOUT
CPU_VR_EN
CPUVR_PROG3
CPUVR_DRSEL
CPUVR_IMON
CPUVR_ISEN1
CPUVR_ISUMN_R
CPUVR_ISEN2
CPUVR_ISUMP
CPUVR_FB2
CPUVR_COMP
CPU_VIDSCLK
CPU_VIDALERT_L
CPUVR_FB
<BRANCH>
<SCH_NUM>
<E4LABEL>
72 OF 120
53 OF 78
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IN
IN
OUT
OUT
OUT
OUT
IN
OUT
OUT
IN
G
D
S
G
D
S
G
D
S
G
D
S
OUT
OUT
OUTOUT
THRM
PAD
PHASE
VCC
LGATE
BOOT
UGATEFCCM
GND
PWM
THRM
PAD
PHASE
VCC
LGATE
BOOT
UGATEFCCM
GND
PWM
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
87 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
D
SIZEDRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
PHASE 1
353S3942
353S3942
.
Vout = 1.85V max
40A MAX OUTPUT
F = 800KHZ
PHASE 2
THESE TWO CAPS ARE FOR EMC
THESE TWO CAPS ARE FOR EMC
152S1821
152S1821
Additonal Input Bulk Caps
Note: C7377, C7379, C7381 were removed. Area
where the pads used to reside was preserved.
CASE-D2E-SM
POLY-TANT
CRITICAL
16V
20%
68UF
C7372
1
2
NOSTUFF
CASED12-SM
POLY-TANT
CRITICAL
16V
20%
33UF
C7371
1
2
POLY-TANT
CASED12-SM
CRITICAL
16V
20%
33UF
C7370
1
2
50V
10%
0402
X7R-CERM
0.001UF
C7319
1
2
50V
10%
0402
X7R-CERM
0.001UF
C7318
1
2
35V
10%
0402
CERM-X6S
1.0UF
C7317
1
2
NOSTUFF
CRITICAL
16V
20%
0603
X6S-CERM
10UF
C7316
1
2
NOSTUFF
CRITICAL
16V
20%
0603
X6S-CERM
10UF
C7315
1
2
1/20W
1%
0201
MF-LF
1.00
R7314
1
2
CRITICAL
16V
20%
CASE-D2E-SM
POLY-TANT
68UF
C7314
1
2
CRITICAL
16V
20%
CASE-D2E-SM
POLY-TANT
68UF
C7313
1
2
CRITICAL
PILE063T-SM
0.4UH-20%-23A
L7310
12
1/10W
5%
603
MF-LF
2.2
NOSTUFF
R7312
1
2
NOSTUFF
50V
10%
0402
X7R-CERM
0.001UF
C7312
1
2
53
53 54
CASE-D2E-SM
POLY-TANT
CRITICAL
16V
20%
68UF
C7373
1
2
NO_XNET_CONNECTION=TRUE
1/20W
1%
201
MF
200K
R7316
1
2
1/20W
1%
201
MF
1K
R7315
1
2
53
53 54
53 54
NO_XNET_CONNECTION=TRUE
OMIT
NONE
NONE
0201
NOSTUFF
NONE
R7317
12
50V
10%
0402
X7R-CERM
0.001UF
C7329
1
2
53 54
50V
10%
0402
X7R-CERM
0.001UF
C7328
1
2
35V
10%
0402
CERM-X6S
1.0UF
C7327
1
2
1/20W
1%
0201
MF-LF
1.00
R7324
1
2
NOSTUFF
CRITICAL
16V
20%
0603
X6S-CERM
10UF
C7326
1
2
NOSTUFF
CRITICAL
16V
20%
0603
X6S-CERM
10UF
C7325
1
2
CRITICAL
16V
20%
CASE-D2E-SM
POLY-TANT
68UF
C7324
1
2
CRITICAL
16V
20%
CASE-D2E-SM
POLY-TANT
68UF
C7323
1
2
CRITICAL
PILE063T-SM
0.4UH-20%-23A
L7320
12
NOSTUFF
50V
10%
0402
X7R-CERM
0.001UF
C7322
1
2 NO_XNET_CONNECTION=TRUE
1/20W
1%
201
MF
200K
R7326
1
2
1/20W
1%
201
MF
1K
R7325
1
2
NOSTUFF
1/10W
5%
603
MF-LF
2.2
R7322
1
2
53
OMIT
NO_XNET_CONNECTION=TRUE
NONE
NONE
0201
NONE
NOSTUFF
R7327
12
53
53 54
1/16W
5%
402
MF-LF
2.2
R7311
21
16V
10%
402
CERM
0.22UF
C7311
12
16V
10%
0402
X6S-CERM
1UF
C7310
1
2
16V
10%
0402
X6S-CERM
1UF
C7320
1
2
53 54
CASED12-SM
POLY-TANT
CRITICAL
16V
20%
33UF
C7376
1
2
CASE-D2E-SM
POLY-TANT
CRITICAL
16V
20%
68UF
C7375
1
2
CASE-D2E-SM
POLY-TANT
CRITICAL
16V
20%
68UF
C7374
1
2
1/16W
5%
402
MF-LF
2.2
R7321
12
16V
10%
402
CERM
0.22UF
C7321
12
OMIT_TABLE
CRITICAL
PWRPAK-SM
SISA18DN
Q7310
5
4
123
OMIT_TABLE
CRITICAL
PWRPAK-SM
SISA18DN
Q7320
5
4
123
CRITICAL
1W
1%
0612
MF
0.00075
R7310
12
34
CRITICAL
1W
1%
0612
MF
0.00075
R7320
12
34
OMIT_TABLE
CRITICAL
PWRPAK-SM
SISA12DN
Q7311
5
4
123
OMIT_TABLE
CRITICAL
PWRPAK-SM
SISA12DN
Q7321
5
4
123
41 54 77 41 77
41 54 77 41 77
CRITICAL
DFN
ISL6208D
U7310
2
7
4
5
8
3
9
1
6
DFN
ISL6208D
CRITICAL
U7320
2
7
4
5
8
3
9
1
6
POLY-TANT
CASED12-SM
16V
20%
33UF
CRITICAL
C7380
1
2
CASED12-SM
CRITICAL
16V
20%
POLY-TANT
33UF
C7378
1
2
SYNC_MASTER=J44 SYNC_DATE=08/12/2013
CPU VR12.5 VCC Power Stage
PPBUS_S5_HS_COMPUTING
PPVCC_S0_CPU
CPUVR_ISNS1_P
CPUVR_ISNS2_P
CPUVR_ISUMN
CPUVR_ISNS2_N
CPUVR_ISNS1_N
PP5V_S0
CPUVR_BOOT1
MIN_LINE_WIDTH=0.25 MM
DIDT=TRUE
MIN_NECK_WIDTH=0.2 MM
GATE_NODE=TRUE
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
DIDT=TRUE
CPUVR_UGATE1
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
DIDT=TRUE
SWITCH_NODE=TRUE
CPUVR_PHASE1
GATE_NODE=TRUE
DIDT=TRUE
MIN_NECK_WIDTH=0.2 MM
MIN_LINE_WIDTH=0.6 MM
CPUVR_LGATE1
CPUVR_ISUMP
CPUVR_ISEN1
CPUVR_ISUMP
VOLTAGE=1.8V
MIN_NECK_WIDTH=0.25 MM
MIN_LINE_WIDTH=0.6 MM
PPVCC_S0_CPU_PH2
DIDT=TRUE
CPUVR_PH2_SNUB
CPUVR_ISUMN
CPUVR_PH1_SNUB
DIDT=TRUE
VOLTAGE=1.8V
MIN_NECK_WIDTH=0.25 MM
MIN_LINE_WIDTH=0.6 MM
PPVCC_S0_CPU_PH1
CPUVR_ISNS2_N
CPUVR_BOOT2_RC
MIN_LINE_WIDTH=0.25 MM
DIDT=TRUE
MIN_NECK_WIDTH=0.2 MM
CPUVR_ISNS1_N
CPUVR_PWM1
CPUVR_FCCM
CPUVR_FCCM
CPUVR_PWM2
CPUVR_ISEN2
PP5V_S0
CPUVR_BOOT2
DIDT=TRUE
MIN_NECK_WIDTH=0.2 MM
MIN_LINE_WIDTH=0.25 MM
GATE_NODE=TRUE
DIDT=TRUE
MIN_NECK_WIDTH=0.2 MM
MIN_LINE_WIDTH=0.6 MM
CPUVR_UGATE2
GATE_NODE=TRUE
DIDT=TRUE
MIN_NECK_WIDTH=0.2 MM
MIN_LINE_WIDTH=0.6 MM
CPUVR_LGATE2
SWITCH_NODE=TRUE
DIDT=TRUE
MIN_NECK_WIDTH=0.2 MM
MIN_LINE_WIDTH=0.6 MM
CPUVR_PHASE2
CPUVR_BOOT1_RC
DIDT=TRUE
MIN_NECK_WIDTH=0.2 MM
MIN_LINE_WIDTH=0.25 MM
<BRANCH>
<SCH_NUM>
<E4LABEL>
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61 65 68
41 54 77
41 54 77
16 17 32 41 44 45 53 54 58 60
61 65 68 www.rosefix.com

OUT
OUT
IN
D
GS
IN
V5IN
REFIN
S5
VREF
S3
MODE
TRIP
SW
DRVL
PGOOD
VDDQSNS
VTT
VTTSNS
VTTREF
DRVH
VBST
VLDOIN
THRMVTT
GND
PGND
PADGND
OUT
IN
IN
PHASE
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
87 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
D
SIZEDRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
DESCRIPTION REFERENCE DES BOM OPTIONQTYPART NUMBER CRITICAL
(DDRREG_LL)
(DDRREG_DRVL)
(DDRREG_VDDQSNS)
10mA max load
VDDQ/VTTREF Enable
C7460, C7461 close to memory
VTT Enable
DDR3L (1V35 S3) REGULATOR
152S1822
VOUT = 1.35V
f = 400 kHz
9A MAX OUTPUT
(DDRREG_DRVH)
PIME063T-SM
CRITICAL
1.0UH-20%-15A-0.0066OHM
L7430
12
41 77
41 77
OMIT_TABLE
MF-LF
1/16W
1%
150K
402
R7419
1
2
15
OMIT_TABLE
SOD-VESM-HF
SSM3K15FV
CRITICAL
Q7419
3
1
2
100K
PLACE_NEAR=U7400.8:5mm
1%
1/16W
MF-LF
OMIT_TABLE
402
R7416
1
2
SM
XW7450
12
PLACE_NEAR=U7400.12:1MM
10V
20%
0402-1
X5R-CERM
10UF
CRITICAL
C7400
1
2
PLACE_NEAR=Q7430.5:3mm
1.0UF
0402
CERM-X6S
35V
10%
C7432
1
2
10%
X5R
0.1UF
25V
402
C7425
12
PLACE_NEAR=C7435.1:3MM
0.001UF
50V
CERM
0402
20%
C7433
1
2
10UF
X5R-CERM
0603
20%
25V
C7445
1
2
50V
X7R-CERM
0.001UF
0402
10%
C7446
1
2
SM
PLACE_NEAR=C7442.1:2MM
XW7401
1
2
61
QFN
CRITICAL
TPS51916
U7400
14
11
7
19
10
20
8
17
16
13
21
18
12 15
9
2
6
3
4
5
1
61
SM
PLACE_NEAR=C7461.1:3mm
XW7460
12
PLACE_NEAR=U7400.21:1MM
SM
XW7400
1
2
10V
10%
CERM
0.22UF
402
C7450
1
2
20%
10UF
CRITICAL
X5R-CERM
0603
PLACE_NEAR=C7461.1:4mm
25V
C7460
1
2
17
PLACE_NEAR=U7400.6:1MM
0402
0.1UF
X7R-CERM
10%
16V
C7415
1
2
0603
20%
10UF
X5R-CERM
CRITICAL
PLACE_NEAR=C7460.1:4mm
25V
C7461
1
2
200K
PLACE_NEAR=U7400.19:3MM
1/16W
1%
MF-LF
402
R7417
1
2
0402
10%
0.01UF
X7R-CERM
16V
PLACE_NEAR=U7400.8:1MM
C7416
1
2
68UF
20%
POLY-TANT
CASE-D2E-SM
CRITICAL
16V
C7431
1
2
10UF
CRITICAL
PLACE_NEAR=U7400.2:1MM
10V
20%
0402-1
X5R-CERM
C7401
1
2
1/16W0
MF-LF402
5%
R7425
12
1/16W
51.1K
PLACE_NEAR=U7400.18:3MM
1%
MF-LF
402
R7418
1
2
CASE-D2E-SM
CRITICAL
68UF
POLY-TANT
20%
16V
C7434
1
2
19
CRITICAL
20%
CASE-B2-SM1
POLY-TANT
2.0V
330UF
C7440
1
2
CRITICAL
330UF
POLY-TANT
CASE-B2-SM1
20%
2.0V
C7441
1
2
FDMS3602S
CRITICAL
POWER56
Q7430
2
1
6
7
345
2.0V
20%
CASE-B2-SM1
POLY-TANT
CRITICAL
330UF
C7442
1
2
PLACE_NEAR=Q7430.5:3MM
1.0UF
PLACE_NEAR=Q7430.2:1MM
CERM-X6S
0402
10%
35V
C7435
1
2
201
1/20W
MF
10
5%
R7401
12
PLACE_NEAR=U7400.8:5MM
19.6K
1/16W
1%
MF-LF
402
R7415
1
2
R7416RES,MTL FILM,1/16W,60.4K,1,0402,SMD,LF114S0391 1 CRITICAL PPDDR:1V35
R7416RES,MTL FILM,1/16W,100K,1,0402,SMD,LF CRITICAL PPDDR:1V51114S0411
R7419114S0428 RES, MTL FILM,1/16W,150k,0402,SMD,LF CRITICAL1 PPDDR:1V5
Q7419MOSFET,N-CH,30V,100MA,7.0OHM,SOT-723,HF376S0612 1 CRITICAL PPDDR:1V5
SYNC_DATE=08/12/2013SYNC_MASTER=J44
1.35V DDR3 SUPPLY
DIDT=TRUE
MIN_NECK_WIDTH=0.17 mm
MIN_LINE_WIDTH=0.6 mm
DDRREG_LL
SWITCH_NODE=TRUE
NC_ISNS_DDR_S3N
MIN_NECK_WIDTH=0.1 MM
PPDDR_S3_REG_R
MIN_LINE_WIDTH=0.8 MM
VOLTAGE=1.35V PP1V35_S3
PPBUS_S5_HS_COMPUTING
DIDT=TRUE
DDRREG_DRVH
GATE_NODE=TRUE
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.17 mm
PP0V675_S0_DDRVTT
DDRREG_VTTSNS
NC_ISNS_DDR_S3P
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.17 mm
GATE_NODE=TRUE
DDRREG_DRVL
DIDT=TRUE
DDRREG_VBST_RC
SWITCH_NODE=TRUE
DIDT=TRUE
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.17 mm
DDRREG_VDDQSNS_R
MIN_NECK_WIDTH=0.17 mm
MIN_LINE_WIDTH=0.2 mm
DDRREG_PGOOD
DDRREG_TRIP
PPVTTDDR_S3
PP5V_S4
PP1V35_S3
DDRREG_P1V35_L
DDRREG_MODE
MEMVTT_PWR_EN
DDRREG_EN
DDRREG_1V8_VREF
MEM_VDD_SEL_1V5_L
DDRREG_FB
MIN_NECK_WIDTH=0.17 mm
MIN_LINE_WIDTH=0.6 mm
VOLTAGE=0V
GND_DDRREG_SGND
SWITCH_NODE=TRUE
DIDT=TRUE
DDRREG_VBST
MIN_NECK_WIDTH=0.17 mm
MIN_LINE_WIDTH=0.6 mm
NO_TEST=TRUE
DDRREG_VDDQSNS
MIN_NECK_WIDTH=0.17 mm
MIN_LINE_WIDTH=0.2 mm
<BRANCH>
<SCH_NUM>
<E4LABEL>
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65
68
73
32 33 46 56 57 60 62 63 65 66
68
17 19 20 21 22 41 55 65 73 www.rosefix.com

OUT
IN
EN
EN2EN1
DRVL2
SKIPSEL1
SKIPSEL2
DRVL1
V5SW
VBST2VBST1
VREG5
VREF2
VIN
THRM_PAD
SW2SW1
RF
PGOOD2PGOOD1
GND
DRVH2DRVH1
CSP2
CSN2CSN1
COMP2COMP1
VREG3
VFB1 VFB2
OCSEL
MODE
CSP1
IN
IN
OUT
VSW
PGND
TGR
TG
BG
VIN
PHASE
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
87 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
D
SIZEDRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
VOUT = 5V
(P5VP3V3_VREF2)
376S0958
152S0754152S0688
100MA MAX OUTPUT
VOUT = 3.3V
(P5VP3V3_VREF2)
F = 600 KHZ
10.5A MAX OUTPUT
VOUT = 5.0V
F = 600 KHZ
10.8A MAX OUTPUT
25V
10%
603-1
X5R
1UF
C7500
1
2
CRITICAL
1.0UH-22A
PCMC063T-SM
L7560
1 2
50V
10%
603-1
X7R
0.1UF
C7564
1
2
25V
0603
10UF
20%
X5R-CERM
CRITICAL
C7590
1
2
50V
10%
603-1
X7R
0.1UF
C7524
1
2
CASE-D3L-SM
6.3V
20%
POLY-TANT
330UF
CRITICAL
C7552
1
2
25V
CRITICAL
20%
0603
X5R-CERM
10UF
C7550
1
2
25V
10%
4.7UF
X6S-CERM
0603
C7581
1
2
402
10V
20%
X5R-CERM
2.2UF
C7503
1
2
CRITICAL
6.3V
20%
603
X5R
10UF
C7505
1
2
165K
1/16W
1%
MF-LF
402
R7506
1
2
61
SM
PLACE_NEAR=L7560.1:3MM
XW7561
1
2
402
10%
0.22UF
10V
CERM
C7501
1
2
1/16W
23.2K
MF-LF
0402
0.5%
R7560
1
2
MF
402
10.0K
0.5%
1/16W
R7561
1
2
1%
41.2K
402
1/16W
MF-LF
R7520
1
2
MF
402
10.0K
0.5%
1/16W
R7521
1
2
CASE-D2E-SM
16V
20%
POLY-TANT
68UF
CRITICAL
C7580
1
2
CRITICAL
16V
20%
CASE-D2E-SM
POLY-TANT
68UF
C7540
1
2
0402
0.1UF
16V
10%
X7R-CERM
C7588
12
PLACE_NEAR=L7560.2:3MM
SM
XW7560
1
2
16V
10%
0402
X7R-CERM
0.1UF
C7518
12
2.49K
MF-LF
1%
1/16W
402
R7547
12
402
3.01K
1/16W
1%
MF-LF
R7556
1
2
PLACE_NEAR=L7520.1:3MM
SM
XW7520
1
2
PLACE_NEAR=L7520.2:3MM
SM
XW7521
1
2 402
1%
12.1K
1/16W
MF-LF
R7536
1
2
402
10K
1/16W
1%
MF-LF
R7537
1
2
402
4700PF
100V
10%
CERM
C7536
1
2
5%
402
50V
CERM
150PF
C7537
1
2
SM
PLACE_NEAR=C7592.1:3MM
XW7562
1
2
SM
PLACE_NEAR=C7553.1:3MM
XW7522
1
2
CASE-D3L-SM
POLY-TANT
6.3V
20%
330UF
CRITICAL
C7592
1
2
402
1/16W
1%
MF-LF
10K
R7539
1
2
5%
402
50V
CERM
47PF
C7539
1
2
402
1/16W
1%
MF-LF
12.1K
R7538
1
2
402
4700PF
100V
10%
CERM
C7538
1
2
61
402
0.0033UF
10%
50V
CERM
NO STUFF
C7599
1
2
5%
1/10W
603
MF-LF
1
NO STUFF
R7599
1
2
5%
1/10W
10
NO STUFF
603
MF-LF
R7598
1
2
50V
10%
0402
X7R-CERM
0.001UF
C7572
1
2
50V
20%
0402
CERM
0.001UF
C7583
1
2
0402
20%
CERM
50V
0.001UF
C7570
1
2
50V
10%
0402
X7R-CERM
0.001UF
C7571
1
2
TPS51980
QFN
CRITICAL
U7501
10 15
8 17
7 18
1 24
30 27
12
4 21
28
11
14
5 20
3
6
19
32 25
33
2
31 26
9 16
23
13
22
29
CRITICAL
POLY-TANT
CASE-D2E-SM
16V
20%
68UF
C7542
1
2
36 37 61
MF-LF
1%
1/16W
402
1.82K
R7546
12
5.23K
1/16W
1%
402
MF-LF
R7516
1
2
5%
0
402
1/16W
MF-LF
R7563
12
5%
402
MF-LF
1/16W
1
R7544
1
2
25V
4.7UF
X6S-CERM
10%
0603
C7541
1
2
61
36 61
NO STUFF
0402
X7R-CERM
10%
50V
0.001UF
C7598
1
2
CRITICAL
1.0UH-21A-0.006OHM
PCMB103T-1R0MS
L7520
1
2
PLACE_NEAR=U7501.28:1MM
SM
XW7500
1
2
SON5X6
CSD58872Q5D
CRITICAL
Q7520
5
9
3
4
1
6
7
8
6.3V
20%
CASE-D3L-SM
POLY-TANT
330UF
CRITICAL
C7553
1
2
16V
20%
CASE-D2E-SM
POLY-TANT
CRITICAL
68UF
C7582
1
2
5%
0
0201
1/20W
MF
SKIP_5V3V3:AUDIBLE
R7500
1
2
5%
0
0201
1/20W
MF
SKIP_5V3V3:INAUDIBLE
R7501
1
2
POWER56
CRITICAL
FDMS3602S
Q7560
2
1
6
7
345
POLY-TANT
CRITICAL
16V
20%
CASE-D2E-SM
68UF
C7543
1
2
16V
20%
CASE-D2E-SM
POLY-TANT
68UF
CRITICAL
C7584
1
2
5%
402
MF-LF
10
1/16W
R7562
1
2
5%
402
10
1/16W
MF-LF
R7522
1
2
5V / 3.3V Power Supply
SYNC_MASTER=J44 SYNC_DATE=08/12/2013
P5VP3V3_VREG3
PP5V_S4
P5VP3V3_SKIPSEL
PPBUS_S5_HS_OTHER5V
SMC_PM_G2_EN
S5_PWRGD
P5VS4_COMP1
P5VS4RS3_EN
SWITCH_NODE=TRUE
MIN_NECK_WIDTH=0.2 MM
MIN_LINE_WIDTH=0.6 MM
P5VS4_SNUBR
DIDT=TRUE
DIDT=TRUE
GATE_NODE=TRUE
MIN_NECK_WIDTH=0.2 MM
MIN_LINE_WIDTH=0.6 MM
P5VS4_TG
DIDT=TRUE
P5VS4_DRVH
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM GATE_NODE=TRUE
MIN_NECK_WIDTH=0.2 MM
MIN_LINE_WIDTH=0.6 MM
P5VS4_DRVL
DIDT=TRUEGATE_NODE=TRUE
MIN_NECK_WIDTH=0.2 MM
GATE_NODE=TRUE
MIN_LINE_WIDTH=0.6 MM
DIDT=TRUE
P3V3S5_TG
P5VS4_CSP1_R
DIDT=TRUE
MIN_NECK_WIDTH=0.2 MM
MIN_LINE_WIDTH=0.6 MM
P3V3S5_DRVH
GATE_NODE=TRUEDIDT=TRUE
PPBUS_S5_HS_OTHER3V3
PP5V_S5
MIN_NECK_WIDTH=0.2 MM
MIN_LINE_WIDTH=0.6 MM
SWITCH_NODE=TRUE
P3V3S5_VBST
DIDT=TRUE
S5_PWR_EN
P3V3S5_COMP2_R
PP3V3_S5
MIN_NECK_WIDTH=0.2 MM
MIN_LINE_WIDTH=0.6 MM
P3V3S5_LL
DIDT=TRUE SWITCH_NODE=TRUE
MIN_NECK_WIDTH=0.2 MM
P3V3S5_SNUBR
MIN_LINE_WIDTH=0.6 MM
DIDT=TRUE
SWITCH_NODE=TRUE
P3V3S5_COMP2
P3V3S5_VFB2_R
P3V3S5_CSP2_R
DIDT=TRUE
MIN_NECK_WIDTH=0.2 MM
DIDT=TRUE
MIN_LINE_WIDTH=0.6 MM
P5VS4_VSW
P5VS4_VFB1_R
P3V3S5_RF
DIDT=TRUESWITCH_NODE=TRUE
MIN_NECK_WIDTH=0.2 MM
MIN_LINE_WIDTH=0.6 MM
P5VS4_LL
P5VS4_COMP1_R
P5VS4RS3_PGOOD
P3V3S5_VFB2
P3V3S5_VFB2_RR
P5VP3V3_VREF2
PP5V_S4
5VS4_VFB1_RR
P3V3S5_CSN2
P3V3S5_CSP2
MIN_LINE_WIDTH=0.6 MMGATE_NODE=TRUE
P3V3S5_DRVL
DIDT=TRUE
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=0V
MIN_NECK_WIDTH=0.2 MM
MIN_LINE_WIDTH=0.2 MM
GND_5V3V3_AGND
P5VS4_VFB1
P5VS4_CSN1
P5VS4_CSP1
MIN_NECK_WIDTH=0.2 MM
MIN_LINE_WIDTH=0.6 MM
SWITCH_NODE=TRUE
P5VS4_VBST
DIDT=TRUE
75 OF 120
<E4LABEL>
<SCH_NUM>
56 OF 78
<BRANCH>
32 33 46 55 56 57 60 62 63 65
66 68
40 65
40 65
34 65 68
8 11 13 15 16
17 18 26 27 29
59 60 61 65 68
77
32 33 46 55 56 57
60 62 63 65 66 68 www.rosefix.com

GND
GND
GND
HSG
V+
V+
LSG
SW
V5IN
REFIN
S5
VREF
S3
MODE
TRIP
SW
DRVL
PGOOD
VDDQSNS
VTT
VTTSNS
VTTREF
DRVH
VBST
VLDOIN
THRMVTT
GND
PGND
PADGND
OUT
OUT
OUT
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
87 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
D
SIZEDRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
Scrub S3 & S5 pins connections!
1.05V S0 Regulator
Vout = 1.05V
F = 400 KHZ
5A MAX OUTPUT
Short Rsense
0402
10%
16V
X7R-CERM
0.1UF
C7630
1
2
5%
1000PF
25V
0402
CERM
PLACE_NEAR=L7630.2:1.5mm
C7623
1
2
5%
25V
0402
CERM
PLACE_NEAR=Q7630.8:1.5mm
1000PF
C7622
1
2
5%
603
2.2
MF-LF
1/10W
R7630
1
2
5%
402
MF-LF
1/16W
0
R7631
12
POLY-TANT
CASE-B2-SM1
20%
CRITICAL
330UF
2.0V
C7648
1
2
CASE-B2-SM1
330UF
POLY-TANT
2.0V
20%
CRITICAL
C7649
1
2
CRITICAL
FDSD0630-SM
1.0UH-20%-11A-0.011OHM
L7630
12
16V
20%
CASE-D2E-SM
68UF
POLY-TANT
C7619
1
2
FDPC1012S
CRITICAL
LLP
Q7630
5
6
10
1
7
2
3
4
8
9
1.0UF
0402
CERM-X6S
35V
10%
C7624
1
2
NOSTUFF
0402
10%
0.001UF
X7R-CERM
50V
C7632
1
2
5%
MF-LF
603
2.2
1/10W
NOSTUFF
R7632
1
2
402
CERM
0.22UF
10V
10%
C7650
1
2
SM
PLACE_NEAR=U7600.21:1mm
XW7600
1
2
10UF
10V
BYPASS=U7600.2:1mm
603
X5R
20%
C7601
1
2
TPS51916
QFN
CRITICAL
U7600
14
11
7
19
10
20
8
17
16
13
21
18
12 15
9
2
6
3
4
5
1
PLACE_NEAR=U7600.18:3mm
1%
MF
201
14.7K
1/20W
R7614
1
2
10UF
BYPASS=U7600.12:1mm
X5R
603
10V
20%
C7600
1
2
PLACE_NEAR=U7600.19:3mm
1/20W
201
47.5K
1%
MF
R7613
1
2
BYPASS=U7600.8:1mm
0402
0.01UF
X7R-CERM
10%
16V
C7616
1
2
PLACE_NEAR=U7600.8:5mm
35.7K
1/20W
1%
201
MF
R7611
1
2
PLACE_NEAR=U7600.8:5mm
1/20W
201
49.9K
1%
MF
R7612
1
2
BYPASS=U7600.6:1mm
10%
0.1UF
X7R-CERM
16V
0402
C7615
1
2
MF
1%
1/20W
1K
201
R7610
1
2
SM
PLACE_NEAR=C7648.1:1mm
XW7610
1
2
5%
MF
1/20W
10
201
R7641
12
41 77
41 77
61
OMIT
0612-SHORT
1w
1%
CYN
0.003
R7640
12
34
1.05V S0 Power Supply
SYNC_DATE=08/12/2013SYNC_MASTER=J44
ISNS_1V05_S0_N
ISNS_1V05_S0_P
PP1V05_S0
MIN_NECK_WIDTH=0.2 mm
PP1V05_S0_REG_R
MIN_LINE_WIDTH=0.6 mm
VOLTAGE=1.05V
MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.1 mm
P1V05_S0_VREF
PPBUS_S5_HS_COMPUTING
P1V05S0_BOOT_RC
DIDT=TRUE
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.2 mm
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
DIDT=TRUE
P1V05S0_DRVH_R
GATE_NODE=TRUE
DIDT=TRUE
P1V05S0_LL
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
SWITCH_NODE=TRUE
P1V05S0_LL_SNUB
DIDT=TRUE
PP1V05_S0
P1V05S0_DRVL
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
GATE_NODE=TRUE
DIDT=TRUE
VOLTAGE=0V
MIN_NECK_WIDTH=0.2 mm
MIN_LINE_WIDTH=0.6 mm
P1V05S0_AGND
P1V05S0_VTTREF
PP5V_S4
P1V05S3_EN
P1V05S0_TRIP
P1V05S0_PGOOD
P1V05S0_EN
P1V05S0_MODE
P1V05S0_VTT
MIN_NECK_WIDTH=0.17 mm
MIN_LINE_WIDTH=0.2 mm
P1V05S0_VDDQSNS_R
MIN_NECK_WIDTH=0.17 mm
MIN_LINE_WIDTH=0.2 mm
P1V05S0_VDDQSNS
MIN_LINE_WIDTH=0.6 mm
GATE_NODE=TRUE
MIN_NECK_WIDTH=0.2 mm
P1V05S0_DRVH
DIDT=TRUE
P1V05S0_VBST
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.2 mm
DIDT=TRUE
MIN_NECK_WIDTH=0.1 mm
MIN_LINE_WIDTH=0.2 mm
P1V05S0_FB
<BRANCH>
<SCH_NUM>
<E4LABEL>
76 OF 120
57 OF 78
6 8 11 15
16 17 37
53 57 60
61 65 68
40 53 54 55 65
6 8 11 15 16 17 37 53 57 60
61 65 68
32 33 46 55 56 60 62 63 65 66
68
61 www.rosefix.com

GND_SW
GND_SW
SW2
FB2
KEYB1
KEYB2
SDA
SCL
PWM_KEYB
EN
SENSE_OUT
FB
THRM
GNDA
GNDDGND_SW2
SD
VSENSE_N
VSENSE_P
SW
ISET_KEYB
GD
VDDA
VDDD
SW
PAD
IN
IN
IN
BI
OUT
OUT
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
87 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
D
SIZEDRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
DESCRIPTION REFERENCE DES BOM OPTIONQTYPART NUMBER CRITICAL
152S1701
LCD BKLT LINE WIDTHS
PLATFORM_RESET NO LONGER GATES THE BKLT_EN AS BOTH COME FROM PCH NOW
371S0704
PBUS LINE WIDTHS
PLACEMENT_NOTE:PLACEMENT_NOTE:
KBD BKLT LINE WIDTHS
PLACEMENT_NOTE:
POWER GOING TO LCD BACKLIGHT
Page Notes
BKLT:ENG - Stuffs 10.2 ohm series R for engineering builds
BOM options provided by this page:
- =PP5V_S0SW_KBDLED (5V KEYBOARD BACKLIGHT INPUT)
- =PP5V_S0_BKLT (5V BACKLIGHT DRIVER INPUT)
- =PPVIN_S0SW_LCDBKLTFET (9-12.6V LCD BACKLIGHT INPUT)
Power aliases required by this page:
152S1527
740S0159
SENSOR ON PAGE 54 USES R7700 TO MEASURE THE
I2C ID DEDICATED.ONLY CONNECTS TO JERRY
BKLT:PROD - Stuffs 0 ohm series R for production
371S0572
PLACEMENT_NOTE:
353S4160
(IPU)
(IPU)
LLP
CRITICAL
LP8548B1SQ_-04
U7700
17
21
8
4
7
23
24
22
3
20
13
14
12
15
11
16
19
6
1
2
25
18
5
9
10
CRITICAL
3AMP-32V
0603
F7700
12
PLACE_NEAR=Q7701.5:3MM
22UH-20%-2.4A-0.105OHM
CRITICAL
DEM8030C-SM
L7710
12
PST041H-SM
PLACE_NEAR=U7700.6:5MM
CRITICAL
10UH-20%-1.4A-0.17OHM
L7720
12
1%
MF-LF
402
80.6K
1/16W
R7701
1
2
X7R-CERM
16V
0201
10%
1000PF
C7700
1
2
402
MF-LF
1/16W
63.4K
1%
R7702
1
2
FDC638APZ_SBMS001
CRITICAL
SSOT6-HF
Q7700
1
2
5
6
3
4
CRITICAL
DFLS2100
POWERDI-123
PLACE_NEAR=L7710.2:3MM
D7710
AK
X7R-CERM
0603
100V
1000PF
10%
PLACE_NEAR=D7710.K:5MM
C7717
1
2
16V
X5R-CERM
0201
0.1UF
10%
PLACE_NEAR=L7720.1:5MM
C7722
1
2
SANDWICH C7720 AND C7721
X5R-CERM
603
2.2UF
PLACE_NEAR=L7720.1:5MM
25V
10%
C7721
1
2
X7R
PLACE_NEAR=D7710.K:5MM
2.2UF
100V
SANDWICH C7713 AND C7714
10%
1210-1
C7713
1
2
PLACE_NEAR=D7720.K:5MM
X7R-CERM
0.001UF
0402
10%
50V
C7725
1
2
5%
0
0201
1/20W
MF
R7747
12
0201
NPO-C0G
25V
5%
33PF
NO STUFF
C7747
1
2
5%
0
0201
1/20W
MF
PLACE_NEAR=U7700.15:10MM
R7750
12
5%
0
0201
1/20W
MF
PLACE_NEAR=U7700.16:10MM
R7751
12
MF
1/20W
5%
0
0201
R7742
12
PLACE_NEAR=U7700.5:5MM
10%
X5R
10V
402-1
1UF
C7740
1
2
1UF
X5R
10%
10V
402-1
PLACE_NEAR=U7700.18:5MM
C7741
1
2
2.4K
5%
201
1/20W
MF
R7752
1
2
2.4K
5%
1/20W
MF
201
R7753
1
2
MF
201
1/20W
1M
5%
R7740
1
2
SM
XW7700
12
0.1UF
25V
402
X5R
10%
PLACE_NEAR=L7710.1:5MM
C7712
1
2
62
36
62 66 68
62 66 68
CERM
NOSTUFF
50V
0.001UF
402
10%
C7701
1
2
X6S-CERM
0603
4.7UF
25V
10%
PLACE_NEAR=L7710.1:5MM
SANDWICH C7710 AND C7711
C7710
1
2
0603
4.7UF
SANDWICH C7710 AND C7711
X6S-CERM
25V
10%
PLACE_NEAR=L7710.1:5MM
C7711
1
2
SM
PLACE_NEAR=D7710.K:2MM
XW7710
1
2
1210-1
2.2UF
X7R
PLACE_NEAR=D7710.K:5MM
SANDWICH C7713 AND C7714
100V
10%
C7714
1
2
1210-1
2.2UF
X7R
PLACE_NEAR=D7710.K:5MM
SANDWICH C7715 AND C7716
100V
10%
C7715
1
2
1210-1
X7R
PLACE_NEAR=D7710.K:5MM
2.2UF
SANDWICH C7715 AND C7716
100V
10%
C7716
1
2
201
1/20W
MF
1%
31.6K
PLACE_NEAR=U7700.20:5MM
R7741
1
2
CRITICAL
SOD-123
RB160M-60G
PLACE_NEAR=L7720.2:5MM
D7720
AK
1.0UF
10%
PLACE_NEAR=D7720.K:5MM
X7R
0805
50V
SANDWICH C7723 AND C7724
C7723
1
2
PLACE_NEAR=D7720.K:5MM
SANDWICH C7723 AND C7724
10%
1.0UF
50V
0805
X7R
C7724
1
2
603
2.2UF
X5R-CERM
SANDWICH C7720 AND C7721
PLACE_NEAR=L7720.1:5MM
25V
10%
C7720
1
2
5%
NPO-C0G
0201
33PF
25V
NO STUFF
C7742
1
2
SM
PLACE_NEAR=D7720.K:2MM
XW7720
1
2
SI7812DN
PWRPK-1212-8
CRITICAL
PLACE_NEAR=U7700.1:3MM
Q7701
5
4
123
1%
1/16W
MF-LF
402
13.3K
R7731
1
2
1/16W
1%
150K
402
MF-LF
R7732
1
2
5%
0
1/16W
MF-LF
402
R7733
1
2
40 77
1W
1%
MTL
0612
0.025
R7700
12
34
40 77
0
402
MF-LF
1/16W
5%
R7744
1
2
PLACE_NEAR=D7720.K:9MM
T-BONE C7726 AND C7727
1.0UF
0805
50V
X7R
10%
C7726
1
2
50V
1.0UF
10%
PLACE_NEAR=D7720.K:9MM
X7R
0805
C7727
1
2
0
402
MF-LF
1/16W
5%
R7745
1
2
0.1%
10.2
1/16W
TF
402
BKLT:ENG
PLACE_NEAR=U7700.13:10MMR7720
12
0.1%
10.2
1/16W
TF
402
BKLT:ENG
PLACE_NEAR=U7700.14:10MMR7721
12
R7720,R7721 CRITICAL BKLT:PROD116S0004 1 RES,MTL FILM,0 OHM,1A MAX,0402,SMD
SYNC_MASTER=J44 SYNC_DATE=08/12/2013
LCD AND KBD BKLT DRIVER
PP5V_S0_BKLT_D
PP5V_S0
PP5V_S0_BKLT_A
GND_BKLT_SGND
ISNS_LCDBKLT_N
ISNS_LCDBKLT_P
LCDBKLT_EN_L
PPVOUT_S0_KBDBKLT
LCDBKLT_SW
PPVOUT_BKLT_FB2
PP5V_S0_KBDBKLT_SW
GND_BKLT_SGND
I2C_BKLT_SDA
MIN_LINE_WIDTH=2 MM
MIN_NECK_WIDTH=0.25 MM
PPVIN_S0SW_LCDBKLT_F
VOLTAGE=12.9V
VOLTAGE=5V
MIN_NECK_WIDTH=0.25 MM
MIN_LINE_WIDTH=2 MM
PP5V_S0_BKLT_D
PPVIN_S0SW_LCDBKLT_R
PPVOUT_S0_LCDBKLT
PPVIN_S0SW_LCDBKLT_F
MIN_NECK_WIDTH=0.25 MM
SWITCH_NODE=TRUE
VOLTAGE=53V
DIDT=TRUE
PPVIN_SW_LCDBKLT_SW
MIN_LINE_WIDTH=2 MM
PPVOUT_S0_LCDBKLT
VOLTAGE=53V
MIN_NECK_WIDTH=0.25 MM
MIN_LINE_WIDTH=0.5 MM
GND_BKLT_SGND
MIN_NECK_WIDTH=0.2 MM
MIN_LINE_WIDTH=0.4 MM
VOLTAGE=0V
LCDBKLT_SW
MIN_NECK_WIDTH=0.25 MM
SWITCH_NODE=TRUE
VOLTAGE=53V
DIDT=TRUE
MIN_LINE_WIDTH=2 MM
BKLT_SCL
GND_BKLT_SGND
MIN_NECK_WIDTH=0.25 MM
PPVIN_S0SW_LCDBKLT
VOLTAGE=12.9V
MIN_LINE_WIDTH=2 MM
PPVIN_S0SW_LCDBKLT_FET
MIN_NECK_WIDTH=0.25 MM
VOLTAGE=12.9V
MIN_LINE_WIDTH=2 MM
VOLTAGE=53V
MIN_NECK_WIDTH=0.25 MM
MIN_LINE_WIDTH=0.4 MM
PPVOUT_BKLT_FB
VOLTAGE=5V
GATE_NODE=TRUE
MIN_NECK_WIDTH=0.25 MM
LCDBKLT_FET_DRV
MIN_LINE_WIDTH=2 MM
DIDT=TRUE
VOLTAGE=5V
MIN_LINE_WIDTH=2 MM
GATE_NODE=TRUE
MIN_NECK_WIDTH=0.25 MM
LCDBKLT_FET_DRV_R
DIDT=TRUE
LCDBKLT_TB_XWR
LCDBKLT_FET_DRV
BKLT_ISET_KEYB
BKLT_SDA
MIN_LINE_WIDTH=2 MM
VOLTAGE=12.9V
MIN_NECK_WIDTH=0.25 MM
PPVIN_S0SW_LCDBKLT_R
I2C_BKLT_SCL
VOLTAGE=40V
PPVOUT_BKLT_FB2
MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.25 MM
SWITCH_NODE=TRUE
VOLTAGE=40V
MIN_NECK_WIDTH=0.25 MM
MIN_LINE_WIDTH=0.5 MM
PP5V_S0_KBDBKLT_SW
DIDT=TRUE
MIN_LINE_WIDTH=0.5 MM
PPVOUT_S0_KBDBKLT
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=40V
EDP_BKLT_PSR_EN
PPBUS_G3H
LCDBKLT_FET_DRV_R
SMC_SYS_KBDLED
BKLT_EN_R
PPVIN_SW_LCDBKLT_SW
VOLTAGE=5V
PP5V_S0_BKLT_A
MIN_LINE_WIDTH=2 MM
MIN_NECK_WIDTH=0.25 MM
PP5V_S0
BKLT_SD
MIN_NECK_WIDTH=0.25 MM
MAKE_BASE=TRUE
VOLTAGE=12.9V
MIN_LINE_WIDTH=2 MM
PPVIN_S0SW_LCDBKLT
BKLT_SENSE_OUT
PP5V_S0
BKLT_PWM_KEYB
LCDBKLT_FB
KBDLED_CATHODE1
MIN_LINE_WIDTH=0.3 MM
MIN_NECK_WIDTH=0.2 MM
BKLT_KEYB1
MIN_NECK_WIDTH=0.2 MM
MIN_LINE_WIDTH=0.3 MM
KBDLED_CATHODE2
BKLT_KEYB2
58 OF 78
77 OF 120
<E4LABEL>
<SCH_NUM>
<BRANCH>
58
16 17 32 41
44 45 53 54
58 60 61 65
68
58
58
35 58 68
58
58
58
58
58
58
58
58 62 68
58
58
58 62 68
58
58
58
58
58
58
58
58
58
58
35 58 68
25 40 51 52 65
68
58
58
58
16 17 32 41 44 45 53 54 58 60
61 65 68
58
16 17 32 41 44 45 53
54 58 60 61 65 68
35 68
35 68 www.rosefix.com

IN
BIAS
NC
OUT
THRM
EN
PADGND
NC
OUT
IN
VIN
LX
VFB
RSI
EN
POR
SKIP
GNDTHRM_PAD
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
87 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
D
SIZEDRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
Vout = 0.8V * (1 + Ra / Rb)
<Ra>
<Rb>
353S2535
Vout = 1.05V
Vout = 1.508V
MAX CURRENT = 0.6A
Freq = 1.6MHZ
152S1051
1.5V S0 Switcher
1.05V SUS LDO
Cougar Point requires JTAG pull-ups to be powered at 1.05V when SUS suspend well is active.
Pull-ups (3) must be 51 ohms to support XDP (not required in production).
70mA is required to support pull-ups. Alternative is strong voltage
dividers (200/100) to 3.3V S5, which burns 100mW in all S-states.
Max Current = 0.35A
6.3V
10%
402
CERM
1UF
XDP
C7840
1
2
XDP_CONN
SON
TPS720105
CRITICAL
U7840
4
3
5
6
2
1
7
6.3V
10%
402
X5R
2.2UF
XDP
C7841
1
2
1/16W
1%
402
MF-LF
113K
R7881
1
2
1/16W
1%
402
MF-LF
100K
R7880
1
2
6.3V
20%
0603
X5R
22UF
CRITICAL
C7873
1
2
61
61
6.3V
20%
0603
X5R
22UF
CRITICAL
C7870
1
2
2512
2.2UH-2A-0.155-OHM
CRITICAL
L7870
12
50V
5%
0402
C0G-CERM
10PF
C7876
1
2
CRITICAL
DFN
ISL8009B
U7870
2
7
8
3
54
9
6
1
1/16W
5%
402
MF-LF
10
R7882
1
2
6.3V
20%
0603
X5R
22UF
CRITICAL
C7874
1
2
SYNC_MASTER=J44 SYNC_DATE=08/12/2013
Misc Power Supplies
PP1V05_SUS
P1V5S0_PGOOD
P1V5S0_EN
PP1V5_S0
PP3V3_S5
MIN_NECK_WIDTH=0.2 mm
MIN_LINE_WIDTH=0.4 mm
P1V5_S0_SW
SWITCH_NODE=TRUE
DIDT=TRUE
PP3V3_SUS
P1V5_S0_FB
P1V5_S0_FB_R
<BRANCH>
<SCH_NUM>
<E4LABEL>
78 OF 120
59 OF 78
16 65
8 47 60 61 63 65 68
8 11 13 15 16 17 18 26 27 29
56 60 61 65 68 77
8 11 14 45 60 61 65 www.rosefix.com

IN
GND
VOUT
ON
VIN
NCNC
IN
NCNC
VIN
ON
GND
VOUT
IN
NCNC
GND
VDD
D
SON
CAP
IN
IN
GND
VOUT
ON
VIN
IN
IN
IN
VIN
ON
GND
VOUT
IN
IN
S
D
ON S
D
VDD
GND
GND
VDD
D
SON
CAP
GND
VOUT
ON
VIN
VOUT
GND
ON
VIN
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
87 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
D
SIZEDRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
REMOVED THE ANALOG POWER GATE AS SLG5AP1471 SHOULD BE AVAILABLE BY THEN
Current
TBD mOhm Max
9.8 mOhm Typ
Type
R(on)
@ 4V Vgs
SLG5AP1417V
1.05V PCH HSIO Switch
Part
U8005
6A Max
Load Switch
EDP: 1.84A
EDP: 2.4A
EDP: 1A
U8030
Sense R on sensor page
18.5 mOhm Typ
Load Switch
Part TPS22924C
R(on)
EDP: 50mA
TPS22924C
U8010
Load SwitchType
R(on)
@ 2.5V 25.8 mOhm Max
@ 2.5V
R(on)
Type
Current 2A Max
2A Max
@ 1.8V
Current
19.6 mOhm Typ
18.5 mOhm Typ
25.8 mOhm Max
Type
EDP: 5A
Part Load Switch
21.8 mOhm Max
2A Max
Type
Current
Part
Sense R on sensor page
Current
3.3V SSD Switch
Loading specs per J41/43_PowerBudget_Riviera_rev0.99e
3.3V SUS Switch
Part Part
U8020
@ 3.6V
63 mOhm Typ
77 mOhm Max
Current
TPS22934
Part
Type
R(on)
Load Switch
U8050
TPS22934
77 mOhm Max
63 mOhm Typ
1A MaxCurrent
@ 3.6V
R(on)
5.3A Max
8.5 mOhm Max
7.8 mOhm Typ
Load Switch
SLG5AP1453V
U8070
EDP: 167mA
1A Max
EDP: 1.02A
3.3V Sensor Switch
5V S0 Switch
U8080
Part
Type
R(on)
2.5ACurrent
EDP: 1.1A
15 mOhm Typ
17 mOhm Max
Load Switch
SLG5AP1443V
U8040
Load SwitchType
TPS22924C
@ 25C
3.3V S3 Switch
3.3V S4 Switch
U8000
TPS22920
5.5 MOHM TYP
8.8 MOHM MAX
4A MAX
@ 3.6V
R(on)
Part
Current
Type
3.3V S0 Switch
EDP: 0.5A
Load Switch
R(on)
1.5V S0 Audio Switch (BYPASSED)
60 61
0201-1
20%
1.0UF
6.3V
X5R
C8030
1
2
CRITICAL
CSP
TPS22924
U8030
C1
C2
A2
B2
A1
B1
18 26 27 61
20%
0201-1
1.0UF
6.3V
X5R
C8000
1
2
TPS22934
WCSP
CRITICAL
U8020
B1
B2
A2 A1
20%
0201-1
1.0UF
6.3V
X5R
C8020
1
2
61
TDFN
CRITICAL
SLG5AP1453V
U8070
73
8
25
1
201
X7R
10V
4700PF
10%
C8071
1
2
CERM-X5R
0201
6.3V
0.1UF
10%
C8070
1
2
15 30
61
61
20%
1.0UF
0201-1
6.3V
X5R
C8010
1
2
TPS22924
CSP
CRITICAL
U8010
C1
C2
A2
B2
A1
B1
MF
1%
OMIT
0.002
0612-SHORT
1W
R8011
12
34
MF
1%
1W
OMIT
0612-SHORT
0.002
R8000
12
34
MF
1%
1W
OMIT
0612-SHORT
0.002
R8020
12
34
0201-1
20%
1.0UF
6.3V
X5R
NOSTUFF
C8040
1
2
61
MF
1/20W
NOSTUFF
201
10K
5%
R8040
1
2
5%
0
0201
1/20W
MF
NOSTUFF
R8070
12
60 61
0201
0
MF
5%
1/20W
R8042
12
36 38 40
TPS22934
WCSP
CRITICAL
U8050
B1
B2
A2 A1
1.0UF
20%
0201-1
6.3V
X5R
C8050
1
2
5%
0
MF-LF
402
1/16W
R8050
12
0201
16V
X5R-CERM
0.1UF
10%
C8080
1
2
61
15
TDFN
SLG5AP1471V
CRITICAL
U8005
2
3
8
95
7
1
SLG5AP1443V
TDFN
CRITICAL
U8080
7 3
8
2 5
1
201
4700PF
10V
X7R
10%
C8081
1
2
CSP
NOSTUFF
CRITICAL
TPS22924
U8040
C1
C2
A2
B2
A1
B1
TPS22920
CSP
CRITICAL
U8000
D1
D2
A2
B2
C2
A1
B1
C1
402
10V
1UF
X5R
10%
C8005
1
2
SYNC_MASTER=J44
Power FETs
SYNC_DATE=08/12/2013
MAKE_BASE=TRUE
MIN_NECK_WIDTH=0.17 mm
VOLTAGE=1.5V
MIN_LINE_WIDTH=0.3 mm
PP1V5_S0SW_AUDIO_HDAPP1V5_S0
P1V5S0SW_AUDIO_EN
P3V3S0_EN
S4_PWR_EN
PP3V3_S5 PP3V3_S4_FET_R
MIN_NECK_WIDTH=0.20MM
MIN_LINE_WIDTH=0.50MM
VOLTAGE=3.3V
PP3V3_S5
PP5V_S0_FET
PP5V_S4
P5VS0_EN
P5VS0_FET_RAMP
PP3V3_S4
PP3V3_S5
SMC_SENSOR_PWR_EN
PP3V3_S5
PP3V3_SUS_FET_R
VOLTAGE=3.3V
MIN_NECK_WIDTH=0.20MM
MIN_LINE_WIDTH=0.50MM
P3V3SUS_EN
PP3V3_S4SW_SNS_FET_R
MIN_NECK_WIDTH=0.2mm
MIN_LINE_WIDTH=0.5mm
VOLTAGE=3.3V
MIN_NECK_WIDTH=0.20MM
VOLTAGE=3.3V
MIN_LINE_WIDTH=0.5 MM
PP3V3_S0SW_SSD_FET
PP3V3_SUS
PP3V3_S5
SSD_PWR_EN
P3V3S0SW_SSD_FET_RAMP
P3V3S0_EN
PP3V3_S3
PP1V5_S0SW_AUDIO_HDA
P3V3S3_EN
PP3V3_S4SW_SNS
VOLTAGE=3.3V
MIN_LINE_WIDTH=0.50MM
PP3V3_S3_FET_R
MIN_NECK_WIDTH=0.20MM
PP3V3_S0_FET
PP1V05_S0
PP1V05_S0SW_PCH_HSIO
PP3V3_S5
PCH_HSIO_PWR_EN
PP5V_S0
<BRANCH>
<SCH_NUM>
<E4LABEL>
80 OF 120
60 OF 78
8 11 17 60 8 47 59
61 63 65
68
8 11 13 15
16 17 18 26
27 29 56 59
60 61 65 68
77
8 11 13
15 16 17
18 26 27
29 56 59
60 61 65
68 77
41 65
32 33 46 55 56 57 62 63 65 66
68
18 29 34 37 38 42 63 64 65 68
8 11
13 15
16
17 18
26
27 29
56
59 60
61
65 68
77
8 11 13 15 16 17 18 26 27 29
56 59 60 61 65 68 77
41 65
8 11 14 45 59 61 65
8 11 13 15
16 17 18 26
27 29 56 59
60 61 65 68
77
15 18 19 39 42 65 68
8 11 17 60
40 41 42 65
41 65
6 8 11 15 16 17 37 53 57 61
65 68
8 11 65
8 11 13 15 16 17 18 26 27 29
56 59 60 61 65 68 77
16 17 32 41 44 45 53 54 58 61
65 68 www.rosefix.com

OUT
OUT
IN
NC
NC
NC
Q3
Q2
Q4
Q1
OUT
VDD
MR*
RST*V4MON
V3MON
V2MON
GNDTHRM_PAD
IN
OUT
NC
NC
IN
IN
OUT
OUT
IN
SYM_VER_2
GS
D
OUT
IN OUT
IN
OUT
OUT
OUT
OUT
IN
OUT
OUT
OUT
OUT
OUTIN
OUTIN
SENSE
THRM
RESET*
CT
GND
MR*
VDD
PAD
OUT
OUT
OUT
IN
OUT
IN
OUT
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
87 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
D
SIZEDRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
1.5V Codec Enable(BYPASSED NOW)
5V needs to be held up
so 1.05V can fall after 1.5V
PM_SLP_S3_L
1
S5 Enables
S5 Power Good
376S0854
S0 Rail PGOOD (BJT Version)
00
0
0
1
9ms RC delay
0
V2MON: 2.815V-3.099V
5.0V Divider: 1.07V
VDD: 2.734V-3.010V
3.3V Divider: 1.07V
SUS Enables
threhold is 3.07V
No stuff C8131, 12ms
Min delay time
SMC-->PM_DSW_PWRGD
Deep Sleep (S5)
Battery Off (G3Hot)
Sleep (S3)
Deep Sleep (S5AC)
State
Run (S0)
toggle 3Hz
0
1
0
1
1
1
1
0
1
0
0
0
1
1
1
0
0
0
0
1
0
0
00
0
0
1
0
0
0
0
0
SMC_PM_G2_ENABLE SMC_S4_WAKESRC_EN
1
X
11
1
PM_SUS_EN
11
PM_SLP_S5_L PM_SLP_S4_L
11
0
353S2310
0.723V @ 1.02Vmin
0.718V @ 1.45Vmin
3.19V @ 4.5Vmin
1.05V Divider:
1.5V Divider:
5V Divider:
SSD Enable
U8130 Sense input
S5_PWRGD-->SMC
Deep Sleep (S4)
Sleep (S3AC)
Battery Off (G3HotAC)
Thresholds:
V3MON: 0.572V-0.630V
(IPU)
Vbe 0.7V max @ 2mA
V4MON: 0.572V-0.630V
Vce(sat) 0.1V max @ 1mA
0
VFRQ Low: Fix Frequency
Q1 Vth 0.7~1V @Id 250uA
S0 Rail PGOOD Circuitry
(ISL version used for development)
0
1
1
0
0
0
VFRQ High: Variable Frequency
Mobile System Power State Table
1
0
1
Standby Enables
S3 Enables
SMC_ADAPTER_EN
CHGR VFRQ Generation
3.3V SUS Detect
1
Deep Sleep (S4AC)
S0 Enables
0 0
330K
MF
1/20W
201
5%
R8131
1
2
52
10K
MF
1/20W
201
5%
R8167
1
2
16 17 36 61
100
MF
1/20W
201
5%
R8157
1
2
100
MF
1/20W
201
5%
R8164
12
S0PGOOD_ISL
330
MF
1/20W
201
5%
R8162
12
57
150K
1%
MF
1/20W
201
R8156
1
2
10%
0.1UF
6.3V
0201
CERM-X5R
S0PGOOD_ISL
C8160
1
2
1%
54.9K
MF
1/20W
201
R8151
1
2
1%
15K
MF
1/20W
201
R8152
1
2
CRITICAL
ASMCC0179
DFN2015H4-8
Q8150
5
7
1
6
4
8
2
3
1K
MF
1/20W
201
5%
R8154
12
1K
MF
1/20W
201
5%
R8155
12
1000PF
10%
X7R-CERM
0201
16V
NO STUFF
C8131
1
2
100K
MF
1/20W
201
5%
R8133
1
2
10%
0.1UF
6.3V
0201
CERM-X5R
BYPASS=U8130.6:2.3mm
C8130
1
2
13 72
S0PGOOD_ISL
CRITICAL
TDFN
ISL88042IRTEZ
U8160
4
1
8
9
3
5
6
2
7
S0PGOOD_ISL
1%
15K
MF
1/20W
201
R8173
1
2
S0PGOOD_ISL
1%
15K
MF
1/20W
201
R8171
1
2
S0PGOOD_ISL
15K
1%
MF
1/20W
201
R8161
1
2
S0PGOOD_ISL
1%
15K
MF
1/20W
201
R8170
1
2
6.04K
S0PGOOD_ISL
1%
MF
1/20W
201
R8172
1
2
6.04K
S0PGOOD_ISL
1%
MF
1/20W
201
R8160
1
2
13 40 61
60 61
1K
MF
1/20W
201
5%
R8153
12
MF
1/20W
0201
0
5%
R8115
12
NOSTUFF
74LVC1G32
SOT891
U8170
2
1
35
6
4
13 36
10%
0.1UF
6.3V
0201
CERM-X5R
NOSTUFF
BYPASS=U8170.6:2.3mm
C8170
1
2
36 37
18 26 27 60 61
18 26 27 60 61
55
DMN32D2LFB4
DFN1006H4-3
Q8131 3
1
2
100
MF
1/20W
201
5%
R8168
12
36 56 61
100K
PLACE_NEAR=U7501.20:7mm
MF
1/20W
201
5%
R8141
1
2
36 37 56
61
PLACE_NEAR=U7501.21:7mm
100
MF
1/20W
201
5%
R8140
12
56 61
13 18 29 36 61 63
402
0.1UF
PLACE_NEAR=U7400.16:6mm
CERM
10V
20%
C8111
1
2
10%
NO STUFF
0.47UF
6.3V
CERM-X5R
402
PLACE_NEAR=U8010.C2:6mm
C8112
1
2
20K
1/20W
5%
201
MF
PLACE_NEAR=U7400.16:6mm
R8111
1
2
PLACE_NEAR=U8010.C2:6mm
0201
MF
1/20W
5%
0
R8112
1
2
402
10%
6.3V
0.47UF
CERM-X5R
PLACE_NEAR=U4600.4:6mm
NO STUFF
C8114
1
2
55 61
60 61
33 61
13 40 61
1%
15K
MF
1/20W
201
R8158
1
2
1%
7.15K
MF
1/20W
201
R8159
1
2
13 17 18 36 63 68
5%
201
1/20W
MF
100
R8178
12
26 27 46 61
SC70-HF
MC74VHC1G08
U8180
3
2
1
4
5
NOSTUFF
5%
201
1/20W
MF
330K
R8180
1
2
PLACE_NEAR=U7600.16:6mm
10V
0.22UF
NO STUFF
CERM
10%
402
C8185
1
2
201
5%
MF
PLACE_NEAR=U7600.16:6mm
820
NO STUFF
1/20W
R8138
12
1/20W
0
0201
MF
5%
PLACE_NEAR=U7600.16:6mm
R8185
1
2
0.1UF
PLACE_NEAR=U8030.C2:6mm
10V
CERM
402
20%
C8186
1
2
39K
PLACE_NEAR=U8030.C2:6mm
5%
1/20W
201
MF
R8186
1
2
402
10%
6.3V
0.68UF
CERM
NO STUFF
PLACE_NEAR=U8080.2:6mm
C8187
1
2
PLACE_NEAR=U8080.2:6mm
1/20W
5%
0
MF
0201
R8187
1
2
57 61
59 61
60 61
15 30 60 61 15 30 60 61
60
402
25V
NOSTUFF
0.1UF
10%
X5R
PLACE_NEAR=U8040.C2:7mm
C8146
1
2
201
1/20W
MF
NOSTUFF
1%
1K
R8146
12
201
PLACE_NEAR=U8040.C2:7mm
100K
NOSTUFF
MF
1/20W
1%
R8145
12
13
BYPASS=U8180.6:3mm
CERM-X5R
0201
6.3V
0.1UF
10%
C8180
1
2
QFN
TPS3808G33
CRITICAL
U8130
3
5
4
62
7
1
PLACE_NEAR=U7501.4:15mm
NO STUFF
SM-201
RB521ZS-30
D8175
A
K
240
MF
1/20W
201
5%
PLACE_NEAR=U7501.4:15mm
NO STUFF
R8176
12
PLACE_NEAR=U7501.4:15mm
MF
1/20W
0201
0
5%
R8175
1
2
402
10%
X5R
6.3V
2.2UF
PLACE_NEAR=U7501.4:15mm
NO STUFF
C8175
1
2
402
10%
6.3V
PLACE_NEAR=U7501.21:7mm
CERM-X5R
0.47UF
NOSTUFF
C8142
1
2
SM-201
RB521ZS-30
PLACE_NEAR=U7600.16:6mm
NO STUFF
D8185
A
K
NOSTUFF
SM-201
PLACE_NEAR=U8040.C2:7mm
RB521ZS-30
D8146
AK
60 61
MF
1/20W
0201
0
5%
R8190
1
2
402
25V
10%
0.1UF
X5R
NO STUFF
C8190
1
2
100
PLACE_NEAR=U4600.4:6mm
MF
1/20W
201
5%
R8117
1
2
36 37 56
61
56
MF
1/20W
0201
0
5%
R8179
12
100
MF
1/20W
201
5%
R8165
12
56
402
10%
X5R
1UF
10V
C8159
1
2
100
MF
1/20W
201
5%
R8169
12
18 26 27 60 61
PLACE_NEAR=U8030.C2:6mm
330
1/20W
MF
201
5%
R8184
1
2
RB521ZS-30
PLACE_NEAR=U8030.C2:6mm
SM-201
D8184
AK
MF
5%
1/20W
3.3K
201
PLACE_NEAR=U4801.4:6mm
R8113
1
2
34
6.3V
10%
CERM-X5R
402
0.47UF
NO STUFF
PLACE_NEAR=U4801.4:6mm
C8113
1
2
68K
5%
1/20W
MF
201
PLACE_NEAR=U7870.2:6mm
R8188
1
2
20%
10V
CERM
0.1UF
PLACE_NEAR=U7870.2:6mm
402
C8188
1
2
RB521ZS-30
SM-201
PLACE_NEAR=U7870.2:6mm
D8183
AK
PLACE_NEAR=U7870.2:6mm
MF
5%
330
1/20W
201
R8183
1
2
Power Control
SYNC_DATE=08/12/2013SYNC_MASTER=J44
MAKE_BASE=TRUE
P5VS0_EN
MAKE_BASE=TRUE
P3V3S0_EN
P1V5S0_EN
MAKE_BASE=TRUE
P1V5S0_EN
MAKE_BASE=TRUE
PM_SLP_S3_BUF_L
MAKE_BASE=TRUE
P1V05S0_EN
P3V3S0_EN
S4_PWR_EN
MAKE_BASE=TRUE
P1V5S0_EN_D
PM_SLP_S3_BUF_L
P1V05_EN_D
P5VS0_EN
P1V05S0_EN
PM_SLP_S3_L PM_SLP_S3_R_L
PP3V3_S5
PM_SLP_S4_L
MAKE_BASE=TRUE
DDRREG_EN
MAKE_BASE=TRUE
P3V3S3_EN P3V3S3_EN
TPAD_VBUS_EN
MAKE_BASE=TRUE
USB_PWR_EN
S4_PWR_EN
S4_PWR_EN
PM_SLP_S5_L
SMC_S4_WAKESRC_EN
S4_PWR_EN
PM_RSMRST_L
PP3V3_SUS
USB_PWR_EN
DDRREG_EN
PP3V3_S0
ALL_SYS_PWRGD
P1V05S0_PGOOD
DDRREG_PGOOD
PP3V42_G3H
PP3V3_SUS
VMON_5V_DIV
S0PGD_BJT_GND_R
P1V5S0_PGOOD
PP3V3_S5
PM_SLP_S3_BUF_L
MAKE_BASE=TRUE
S5_PWR_EN
MAKE_BASE=TRUE
SMC_PM_G2_EN
MAKE_BASE=TRUE
P3V3SUS_EN
SSD_PWR_EN
MAKE_BASE=TRUE
S5_PWRGD
MAKE_BASE=TRUE
PM_SLP_SUS_L
MAKE_BASE=TRUE
PP3V3_S5
SSD_PWR_EN
P3V3SUS_EN
SUS_PGOOD_CT
S5_PWRGD
PP1V5_S0
PP1V05_S0
ALL_SYS_PWRGD_R
CHGR_VFRQ
PP5V_S0
P1V5_DIV_VMON
P5V_DIV_VMON
P1V05_DIV_VMON
S0PGD_C
ALL_SYS_PWRGD
PM_SLP_SUS_L
PM_SLP_S3_R_L
PP5V_S0
TP_SUS_PGOOD_MR_L
PP3V3_S0
VMON_Q3_BASE
VMON_3V3_DIV
VMON_Q2_BASE
PP1V5_S0 VMON_Q4_BASE
S5_PWR_EN
SMC_PM_G2_EN
PP3V42_G3H
P5VS4RS3_PGOOD
PM_SLP_S4_L
P5VS4RS3_EN P5VS4RS3_EN_RC
P5VS4RS3_EN_D
P1V5S0SW_AUDIO_EN
P1V5CODEC_EN_D
AUD_PWR_EN
P3V3S0_EN_D
PP3V3_S5
<BRANCH>
<E4LABEL>
81 OF 120
<SCH_NUM>
61 OF 78
60 61
60 61
59 61
26 27 46
61
57 61
61
8 11 13 15 16 17 18 26 27 29
56 59 60 61 65 68 77
55 61
60 61
33 61
8 11 14 45 59 60 61 65
8 11 12 13 15 17 18 24 28 30
37 38 39 40 41 42 43 44 46 47
50 61 62 64 65 68 77
17 30 33 34 36 37 38 39 45 51
52 61 65 68
8 11 14 45 59 60 61 65
8 11 13 15 16 17 18 26 27 29
56 59 60 61 65 68 77
26 27 46 61
56 61
60 61
8 11 13 15 16 17 18 26 27 29
56 59 60 61 65 68 77
36 56 61
8 47 59 60 61 63 65 68
6 8 11 15 16 17 37 53 57 60
65 68
16 17
32 41
44 45
53 54
58 60
61 65
68
16 17 36 61
61
16 17 32 41 44 45 53 54 58 60
61 65 68
8 11 12 13 15
17 18 24 28 30
37 38 39 40 41
42 43 44 46 47 50 61
62 64 65 68 77
8 47 59 60 61 63 65 68
17 30 33 34
36 37 38 39
45 51 52 61
65 68
13 18 29 36 61 63
8 11 13 15 16 17 18 26 27 29
56 59 60 61 65 68 77 www.rosefix.com

IN
IN
IN
IN
IN
IN
IN
IN
BI
BI
NC
OUT
OUT
OUT
VCC
GND
A
B
A
B
Y
Y
YA
B
C
VCC
GND
GND
VDD
D
SON
CAP
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
87 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
D
SIZEDRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
LCD PANEL INTERFACE (eDP)
NEEDS FINAL CHECK AGAINST UPDATE FOR NEW PANEL
EDP: 1 A
Y = B
518S0829
2.5A
TypeCurrent
R(on)
Part
U8300
LCD Panel HPD & AUX strapping
17 mOhm Max
15 mOhm Typ
Load Switch
SLG5AP1443V
PANEL USES EDP_PANEL_PWR_PSR_EN TO DISCHARGE THE LCD BEFORE POWER GOES AWAY
NEEDS TO BE LEVEL SHIFTED TO 3.3V
LCD_HPD_CONN IS A 2.5V SIGNAL
Short Rsense
16V
10%
0201
X5R-CERM
0.1UF
C8301
1
2
0805
FERR-220-OHM
CRITICAL
L8300
12
1/16W
5%
402
MF-LF
100K
R8310
1
2
16V
10%
0201
X5R-CERM
0.1UF
C8302
1
2
10%
16V
0402
X7R-CERM
0.1UF
C8309
1
2
16V
10%
0402
X7R-CERM
0.1UF
C8311
1
2
6.3V
20%
603
X5R
10UF
C8312
1
2
020116V
10%
X5R-CERM0.1UF
C832112
020116V
10%
X5R-CERM0.1UF
C832012
5 74
5 74
020116V
10%
X5R-CERM0.1UF
C832312
020116V
10%
X5R-CERM0.1UF
C832212
5 74
5 74
16V0201
10%
X5R-CERM0.1UF
C832512
020116V
10%
X5R-CERM0.1UF
C832412
5 74
5 74
0.1UF
020116V
10%
X5R-CERM
C832712
020116V
10%
X5R-CERM0.1UF
C832612
5 74
5 74
0201
16V10%
X5R-CERM0.1UF
C832912
0201
16V10%
X5R-CERM0.1UF
C832812
5 74
5 74
F-RT-SM
20525-130E-01
CRITICAL
J8300
1
10
11
12
13
14
15
16
17
18
19
2
20
21
22
23
24
25
26
27
28
29
3
30
31
32
33
34
35
36
37
38
39
4
40
41
5
6
7
8
9
13
1/20W
5%
201
MF
1M
NO_XNET_CONNECTION=TRUE
R8302
1
2
1/20W
5%
201
MF
1M
NO_XNET_CONNECTION=TRUE
R8303
1
2
1/20W
5%
201
MF
1M
R8301
1
2
NO_XNET_CONNECTION=TRUE
1/20W
5%
201
MF
1M
R8313
12
1/20W
5%
201
MF
1M
NO_XNET_CONNECTION=TRUE
R8314
12
NO_XNET_CONNECTION=TRUE
1/20W
5%
201
MF
1M
R8315
12
1/20W
5%
201
MF
1M
NO_XNET_CONNECTION=TRUE
R8316
12
1/20W
5%
201
MF
1M
NO_XNET_CONNECTION=TRUE
R8312
12
NO_XNET_CONNECTION=TRUE
1/20W
5%
201
MF
1M
R8317
12
NO_XNET_CONNECTION=TRUE 1/20W
5%
201
MF
1M
TRUE
R8318
12
1/20W
5%
201
MF
1M
NO_XNET_CONNECTION=TRUE
R8311
12
100V
10%
0603
X7R-CERM
1000PF
C8300
1
2
100V
10%
0603
X7R-CERM
1000PF
C8303
1
2
42 77
42 77
SOT833
74LVC2G32GT
U8330
5
1
6
2
48
3
7
NO STUFF
1/20W5% 0201MF
0
R833012
NO STUFF
1/20W5% 0201MF
0
R833112
CERM-X5R
NOSTUFF
BYPASS=U8330.8:3MM
6.3V
10%
0201
0.1UF
C8330
1
2
SOT891
74AUP1T97
CRITICAL
U8340
2
3
1
6
5
4
16V
10%0201
X5R-CERM
0.1UF
BYPASS=U8340.5:3MM
C8340
1
2
1/16W
5%
402
MF-LF
100K
R8309
1
2
1/16W
5%
402
MF-LF
100K
R8340
1
2
TDFN
SLG5AP1443V
CRITICAL
U8300
73
8
25
1
10V
10%
201
X7R
4700PF
C8310
1
2
6.3V
10%
402
CERM
1UF
C8319
1
2
1/20W
5%
201
MF
1K
R8319
12
EDP_LS_CAP
25V
+/-0.1PF
0201
COH
9.1PF
C8350
1
2
EDP_LS_CAP
25V
+/-0.1PF
0201
COH
9.1PF
C8351
1
2
EDP_LS_CAP
25V
+/-0.1PF
0201
COH
9.1PF
C8352
1
2
EDP_LS_CAP
25V
+/-0.1PF
0201
COH
9.1PF
C8353
1
2
EDP_LS_CAP
25V
+/-0.1PF
0201
COH
9.1PF
C8354
1
2
EDP_LS_CAP
25V
+/-0.1PF
0201
COH
9.1PF
C8355
1
2
EDP_LS_CAP
25V
+/-0.1PF
0201
COH
9.1PF
C8356
1
2
EDP_LS_CAP
25V
+/-0.1PF
0201
COH
9.1PF
C8357
1
2
EDP_LS_CAP
25V
+/-0.1PF
0201
COH
9.1PF
C8358
1
2
EDP_LS_CAP
25V
+/-0.1PF
0201
COH
9.1PF
C8359
1
2
0
MF
0
1 W
0612-SHORT
OMIT
R8320
12
34
eDP Display Connector
SYNC_DATE=08/12/2013SYNC_MASTER=J44
ISNS_LCDPANEL_N
ISNS_LCDPANEL_P
PP5VR3V3_SW_LCD_UF
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=5V
PP5VR3V3_SW_LCD_ISNS
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=5V
DP_INT_AUX_N
EDP_PANEL_PWR_OR_PSR_EN
DP_INT_AUX_P
SMBUS_SMC_0_S0_SDA
SMBUS_SMC_0_S0_SCL
DP_INT_ML_C_N<3>
PP5V_S4
I2C_BKLT_SCL
I2C_BKLT_SDA
DP_INT_ML_C_N<2>
DP_INT_ML_C_P<3>
DP_INT_ML_C_N<1>
DP_INT_ML_C_P<2>
DP_INT_ML_C_N<0>
DP_INT_ML_C_P<1>
DP_INT_ML_C_P<0>
PP3V3_S0
DP_INT_AUX_P
DP_INT_AUX_N
LCD_HPD_CONN
PP5V_S0_LCD_FETCAP
MIN_LINE_WIDTH=0.25 mm
MIN_NECK_WIDTH=0.1 mm
VOLTAGE=5V
EDP_PANEL_PWR_OR_PSR_EN
EDP_BKLT_PSR_EN
DP_INT_ML_P<2>
EDP_PANEL_PWR
EDP_BKLT_EN
LCD_PSR_EN
DP_INT_HPD
LCD_HPD_CONN
LCD_IRQ_L
DP_INT_AUXCH_C_P
DP_INT_AUXCH_C_N
DP_INT_ML_N<3>
DP_INT_ML_P<3>
EDP_PANEL_PWR_OR_PSR_EN EDP_PANEL_PWR_EN_RC
DP_INT_ML_P<0>
DP_INT_ML_N<2>
DP_INT_ML_N<1>
DP_INT_ML_P<1>
DP_INT_ML_N<0>
PP5VR3V3_SW_LCD
VOLTAGE=5V
MIN_NECK_WIDTH=0.25 mm
MIN_LINE_WIDTH=0.5 mm
DP_INT_ML_P<0>
DP_INT_ML_N<0>
DP_INT_ML_P<1>
DP_INT_ML_P<2>
DP_INT_ML_N<2>
DP_INT_ML_P<3>
DP_INT_ML_N<3>
PPVOUT_S0_LCDBKLT
DP_INT_ML_N<1>
EDP_BKLT_PWM
PP3V3_S0
<BRANCH>
<SCH_NUM>
<E4LABEL>
83 OF 120
62 OF 78
62 68 74
62 68
62 68 74
36 39 68
76
36 39 68
76
32 33 46 55 56 57 60 63
65 66 68
58 66 68
58 66 68
8 11 12 13 15 17 18 24 28 30
37 38 39 40 41 42 43 44 46 47
50 61 62 64 65 68 77
62 68 74
62 68 74
62 68
62 68
58
62 68 74
13
13
15
62 68
15 68
62 68 74
62 68 74
62 68
62 68 74
62 68 74
62 68 74
62 68 74
62 68 74
68
62 68 74
62 68 74
62 68 74
62 68 74
62 68 74
62 68 74
62 68 74
58 68
62 68 74
13 68
8 11 12 13 15 17 18 24 28 30
37 38 39 40 41 42 43 44 46 47
50 61 62 64 65 68 77 www.rosefix.com

IN
IN
IN
OUT
OUT
IN
OUT
OUT
SYM_VER-1
IN
IN
OUT
OUT
OUT
OUT
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
BI
BI
BI
IN
IN
BI
BI
OUT
IN
IN
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
BI
BI
OUT
OUT
BI
OUT
BI
OUT
OUT
BI
IN
OUT
OUT
IN
IN
OUT
OUT
IN
IN
BI
BI
IN
IN
IN
OUT
OUT
BI
BI
OUT
OUT
OUT
IN
IN
IN
IN
IN
OUT
BI
OUT
BI
OUT
BI
OUT
OUT
OUT
IN
OUT
OUT
OUT
IN OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
IN
TP
TP
TP
TP
TP
TP
TP
TP
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
87 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
D
SIZEDRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
MAKE BASE
MAKE BASE FOR I2C IS ON I2C PAGE
MAKE BASE FOR I2C IS ON I2C PAGE
518S0882
RIO Power Connector
(USB3_EXTB_R2D caps on RIO)
NOTE: This connector is shielded 70P Hirose Plug APN 516S1059, mates with APN 516S1058.
516S1059
RIO FLEX CONNECTOR
14 68 70
14 68 70
12 68 70
14 63 68 70
14 63 68 70
12 68 70
X7R-CERM
10%
0402
16V
0.1UF
PLACE_NEAR=J9510.1:2.54MM
C9533
12
PLACE_NEAR=J9510.3:2.54MM
16V10%
0402
X7R-CERM
0.1UF
C9532
12
63 68 70
63 68 70
TCM0605-1
90-OHM-50MA
CRITICAL
PLACE_NEAR=J9510.42:2.54MM
L9501
1
23
4
14 63 68 70
14 63 68 70
63 70
63 70
14 63 68 71
14 63 68 71
63 64 68 74
63 64 68 74
64 68 74
64 68 74
63 64 68 74
63 64 68 74
64 68 74
64 68 74
14 63 71
14 63 71
63 64
63 64
29 63 71
29 63 71
14 16 19 39 63 68 72
36 39 43 63 76
14 16 19 39 63 68 72
36 39 43 63 76
18 63
63 70
63 70
16V
10%
0.1UF
X5R-CERM
0201
PLACE_NEAR=J9500.2:2.5MM
C9591
1
2
PLACE_NEAR=J9500.1:2.5MM
16V
10%
0201
0.1UF
X5R-CERM
C9592
1
2
16V
10%
0201
X5R-CERM
0.1UF
PLACE_NEAR=J9510.39:2.54MM
C9593
1
2
63 64 68 74
63 64 68 74
63 64 68 74
63 64 68 74
63
63
63
63
29 63 71
29 63 71
63 70
63 70
14 16 19 39 63 68 72
14 16 19 39 63 68 72
63 64
63 64
36 39 43 63 76
36 39 43 63 76
18 63
14 63 71
14 63 68 71
14 63 68 71
63 70
63 70
14 63 68 70
14 63 68 70
14 71
14 71
14 68 71
14 68 71
63 64
14 68 71
14 68 71
29 63 71
29 63 71
63 68 70
14 63 71
14 63 71
14 63 68 71
14 63 68 71
12
29 63 72
18 63
15
36 39 43 63 76
36 39 43 63 76
63 64
63 64
14 16 19 39 63 68 72
14 16 19 39 63 68 72
15
15
14 16
13 18 29 36 61
13 17 18 36 61 68
63 68 70
29 63 72 29 63 72
63
63
63 64 68 74
63 64 68 74
63
63
63 64 68 74
63 64 68 74
36 38
36
504050-0491
M-RT-SM
J9500
5
6
1
2
3
4
63 64
300K
MF
1/20W
5%
201
R9530
1
2
DF40BG-70DP-0.4V
M-ST-SM
CRITICAL
GND_VOID=TRUE
GND_VOID=TRUE
GND_VOID=TRUE
GND_VOID=TRUE
GND_VOID=TRUE
GND_VOID=TRUE
GND_VOID=TRUE
GND_VOID=TRUE
GND_VOID=TRUE
GND_VOID=TRUE
GND_VOID=TRUE
GND_VOID=TRUE
GND_VOID=TRUE
GND_VOID=TRUE
GND_VOID=TRUE
GND_VOID=TRUE
GND_VOID=TRUE
GND_VOID=TRUE
J9510
1
10
11 12
13 14
15 16
17 18
19
2
20
21 22
23 24
25 26
27 28
29
3
30
31 32
33 34
35 36
37 38
39
4
40
41 42
43 44
45 46
47 48
49
5
50
51 52
53 54
55 56
57 58
59
6
60
61 62
63 64
65 66
67 68
69
7
70
71 72
73 74
8
9
SMBEAD-PROBEBP95001
SMBEAD-PROBEBP95011
SMBEAD-PROBEBP95021
SMBEAD-PROBEBP95031
SMBEAD-PROBEBP95041
SMBEAD-PROBEBP95051
SMBEAD-PROBEBP95061
SMBEAD-PROBEBP95071
SYNC_MASTER=J44 SYNC_DATE=08/12/2013
RIO Connector
=HDMI_DATA_C_P<0>
HDMI_IG_DATA_C_P<1>
HDMI_IG_DATA_C_N<1>
SD_RESET_L
PCIE_CLK100M_AP_CONN_N
PCIE_CLK100M_AP_CONN_P
USB_EXTB_N
PCIE_AP_D2R_P
PCIE_AP_D2R_N
USB_BT_CONN_N
USB3_EXTB_R2D_C_P
HDMI_HPD
USB3_EXTB_D2R_P
USB3_EXTB_D2R_N
USB3_EXTB_R2D_C_N
USB_BT_CONN_P
=HDMI_DATA_C_P<2>
=HDMI_DATA_C_N<2>
USB3RPCIE_SD_D2R_P
SDCONN_STATE_CHANGE_RIO
AP_PCIE_WAKE_L
AP_CLKREQ_L
SMBUS_SMC_3_SCL
SD_PWR_EN
PP1V5_S0
WIFI_EVENT_L
SMBUS_SMC_3_SDA
HDMI_IG_DDC_DATA
HDMI_IG_DDC_CLK
SMC_WIFI_PWR_EN
SMBUS_PCH_DATA
SMBUS_PCH_CLK
USB_EXTB_P
USB3RPCIE_SD_R2D_C_P
USB3RPCIE_SD_R2D_C_N
PCIE_AP_R2D_N
PCIE_AP_R2D_P
AP_RESET_L=HDMI_DATA_C_N<0>
XDP_USB_EXTB_OC_L
HDMI_IG_CLK_C_P PM_SLP_S4_L
HDMI_IG_CLK_C_N PM_SLP_S3_L
USB3RPCIE_SD_D2R_N
PCIE_AP_D2R_P
PCIE_AP_D2R_N
PCIE_CLK100M_AP_P
PCIE_CLK100M_AP_N
PCIE_AP_R2D_N
PCIE_CLK100M_AP_CONN_N
PCIE_CLK100M_AP_CONN_P
PCIE_AP_R2D_P
PCIE_AP_R2D_C_P
PCIE_AP_R2D_C_N
PP5V_S4
PP3V3_S4
HDMI_HPD
PP1V5_S0PP1V5_S0
TRUEUSB_BT_CONN_P
TRUEUSB_BT_CONN_N
=HDMI_DATA_C_P<2>
=HDMI_DATA_C_N<2>
HDMI_IG_DATA_C_N<1>
HDMI_IG_DATA_C_P<1>
=HDMI_DATA_C_N<0>
=HDMI_DATA_C_P<0>
HDMI_IG_CLK_C_P
HDMI_IG_CLK_C_N
USB_BT_CONN_P
USB_BT_CONN_N
TRUEPCIE_CLK100M_AP_CONN_N
TRUEPCIE_CLK100M_AP_CONN_P
SMBUS_PCH_CLK
SMBUS_PCH_DATA
TRUEHDMI_IG_DDC_CLK
TRUEHDMI_IG_DDC_DATA
SMBUS_SMC_3_SCL
SMBUS_SMC_3_SDA
SDCONN_STATE_CHANGE_RIOTRUE
USB3RPCIE_SD_D2R_P
TRUE
TRUE
USB3RPCIE_SD_D2R_N
TRUEUSB3RPCIE_SD_R2D_C_N
TRUEUSB3RPCIE_SD_R2D_C_P
AP_PCIE_WAKE_L
TRUE
PCIE_CLK100M_AP_CONN_P
PCIE_CLK100M_AP_CONN_N
SMBUS_PCH_CLK
SMBUS_PCH_DATA
HDMI_IG_DDC_CLK
HDMI_IG_DDC_DATA
SMBUS_SMC_3_SCL
SMBUS_SMC_3_SDA
USB3RPCIE_SD_D2R_P
SDCONN_STATE_CHANGE_RIO
USB3RPCIE_SD_D2R_N
USB3RPCIE_SD_R2D_C_P
USB3RPCIE_SD_R2D_C_N
AP_PCIE_WAKE_L
TRUEHDMI_IG_CLK_C_P
TRUEHDMI_IG_CLK_C_N
TRUEHDMI_IG_DATA_C_P<0>
TRUEHDMI_IG_DATA_C_N<0>
HDMI_IG_DATA_C_P<1>
TRUE
TRUE
HDMI_IG_DATA_C_N<1>
HDMI_IG_DATA_C_P<2>
TRUE
HDMI_IG_DATA_C_N<2>TRUE
<BRANCH>
<SCH_NUM>
<E4LABEL>
95 OF 120
63 OF 78
8 47 59 60 61 63 65 68
32 33 46 55 56 57 60 62 65
66 68
18 29 34 37 38 42 60 64 65
68
8 47 59 60 61 63 65 68 www.rosefix.com

VCC
GND
SELOE*
D+
D-
Y+
Y-
M+
M-
BI
BI
BI
OUT
BI
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
BI
BI
IN
IN
NC
NC
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
BI
BI
BI
BI
SYM_VER_2
GS
D
THRM_PAD
VDD
GPIO(3)
GPI(2)
GPIO(4)
GPIO(6)
GPIO(5)
GPIO(12)
GPIO(11)
GPIO(9)
GPIO(10)
GND
GPIO(8)
NC
NC
NC
THRM
IO_3
IO_2
IO_4
VDD IO_8
IO_7
IO_6
GND
PAD
SYM_VER_2
GS
D
DDCDAT_B
DDCDAT_A
DDCDAT_C
DDCCLK_B
DDCCLK_A
DDCCLK_C
HPDB
HPDA
HPDC
DX_SEL AUX_SEL
DB3(P)
DA3(P)
DC3(P)
DB3(N)
DA3(N)
DC3(N)
DB2(P)
DA2(P)
DC2(P)
DB2(N)
DA2(N)
DC2(N)
DB1(P)
DA1(P)
DC1(P)
DB1(N)
DA1(N)
DC1(N)
DB0(P)
DA0(P)
DC0(P)
DB0(N)
DA0(N)
DC0(N)
AUXB(P)
AUXA(P)
AUXC(P)
AUXB(N)
AUXA(N)
AUXC(N)
VDD
OE
VDD
GND
GND
GND
GND
GND
GND
BI
BI
OUT
OUT
BI
IN
IN
IN
IN
IN
IN
IN
IN
IN
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
87 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
D
SIZEDRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
DESCRIPTION REFERENCE DES BOM OPTIONQTYPART NUMBER CRITICAL
DISP MUX SEL
SEL 0 = HDMI
SEL 1 = DP
SEL_L 1 = HDMI
DP 1:2 ANALOG DEMUX
TOWARDS PORTS
DISP MUX SEL
SEL 0 = HDMI
SEL 1 = DP
TOWARDS CPU
DISPLAY MUX: DP OR HDMI
SEL_L 0 = DP
DISP MUX SEL_L
PRIORITY 0 = HDMI WINS OVER DP
PRIORITY 1 = DP WINS OVER HDMI
AUX_SEL 0 = AUX ONLY
AUX_SEL 1 = DDC ONLY
AUX_SEL Vdd/2 = AUX & DDC
TOWARDS CPU
TOWARDS PORTS
NOTE: HDMI ML SWIZZLED INTENTIONALLY AS PER TABLE 9-1 HASWELL-ULT PDG
0.1UF
10V
20%
0402
X7R-CERM
C9751
1
2
0.1UF
16V
20%
0201
X6S-CERM
C9725
1
2
NO STUFF
SIGNAL_MODEL=MOJO_MUX
CRITICAL
PI3USB102ZLE
TQFN
U9725
6
7
3
4
5
8 10
9
2
1
MF
NO STUFF
1/20W
10K
5%
201
R9725
1
2
13 66 74
13 64 66
13 64 66
13 66
13 66 74
201
MF
1/20W
5%
10K
R9726
1
2
201
1/20W
5%
MF
10K
R9727
1
2
23 74
23 74
23 74
23 74
23 74
23 74
23 74
23 74
23 74
23 74
23 64
63 64
63 68 74
63 68 74
63 68 74
63 68 74
63 68 74
63 68 74
63 68 74
63 68 74
28 64
28 64
63 64
63 64
201
100K
MF
5%
1/20W
R9752
1
2
DFN1006H4-3
DMN32D2LFB4
Q9700 3
1
2
201
5%
MF
100K
1/20W
R9753
1
2
201
NOSTUFF
100K
MF
5%
1/20W
R9701
1
2
201
100K
5%
MF
1/20W
R9702
1
2
CRITICAL
SLG46400V
TDFN
NOSTUFF
U9775
7
2
10
11
12
3
4
5
6
8
9
13
1
CERM-X5R
0201
6.3V
0.1UF
10%
C9775
1
2
10%
0.1UF
6.3V
0201
CERM-X5R
C9700
1
2
SLG4APXXX
TDFN
OMIT_TABLE
U9700
5
2
3
4
6
7
8
9
1
100K
MF
5%
1/20W
201
R9754
1
2
NO STUFF
DFN1006H4-3
DMN32D2LFB4
Q9701 3
1
2
100K
NO STUFF
201
1/20W
5%
MF
R9755
1
2
BGA
HD3SS213ZQE
CRITICAL
U9750
C2
J9
H9
J6
H6
H1
H2
A4
B4
A5
B5
A6
B6
A9
A8
B9
B8
D9
D8
E9
E8
F9
F8
B1
B2
D1
D2
E1
E2
F1
F2
H8
H5
J3
J8
J5
J7
A1
B3
C8
G8
H4
H7
G2
J2
H3
J1
B7
A2
J4
63 64
28 64
0.1UF
20%
0402
X7R-CERM
10V
C9750
1
2
28 64
63 64
13 64 66
13 64 66
201
MF
1/20W
5%
510K
R9703
1
2
201
5%
MF
1/20W
510K
R9704
1
2
66 74
66 74
66 74
66 74
66 74
66 74
66 74
66 74
IC, SAK,AP4179,DP MUX CTRLR,TDFN-8343S0666 1 CRITICALU9700
Display Mux: HDMI vs DP
SYNC_DATE=08/12/2013SYNC_MASTER=J44
DISP_MUX_EN_L HDMITBTMUX_SEL_TBT
HDMI_IG_DDC_DATA DP_HDMI_TBT_DDC_DATA
DP_HDMI_TBT_DDC_CLK
DP_TBTSNK1_ML_C_N<0>
PP3V3_S0
DPMUX_HPD_OUT
DP_HDMI_TBT_AUX_N
DP_TBTSNK1_ML_C_P<3>
DP_TBTSNK1_ML_C_P<2>
DP_TBTSNK1_DDC_DATA
DPMUX_AUX_DDC_SEL
DP_HDMI_TBT_DDC_DATA
DP_HDMI_TBT_DDC_CLK
DP_HDMI_TBT_ML_N<3>
DP_TBTSNK1_ML_C_P<0>
DP_TBTSNK1_ML_C_N<3>
HDMI_IG_DATA_C_P<0>
HDMI_IG_CLK_C_N
HDMI_IG_DDC_CLK
HDMI_IG_DDC_DATA
DP_TBTSNK1_DDC_CLK
PP3V3_S0
DPMUX_AUX_DDC_SEL
HDMI_IG_DATA_C_N<1>
HDMI_IG_DATA_C_N<2>
DP_TBTSNK1_HPD
DP_TBTSNK1_AUXCH_C_N
DISP_MUX_EN
DISP_MUX_PRIORITY
PP3V3_S0
HDMI_HPD
HDMI_IG_DATA_C_N<0>
HDMI_IG_DATA_C_P<2>
DP_HDMI_TBT_ML_P<0>
DP_TBTSNK1_DDC_DATA
DP_HDMI_TBT_ML_P<3>
DP_HDMI_TBT_ML_N<2>
HDMI_IG_CLK_C_P
DP_HDMI_TBT_ML_P<2>
DP_TBTSNK1_ML_C_N<2>
HDMI_IG_DATA_C_P<1>
DP_TBTSNK1_ML_C_P<1>
DP_HDMI_TBT_ML_P<1>
DP_TBTSNK1_ML_C_N<1>
DP_HDMI_TBT_ML_N<1>
DP_HDMI_TBT_ML_N<0>
DP_TBTSNK1_AUXCH_C_P
DP_HDMI_TBT_AUX_P
PP3V3_S0
HDMITBTMUX_SEL_TBT
PP3V3_S0
DISP_MUX_EN
PP3V3_S0
DP_TBTSNK1_HPD
DISP_MUX_EN
HDMITBTMUX_SEL_TBT
HDMI_HPD
HDMITBTMUX_LATCH
HDMITBTMUX_FLAG_L
PP3V3_S0
DISP_MUX_SEL_L
HDMI_IG_DDC_CLK
DP_TBTSNK1_DDC_CLK
PP3V3_S0
DP_TBTSNK1_HPD
DISP_MUX_PRIORITY
HDMITBTMUX_LATCH
DISP_MUX_EN
PP3V3_S4
HDMI_HPD
HDMITBTMUX_FLAG_L
HDMITBTMUX_SEL_TBT
<BRANCH>
<SCH_NUM>
<E4LABEL>
97 OF 120
64 OF 78
15 23 64 66
8 11 12 13 15 17 18 24 28
30 37 38 39 40 41 42 43 44
46 47 50 61 62 64 65 68
77
64
8 11 12 13 15 17 18 24 28
30 37 38 39 40 41 42 43 44
46 47 50 61 62 64 65 68 77
64
64
64 8 11 12 13 15 17 18 24 28
30 37 38 39 40 41 42 43 44
46 47 50 61 62 64 65 68
77
8 11 12 13 15 17 18 24 28 30
37 38 39 40 41 42 43 44 46 47
50 61 62 64 65 68 77
15 23
64 66
8 11 12 13 15 17 18
24 28 30 37 38 39 40
41 42 43 44 46 47
50 61 62 64 65 68 77
64
8 11 12 13 15 17 18 24 28 30
37 38 39 40 41 42 43 44 46 47
50 61 62 64 65 68 77
23 64
64
15 23 64 66
63 64
13 64 66
15 64
8 11 12 13 15 17 18 24 28 30
37 38 39 40 41 42 43 44 46 47
50 61 62 64 65 68 77
8 11 12 13 15 17 18 24 28
30 37 38 39 40 41 42 43 44
46 47 50 61 62 64 65 68
77
23 64
64
13 64 66
64
18 29 34 37 38 42 60 63 65 68
63 64
15 64
15 23 64 66 www.rosefix.com

Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
87 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
D
SIZEDRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
1.5V/1.35V/1.05V RAILS
TBT RAILS (OFF WHEN NO CABLE)
Digital Ground
CPU "VCORE" RAILS
1.84A
? mA
3.3V Rails"G3Hot" (Always-Present) Rails
5V Rails
SYNC_DATE=08/12/2013
Power Aliases
SYNC_MASTER=J44
MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=5V
PP5V_S0
MAKE_BASE=TRUE
PP5V_S0
PP5V_S0
PP5V_S0
PP5V_S0
PP5V_S0
PP5V_S0
PP5V_S0
PP5V_S0
PP5V_S0
PP5V_S0
PP5V_S0
PP1V05_S0
VOLTAGE=1.05V
MAKE_BASE=TRUE
MIN_NECK_WIDTH=0.2 MM
MIN_LINE_WIDTH=0.2 MM
MIN_NECK_WIDTH=0.2 MM
MAKE_BASE=TRUE
PP3V42_G3H
VOLTAGE=3.42V
MIN_LINE_WIDTH=0.2 MM
PPVRTC_G3H
PP5V_S4
PP3V3_S4
PP3V3_S4
MAKE_BASE=TRUE
VOLTAGE=3.3VMIN_LINE_WIDTH=0.20MM
MIN_NECK_WIDTH=0.20MM
PP3V3_S4
PP3V3_S4
PP3V3_S4
PP3V3_S4
PP3V3_S4
PP3V3_S4
PP3V3_S5
MIN_NECK_WIDTH=0.20MM
VOLTAGE=3.3V
MAKE_BASE=TRUE
MIN_LINE_WIDTH=0.2 MM
PP3V3_S5
PP3V3_S5
PP3V3_S5
PP3V3_S5
PP3V3_S5
PP3V3_S5
PP3V3_S5
PP3V3_S5
PP3V3_SUS
PP3V3_S3
MIN_LINE_WIDTH=0.20MM
MIN_NECK_WIDTH=0.20MM VOLTAGE=3.3V
MAKE_BASE=TRUE
PPBUS_G3H
MAKE_BASE=TRUE
VOLTAGE=8.6V
MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.2 mm
PPBUS_S5_HS_COMPUTING
PPBUS_S5_HS_OTHER3V3
PPBUS_S5_HS_OTHER5V
PPBUS_S5_HS_COMPUTING
PPBUS_S5_HS_COMPUTING
VOLTAGE=5V
MIN_NECK_WIDTH=0.175 MM
MAKE_BASE=TRUE
PP5V_S4
MIN_LINE_WIDTH=0.2 MM
PP5V_S5
VOLTAGE=5V
PP5V_S5
MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.2 MM
MAKE_BASE=TRUE
PPVRTC_G3H
MAKE_BASE=TRUE
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=3V
MIN_LINE_WIDTH=0.2 MM
PP3V3_S3
PP3V3_SUS
MIN_LINE_WIDTH=0.20MM
MAKE_BASE=TRUE VOLTAGE=3.3V
MIN_NECK_WIDTH=0.20MM
PP3V3_S3
PP3V3_S0
PP3V42_G3H
PP3V3_S3
PP3V3_S3
PP3V42_G3H
PP3V3_S3
PP3V3_S3
PP1V05_S0
PP1V05_S0
PP1V05_S0
PP1V5_S0
PP1V5_S0
VOLTAGE=1.5V
MIN_NECK_WIDTH=0.17 mm
MAKE_BASE=TRUE
MIN_LINE_WIDTH=0.3 mm
PP1V05_S0
PP1V05_S0
PP1V35_S3
PP0V675_S0_DDRVTT
PP1V35_S3
PP1V35_S3
PP1V35_S3
PP1V35_S3
PP1V35_S3
MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.17 mm
VOLTAGE=1.35V
MAKE_BASE=TRUE
PP1V35_S3_CPUDDR
PP3V3_S3
PP3V3_S0
PP3V3_S0
PP3V3_S0
PP3V3_S0
PP3V3_S0
PP3V3_S0
PP3V3_S0
PP3V3_S0
PP3V3_S0
PP3V3_S0
PP3V3_S0
PP3V3_S0
PP3V3_S0
PP3V3_S0
PP3V3_S0
PP3V3_S0
PP3V3_S0
PP3V3_S0
PP3V3_S0
PP3V3_S0
PP3V3_S0
MIN_LINE_WIDTH=0.6 mm
MAKE_BASE=TRUE
VOLTAGE=8.6V
PPBUS_S5_HS_COMPUTING
MIN_NECK_WIDTH=0.25 mm
PPBUS_G3H
PPBUS_G3H
PP3V42_G3H
PP3V42_G3H
PP3V42_G3H
PP5V_S4
PP5V_S4
PP3V42_G3H
PP3V42_G3H
PP3V42_G3H
PPBUS_G3H
PPBUS_G3H
PP1V35_S3
PP3V3_SUS
PP3V3_SUS
PP3V3_SUS
MIN_NECK_WIDTH=0.25 mm
MAKE_BASE=TRUE
MIN_LINE_WIDTH=0.6 mm
PPBUS_S5_HS_OTHER5V
VOLTAGE=8.6V
PP15V_TBT
PP15V_TBT
MIN_NECK_WIDTH=0.20MM
MIN_LINE_WIDTH=0.5 MM
MAKE_BASE=TRUE
VOLTAGE=3.3V
PP3V3_S0SW_SSD
PP3V3_S4_TBT
PP3V3_SUS
PP3V3_S5
PP3V3_S5
PPDCIN_G3H_ISOL
PPDCIN_G3H_ISOL
PP3V3_S5
MIN_LINE_WIDTH=0.6 MM
VOLTAGE=18.5V
PPDCIN_G3H
MIN_NECK_WIDTH=0.25 MM
MAKE_BASE=TRUE
PP3V3_S5
PP3V3_S5
PP3V3_S0SW_SSD
VOLTAGE=3.3VMIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.20MM MAKE_BASE=TRUE
PP3V3_S0SW_SSD_FET
PP3V3_S0SW_SSD_FET
PP3V3_S0SW_SSD
PP3V3_S0SW_SSD_FET
MIN_NECK_WIDTH=0.25 mm
MAKE_BASE=TRUE
PPBUS_S5_HS_OTHER3V3
VOLTAGE=8.6V
MIN_LINE_WIDTH=0.6 mm
PPDCIN_G3H
PP0V675_S3_MEM_VREFCA_B
PP0V675_S3_MEM_VREFDQ_B
PP0V675_S3_MEM_VREFCA_B
VOLTAGE=0.6VMAKE_BASE=TRUE
PP0V675_S3_MEM_VREFDQ_B
VOLTAGE=0.6VMAKE_BASE=TRUE
PPBUS_G3H
PP3V3_S0
PP5V_S4
PPBUS_G3H
PPBUS_G3H
PP15V_TBT
PP1V05_S0
PP1V05_S0SW_PCH_HSIO
PPVCC_S0_CPU
PP1V05_S0SW_PCH_HSIO
PP1V05_S0SW_PCH_HSIO
PP1V05_S0
PP1V05_S0
PP1V05_S0
PP1V05_S0
PP1V05_S0
PP1V05_S0
PP1V05_S0SW_PCH_HSIO
MAKE_BASE=TRUE
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.05V
MIN_LINE_WIDTH=0.2 MM
PPVCC_S0_CPU
MAKE_BASE=TRUE
MIN_NECK_WIDTH=0.25 MM
VOLTAGE=1.8V
MIN_LINE_WIDTH=0.6 MM
VOLTAGE=12.8V
MIN_LINE_WIDTH=0.5 mm
PPVIN_SW_TBTBST
MIN_NECK_WIDTH=0.25 mm
PP0V675_S0_DDRVTT
PP0V675_S0_DDRVTT
PP1V5_S0
PP1V5_S0
PP1V5_S0
PP5V_S4
PP0V675_S3_MEM_VREFDQ_A
VOLTAGE=0.6V
PP0V675_S3_MEM_VREFDQ_A
MAKE_BASE=TRUE
VOLTAGE=0.6V
PP0V675_S3_MEM_VREFCA_A
MAKE_BASE=TRUE
PP0V675_S3_MEM_VREFCA_A
PP15V_TBT
VOLTAGE=15V
MAKE_BASE=TRUE
MIN_NECK_WIDTH=0.2 mm
MIN_LINE_WIDTH=0.4 mm
PP3V3_S4SW_SNS
PP1V35_S3_CPUDDR
MIN_LINE_WIDTH=0.5MM
MIN_NECK_WIDTH=0.2MM
VOLTAGE=1.35V
MAKE_BASE=TRUE
PP1V35_S3_CPUDDR
PP3V3_S0_FET
PP3V3_S0
PP5V_S0_FET
PPVTTDDR_S3
MAKE_BASE=TRUE
VOLTAGE=0.675V
MIN_LINE_WIDTH=0.3 MM
MIN_NECK_WIDTH=0.2 MM
PPVTTDDR_S3
PPBUS_S5_HS_COMPUTING
VOLTAGE=18.5V MAKE_BASE=TRUE
PPDCIN_G3H_ISOL
MIN_LINE_WIDTH=0.2 MM
MIN_NECK_WIDTH=0.2 MM
PP3V3_S4SW_SNS
PP1V05_SUS
MIN_NECK_WIDTH=0.2 MM
PP1V05_SUS
VOLTAGE=1.05V
MIN_LINE_WIDTH=0.4 MM
MAKE_BASE=TRUE
PP1V5_S0
MIN_NECK_WIDTH=0.20MM
PP3V3_S4SW_SNS
VOLTAGE=3.3V
MAKE_BASE=TRUE
MIN_LINE_WIDTH=0.20MM
PP3V3_S4SW_SNS
PP5V_S0_FET PP5V_S0_FET
MIN_LINE_WIDTH=0.5MM
MAKE_BASE=TRUE
MIN_NECK_WIDTH=0.2MM
VOLTAGE=5V
PP3V3_S0
PP3V3_S0
PP1V05_SUS
PP3V3_TBTLC
MAKE_BASE=TRUE
VOLTAGE=3.3V
PP3V3_TBTLC
MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
PP3V3_S4_TBT
MIN_LINE_WIDTH=0.5 MM
PP3V3_S4_TBT
VOLTAGE=3.3V
MAKE_BASE=TRUEMIN_NECK_WIDTH=0.20MM
PP3V3_S0_FET
VOLTAGE=3.3V
MIN_NECK_WIDTH=0.20MM
PP3V3_S0_FET
MIN_LINE_WIDTH=0.50MM
MAKE_BASE=TRUE
PP3V3_S0
PP3V3_S0
PP3V42_G3H
PP1V05_S0
PP1V5_S0
PPVCC_S0_CPU
PP1V35_S3
PP0V675_S0_DDRVTT
MIN_LINE_WIDTH=0.6 mm
MAKE_BASE=TRUE
MIN_NECK_WIDTH=0.17 mm
VOLTAGE=0.675V
PP3V3_SUS
PP3V3_S5
PP3V3_S5
PP3V3_S5
PP3V3_S5
PP3V3_S5
PP3V3_S5
PP3V3_S5
PP3V3_SUS
PP3V42_G3H
PP3V42_G3H
PP3V3_SUS
PP3V3_SUS
PP3V42_G3H
PP3V42_G3H
PPDCIN_G3H_ISOL
PPDCIN_G3H
PP5V_S5
PPVRTC_G3H
PP5V_S4
PP3V42_G3H
PP5V_S4
PP5V_S4
PP5V_S4
PP5V_S4
PP3V3_S0
PP3V3_S0
PP3V3_S3
PP3V3_S3
MAKE_BASE=TRUEMIN_NECK_WIDTH=0.20MM
PP3V3_S0
VOLTAGE=3.3VMIN_LINE_WIDTH=0.2 MM
GND
VOLTAGE=0V
MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM
<BRANCH>
<SCH_NUM>
<E4LABEL>
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65 OF 78
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61 65 68
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54 58 60 61 65 68
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61 65 68
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61 65 68
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53 54 58 60 61 65
68
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61 65 68
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61 65 68
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61 65 68
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65 68
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8 12 13
17 65
32 33 46 55 56 57
60 62 63 65 66 68
18 29 34 37 38 42 60 63 64 65
68
18 29 34 37 38 42 60 63 64 65
68
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68
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68
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68
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68
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68
18 29 34 37 38 42 60 63 64 65
68
8 11 13 15 16 17 18 26 27 29 56
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59 60 61 65 68 77
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66 68
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37 38 39 40 41 42 43 44 46 47
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68
77
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77
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77
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66 68
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36 37
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45 51
52 61
65 68
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52 58 65
68
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65 68
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65 68
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65 68
6 8 11 15 16 17 37 53 57 60 61
65 68
6 8 11 15 16 17 37 53 57 60 61
65 68
6 8 11 15 16 17 37 53 57 60 61
65 68
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8 10 42 54
65 68
25
22 55 65 68 73
22 55 65 68 73
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66 68
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65 68
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52 61 65 68
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8 11 14 45 59 60 61 65
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40 51
52 65
51 52
65 68
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52 61 65 68
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66 68
32 33 46 55 56 57 60 62 63 65
66 68
32 33 46 55 56 57 60 62 63 65
66 68
32 33 46 55 56 57 60 62 63 65
66 68
8
11
12
13 15 17 18 24 28 30 37 38 39
40
41 42 43 44 46 47 50 61 62
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77 www.rosefix.com

Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
124578
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NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
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PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
D
SIZEDRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
MEMORY ADDRESS/CTRL
EPD PANEL
MAKE_BASE
MAKE_BASE
HDMI VS TBT
MAKE_BASE
MAKE_BASE
Digital Ground
NO_TEST
MAKE_BASE
UNUSED SIGNALS
UNUSED MEMORY SIGNALS
MAKE_BASE
MAKE_BASE
MAKE_BASE
SM
XWA202
12
SM
XWA203
12
Signal Aliases
SYNC_DATE=MASTERSYNC_MASTER=MASTER
NC_SMC_TRST_LNO_TEST=TRUE
TRUE
NC_SMC_MD1NO_TEST=TRUE
TRUE
TRUE
NO_TEST=TRUE
NC_HDA_SDIN1
NC_SMC_MD1
NC_HDA_SDIN1
NC_SMC_TRST_L
NO_TEST=TRUE
TRUE NC_CLINK_CLK
TRUE
NO_TEST=TRUE NC_CLINK_RESET_L
TRUE
NO_TEST=TRUE NC_CLINK_DATA
NC_PCI_PME_L
NC_USB_IRP
NC_PCIE_CLK100M_ENETSDN
NC_PCIE_FW_D2RN
MEM_B_RAS_L
MEM_B_WE_L
MEM_B_CAS_L
=MEM_B_BA<0>
MEM_B_BA<1>
=MEM_B_BA<2>
TRUE
MEM_RESET_HSW_LMEM_RESET_HSW_L
MEM_B_BA<2>TRUE
MEM_B_BA<0>TRUE
MEM_A_CAS_L
=MEM_A_A<12>
MEM_B_A<0>TRUE
I2C_BKLT_SCL
=DP_TBTSNK1_ML_C_N<1>
=MEM_B_A<3>
=MEM_B_A<4>
MEM_B_A<6>TRUE
MEM_B_A<8>TRUE
TRUE
MEM_B_A<10>
HDMITBTMUX_SEL_TBT
TRUE DP_HDMI_TBT_AUX_P
=DP_TBTSNK1_ML_C_N<0>
=DP_TBTSNK1_ML_C_P<1>
=DP_TBTSNK1_ML_C_N<2>
=DP_TBTSNK1_ML_C_P<3>
=DP_TBTSNK1_ML_C_N<3>
DP_HDMI_TBT_AUX_N
DP_HDMI_TBT_DDC_DATA
DPMUX_HPD_OUT
HDMITBTMUX_SEL_TBT
MAKE_BASE=TRUE
I2C_BKLT_SDA
NC_PCIE_CLK100M_FWP
NO_TEST=TRUE NC_PCIE_FW_R2D_CPTRUE
NC_PCIE_CLK100M_ENETSDPTRUE
NO_TEST=TRUE
NO_TEST=TRUE
TRUE
NC_PCI_PME_L
MEM_B_A<3>TRUE
HDMITBTMUX_LATCH HDMITBTMUX_LATCH
MAKE_BASE=TRUE
HDMITBTMUX_SEL_TBT
MEM_A_A<13>TRUE
DPMUX_HPD_OUTTRUE
DP_HDMI_TBT_AUX_P
MEM_A_A<9>TRUE
MEM_A_A<10>TRUE
MEM_B_A<7>TRUE
MEM_A_WE_L
DP_HDMI_TBT_DDC_CLK
TRUE DP_HDMI_TBT_AUX_N
TRUE DP_HDMI_TBT_ML_P<2>
TRUE DP_HDMI_TBT_ML_N<0>
NC_MEM_A_CLKN<1>
MAKE_BASE=TRUE
TRUE
NC_MEM_B_CLKN<1>TRUE
MAKE_BASE=TRUE
NC_MEM_A_CKE<3>TRUE
MAKE_BASE=TRUE
NC_MEM_B_CKE<2>TRUE
MAKE_BASE=TRUE
NC_MEM_B_CKE<3>
MAKE_BASE=TRUE
TRUE
TRUE NC_USB_SDPNO_TEST=TRUE
NC_USB_SDN
TRUE MEM_B_BA<1>
NC_CLINK_RESET_L
NC_CLINK_DATA
NC_CLINK_CLK
NO_TEST=TRUE NC_USB_SDNTRUE
NC_USB_SDP
NC_USB_CAMERAP
NC_MEM_B_CLKP<1>TRUE
MAKE_BASE=TRUE
NC_PCIE_CLK100M_FWPTRUENO_TEST=TRUE
NC_PCIE_FW_R2D_CNNO_TEST=TRUETRUE
NC_PCIE_FW_D2RNNO_TEST=TRUETRUE
NC_PCIE_FW_D2RPNO_TEST=TRUETRUE
MEM_A_ODT_CPU0
NC_MEM_A_CLKN<1>
NC_MEM_A_CLKP<1>
TRUE
MAKE_BASE=TRUE
NC_MEM_A_CKE<2>TRUE
MAKE_BASE=TRUE
PP5V_S4
MIN_NECK_WIDTH=0.2MM
PP5V_S0_AUDIO_AMP_L
VOLTAGE=5V
MIN_LINE_WIDTH=0.6MM
MEM_B_CAS_LTRUE
TRUE
MEM_A_BA<2>
TRUE MEM_A_BA<1>
MEM_A_CAS_L
TRUE
MEM_A_BA<0>TRUE
MEM_A_WE_LTRUE
MEM_A_RAS_LTRUE
MEM_A_ODT_CPU0TRUE
MEM_B_A<14>TRUE
MEM_B_A<12>TRUE
MEM_B_A<11>TRUE
MEM_B_A<13>TRUE
MEM_B_A<4>TRUE
TRUE
MEM_B_A<5>
MEM_B_A<1>
TRUE
TRUE
MEM_B_A<2>
MEM_A_A<14>TRUE
MEM_A_A<8>TRUE
MEM_A_A<7>TRUE
TRUE
MEM_A_A<6>
TRUE MEM_A_A<5>
MEM_A_A<4>
TRUE
MEM_A_A<3>TRUE
MEM_A_A<2>TRUE
TRUE
MEM_A_A<0>
TRUE DP_HDMI_TBT_DDC_DATA
TRUE DP_HDMI_TBT_DDC_CLK
PP5V_S0_AUDIO_AMP_R
VOLTAGE=5V
MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM
=MEM_B_A<5>
MEM_B_A<6>
=MEM_B_A<7>
=MEM_B_A<10>
=MEM_B_A<9>
=MEM_B_A<13>
=MEM_B_A<11>
=MEM_B_A<12>
=MEM_B_A<14>
=MEM_A_BA<0>
MEM_A_BA<1>
=MEM_B_A<8>
MEM_B_A<9>TRUE
TRUE
MEM_B_WE_L
MEM_B_ODT_CPU0TRUEMEM_B_ODT_CPU0
TRUE DP_HDMI_TBT_ML_P<3>
TRUE DP_HDMI_TBT_ML_N<3>
MEM_A_A<1>TRUE
=DP_TBTSNK1_ML_C_P<2>
DP_HDMI_TBT_ML_N<1>TRUE
TRUE
DP_HDMI_TBT_ML_P<1>
TRUE DP_HDMI_TBT_ML_N<2>
NC_MEM_B_CLKP<1>
MEM_A_CKE<2>
NC_MEM_A_CLKP<1>
NC_MEM_B_CLKN<1>
NC_MEM_A_CKE<3>
NC_MEM_B_CKE<3>
TRUENO_TEST=TRUE NC_PCIE_CLK100M_FWN
MEM_B_RAS_LTRUE
=MEM_A_BA<2>
MEM_A_RAS_L
=DP_TBTSNK1_ML_C_P<0> DP_HDMI_TBT_ML_P<0>TRUE
NC_USB_IRN
NC_USB_CAMERAN TRUE
NO_TEST=TRUE NC_USB_CAMERAN
NC_USB_CAMERAP
NO_TEST=TRUE
TRUE
NC_USB_IRNTRUE
NO_TEST=TRUE
NO_TEST=TRUE
NC_USB_IRPTRUE
NO_TEST=TRUE
NC_PCIE_CLK100M_ENETSDNTRUE
NC_PCIE_CLK100M_ENETSDP
NC_PCIE_FW_R2D_CN
NC_PCIE_FW_R2D_CP
NC_PCIE_FW_D2RP
NC_PCIE_CLK100M_FWN
TRUE I2C_BKLT_SDA
TRUE I2C_BKLT_SCL
MEM_B_CKE<2>
=MEM_A_A<2>
=MEM_B_A<2>
=MEM_B_A<1>
=MEM_B_A<0>
MEM_A_A<12>
TRUE
MEM_A_A<11>TRUE
MEM_A_A<6>
=MEM_A_A<5>
=MEM_A_A<0>
=MEM_A_A<4>
=MEM_A_A<11>
=MEM_A_A<13>
=MEM_A_A<10>
=MEM_A_A<8>
=MEM_A_A<1>
=MEM_A_A<7>
=MEM_A_A<14>
=MEM_A_A<9>
=MEM_A_A<3>
MIN_NECK_WIDTH=0.2MM
GND
VOLTAGE=0V
MIN_LINE_WIDTH=0.6MM
<BRANCH>
<SCH_NUM>
<E4LABEL>
102 OF 120
66 OF 78
45 66
45 66
12 66
45 66
12 66
45 66
14 66
14 66
14 66
13 66
14 66 71
12 66
14 66
7 21 22 66
73
7 21 22 66
73
7 21 22 66
73
7
7
21 22 66
73
7
6
22 66 6 22 66
21 22 73
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7 20 22 66
73
7
21 22 73
58 62 66 68
5
7
7
7
21 22 66 73
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5
5
5
5
13 64 66 74
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73
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64 74
64 74
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7 66
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14 66 71
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14 66
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14 66
14 66
14 66
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68
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7 21 22 66 73
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64 74
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66
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14 66 71
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58 62 66 68
58 62 66 68
7
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7 www.rosefix.com

Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
124578
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D
87 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
D
SIZEDRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
MAKE_BASEMAKE_BASE
Memory Bit/Byte Swizzle
Memory Bit/Byte Swizzle
SYNC_DATE=01/03/2013SYNC_MASTER=J44
MEM_A_DQ<47>TRUE
TRUE
MEM_A_DQ<48>
TRUE MEM_A_DQ<50>
MEM_A_DQ<53>
TRUE
=MEM_A_DQ<51>
=MEM_A_DQ<49>
=MEM_A_DQ<2>
=MEM_A_DQ<1>
=MEM_A_DQ<6>
=MEM_A_DQ<4>MEM_A_DQ<59>
TRUE
MEM_A_DQ<60>TRUE
TRUE
MEM_A_DQ<61>
TRUE MEM_A_DQ<62>
MEM_A_DQ<23>
TRUE
MEM_A_DQ<29>TRUE
TRUE
MEM_A_DQ<34>
MEM_A_DQ<40>
TRUE
TRUE
MEM_A_DQ<41>
TRUE MEM_A_DQ<44>
=MEM_B_DQS_N<1>
=MEM_B_DQ<52>
=MEM_B_DQ<55>
=MEM_B_DQ<50>
=MEM_B_DQ<49>
=MEM_B_DQ<48>
=MEM_B_DQ<53>
=MEM_B_DQ<54>
=MEM_B_DQ<51>
TRUE MEM_B_DQ<56>
TRUE MEM_B_DQ<58>
TRUE MEM_B_DQ<59>
TRUE MEM_B_DQ<60>
TRUE MEM_B_DQ<61>
TRUE MEM_B_DQ<62>
TRUE MEM_B_DQ<52>
MEM_B_DQS_N<0>TRUE
MEM_B_DQS_P<0>TRUE
MEM_B_DQ<48>TRUE
MEM_B_DQ<42>TRUE
MEM_B_DQ<47>TRUE
=MEM_B_DQ<16>
=MEM_B_DQ<18>
=MEM_B_DQ<19>
=MEM_B_DQ<20>
=MEM_B_DQ<21>
=MEM_B_DQ<2>
MEM_A_DQ<14>
TRUE
MEM_A_DQ<15>TRUE =MEM_A_DQ<43>
=MEM_A_DQ<20>
=MEM_A_DQ<18>
=MEM_A_DQ<47>
MEM_A_DQ<11>TRUE
MEM_A_DQ<10>TRUE
MEM_A_DQ<9>TRUE
MEM_A_DQ<22>TRUE
MEM_A_DQ<24>TRUE
MEM_A_DQ<25>TRUE
TRUE
MEM_A_DQ<17>
MEM_A_DQ<12>
TRUE
TRUE
MEM_A_DQ<19>
MEM_A_DQ<0>TRUE
TRUE
MEM_A_DQ<1>
MEM_A_DQ<2>
TRUE =MEM_A_DQ<57>
=MEM_B_DQ<35>
=MEM_B_DQ<33>
=MEM_B_DQ<32>
=MEM_B_DQ<42>
=MEM_B_DQ<43>
=MEM_B_DQ<45>
=MEM_B_DQ<40>
MEM_B_DQ<32>
=MEM_B_DQ<47>
=MEM_B_DQ<46>
=MEM_B_DQ<17>
=MEM_B_DQ<23>
=MEM_B_DQ<22>
=MEM_B_DQ<0>
=MEM_B_DQ<7>
=MEM_B_DQ<4>
=MEM_B_DQ<3>
=MEM_B_DQ<6>
=MEM_B_DQ<1>
=MEM_B_DQ<5>
=MEM_B_DQ<31>
=MEM_B_DQ<8>
=MEM_B_DQ<14>
=MEM_B_DQ<9>
=MEM_B_DQ<12>
=MEM_B_DQ<10>
=MEM_B_DQ<15>
=MEM_B_DQ<13>
=MEM_B_DQ<11>
MEM_A_DQ<31>TRUE
TRUE
MEM_A_DQ<20> =MEM_A_DQ<17>
=MEM_A_DQ<25>
=MEM_A_DQ<31>
MEM_A_DQ<42>TRUE
TRUE
MEM_A_DQ<45>
TRUE MEM_A_DQ<46>
MEM_A_DQ<37>
TRUE
MEM_A_DQ<26>TRUE
=MEM_A_DQ<0>
=MEM_A_DQ<7>
=MEM_A_DQ<3>
=MEM_A_DQ<11>
=MEM_A_DQ<15>
=MEM_A_DQ<8>
=MEM_A_DQ<14>
=MEM_A_DQ<12>
MEM_A_DQS_N<2>TRUE
MEM_A_DQS_P<3>TRUE
MEM_A_DQS_N<4>TRUE
MEM_A_DQS_P<5>TRUE
MEM_A_DQS_N<5>TRUE
TRUE
MEM_A_DQS_P<6>
TRUE MEM_A_DQS_N<6>
MEM_A_DQS_P<7>
TRUE
MEM_A_DQS_N<7>TRUE
MEM_A_DQS_P<2>TRUE
=MEM_A_DQ<48>
=MEM_A_DQ<27>
MEM_A_DQ<32>
=MEM_A_DQ<26>
=MEM_A_DQ<30>
=MEM_A_DQ<24>
=MEM_A_DQ<16>
=MEM_A_DQ<21>
=MEM_A_DQ<22>
=MEM_A_DQ<19>
=MEM_A_DQ<23>
=MEM_A_DQ<33>
=MEM_A_DQ<38>
=MEM_A_DQ<37>
=MEM_A_DQ<35>
=MEM_A_DQ<39>
=MEM_A_DQ<36>
=MEM_A_DQ<32>
=MEM_A_DQ<34>
=MEM_A_DQ<46>
=MEM_A_DQ<42>
=MEM_A_DQ<41>
=MEM_A_DQ<40>
=MEM_A_DQ<63>
=MEM_A_DQ<58>
=MEM_A_DQ<62>
=MEM_A_DQ<61>
=MEM_A_DQ<56>
=MEM_A_DQ<59>
=MEM_A_DQ<60>
TRUE MEM_B_DQ<51>
MEM_B_DQ<50>
TRUE
TRUE
MEM_B_DQ<49>
TRUE MEM_B_DQ<34>
TRUE MEM_B_DQ<33>
MEM_B_DQ<32>
TRUE
MEM_B_DQ<31>TRUE
TRUE
MEM_B_DQ<14>
TRUE MEM_B_DQ<15>
TRUE MEM_B_DQ<16>
TRUE MEM_B_DQ<18>
TRUE MEM_B_DQ<19>
MEM_B_DQ<20>
TRUE
TRUE
MEM_B_DQ<22>
TRUE MEM_A_DQ<43>
TRUE MEM_A_DQ<51>
TRUE MEM_A_DQ<49>
=MEM_A_DQS_P<5>
=MEM_A_DQS_P<2>
=MEM_A_DQS_N<2>
=MEM_A_DQS_P<4>
=MEM_A_DQS_N<4>
=MEM_A_DQS_N<5>
=MEM_B_DQS_P<3>
MEM_B_DQS_P<6>
=MEM_B_DQS_N<7>
=MEM_B_DQS_N<5>
=MEM_B_DQS_P<5>
=MEM_B_DQS_N<2>
=MEM_B_DQS_N<0>
=MEM_B_DQS_P<2>
=MEM_B_DQS_N<3>
=MEM_B_DQS_P<0>
=MEM_B_DQS_N<6>
=MEM_B_DQS_P<6>
=MEM_B_DQS_P<7>
MEM_B_DQS_N<6>
MEM_B_DQ<0>TRUE
MEM_B_DQ<1>TRUE
TRUE
MEM_B_DQ<2>
MEM_B_DQ<5>
TRUE
MEM_B_DQ<6>TRUE
MEM_B_DQS_P<7>TRUE
MEM_B_DQS_P<6>TRUE
MEM_B_DQS_N<6>TRUE
MEM_B_DQS_N<1>TRUE
MEM_B_DQS_P<3>TRUE
MEM_B_DQS_P<4>TRUE
MEM_B_DQS_N<3>TRUE
MEM_B_DQS_N<4>TRUE
MEM_B_DQS_P<5>TRUE
MEM_B_DQS_N<5>TRUE
MEM_B_DQS_N<2>TRUE
MEM_B_DQS_P<1>TRUE
MEM_B_DQS_N<7>TRUE
MEM_B_DQ<8>TRUE
MEM_A_DQ<33>TRUE
TRUE
MEM_A_DQ<35>
TRUE MEM_B_DQ<13>
MEM_B_DQ<9>TRUE
MEM_A_DQ<54>TRUE
TRUE
MEM_A_DQ<39>
TRUE MEM_A_DQ<36>
TRUE MEM_A_DQ<27>
MEM_A_DQ<30>
TRUE
TRUE
MEM_A_DQ<18>
MEM_A_DQ<28>
TRUE
MEM_A_DQ<16>TRUE
MEM_A_DQ<21>TRUE
MEM_A_DQ<13>TRUE
TRUE
MEM_B_DQ<30>
TRUE MEM_B_DQ<29>
TRUE MEM_B_DQ<28>
TRUE MEM_B_DQ<27>
MEM_B_DQ<26>
TRUE
MEM_B_DQ<25>TRUE
MEM_B_DQ<24>TRUE
MEM_B_DQS_P<2>TRUE
TRUE
MEM_B_DQ<54>
MEM_B_DQ<55>
TRUE
TRUE
MEM_B_DQ<57>
TRUE MEM_B_DQ<53>
MEM_A_DQS_P<1>TRUE
MEM_A_DQS_N<1>TRUE
=MEM_A_DQ<29>
MEM_A_DQ<38>TRUE
=MEM_A_DQS_N<7>
=MEM_A_DQS_P<7>
=MEM_A_DQ<5>
=MEM_A_DQS_N<0>
=MEM_A_DQS_P<0>
MEM_A_DQS_N<6>
MEM_A_DQS_P<6>
=MEM_A_DQS_N<1>
=MEM_A_DQS_P<1>
=MEM_A_DQS_N<3>
=MEM_A_DQS_P<3>
MEM_A_DQS_N<3>TRUE
MEM_A_DQS_P<4>TRUE
MEM_A_DQS_N<0>TRUE
MEM_A_DQ<56>TRUE
MEM_A_DQ<32>TRUE
MEM_A_DQ<3>TRUE
TRUE
MEM_A_DQ<7>
MEM_A_DQ<6>
TRUE
MEM_A_DQ<5>TRUE
TRUE
MEM_A_DQ<4>
MEM_A_DQ<8>
TRUE
=MEM_A_DQ<45>
=MEM_A_DQ<44>
MEM_A_DQ<57>TRUE
MEM_A_DQ<55>TRUE
TRUE
MEM_A_DQ<52>
=MEM_A_DQ<10>
=MEM_A_DQ<9>
=MEM_A_DQ<13>
=MEM_A_DQ<53>
=MEM_A_DQ<55>
=MEM_A_DQ<50>
=MEM_A_DQ<54>
=MEM_A_DQ<52>
MEM_A_DQ<58>TRUE
TRUE
MEM_A_DQ<63>
MEM_A_DQS_P<0>TRUE =MEM_B_DQS_P<1>
TRUE MEM_B_DQ<12>
TRUE MEM_B_DQ<11>
MEM_B_DQ<4>TRUE
MEM_B_DQ<3>TRUE
TRUE
MEM_B_DQ<21>
TRUE MEM_B_DQ<17>
=MEM_B_DQ<25>
=MEM_B_DQ<26>
=MEM_B_DQ<28>
=MEM_B_DQ<27>
TRUE MEM_B_DQ<10> =MEM_B_DQ<29>
=MEM_B_DQ<30>
=MEM_B_DQ<24>
MEM_B_DQ<7>TRUE
MEM_B_DQ<41>TRUE
MEM_B_DQ<40>TRUE
MEM_B_DQ<23>TRUE
TRUE
MEM_B_DQ<63>
MEM_B_DQ<39>
TRUE
MEM_B_DQ<38>TRUE
=MEM_B_DQ<58>
=MEM_B_DQ<59>
=MEM_B_DQ<57>
=MEM_B_DQ<38>
=MEM_B_DQ<37>
=MEM_B_DQ<39>
=MEM_B_DQ<34>
=MEM_B_DQ<36>
=MEM_B_DQ<62>
=MEM_B_DQ<61>
=MEM_B_DQ<63>
=MEM_B_DQ<56>
=MEM_B_DQ<60>
=MEM_B_DQ<41>
MEM_B_DQ<37>TRUE
MEM_B_DQ<36>TRUE
MEM_B_DQ<35>TRUE
TRUE
MEM_B_DQ<46>
MEM_B_DQ<45>
TRUE
MEM_B_DQ<44>TRUE
MEM_B_DQ<43>TRUE
<BRANCH>
<SCH_NUM>
<E4LABEL>
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PP
PP
PP
PP
PP
PP
PP
PP
PP
PP
PP
PP
PP
PP
PP
PP
PP
PP
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
87 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
D
SIZEDRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
High Speed NO_TEST
Unused nets with offpage
Functional Test Points
J7715 (KBD BACKLIGHT CONN)
J4813 (KEY BOARD CONN)
U0500 CHARZ TPS
FUNC_TEST
J6050 (LEFT FAN CONN)
NO_TESTs
ICT Test Points
4 TPs
POWER RAILS
6 TPs
J4600 (LEFT USB CONN)
J6601 (2 MIC CONN)
J7050 (MAIN BATT CONN) (Nets with offpages not used on this project)
NC NO_TEST
J7000 (DC POWER CONN)
3 TPs
per Fan
J6100 (LPC + SPI CONN)
FUNC_TEST
FUNC_TEST
2 TP needed
J8300 (EDP CONN)
J6603 (AUDIO RIGHT SPEAKER CONN)
J6602 (AUDIO LEFT SPEAKER CONN)
J6601 (AUDIO 2-MIKE CONN)
J4002 (ALS/CAMERA CONN)
U5000 CHARZ TPS
J9500 (RIO POWER PINS)
J4800 (TPAD CONN)
SM
P2MM
PPA400
1
SM
P2MM
PPA401
1
SM
P2MM
PPA410
1
P2MM
SM
PPA411
1
SM
P2MM
PPA419
1
SM
P2MM
PPA423
1P2MM
SM
PPA424
1
P2MM
SM
PPA403
1
SM
P2MM
PPA402
1
P2MM
SM
PPA405
1
P2MM
SM
PPA404
1
P2MM
SM
PPA420
1
P2MM
SM
PPA421
1
P2MM
SM
PPA441
1P2MM
SM
PPA442
1
P2MM
SM
PPA443
1P2MM
SM
PPA444
1
PLACE_NEAR=U0500.AY10:6MM
P2MM
SM
PPA408
1
SYNC_MASTER=J44
Functional / ICT Test
SYNC_DATE=08/12/2013
I2C_CAM_SCKTRUE
I2C_CAM_SDATRUE
MIPI_DATA_P
WS_CONTROL_KBDTRUE
WS_LEFT_OPTION_KBDTRUE
WS_KBD19TRUE
WS_LEFT_SHIFT_KBDTRUE
MIPI_CLK_CONN_PTRUE
TRUE
WS_KBD18
WS_KBD22
TRUE
WS_KBD23TRUE
WS_KBD_ONOFF_LTRUE
MIPI_CLK_P
MIPI_DATA_CONN_NTRUE
PP1V5_S0TRUE
PP5V_S4TRUE
PP3V3_S4TRUE
CAM_SENSOR_WAKE_L_CONNTRUE
LPC_CLK24M_SMC
SMBUS_SMC_1_S0_SCLTRUE
TRUE
PPVOUT_S0_KBDBKLT
PPVBAT_G3H_CONNTRUE
TRUE
DMIC_SDA3
TRUE
DMIC_SDA2
TRUE DMIC_CLK3
TRUESPKRCONN_L_OUT_N
TRUESPKRCONN_L_OUT_P
TRUEPPVTTDDR_S3
PP3V42_G3HTRUE
PP3V3_S5
TRUE
PP3V3_S3
TRUE
PP3V3_S0TRUE
PP5V_S4TRUE
WS_KBD11TRUE
TRUE
WS_KBD10
TRUEWS_KBD9
TRUEWS_KBD8
TRUESMBUS_SMC_2_S3_SCL
TRUE PSOC_MISO
Z2_CS_LTRUE
PCIE_CAMERA_D2R_N
PCIE_CAMERA_D2R_P
SPKRCONN_SR_OUT_N
TRUE
TRUE
I2C_BKLT_SCL
TRUEI2C_BKLT_SDA
TRUELCD_HPD_CONN
DP_INT_ML_P<0>
TRUE
DP_INT_ML_P<2>TRUE
DP_INT_ML_N<2>TRUE
DP_INT_ML_P<3>TRUE
PPVOUT_S0_LCDBKLTTRUE
SMBUS_SMC_0_S0_SCLTRUE
SMBUS_SMC_0_S0_SDA
TRUE
DP_INT_ML_N<3>TRUE
DP_INT_ML_N<1>TRUE
DP_INT_ML_P<1>
TRUE
DP_INT_ML_N<0>
TRUE
DP_INT_AUX_N
TRUE
EDP_PANEL_PWR_OR_PSR_ENTRUE
DP_INT_AUX_PTRUE
EDP_BKLT_PWMTRUE
LCD_IRQ_LTRUE
TRUE
PP5VR3V3_SW_LCD
SPKRCONN_SR_OUT_PTRUE
SMC_TMSTRUE
SMC_RX_LTRUE
TRUE
SMC_ROMBOOT
SMC_RESET_L
TRUE
TRUE
SMC_TCK
TRUELPC_PWRDWN_L
TRUESMBUS_SMC_5_G3_SCL
PCIE_TBT_D2R_P<0>
TRUEWS_KBD4
PM_SLP_S3_LTRUE
TRUE
WS_KBD5
WS_KBD1
TRUE
TRUE
WS_KBD3
TRUEWS_KBD6
TRUEWS_KBD7
PP3V3_TPAD_CONNTRUE
TRUE
SMBUS_SMC_2_S3_SDA
TRUE PSOC_MOSI
TRUE Z2_SCLK
PSOC_SCLKTRUE
TRUE
Z2_CLKIN
PP5V_S4_CUMULUSTRUE
TRUE
TDM_ONEWIRE_MPM
WS_KBD20TRUE
TRUE
MEM_A_DQ<63..0>
TRUE
PPVTTDDR_S3
TBT_A_D2R_N<0>
TRUE
TBTAPWRSW_ISET_S0
TRUE
TBT_A_R2D_P<1..0>
TRUE
TRUE
TBT_A_R2D_N<1..0>
TBTBPWRSW_ISET_V3P3
TRUE
TBTBPWRSW_ISET_S0_R
TRUE
TBTBPWRSW_ISET_S3
TRUE
TBT_A_D2R_C_N<1>
TRUE
PCIE_TBT_D2R_N<0>
TRUEWS_KBD17
SPKRCONN_SL_OUT_NTRUE
SPKRCONN_R_IDTRUE
SPKRCONN_R_OUT_NTRUE
TBTAPWRSW_ISET_S3
TRUE
HDMI_IG_CLK_C_P
TRUE
SMC_TDOTRUE
TBT_B_D2R_N<1>
TRUE
TBT_B_D2R_C_N<1>
TRUEPP5V_S0TRUE
LPC_CLK24M_LPCPLUSTRUE
LPC_AD<0>TRUE
TRUE
LPC_AD<2>
LPC_AD<1>
TRUE
TRUE
XDP_LPCPLUS_GPIO
LPC_FRAME_LTRUE
TRUE
SPIROM_USE_MLB
PP3V42_G3HTRUE
TBT_B_R2D_N<1..0>
TRUE
SMC_ONOFF_LTRUE
TRUE
LPCPLUS_RESET_L
TRUESMC_TDI
PP3V3_S5_AVREF_SMCTRUE
PPVCC_S0_CPUTRUE
PP5V_S3RS0_ALSCAM_FTRUE
WS_KBD14TRUE
TRUE
FAN_LT_TACH
FAN_LT_PWMTRUE
PCIE_CLK100M_TBT_P
WS_KBD2TRUE
WS_KBD15_CAPTRUE
WS_KBD12TRUE
TRUE
ADAPTER_SENSE
TRUEPP18V5_DCIN_FUSE
SMBUS_PCH_DATATRUE
TRUE
SMBUS_PCH_CLK
WS_KBD16_NUMTRUE
KBDLED_CATHODE2TRUE
TRUE
MEM_B_DQ<63..0>
TBT_A_D2R_C_P<0>
TRUE
TBT_B_D2R_C_P<1>
TRUE
TRUE
SMBUS_SMC_5_G3_SDA
PM_CLKRUN_LTRUE
SYS_DETECT_LTRUE
TRUE
PM_SYSRST_L
SPKRCONN_R_OUT_PTRUE
PP5V_S3_LTUSB_A_FTRUE
USB_LT1_PTRUE
CON_DMIC_SDA1TRUE
USB_LT1_NTRUE
TRUE
PM_CLKRUN_L
NC_XDP_PCH_HOOK4
MAKE_BASE=TRUE
TRUE
TBT_B_R2D_P<1..0>
TRUE
TBT_B_R2D_C_N<1..0>
TRUE
HDMI_IG_CLK_C_N
TRUE
PP5V_S5TRUE
TBT_A_D2R_N<1>
TRUE
PCH_VSS_NCTF<19>TRUE
NC_AUD_MIC_INRP
NC_AUD_CODEC_MICBIAS
NC_XDP_PCH_HOOK5
TP_XDP_PCH_OBSFN_B<0>
NC_XDP_PCH_OBSFN_B<1>
TP_XDP_PCH_OBSFN_D<0>
NC_XDP_PCH_OBSFN_A<1>
NC_XDP_PCH_TRST_L
NC_XDP_PCH_OBSFN_D<1>
NC_1V05_S0_PCH_VCCAPLLEXP
NC_AUD_MIC_INRN
NC_XDP_PCH_HOOK4
CON_DMIC_PWRTRUE
TBTAPWRSW_ISET_V3P3
TRUE
TBT_B_R2D_C_P<1..0>
TRUE
NC_AUD_MIC_INRN
MAKE_BASE=TRUE
TRUE
LPC_SERIRQTRUE
NC_XDP_PCH_HOOK5
MAKE_BASE=TRUE
TRUE
NC_XDP_PCH_OBSFN_B<0>
MAKE_BASE=TRUE
TRUE
NC_XDP_PCH_OBSFN_B<1>
MAKE_BASE=TRUE
TRUE
NC_XDP_PCH_OBSFN_A<0>
MAKE_BASE=TRUE
TRUE
NC_XDP_PCH_OBSFN_D<0>
MAKE_BASE=TRUE
TRUE
NC_XDP_PCH_OBSFN_A<1>
MAKE_BASE=TRUE
TRUE
NC_XDP_PCH_TRST_L
MAKE_BASE=TRUE
TRUE
NC_XDP_PCH_OBSFN_D<1>
MAKE_BASE=TRUE
TRUE
NC_1V05_S0_PCH_VCCAPLLEXP
MAKE_BASE=TRUE
TRUE
NC_AUD_CODEC_MICBIAS
MAKE_BASE=TRUE
TRUE
NC_AUD_MIC_INRP
MAKE_BASE=TRUE
TRUE
TRUE
TBT_A_D2R_C_P<1>
TRUELPC_AD<3>
HDMI_IG_DATA_C_P<2..0>
TRUE
PPBUS_G3HTRUE
PCIE_AP_R2D_PTRUE
PCIE_AP_R2D_NTRUE
TRUE
PCH_VSS_NCTF<19>
CON_DMIC_CLKTRUE
SMC_TX_LTRUE
HDMI_IG_DATA_C_N<2..0>
TRUE
TP_XDP_PCH_OBSFN_A<0>
HDD_PWR_EN
BT_PWRRST_L
TBT_B_D2R_N<0>
TRUE
TBT_B_D2R_P<1>
TRUE
TBT_B_D2R_P<0>
TRUE
PCIE_AP_D2R_NTRUE
TRUE
PCIE_AP_D2R_P
TBT_B_D2R_C_N<0>
TRUE
TBT_B_D2R_C_P<0>
TRUE
TBT_A_D2R_P<0>
TRUE
TBT_A_D2R_P<1>
TRUE
TBT_A_D2R_C_N<0>
TRUE
TBT_A_R2D_C_N<1..0>
TRUE
TBT_A_R2D_C_P<1..0>
TRUE
TBTAPWRSW_ISET_S3_R
TRUE
PP5V_S0TRUE
FW_PWR_EN
FW_PME_L
ENET_MEDIA_SENSE
ODD_PWR_EN_L
ENET_LOW_PWR
AUD_IP_PERIPHERAL_DET
AUD_I2C_INT_L
AUD_IPHS_SWITCH_EN
ENETSD_CLKREQ_L
WS_KBD13TRUE
PP5V_S0TRUE
PCIE_CLK100M_TBT_N
PCIE_SSD_D2R_N<0>
PCIE_SSD_D2R_P<0>
PP3V42_G3HTRUE
PP3V3_S4TRUE
HDA_SDIN0
SPKRCONN_L_IDTRUE
SPKRCONN_SL_OUT_PTRUE
TRUE
KBDLED_CATHODE1
TRUE PSOC_F_CS_L
TRUE Z2_KEY_ACT_L
TRUE Z2_HOST_INTN
TRUE PICKB_L
Z2_MOSI
TRUE
Z2_MISOTRUE
MIPI_CLK_CONN_NTRUE
USB3RPCIE_SD_D2R_N
PCIE_AP_D2R_P
PCIE_AP_D2R_N
USB3RPCIE_SD_D2R_P
MIPI_DATA_N
MIPI_CLK_N
TRUESMBUS_SMC_1_S0_SDA
PP1V05_S0TRUE
PP0V675_S0_DDRVTTTRUE
NC_PM_SLP_A_L TRUE NC_PM_SLP_A_L
MAKE_BASE=TRUE
WOL_EN
WS_KBD21TRUE
TRUE
USB3_EXTA_R2D_C_N
PCIE_AP_R2D_C_P
TRUE
TRUE
PCIE_AP_D2R_P
TRUE
PCIE_AP_R2D_C_N
TRUE
PCIE_AP_D2R_N
TRUE
PCIE_SSD_R2D_C_P<3..0>
TRUE
PCIE_SSD_R2D_C_N<3..0>
TRUE
PCIE_SSD_R2D_P<3..0>
TRUE
PCIE_SSD_R2D_N<3..0>
TRUE
PCIE_SSD_D2R_P<3..0>
TRUE
PCIE_TBT_R2D_C_P<3..0>
TRUE
PCIE_TBT_R2D_C_N<3..0>
PCIE_SSD_D2R_N<3..0>
TRUE
USB3_EXTA_R2D_C_P
TRUE
PCIE_CLK100M_SSD_P
TRUE
PCIE_CLK100M_SSD_N
TRUE
PCIE_CLK100M_TBT_P
TRUE
PCIE_CLK100M_AP_P
TRUE
TRUE
PCIE_CLK100M_CAMERA_P
TRUE
PCIE_CLK100M_CAMERA_N
PCIE_CLK100M_AP_N
TRUE
PCIE_CLK100M_TBT_N
TRUE
PPDCIN_G3HTRUE
TRUE
PCIE_TBT_R2D_P<3..0>
PCIE_TBT_R2D_N<3..0>
TRUE
TRUE
PCIE_TBT_D2R_P<3..1>
PCIE_TBT_D2R_N<3..1>
TRUE
PCIE_TBT_D2R_C_P<3..1>
TRUE
PCIE_TBT_D2R_C_N<3..1>
TRUE
USB3_EXTA_R2D_N
TRUE
USB3_EXTA_R2D_N
TRUE
USB3_EXTB_R2D_C_N
TRUE
USB3_EXTB_R2D_C_P
TRUE
TRUE
USB3_EXTA_D2R_N
TRUE
USB3_EXTA_D2R_P
TRUE
USB3_EXTB_D2R_P
USB3_EXTB_D2R_N
TRUE
MIPI_DATA_CONN_PTRUE
GNDTRUE
TRUE
GND
TRUEGND
GND
TRUE
GNDTRUE
GNDTRUE
GNDTRUE
<BRANCH>
<SCH_NUM>
<E4LABEL>
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48 50 77
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53 54 58 60 61 65 68
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48 50 77
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63 64 74
34 56 65
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23 27 74
68
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14 36 45 72
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63 70
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12 30 68 70
12 30 68 70
17 30 33 34 36 37 38 39 45 51
52 61 65 68
18 29 34 37 38 42 60
63 64 65 68
12 47 72
47 50
48 50 77
35 58
34
34
34
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14 63 71
14 63 68 70
14 63 68 70
14 63 71
31
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31
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14 32 36 39 43 72
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6 8 11 15 16 17 37 53 57 60 61
65
22 55 65 73
13 68
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14 63 70
14 63 68 70
14 63 70
14 63 68 70
12 30 70
12 30 70
30 70
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14 23 70
14 23 70
12 30 68 70
14 33 71
12 30 70
12 30 70
12 23 68 70
12 63 70
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12 32 70
12 63 70
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51 52 65
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32 75 www.rosefix.com

TABLE_BOARD_INFO
VERSION
ALLEGRO(MIL or MM)
BOARD UNITS
BOARD LAYERS BOARD AREAS
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
87 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
D
SIZEDRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
MINIMUM LINE WIDTH
ALLOW ROUTE
ON LAYER?
LAYER MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
MINIMUM LINE WIDTH
ALLOW ROUTE ON LAYER?
LAYER MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
MINIMUM LINE WIDTH
ALLOW ROUTE
ON LAYER?
LAYER MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
PHYSICAL_RULE_SETAREA_TYPENET_PHYSICAL_TYPE
TABLE_PHYSICAL_ASSIGNMENT_HEAD
TABLE_SPACING_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
MINIMUM LINE WIDTH
ALLOW ROUTE
ON LAYER?
LAYER MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
MINIMUM LINE WIDTH
ALLOW ROUTE ON LAYER?
LAYER MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
MINIMUM LINE WIDTH
ALLOW ROUTE
ON LAYER?
LAYER MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
MINIMUM LINE WIDTH
ALLOW ROUTE
ON LAYER?
LAYER MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_RULE_ITEM
AREA_TYPE SPACING_RULE_SETNET_SPACING_TYPE1 NET_SPACING_TYPE2
TABLE_SPACING_ASSIGNMENT_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_SPACING_RULE_ITEM
LINE-TO-LINE SPACINGLAYERSPACING_RULE_SET WEIGHT
TABLE_SPACING_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
LINE-TO-LINE SPACINGLAYERSPACING_RULE_SET WEIGHT
TABLE_SPACING_RULE_HEAD
TABLE_PHYSICAL_ASSIGNMENT_ITEM
TABLE_PHYSICAL_RULE_ITEM
LINE-TO-LINE SPACINGLAYERSPACING_RULE_SET WEIGHT
TABLE_SPACING_RULE_HEAD
TABLE_SPACING_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
MINIMUM LINE WIDTH
ALLOW ROUTE
ON LAYER?
LAYER MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_SPACING_RULE_ITEM
MINIMUM LINE WIDTH
ALLOW ROUTE
ON LAYER?
LAYER MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
MINIMUM LINE WIDTH
ALLOW ROUTE ON LAYER?
LAYER MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
MINIMUM LINE WIDTH
ALLOW ROUTE ON LAYER?
LAYER MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
MINIMUM LINE WIDTH
ALLOW ROUTE ON LAYER?
LAYER MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
J44 BOARD-SPECIFIC SPACING & PHYSICAL CONSTRAINTS
Stackup-Defined Spacing Rules
Inner dielectric is 0.053 mm nominal.
Note: Outer dielectric is 0.058 mm nominal,
?0.075 MM*P075_SPACE
P072_SPACE
* 0.071 MM ?
*Y
=STANDARD =STANDARD =STANDARD 0.1 MM 0.1 MM1TO1_DIFFPAIR
P65_BGA *Y 0.071MM 0.071MM 0.126MM0.075MM
90_OHM_DIFFTOP,BOTTOM Y 0.101 MM 0.101 MM 0.180 MM 0.180 MM
72_OHM_DIFFTOP,BOTTOM Y 0.146 MM 0.146 MM 0.120 MM 0.120 MM
80_OHM_DIFF Y 0.120 MM0.120 MM0.092 MM0.092 MMISL3,ISL4,ISL9,ISL10
80_OHM_DIFFTOP,BOTTOM Y 0.155 MM0.155 MM0.125 MM0.125 MM
ISL2,ISL5,ISL6,ISL7,ISL8,ISL11 0.101 MM ?1X_DIELECTRIC
*85_OHM_DIFF N =STANDARD =STANDARD =STANDARD =STANDARD =STANDARD
80_OHM_DIFFISL2,ISL11 Y 0.120 MM0.120 MM0.092 MM0.092 MM
80_OHM_DIFF *N =STANDARD=STANDARD=STANDARD=STANDARD=STANDARD
85_OHM_DIFF Y 0.080 MM 0.080 MM 0.120 MM 0.120 MMISL3,ISL4,ISL9,ISL10
85_OHM_DIFFISL2,ISL11 Y 0.080 MM 0.080 MM 0.120 MM 0.120 MM
DEFAULT * 0.1 MM ?
72_OHM_DIFFISL2,ISL11 Y 0.105 MM 0.105 MM 0.120 MM 0.120 MM
P65BGA P65_BGA*
37_OHM_SE *Y 0.118 MM 0.090 MM =STANDARD =STANDARD=STANDARD
*1:1_SPACING 0.1 MM ?
85_OHM_DIFFTOP,BOTTOM Y 0.105 MM 0.105 MM 0.125 MM 0.125 MM
STANDARD
* =DEFAULT ?
* * P65BGA
P075_SPACE
* * BGA P072_SPACE
TOP,BOTTOM
0.058 MM ?1x_DIELECTRIC
TOP,BOTTOM37_OHM_SE Y 0.165 MM 0.095 MM
90_OHM_DIFF *N =STANDARD =STANDARD =STANDARD =STANDARD =STANDARD
72_OHM_DIFF N* =STANDARD =STANDARD =STANDARD =STANDARD =STANDARD
72_OHM_DIFF Y 0.105 MM 0.105 MM 0.120 MM 0.120 MMISL3,ISL4,ISL9,ISL10
45_OHM_SE *Y 0.083 MM 0.083 MM =STANDARD =STANDARD=STANDARD
27P4_OHM_SETOP,BOTTOM Y 0.265 MM 0.095 MM
27P4_OHM_SE *Y 0.186 MM 0.090 MM =STANDARD =STANDARD =STANDARD
0.053 MM ?1x_DIELECTRIC ISL3,ISL4,ISL9,ISL10
90_OHM_DIFFISL2,ISL11 Y 0.078 MM 0.078 MM 0.200 MM 0.200 MM
90_OHM_DIFF Y 0.078 MM 0.078 MM 0.200 MM 0.200 MMISL3,ISL4,ISL9,ISL10
40_OHM_SE *Y 0.102 MM 0.090 MM =STANDARD =STANDARD =STANDARD
40_OHM_SE
TOP,BOTTOM Y 0.145 MM 0.095 MM
50_OHM_SE *Y 0.066 MM 0.066 MM =STANDARD =STANDARD =STANDARD
50_OHM_SE
TOP,BOTTOM Y 0.095 MM 0.095 MM
STANDARD
*Y =DEFAULT =DEFAULT 10 MM =DEFAULT=DEFAULT
SYNC_DATE=08/12/2013SYNC_MASTER=J44
PCB Rule Definitions
DEFAULT *Y 10 MM 0 MM 0 MM =45_OHM_SE =45_OHM_SE
TOP,BOTTOM45_OHM_SE Y 0.116 MM 0.116 MM
NO_TYPE,BGA,P65BGA,BGA_MEM MM 16.5TOP,ISL2,ISL3,ISL4,ISL5,ISL6,ISL7,ISL8,ISL9,ISL10,ISL11,BOTTOM
<BRANCH>
<SCH_NUM>
<E4LABEL>
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TABLE_SPACING_ASSIGNMENT_ITEM
AREA_TYPE SPACING_RULE_SETNET_SPACING_TYPE1 NET_SPACING_TYPE2
TABLE_SPACING_ASSIGNMENT_HEAD
TABLE_SPACING_RULE_ITEM
MINIMUM LINE WIDTH
ALLOW ROUTE
ON LAYER?
LAYER MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
LINE-TO-LINE SPACINGLAYERSPACING_RULE_SET WEIGHT
TABLE_SPACING_RULE_HEAD
TABLE_SPACING_RULE_ITEM
LINE-TO-LINE SPACINGLAYERSPACING_RULE_SET WEIGHT
TABLE_SPACING_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
MINIMUM LINE WIDTH
ALLOW ROUTE ON LAYER?
LAYER MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
LINE-TO-LINE SPACINGLAYERSPACING_RULE_SET WEIGHT
TABLE_SPACING_RULE_HEAD
TABLE_SPACING_RULE_ITEM
LINE-TO-LINE SPACINGLAYERSPACING_RULE_SET WEIGHT
TABLE_SPACING_RULE_HEAD
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEMTABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
87 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
D
SIZEDRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
PCI Express Constraints
CPU Signal Constraints
NET TYPE
CPU Signal Properties PCI Express Properties
PHYSICAL
ELECTRICAL CONST SET
NET TYPE
PHYSICAL
SPACING
ELECTRICAL CONST SET
SPACING
CPU & PCIe Constraints
SYNC_DATE=08/12/2013SYNC_MASTER=J44
=7X_DIELECTRICPCIECLK_2OTHER ?*
PCIE_2OTHER TOP,BOTTOM ?=6X_DIELECTRIC
TOP,BOTTOMPCIE_TXRX ?=10X_DIELECTRIC
* PCIE_2CLKCLK_*PCIE_*
PCIECLK_2OTHER**CLK_PCIE
PCIE_2SAME TOP,BOTTOM ?=4X_DIELECTRIC
=7X_DIELECTRIC
?*PCIE_2CLK TOP,BOTTOMPCIE_2CLK ?=10X_DIELECTRIC
PCIECLK_2OTHERTOP,BOTTOM ?=10X_DIELECTRIC
?*0.305 MMCPU_12MIL
CPU_27P4S
* =27P4_OHM_SE =27P4_OHM_SE 7 MIL 7 MIL=27P4_OHM_SE=27P4_OHM_SE
* PCIE_TXRX*_RXPCIE_TX
PCIE_2SAME*=SAMEPCIE_*
=4X_DIELECTRIC ?*PCIE_2OTHER
=3X_DIELECTRICPCIE_2SAME ?*
*PCIE_*
PCIE_2OTHER*
PCIE_TXRX =6X_DIELECTRIC ?*
?*
CPU_18MIL 0.457 MM
CPU_25MIL 0.635 MM ?*
=45_OHM_SE =STANDARD=STANDARD*CPU_45S =45_OHM_SE =45_OHM_SE =45_OHM_SE
*CPU_VCCSENSE 25 MIL ?
=85_OHM_DIFF=85_OHM_DIFFCLK_PCIE_85D * =85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF=85_OHM_DIFF
=85_OHM_DIFF
PCIE_85D =85_OHM_DIFF =85_OHM_DIFF=85_OHM_DIFF=85_OHM_DIFF=85_OHM_DIFF*
CPU_08MIL *? 0.203 MM
* PCIE_TXRX*_TXPCIE_RX
PCIE_SSD_D2R_PP PCIE_SSD_D2R_P<0>PCIE_85D PCIE_RX
PCIE_SSD_D2R_PP PCIE_SSD_D2R_N<0>PCIE_85D PCIE_RX
PCIE_SSD_D2R_N<3..1>PCIE_SSD_D2R PCIE_RXPCIE_85D
PCIE_SSD_D2R_P<3..1>PCIE_SSD_D2R PCIE_RXPCIE_85D
CPU_45S PCH_JTAGXXDP_TCK0 CPU_18MIL
PCIE_85D PCIE_RXPCIE_CAMERA_D2R PCIE_CAMERA_D2R_N
PCIE_CAMERA_D2R_C_PPCIE_CAMERA_D2R PCIE_85D PCIE_RX
CPU_45S
XDP_CPU_TDOXDP_TDO
XDP_PREQ_L CPU_45S XDP_CPU_PREQ_L
PCIE_TBT_D2R PCIE_85D PCIE_RX PCIE_TBT_D2R_N<3..1>
PCIE_TBT_D2R_0 PCIE_TBT_D2R_P<0>PCIE_RXPCIE_85D
PCIE_TBT_D2R
PCIE_TBT_D2R_C_P<3..1>PCIE_RXPCIE_85D
PCIE_CLK100M_AP_CONN_PCLK_PCIEPCIE_CLK100M_AP CLK_PCIE_85D
PCIE_TBT_D2R_0 PCIE_TBT_D2R_N<0>PCIE_85D PCIE_RX
CPU_45S
XDP_CPU_TDIXDP_TDI
PCIE_SSD_R2D_C_P<3..0>PCIE_TXPCIE_85DPCIE_SSD_R2D
PCIE_SSD_R2D_C_N<3..0>PCIE_TXPCIE_85DPCIE_SSD_R2D
PCIE_SSD_R2D_P<3..0>PCIE_TXPCIE_85DPCIE_SSD_R2D
CPU_45S XDP_PCH_TDIXDP_TDI
CPU_45S
XDP_CPU_TMSXDP_TMS
CPU_45S
XDP_PCH_TMSXDP_TMS
CPU_45S
XDP_PCH_TDOXDP_TDO
CPU_45S
XDP_PCH_TCKXDP_TCK1 CPU_18MIL
XDP_CPU_TCKCPU_45SXDP_TCK0 CPU_18MIL
PCIE_CLK100M_SSD CLK_PCIE_85D CLK_PCIE PCIE_CLK100M_SSD_N
PCIE_CLK100M_CAM CLK_PCIE_85D CLK_PCIE PCIE_CLK100M_CAMERA_C_N
PCIE_CLK100M_TBT CLK_PCIE_85D CLK_PCIE PCIE_CLK100M_TBT_P
PCIE_AP_R2D PCIE_85D PCIE_TX PCIE_AP_R2D_C_P
PCIE_AP_R2D PCIE_85D PCIE_TX PCIE_AP_R2D_C_N
PCIE_AP_R2D PCIE_85D PCIE_TX PCIE_AP_R2D_P
PCIE_CAMERA_D2R_C_NPCIE_RXPCIE_85DPCIE_CAMERA_D2R
PCIE_85D PCIE_TXPCIE_TBT_R2D PCIE_TBT_R2D_N<3..0>
PCIE_AP_R2D PCIE_85D PCIE_TX PCIE_AP_R2D_N
PCIE_TBT_R2D PCIE_85D PCIE_TX PCIE_TBT_R2D_P<3..0>
PCIE_TBT_D2R_C_N<3..1>PCIE_TBT_D2R PCIE_85D PCIE_RX
PCIE_85D PCIE_TXPCIE_TBT_R2D PCIE_TBT_R2D_C_P<3..0>
PCIE_TBT_R2D PCIE_85D PCIE_TX PCIE_TBT_R2D_C_N<3..0>
CLK_PCIE_85D CLK_PCIEPCIE_CLK100M_AP PCIE_CLK100M_AP_N
CLK_PCIE_85D CLK_PCIEPCIE_CLK100M_SSD PCIE_CLK100M_SSD_P
PCIE_TXPCIE_CAMERA_R2D PCIE_85D PCIE_CAMERA_R2D_N
PCIE_85D PCIE_TXPCIE_CAMERA_R2D PCIE_CAMERA_R2D_P
PCIE_85DPCIE_CAMERA_D2R PCIE_RX PCIE_CAMERA_D2R_P
CLK_PCIE_85D CLK_PCIEPCIE_CLK100M_CAM PCIE_CLK100M_CAMERA_N
CLK_PCIE_85D CLK_PCIEPCIE_CLK100M_CAM PCIE_CLK100M_CAMERA_P
CLK_PCIE_85D CLK_PCIEPCIE_CLK100M_CAM PCIE_CLK100M_CAMERA_C_P
PCIE_CLK100M_TBT CLK_PCIE_85D CLK_PCIE PCIE_CLK100M_TBT_N
PCIE_85D PCIE_TXPCIE_SSD_R2D PCIE_SSD_R2D_N<3..0>
XDP_PRDY_L CPU_45S XDP_CPU_PRDY_L
XDP_TRST_LXDP_TRST_L CPU_45S
CPU_45S
XDP_CPUPCH_TRST_LXDP_TRST_L
PCIE_85D PCIE_TXPCIE_CAMERA_R2D PCIE_CAMERA_R2D_C_P
PCIE_CAMERA_R2D PCIE_85D PCIE_TX PCIE_CAMERA_R2D_C_N
PCIE_AP_D2R PCIE_85D PCIE_RX PCIE_AP_D2R_N
PCIE_CLK100M_AP_CONN_NCLK_PCIE_85D CLK_PCIEPCIE_CLK100M_AP
PCIE_CLK100M_AP_PCLK_PCIE_85D CLK_PCIEPCIE_CLK100M_AP
PCIE_TBT_D2R_0 PCIE_RX PCIE_85D PCIE_TBT_D2R_C_P<0>
PCIE_85D PCIE_RXPCIE_TBT_D2R_0PCIE_TBT_D2R_C_N<0>
PCIE_TBT_D2R PCIE_85D PCIE_RX PCIE_TBT_D2R_P<3..1>
PCIE_AP_D2R PCIE_85D PCIE_RX PCIE_AP_D2R_P
CPU_27P4S CPU_25MIL MCP_EDP_RCOMPCPU_RCOMP_EDP
CPU_27P4S CPU_OPI_RCOMPCPU_12MILCPU_RCOMP_OPI
CPU_25MILCPU_27P4S CPU_SM_RCOMP<2..0>CPU_RCOMP_SM
CPU_45S CPU_PROCHOT_LCPU_PROCHOT CPU_08MIL
CPU_45SCPU_PROCHOT CPU_PROCHOT_R_LCPU_08MIL
CPU_45S CPU_CATERR_LCPU_CATERR CPU_08MIL
CPU_CFG_PD CPU_45S CPU_CFG<1..0>
CPU_MEM_RESET CPU_08MIL MEM_RESET_LCPU_45S
CPU_VCCSENSE CPU_27P4S CPU_VCCSENSECPU_VCCSENSE_N
CPU_VCCSENSE CPU_27P4S CPU_VCCSENSECPU_VCCSENSE_P
CPU_45S CPU_VCCST_PWRGDCPU_VCCST_PWRGD CPU_08MIL
CPU_VIDSOUT CPU_18MIL CPU_VIDSOUT_RCPU_45S
CPU_18MILCPU_VIDSOUT CPU_VIDSOUTCPU_45S
CPU_VIDSCLK_RCPU_18MILCPU_45SCPU_VIDSCLK
CPU_45SCPU_VIDSCLK CPU_18MIL CPU_VIDSCLK
CPU_18MIL CPU_VIDALERT_R_LCPU_45SCPU_VIDALERT
CPU_VIDALERT
CPU_18MIL CPU_VIDALERT_LCPU_45S
CPU_45S
XDP_BPM_L<7..2>CPU_BPM_TP
CPU_45S CPU_08MILCPU_BPM XDP_BPM_L<1..0>
CPU_08MILCPU_VCCST_PWRGD CPU_45S XDP_CPU_VCCST_PWRGD
CPU_45S CPU_CFG<4>CPU_CFG_PD
CPU_45SCPU_CFG_PD CPU_CFG<10..8>
CPU_CFG CPU_45S CPU_CFG<19..11>
CPU_PECI CPU_18MIL CPU_PECI_RCPU_45S
CPU_PECICPU_PECI CPU_18MILCPU_45S
CPU_PECI_SMC CPU_18MIL SMC_PECI_LCPU_45S
CPU_45S
CPU_CFG<2>CPU_CFG
CPU_45S
CPU_CFG_3 CPU_CFG<3>
CPU_45SCPU_CFG CPU_CFG<7..5>
CPU_PECI_SMC CPU_18MIL SMC_PECI_L_RCPU_45S
<BRANCH>
<SCH_NUM>
<E4LABEL>
111 OF 120
70 OF 78
12 30 68
12 30 68
12 30 68
12 30 68
12 16
14 32 68
31 32
6 16
6 16
14 23 68
14 23 68
23 68
63
14 23 68
6 16
12 30 68
12 30 68
30 68
12 16
6 16
12 16
12 16
12 16
6 16
12 30 68
31 32
12 23 68
14 63 68
14 63 68
63 68
31 32
23 68
63 68
23 68
23 68
14 23 68
14 23 68
12 63 68
12 30 68
31 32
31 32
14 32 68
12 32 68
12 32 68
31 32
12 23 68
30 68
6 16
16
6 12 16
14 32
14 32
14 63 68
63
12 63 68
23
23
14 23 68
14 63 68
5
6
6
6
36 37 53
6
6
36
6 16
20 21 22
9 53
8 53
8 16 17
8
8
53
8
8
53
8
8
53
6 16
6 16
16
6 16
6 16
6 16
36 37
6 37
36 37
6 16
6 16
6 16
37 www.rosefix.com

TABLE_PHYSICAL_RULE_ITEM
TABLE_SPACING_RULE_ITEM
MINIMUM LINE WIDTH
ALLOW ROUTE
ON LAYER?
LAYER MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
MINIMUM LINE WIDTH
ALLOW ROUTE ON LAYER?
LAYER MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
LINE-TO-LINE SPACINGLAYERSPACING_RULE_SET WEIGHT
TABLE_SPACING_RULE_HEAD
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_SPACING_RULE_ITEM
LINE-TO-LINE SPACINGLAYERSPACING_RULE_SET WEIGHT
TABLE_SPACING_RULE_HEAD
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
AREA_TYPE SPACING_RULE_SETNET_SPACING_TYPE1 NET_SPACING_TYPE2
TABLE_SPACING_ASSIGNMENT_HEAD
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
LINE-TO-LINE SPACINGLAYERSPACING_RULE_SET WEIGHT
TABLE_SPACING_RULE_HEAD
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
LINE-TO-LINE SPACINGLAYERSPACING_RULE_SET WEIGHT
TABLE_SPACING_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_RULE_ITEM
LINE-TO-LINE SPACINGLAYERSPACING_RULE_SET WEIGHT
TABLE_SPACING_RULE_HEAD
MINIMUM LINE WIDTH
ALLOW ROUTE ON LAYER?
LAYER MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
MINIMUM LINE WIDTH
ALLOW ROUTE ON LAYER?
LAYER MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
LINE-TO-LINE SPACINGLAYERSPACING_RULE_SET WEIGHT
TABLE_SPACING_RULE_HEAD
LINE-TO-LINE SPACINGLAYERSPACING_RULE_SET WEIGHT
TABLE_SPACING_RULE_HEAD
AREA_TYPE SPACING_RULE_SETNET_SPACING_TYPE1 NET_SPACING_TYPE2
TABLE_SPACING_ASSIGNMENT_HEAD
TABLE_SPACING_RULE_ITEM
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
87 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
D
SIZEDRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
This is here to keep the SATA rules.
Notes:
SPACINGPHYSICAL
NET TYPE
ELECTRICAL CONST SET
USB Constraints
USB 3 Interface Constraints
USB 2 Interface Constraints
SATA Interface Constraints (Not Used)
System Clock Signal Constraints
I330
I331
USB Constraints
SYNC_DATE=08/12/2013SYNC_MASTER=J44
CLK_25M * =5x_DIELECTRIC ?
?
=4x_DIELECTRICTOP,BOTTOMSATA_2SAME
* USB3_TXRX*_RXUSB3_TX
* USB3_2SAME=SAMEUSB3_*
=STANDARD=STANDARD=STANDARD=STANDARD=STANDARD=STANDARD*PCH_USB_RBIAS
USB_RBIAS * =6X_DIELECTRIC ?
USB *
=4X_DIELECTRIC ?
=85_OHM_DIFF =85_OHM_DIFF=85_OHM_DIFF=85_OHM_DIFF=85_OHM_DIFF=85_OHM_DIFF*USB_85D
?=3X_DIELECTRIC*USB3_2SAME
** USB3_2OTHERUSB3_*
*
USB3_TXRX*_TXUSB3_RX
USB3_TXRX TOP,BOTTOM=10X_DIELECTRIC ?
USB
TOP,BOTTOM=6X_DIELECTRIC ?
=4X_DIELECTRIC ?*SATA_2OTHER
=6X_DIELECTRIC ?*SATA_TXRX
=3X_DIELECTRIC ?*SATA_2SAME
?=10X_DIELECTRICTOP,BOTTOMSATA_TXRX
=85_OHM_DIFF =85_OHM_DIFF=85_OHM_DIFF=85_OHM_DIFF=85_OHM_DIFF=85_OHM_DIFF*SATA_85D
?=6X_DIELECTRIC*USB3_TXRX
?=4X_DIELECTRIC*USB3_2OTHER
*_TX * SATA_TXRXSATA_RX
*_RX * SATA_TXRXSATA_TX
SATA_* * * SATA_2OTHER
SATA_* =SAME * SATA_2SAME
=45_OHM_SE
=45_OHM_SE =45_OHM_SE=45_OHM_SE=45_OHM_SE=45_OHM_SE*SATA_45SE
USB_RBIAS
TOP,BOTTOM=10X_DIELECTRIC ?
TOP,BOTTOMUSB3_2SAME=4x_DIELECTRIC ?
USB3_2OTHER TOP,BOTTOM=6X_DIELECTRIC ?
=85_OHM_DIFF=85_OHM_DIFF =85_OHM_DIFF=85_OHM_DIFF=85_OHM_DIFF=85_OHM_DIFF*USB3_85D
?=6X_DIELECTRICTOP,BOTTOMSATA_2OTHER
=STANDARDCLK_25M_45S * =45_OHM_SE =45_OHM_SE =STANDARD=45_OHM_SE =45_OHM_SE
USB_NC USBUSB_85D NC_USB_CAMERAN
USB_NC USBUSB_85D NC_USB_CAMERAP
USB_85D USBUSB_NC NC_USB_SDP
USB_85D USBUSB_NC NC_USB_SDN
TP_USB_5NUSB_NC USBUSB_85D
NC_USB_IRNUSB_NC USBUSB_85D
USB_NC USBUSB_85D TP_USB_5P
NC_USB_IRPUSB_NC USBUSB_85D
USB3RPCIE_SD_R2D_C_NUSB3_SD_R2D USB3_TXUSB3_85D
USB3RPCIE_SD_R2D_C_PUSB3_SD_R2D USB3_TXUSB3_85D
USB3RPCIE_SD_D2R_NUSB3_SD_D2R USB3_RXUSB3_85D
USB3RPCIE_SD_D2R_PUSB3_SD_D2R USB3_RXUSB3_85D
USB_EXTA
USB_85D USB USB2_EXTA_MUXED_P
SYSCLK_CLK25M_CAM CLK25M_CAM_CLKPCLK_25M_45S CLK_25M
SYSCLK_CLK25M_CAM SYSCLK_CLK25M_CAMERACLK_25MCLK_25M_45S
SYSCLK_CLK25M SYSCLK_CLK25M_X2CLK_25MCLK_25M_45S
SYSCLK_CLK25M SYSCLK_CLK25M_X2_RCLK_25MCLK_25M_45S
SYSCLK_CLK25M SYSCLK_CLK25M_X1CLK_25MCLK_25M_45S
CLK25M_CAM_CLKNSYSCLK_CLK25M_CAM CLK_25M_45S CLK_25M
CLK25M_CAM_XTALNSYSCLK_CLK25M_CAM CLK_25M_45S CLK_25M
SYSCLK_CLK25M_TBT_RCLK_25M_45S CLK_25MSYSCLK_CLK25M_TBT
SYSCLK_CLK25M_TBTCLK_25M_45S CLK_25MSYSCLK_CLK25M_TBT
CLK25M_CAM_XTALPSYSCLK_CLK25M_CAM CLK_25M_45S CLK_25M
CLK25M_CAM_XTALP_RSYSCLK_CLK25M_CAM CLK_25M_45S CLK_25M
SATA_85D SATA_TX DUMMY_SATA_R2D_P
USB_85D USB3_RXUSB3_EXTA_D2R USB3_EXTA_D2R_P
USB3_TXUSB_85DUSB3_EXTA_R2D USB3_EXTA_R2D_P
USB2_EXTA_MUXED_F_PUSB_85D USBUSB_EXTA
USB_85D USBUSB_EXTA USB2_EXTA_MUXED_F_N
USB_85D USB3_TXUSB3_EXTA_R2D USB3_EXTA_R2D_C_P
USB_85D USBUSB_BT USB_BT_CONN_P
SATA_85D SATA_TX DUMMY_SATA_R2D_N
SATA_85D SATA_RX DUMMY_SATA_D2R_N
SATA_85D SATA_RX DUMMY_SATA_D2R_P
PCH_USB_RBIAS USB_RBIASPCH_USB_RBIAS PCH_USB_RBIAS
USB3_RX USB3_EXTA_D2R_NUSB_85DUSB3_EXTA_D2R
USB_85D USBUSB_BT USB_BT_N
USB_85D USBUSB_BT USB_BT_P
USB_85D USBUSB_BT USB_BT_CONN_N
USB_EXTB_PUSB_EXTB USBUSB_85D
USB_LT1_NUSB_EXTA USBUSB_85D
USB_EXTB_NUSB_EXTB USBUSB_85D
USB3_EXTB_D2R_PUSB3_EXTB_D2R USB3_RXUSB_85D
USB_85D USB3_TX
USB3_EXTB_R2D USB3_EXTB_R2D_C_P
USB3_EXTB_D2R USB3_EXTB_D2R_NUSB3_RXUSB_85D
USB_85D USB3_TX
USB3_EXTB_R2D USB3_EXTB_R2D_C_N
USB_EXTA USB_85D USB USB2_EXTA_MUXED_N
USB_85D USB3_TXUSB3_EXTA_R2D USB3_EXTA_R2D_C_N
USB_85D USB3_TXUSB3_EXTA_R2D USB3_EXTA_R2D_N
USB_LT1_PUSB_EXTA USBUSB_85D
DEFAULT DEFAULT
SMC_DEBUGPRT_TX_L
USB_EXTA USB_85D USB USB_EXTA_P
USB_EXTA USB_85D USB USB_EXTA_N
DEFAULT DEFAULT SMC_DEBUGPRT_RX_L
USB_TPAD_PUSB_TPAD USBUSB_85D
USBUSB_85D USB_TPAD_NUSB_TPAD
USB_TPAD_R_NUSB_85D USBUSB_TPAD
USB_TPAD_R_PUSB_TPAD USB_85D USB
<BRANCH>
<SCH_NUM>
<E4LABEL>
112 OF 120
71 OF 78
14 66
14 66
14 66
14 66
14
14 66
14
14 66
14 63
14 63
14 63 68
14 63 68
33
31 32
17 32
17
17
17
31 32
32
23
17 23
32
32
14 33 68
33
33
33
14 33 68
29 63
14
14 33 68
14 29
14 29
29 63
14 63
68
14 63
14 63 68
14 63 68
14 63 68
14 63 68
33
14 33 68
33 68
68
33 36 37
14 33
14 33
33 36 37
14 34
14 34
34
34 www.rosefix.com

TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
LINE-TO-LINE SPACINGLAYERSPACING_RULE_SET WEIGHT
TABLE_SPACING_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
LINE-TO-LINE SPACINGLAYERSPACING_RULE_SET WEIGHT
TABLE_SPACING_RULE_HEAD
MINIMUM LINE WIDTH
ALLOW ROUTE
ON LAYER?
LAYER MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
MINIMUM LINE WIDTH
ALLOW ROUTE ON LAYER?
LAYER MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
TABLE_SPACING_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
LINE-TO-LINE SPACINGLAYERSPACING_RULE_SET WEIGHT
TABLE_SPACING_RULE_HEAD
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
LINE-TO-LINE SPACINGLAYERSPACING_RULE_SET WEIGHT
TABLE_SPACING_RULE_HEAD
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
MINIMUM LINE WIDTH
ALLOW ROUTE
ON LAYER?
LAYER MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
LINE-TO-LINE SPACINGLAYERSPACING_RULE_SET WEIGHT
TABLE_SPACING_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
MINIMUM LINE WIDTH
ALLOW ROUTE ON LAYER?
LAYER MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
MINIMUM LINE WIDTH
ALLOW ROUTE ON LAYER?
LAYER MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
87 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
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A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
D
SIZEDRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
LPC Bus Constraints
PCH Net Properties
SPACING
NET TYPE
PHYSICAL
ELECTRICAL CONST SET
PCH Single Net Constraints
SPI Interface Constraints
HD Audio Interface Constraints
SMBus Interface Constraints
SYNC_DATE=08/12/2013SYNC_MASTER=J44
PCH Constraints
CLK_LPC_45S * =45_OHM_SE =45_OHM_SE =45_OHM_SE =STANDARD =STANDARD=45_OHM_SE
=STANDARD=45_OHM_SE=45_OHM_SE=45_OHM_SEHDA_45S * =45_OHM_SE =STANDARD
SPI_45S * =45_OHM_SE =45_OHM_SE =STANDARD =STANDARD=45_OHM_SE =45_OHM_SE
?HDA * =2x_DIELECTRIC
LPC * 6 MIL ?
SMB ?*
=2x_DIELECTRIC
SPI 8 MIL*?
SMB_45S * =45_OHM_SE =45_OHM_SE =STANDARD=45_OHM_SE =STANDARD=45_OHM_SE
CLK_LPC * 8 MIL ?
PCH_45S * =45_OHM_SE =45_OHM_SE =45_OHM_SE =STANDARD =STANDARD=45_OHM_SE
LPC_45S * =45_OHM_SE =45_OHM_SE =STANDARD =STANDARD=45_OHM_SE =45_OHM_SE
* =27P4_OHM_SE =27P4_OHM_SE 7 MIL 7 MIL=27P4_OHM_SE=27P4_OHM_SEPCH_27P4S
*?PCH_20MIL 0.508 MM
PCH_12MIL 0.305 MM*?
?*
0.381 MMPCH_15MIL
PCH_18MIL
0.457 MM ?*
SPI_45S SPI SPI_IO<2>SPI_MLB_IO2
SPI_SMC_MOSISPISPI_45SSPI_MLB
SPI_MOSI_RSPISPI_45SSPI_MLB
SPI_45S
SPI SPI_IO<3>SPI_MLB_IO3
SPISPI_45S SPIROM_HOLD_LSPI_MLB_IO3
SPI_45S SPI SPIROM_USE_MLBSPI_MLB_IO3
SPI_45S SPI SPIROM_WP_LSPI_MLB_IO2
SPI_MOSISPISPI_45SSPI_MLB
SPI_MLB_MOSISPISPI_45SSPI_MLB
PCH_SATA_RCOMPPCH_12MILPCH_27P4SPCH_RCOMP_SATA
PCH_OPI_COMPPCH_12MILPCH_27P4SPCH_RCOMP_OPI
PCH_PCIE_RCOMPPCH_12MILPCH_27P4SPCH_RCOMP_PCIE
PCH_CLK24M_XTALOUT_RPCH_45S PCH_20MILPCH_CLK24M_XTAL
PCH_CLK24M_XTALOUTPCH_45S PCH_20MILPCH_CLK24M_XTAL
PCH_CLK24M_XTAL
PCH_20MIL PCH_CLK24M_XTALINPCH_45S
PCH_15MIL TBT_CIO_PLUG_EVENT_LPCH_45S
PCH_45S
PCH_15MIL CAM_PCIE_WAKE_L
PCH_45S PCIE_WAKE_LPCH_15MIL
PCH_45S PCH_15MIL AP_PCIE_WAKE_L
PCH_45S XDP_CPU_PWRBTN_LPCH_15MIL
PCH_45S PCH_15MIL PM_PWRBTN_L
PCH_45S PM_DSW_PWRGDPCH_15MIL
PCH_45S SMC_DELAYED_PWRGDPCH_15MIL
PCH_45S PM_S0_PGOODPCH_15MIL
PCH_45S PCH_15MIL SYS_PWROK_R
PCH_45S PCH_15MIL PM_PCH_PWROK
PCH_45S XDP_SYS_PWROKPCH_15MIL
PCH_45S PM_PCH_SYS_PWROKPCH_15MIL
PCH_45S XDP_DBRESET_LPCH_15MIL
PCH_45S PCH_15MIL PM_SYSRST_L
PCH_45S PM_RSMRST_LPCH_15MIL
PCH_45S PCH_15MIL PCH_DSWVRMEN
PCH_45S PCH_INTVRMENPCH_15MIL
PCH_45S PCH_INTRUDER_LPCH_15MIL
PCH_45S PCH_18MILPCH_THRMTRIP PM_THRMTRIP_L
PCH_45S PCH_18MIL PM_THRMTRIP_R_LPCH_THRMTRIP
PCH_45S PCH_15MIL RTC_RESET_LPCH_RTCRST
PCH_RTCX PCH_CLK32K_RTCX1PCH_15MILPCH_45S
PCH_45S
PCH_15MILPCH_SRTCRST PCH_SRTCRST_L
SMB_45S SMB SMBUS_SMC_1_S0_SDA
SPI_45S SPI SPI_ALT_MISOSPI_MLB
HDA_45S
HDAHDA_SDIN HDA_SDIN0
SPI_45S SPISPI_MLB SPI_CS0_R_L
SPI_45S SPISPI_MLB SPI_SMC_MISO
HDA_45S HDAHDA_RST HDA_RST_R_L
SPI_45S SPISPI_MLB SPI_SMC_CS_L
SPI_45S SPISPI_MLB SPI_ALT_MOSI
SPI_45S SPISPI_MLB SPI_MLB_MISO
SPI_45S SPISPI_MLB SPI_MISO_R
SPI_45S SPISPI_MLB SPI_MISO
SPI_45S SPI SPI_MLB_CS_LSPI_MLB
SPI_45S
SPISPI_MLB SPI_ALT_CS_L
SPI_45S SPISPI_MLB SPI_CS0_L
SPI_45S SPI SPI_CLKSPI_MLB
SPI_45S
SPI SPI_ALT_CLKSPI_MLB
SPI_45S
SPI SPI_CLK_RSPI_MLB
SPI_45S
SPI SPI_SMC_CLKSPI_MLB
SPI_45S
SPI SPI_MLB_CLKSPI_MLB
HDA_45S
HDAHDA_RST HDA_RST_L
HDA_45S HDAHDA_SDIN CS4208_HDA_SDOUT0_R
HDA_45S HDAHDA_SDOUT HDA_SDOUT
HDA_45S HDAHDA_SDOUT HDA_SDOUT_R
HDA_45S HDAHDA_BIT_CLK HDA_BIT_CLK_R
LPC_AD LPC_45S LPC_FRAME_LLPC
LPC_45SLPC_AD LPC_AD<3..0>LPC
HDA_45S HDAHDA_BIT_CLK HDA_BIT_CLK
HDA_45S HDAHDA_SYNC HDA_SYNC
HDA_45S HDAHDA_SYNC HDA_SYNC_R
SMB_45S SMBSMBUS_PCH SMBUS_PCH_DATA
SMB_45S SMBSMBUS_PCH SMBUS_PCH_CLK
LPC_CLK24M_SMC_RCLK_LPC_45SLPC_CLK24M_SMC CLK_LPC
LPC_CLK24M_SMCCLK_LPC_45S CLK_LPCLPC_CLK24M_SMC
CLK_LPC_45S CLK_LPCLPC_CLK24M_LPCPLUS LPC_CLK24M_LPCPLUS
LPC_CLK24M_LPCPLUS_RCLK_LPC_45SLPC_CLK24M_LPCPLUS CLK_LPC
SMB_45S
SMB SML_PCH_0_CLKSML_PCH_0
SMB_45S SMB SML_PCH_0_DATASML_PCH_0
SMB_45S SMB SMBUS_SMC_1_S0_SCL
<BRANCH>
<SCH_NUM>
<E4LABEL>
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72 OF 78
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36 45
14 45
14 45
45
15 45 68
45
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31
13 29 31
29 63
16
13 16 36
13 36
17 24 25 36 37
17
17
13 17
16
13 16 17 36
16 17
13 17 36 68
13 61
13
12
12
15 37
37
12
12 17
12
14 32 36 39 43 68 76
45
12 47 68
14 45
36 45
12
36 45
45
45
45
14 45
45
45
45
45
45
14 45
36 45
45
12 47
47
12 47
12 17
12
14 36 45 68
14 36 45 68
12 47
12 47
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14 16 19 39 63 68
14 16 19 39 63 68
12 17
17 36 68
17 45 68
12 17
14 39
14 39
14 32 36 39 43 68 76 www.rosefix.com

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TABLE_SPACING_RULE_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
AREA_TYPE SPACING_RULE_SETNET_SPACING_TYPE1 NET_SPACING_TYPE2
TABLE_SPACING_ASSIGNMENT_HEAD
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
AREA_TYPE SPACING_RULE_SETNET_SPACING_TYPE1 NET_SPACING_TYPE2
TABLE_SPACING_ASSIGNMENT_HEAD
TABLE_PHYSICAL_RULE_ITEM
AREA_TYPE SPACING_RULE_SETNET_SPACING_TYPE1 NET_SPACING_TYPE2
TABLE_SPACING_ASSIGNMENT_HEAD
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
AREA_TYPE SPACING_RULE_SETNET_SPACING_TYPE1 NET_SPACING_TYPE2
TABLE_SPACING_ASSIGNMENT_HEAD
TABLE_SPACING_ASSIGNMENT_ITEM
AREA_TYPE SPACING_RULE_SETNET_SPACING_TYPE1 NET_SPACING_TYPE2
TABLE_SPACING_ASSIGNMENT_HEAD
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TABLE_SPACING_ASSIGNMENT_ITEM
AREA_TYPE SPACING_RULE_SETNET_SPACING_TYPE1 NET_SPACING_TYPE2
TABLE_SPACING_ASSIGNMENT_HEAD
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_RULE_ITEM
LINE-TO-LINE SPACINGLAYERSPACING_RULE_SET WEIGHT
TABLE_SPACING_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
LINE-TO-LINE SPACINGLAYERSPACING_RULE_SET WEIGHT
TABLE_SPACING_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
MINIMUM LINE WIDTH
ALLOW ROUTE
ON LAYER?
LAYER MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
87 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
D
SIZEDRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
Spacing Rule Sets
SPACING
DDR3 Signal Group Unit Min Length Max Length
CTL to CLK mils CLK - 500 CLK + 500
CMDi to CMDj mils CMDj - 100 CMDj + 100
CMD to CLK mils CLK - 500 CLK + 500
(DQmax - DQmin) per byte mils 0 250
(DQS - DQmax) per byte mils -100 150
DQS to DQS# mils -5 5
DQS to CLK (Rule 1) mils CLK - 6500 CLK + 500
Max(CLK-DQS) - Min(CLK-DQS) mils 0 5500
Haswell ULT Memory Down DDR3L 1x8 Length Matching
Memory to Power Spacing
Memory to GND Spacing
CLK to CLK# mils -5 5
CTLmax - CTLmin mils 0 100
Memory Bus Spacing Group Assignments
Memory Bus Constraints
PHYSICAL
NET TYPE
Memory Net Properties
ELECTRICAL CONST SET
I146
SYNC_MASTER=J44
Memory Constraints
SYNC_DATE=01/03/2013
=80_OHM_DIFF =80_OHM_DIFFMEM_80D * =80_OHM_DIFF =80_OHM_DIFF =80_OHM_DIFF=80_OHM_DIFF
=85_OHM_DIFF=85_OHM_DIFFMEM_85D * =85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF
** MEM_2OTHERMEM_CTL
=40_OHM_SE =STANDARD =STANDARD*MEM_40S =40_OHM_SE =40_OHM_SE=40_OHM_SE
=72_OHM_DIFF*MEM_72D =72_OHM_DIFF =72_OHM_DIFF =72_OHM_DIFF=72_OHM_DIFF =72_OHM_DIFF
=45_OHM_SE =45_OHM_SE* =45_OHM_SE =STANDARD =STANDARDMEM_45S =45_OHM_SE
MEM_CMD2CTL_BM ?*=2x_DIELECTRIC
*MEM_CTL MEM_CTL MEM_CTL2CTL
MEM_A_DQS_0
* MEM_DQS2OWNDATAMEM_A_DQBYTE_0
BGA_MEMMEM_CTL MEM_CTL MEM_CTL2CTL_BM
MEM_CMD BGA_MEMMEM_CTL MEM_CMD2CTL_BM
MEM_CMD
*MEM_CTL MEM_CMD2CTL
MEM_CMD MEM_CMD * MEM_CMD2CMD
MEM_* MEM_* * MEM_2OTHERMEM
MEM_CMD ** MEM_2OTHER
MEM_*_DQS_* ** MEM_2OTHER
MEM_2OTHER
**MEM_*_DQBYTE_*
MEM_B_DQS_7 * MEM_DQS2OWNDATAMEM_B_DQBYTE_7
MEM_B_DQS_4 * MEM_DQS2OWNDATAMEM_B_DQBYTE_4
MEM_B_DQS_5 * MEM_DQS2OWNDATAMEM_B_DQBYTE_5
MEM_B_DQS_6 * MEM_DQS2OWNDATAMEM_B_DQBYTE_6
MEM_B_DQS_3 * MEM_DQS2OWNDATAMEM_B_DQBYTE_3
MEM_B_DQS_2 * MEM_DQS2OWNDATAMEM_B_DQBYTE_2
MEM_B_DQS_1 * MEM_DQS2OWNDATAMEM_B_DQBYTE_1
MEM_B_DQS_0 * MEM_DQS2OWNDATAMEM_B_DQBYTE_0
MEM_A_DQS_7 * MEM_DQS2OWNDATAMEM_A_DQBYTE_7
MEM_A_DQS_6 * MEM_DQS2OWNDATAMEM_A_DQBYTE_6
MEM_A_DQS_2 * MEM_DQS2OWNDATAMEM_A_DQBYTE_2
MEM_A_DQS_3 * MEM_DQS2OWNDATAMEM_A_DQBYTE_3
MEM_A_DQS_4 * MEM_DQS2OWNDATAMEM_A_DQBYTE_4
MEM_PWR
** DEFAULT
MEM_PWR
MEM_* * MEM_2PWR
MEM_2GND
MEM_*GND *
=50_OHM_SEMEM_50S * =50_OHM_SE =STANDARD =STANDARD=50_OHM_SE =50_OHM_SE
MEM_A_DQS_5 * MEM_DQS2OWNDATAMEM_A_DQBYTE_5
MEM_A_DQS_1 * MEM_DQS2OWNDATAMEM_A_DQBYTE_1
BGA_MEMMEM_CMD MEM_CMD2CMD_BMMEM_CMD
MEM_CLK MEM_CLK
* MEM_CLK2CLK
=SAME * MEM_DATA2SELFMEM_*_DQBYTE_*
MEM_CLK
** MEM_2OTHER
?TOP,BOTTOMMEM_DATA2SELF =5x_DIELECTRIC
=5x_DIELECTRIC
TOP,BOTTOMMEM_CMD2CMD ?
MEM_DQS2OWNDATA ?TOP,BOTTOM =5x_DIELECTRIC
?=5x_DIELECTRICTOP,BOTTOMMEM_CMD2CTL
?=2x_DIELECTRIC*MEM_DATA2SELF
?=2x_DIELECTRIC*MEM_CMD2CMD
MEM_DQS2OWNDATA ?=2x_DIELECTRIC*
MEM_CMD2CTL ?*=2x_DIELECTRIC
MEM_CTL2CTL ?=5x_DIELECTRICTOP,BOTTOM
?=8x_DIELECTRICTOP,BOTTOMMEM_2OTHERMEM
?=8x_DIELECTRICTOP,BOTTOMMEM_CLK2CLK
?=4x_DIELECTRICTOP,BOTTOMMEM_2PWR
?=10x_DIELECTRICTOP,BOTTOMMEM_2OTHER
?=4x_DIELECTRICTOP,BOTTOMMEM_2GND
MEM_CMD2CMD_BM ?=3x_DIELECTRICTOP,BOTTOM
MEM_CMD2CTL_BM ?=3x_DIELECTRICTOP,BOTTOM
MEM_CTL2CTL_BM ?=3x_DIELECTRICTOP,BOTTOM
MEM_CTL2CTL ?=2x_DIELECTRIC*
?
=4x_DIELECTRIC*MEM_CLK2CLK
MEM_2OTHERMEM ?=4x_DIELECTRIC*
?*
MEM_2PWR =2x_DIELECTRIC
MEM_2GND ?=2x_DIELECTRIC*
MEM_CMD2CMD_BM ?=2x_DIELECTRIC*
?
=6x_DIELECTRIC*MEM_2OTHER
MEM_CTL2CTL_BM ?=2x_DIELECTRIC*
MEM_12MIL *? 0.305 MM
MEM_72D MEM_CLK MEM_A_CLK_P<0>MEM_A_CLK
MEM_CTLMEM_A_CTL MEM_40S MEM_A_CS_L<0>
MEM_CTLMEM_A_CTL MEM_40S MEM_A_CKE<0>
MEM_40S MEM_A_RAS_LMEM_A_CMD MEM_CMD
MEM_12MIL CPU_DIMM_VREFCA_B_ISOL
MEM_12MIL CPU_DIMM_VREFCA_A_ISOL
MEM_12MIL PP0V675_S3_MEM_VREFCA_B
MEM_12MIL PP0V675_S3_MEM_VREFCA_A
MEM_12MIL PP0V675_S3_MEM_VREFDQ_A
MEM_12MIL PP0V675_S3_MEM_VREFDQ_B
MEM_A_DQBYTE_7MEM_A_DQBYTE7 MEM_A_DQ<63..56>MEM_45S
MEM_A_CLK MEM_72D MEM_CLK MEM_A_CLK_N<0>
MEM_CTLMEM_40SMEM_A_ODT0 MEM_A_ODT<0>
MEM_A_CMD MEM_A_BA<2..0>MEM_CMDMEM_40S
MEM_A_CMD MEM_CMDMEM_40S MEM_A_A<15..0>
MEM_A_CMD MEM_A_CAS_LMEM_CMDMEM_40S
MEM_A_WE_LMEM_A_CMD MEM_CMDMEM_40S
MEM_A_DQBYTE_0
MEM_A_DQBYTE0 MEM_A_DQ<7..0>MEM_45S
MEM_A_DQBYTE_1
MEM_A_DQBYTE1 MEM_A_DQ<15..8>MEM_45S
MEM_A_DQBYTE2 MEM_A_DQ<23..16>MEM_45S MEM_A_DQBYTE_2
MEM_A_DQBYTE_4
MEM_A_DQBYTE4 MEM_A_DQ<39..32>MEM_45S
MEM_A_DQBYTE_3
MEM_A_DQBYTE3 MEM_A_DQ<31..24>MEM_45S
MEM_A_DQBYTE_6
MEM_A_DQBYTE6 MEM_A_DQ<55..48>MEM_45S
MEM_A_DQBYTE_5
MEM_A_DQBYTE5 MEM_A_DQ<47..40>MEM_45S
MEM_A_DQS0 MEM_A_DQS_0MEM_80D MEM_A_DQS_P<0>
MEM_A_DQS_N<0>
MEM_A_DQS0 MEM_A_DQS_0MEM_80D
MEM_A_DQS_N<1>MEM_A_DQS1 MEM_A_DQS_1MEM_80D
MEM_A_DQS_P<1>MEM_A_DQS1 MEM_A_DQS_1MEM_80D
MEM_A_DQS_P<2>MEM_A_DQS2 MEM_A_DQS_2MEM_80D
MEM_A_DQS_P<3>MEM_A_DQS3 MEM_A_DQS_3MEM_80D
MEM_A_DQS_N<2>MEM_A_DQS2 MEM_A_DQS_2MEM_80D
MEM_A_DQS_N<3>MEM_A_DQS3 MEM_A_DQS_3MEM_80D
MEM_A_DQS_N<4>MEM_A_DQS4 MEM_A_DQS_4MEM_80D
MEM_A_DQS_P<4>MEM_A_DQS4 MEM_A_DQS_4MEM_80D
MEM_A_DQS_N<5>MEM_A_DQS5 MEM_A_DQS_5MEM_80D
MEM_A_DQS_P<5>MEM_A_DQS5 MEM_A_DQS_5MEM_80D
MEM_A_DQS_P<6>MEM_A_DQS6 MEM_80D MEM_A_DQS_6
MEM_A_DQS_P<7>MEM_A_DQS7 MEM_A_DQS_7MEM_80D
MEM_A_DQS_N<6>MEM_A_DQS6 MEM_A_DQS_6MEM_80D
MEM_A_DQS_N<7>MEM_A_DQS7 MEM_A_DQS_7MEM_80D
MEM_B_CLK_P<0>MEM_B_CLK MEM_CLKMEM_72D
MEM_B_CLK_N<0>MEM_B_CLK MEM_CLKMEM_72D
MEM_B_CTL MEM_40S MEM_B_CKE<0>MEM_CTL
MEM_40S
MEM_B_CS_L<0>MEM_CTLMEM_B_CTL
MEM_40S MEM_B_ODT<0>MEM_B_ODT0 MEM_CTL
MEM_40S MEM_CMD
MEM_B_CMD MEM_B_BA<2..0>
MEM_B_CMD MEM_40S MEM_CMD MEM_B_A<15..0>
MEM_40S MEM_CMDMEM_B_CMD MEM_B_RAS_L
MEM_40S MEM_CMDMEM_B_CMD MEM_B_WE_L
MEM_40S MEM_CMDMEM_B_CMD MEM_B_CAS_L
MEM_45S MEM_B_DQ<15..8>MEM_B_DQBYTE1 MEM_B_DQBYTE_1
MEM_45S
MEM_B_DQ<7..0>MEM_B_DQBYTE0 MEM_B_DQBYTE_0
MEM_45S
MEM_B_DQ<23..16>MEM_B_DQBYTE2 MEM_B_DQBYTE_2
MEM_45S
MEM_B_DQ<39..32>MEM_B_DQBYTE4 MEM_B_DQBYTE_4
MEM_45S
MEM_B_DQ<31..24>MEM_B_DQBYTE3 MEM_B_DQBYTE_3
MEM_B_DQBYTE6 MEM_45S MEM_B_DQ<55..48>MEM_B_DQBYTE_6
MEM_B_DQBYTE5 MEM_45S MEM_B_DQ<47..40>MEM_B_DQBYTE_5
MEM_45S
MEM_B_DQ<63..56>MEM_B_DQBYTE7 MEM_B_DQBYTE_7
MEM_80D
MEM_B_DQS_0MEM_B_DQS0 MEM_B_DQS_P<0>
MEM_80D MEM_B_DQS_1MEM_B_DQS1 MEM_B_DQS_N<1>
MEM_B_DQS_P<1>
MEM_80D MEM_B_DQS_1MEM_B_DQS1
MEM_80D MEM_B_DQS_2MEM_B_DQS2 MEM_B_DQS_P<2>
MEM_B_DQS3 MEM_80D MEM_B_DQS_3 MEM_B_DQS_P<3>
MEM_B_DQS3 MEM_B_DQS_N<3>MEM_80D MEM_B_DQS_3
MEM_B_DQS4 MEM_B_DQS_P<4>MEM_80D MEM_B_DQS_4
MEM_B_DQS_4
MEM_B_DQS4 MEM_80D MEM_B_DQS_N<4>
MEM_B_DQS5 MEM_B_DQS_5 MEM_B_DQS_P<5>MEM_80D
MEM_80D
MEM_B_DQS_6 MEM_B_DQS_P<6>MEM_B_DQS6
MEM_80D MEM_B_DQS_7 MEM_B_DQS_P<7>MEM_B_DQS7
PP1V35_S3MEM_PWR
MEM_PWR
PP0V675_S0_DDRVTT
PP1V35_S3_CPUDDRMEM_PWR
MEM_PWR
PPVTTDDR_S3
MEM_80D MEM_B_DQS_2MEM_B_DQS2 MEM_B_DQS_N<2>
CPU_DIMMB_VREFDQMEM_12MIL
MEM_12MIL
CPU_DIMMA_VREFDQ_A_ISOL
MEM_12MIL CPU_DIMMB_VREFDQ_B_ISOL
CPU_DIMM_VREFCAMEM_12MIL
CPU_DIMMA_VREFDQMEM_12MIL
MEM_B_DQS_N<7>MEM_80D MEM_B_DQS_7MEM_B_DQS7
MEM_80D MEM_B_DQS_6MEM_B_DQS6 MEM_B_DQS_N<6>
MEM_80D MEM_B_DQS_5 MEM_B_DQS_N<5>MEM_B_DQS5
MEM_80D MEM_B_DQS_0MEM_B_DQS0 MEM_B_DQS_N<0>
<BRANCH>
<SCH_NUM>
<E4LABEL>
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7 67 www.rosefix.com

TABLE_SPACING_ASSIGNMENT_ITEM
AREA_TYPE SPACING_RULE_SETNET_SPACING_TYPE1 NET_SPACING_TYPE2
TABLE_SPACING_ASSIGNMENT_HEAD
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
LINE-TO-LINE SPACINGLAYERSPACING_RULE_SET WEIGHT
TABLE_SPACING_RULE_HEAD
AREA_TYPE SPACING_RULE_SETNET_SPACING_TYPE1 NET_SPACING_TYPE2
TABLE_SPACING_ASSIGNMENT_HEAD
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
LINE-TO-LINE SPACINGLAYERSPACING_RULE_SET WEIGHT
TABLE_SPACING_RULE_HEAD
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
LINE-TO-LINE SPACINGLAYERSPACING_RULE_SET WEIGHT
TABLE_SPACING_RULE_HEAD
TABLE_SPACING_RULE_ITEM
LINE-TO-LINE SPACINGLAYERSPACING_RULE_SET WEIGHT
TABLE_SPACING_RULE_HEAD
TABLE_SPACING_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
LINE-TO-LINE SPACINGLAYERSPACING_RULE_SET WEIGHT
TABLE_SPACING_RULE_HEAD
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
AREA_TYPE SPACING_RULE_SETNET_SPACING_TYPE1 NET_SPACING_TYPE2
TABLE_SPACING_ASSIGNMENT_HEAD
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
MINIMUM LINE WIDTH
ALLOW ROUTE
ON LAYER?
LAYER MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
MINIMUM LINE WIDTH
ALLOW ROUTE
ON LAYER?
LAYER MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
MINIMUM LINE WIDTH
ALLOW ROUTE
ON LAYER?
LAYER MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
TABLE_SPACING_RULE_ITEM
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
124578
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D
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C
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A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
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A
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PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
D
SIZEDRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
to save routing space.
Notes:
SOURCE: Calpella SFF DG Rev 1.5 (407364) and Family GPU DG-04202-001-v04.
DisplayPort AUX CH intra-pair matching should be 0.127mm. Max length 330.2mm.
MAX LENGTH OF DISPLAYPORT/TMDS TRACES: 13 INCHES.
DisplayPort/TMDS intra-pair matching should be 0.127mm. Inter-pair matching should be within 2.54cm. Max Length 241.3mm.
DisplayPort & HDMI Constraints
Thunderbolt, DP, HDMI Net Properties
SPACINGPHYSICAL
NET TYPE
ELECTRICAL CONST SET
Only used on hosts supporting Thunderbolt video-in
SPACINGPHYSICAL
NET TYPE
ELECTRICAL CONST SET
TBTDP_RX/TX because it’s not high speed, and
AUX and DDC was removed from DISPLAYPORT or
Thunderbolt & DisplayPort Constraints
Thunderbolt SPI Signal Constraints
Thunderbolt, DP, HDMI Constraints
Only used on dual-port hosts.
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SYNC_DATE=08/12/2013SYNC_MASTER=J44
TBT,DP,HDMI Constraints
=4x_DIELECTRIC ?TOP,BOTTOMTBTDP_2SAME
HDMI_85D * =85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF=85_OHM_DIFF =85_OHM_DIFF
=10X_DIELECTRIC ?TOP,BOTTOMTBTDP_TXRX
=6X_DIELECTRICTOP,BOTTOMTBTDP_2OTHER ?
TBTDP_85D =85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF* =85_OHM_DIFF =85_OHM_DIFF
HDMI_DATA
TBTDP_TX * HDMIDATA_2SAME
HDMI_DATA TBTDP_RX * TBTDP_TXRX
*HDMI_DATA DP_2SAMEDISPLAYPORT
DP_2SAME*=SAMEDISPLAYPORT
**DISPLAYPORT DP_2OTHER
* =7x_DIELECTRIC ?HDMICLK_2OTHER
* =4x_DIELECTRIC ?HDMICLK_2DPHDMI
DP_85D * =85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF=85_OHM_DIFF =85_OHM_DIFF
?=6X_DIELECTRIC*TBTDP_TXRX
?=2x_DIELECTRIC*TBT_SPI
TOP,BOTTOM =6x_DIELECTRIC ?HDMICLK_2DPHDMI
TOP,BOTTOM =10x_DIELECTRIC ?HDMICLK_2OTHER
?=3X_DIELECTRIC*TBTDP_2SAME
?=4X_DIELECTRIC*TBTDP_2OTHER
TBTDP_* ** TBTDP_2OTHER
TBTDP_RX *_TX * TBTDP_TXRX
DP_2SAME * =3x_DIELECTRIC ?
*
=3x_DIELECTRIC ?HDMIDATA_2SAME
DP_2OTHER * =4x_DIELECTRIC ?
DP_2SAME TOP,BOTTOM =4x_DIELECTRIC ?
DP_2OTHER TOP,BOTTOM =6x_DIELECTRIC ?
HDMI_CLK ** HDMICLK_2OTHER
HDMI_CLK TBTDP_TX * HDMICLK_2DPHDMI
HDMI_CLK DISPLAYPORT * HDMICLK_2DPHDMI
TBTDP_TXRX*TBTDP_RXDISPLAYPORT
TBT_SPI_45S
=45_OHM_SE* =45_OHM_SE =45_OHM_SE =45_OHM_SE =STANDARD =STANDARD
TBTDP_* =SAME * TBTDP_2SAME
TBTDP_TX *_RX * TBTDP_TXRX
* =4x_DIELECTRIC ?HDMIDATA_2OTHER
TOP,BOTTOM =4x_DIELECTRIC ?HDMIDATA_2SAME
HDMI_DATA =SAME * HDMIDATA_2SAME
DP_2SAME*TBTDP_TXDISPLAYPORT
HDMI_DATA ** HDMIDATA_2OTHER
=6x_DIELECTRIC ?TOP,BOTTOMHDMIDATA_2OTHER
HDMI_CLK HDMI_DATA * HDMICLK_2DPHDMI
DP_INT_ML DP_85D DISPLAYPORT DP_INT_ML_C_P<3..0>
DP_INT_ML DP_85D DISPLAYPORT DP_INT_ML_C_N<3..0>
DP_85D DISPLAYPORT DP_TBTSNK0_ML_C_P<3..0>DP_TBTSNK0_ML
DP_85D DISPLAYPORT DP_TBTSNK0_ML_P<3..0>DP_TBTSNK0_ML
DP_85D DISPLAYPORT DP_TBTSNK0_ML_C_N<3..0>DP_TBTSNK0_ML
DP_85D DISPLAYPORT DP_TBTSNK0_ML_N<3..0>DP_TBTSNK0_ML
DP_TBTSNK_AUXCH DP_TBTSNK0_AUXCH_C_NDP_85D
DP_TBTSNK_AUXCH DP_85D DP_TBTSNK0_AUXCH_C_P
DP_TBTSNK_AUXCH DP_85D DP_TBTSNK0_AUXCH_P
DP_TBTSNK_AUXCH DP_85D DP_TBTSNK0_AUXCH_N
DP_85D DISPLAYPORT DP_TBTSNK1_ML_C_P<3..0>DP_TBTSNK1_ML
DP_85D DISPLAYPORT DP_TBTSNK1_ML_P<3..0>DP_TBTSNK1_ML
DP_85D DISPLAYPORT DP_TBTSNK1_ML_C_N<3..0>DP_TBTSNK1_ML
DP_TBTSNK_AUXCH DP_85D DP_TBTSNK1_AUXCH_C_P
DP_85D DISPLAYPORT DP_TBTSNK1_ML_N<3..0>DP_TBTSNK1_ML
DP_TBTSNK_AUXCH DP_85D DP_TBTSNK1_AUXCH_C_N
DP_TBTSNK_AUXCH DP_85D DP_TBTSNK1_AUXCH_N
DP_TBTSNK_AUXCH DP_85D DP_TBTSNK1_AUXCH_P
TBT_SPI_CS_L
TBT_SPITBT_SPI_45SSPI_TBT_CS_L
TBT_SPI_MOSITBT_SPITBT_SPI_45SSPI_TBT_MOSI
DP_TBTSRC_ML_C_P<3..0>DISPLAYPORTDP_85D
TBT_B_R2D TBTDP_85D TBTDP_TX TBT_B_R2D_N<1..0>
TBT_B_R2D_P<1..0>
TBT_B_R2D TBTDP_TXTBTDP_85D
DP_TBTPA_AUXCH_PDP_85DDP_TBTPA_AUXCH
DP_TBTPB_ML_C_N<3>DP_TBTPB_ML DISPLAYPORT DP_85D
TBT_A_R2D_C_N<1..0>TBT_A_R2D TBTDP_TXTBTDP_85D
DP_TBTPB_ML_N<3>DP_TBTPB_ML DP_85D DISPLAYPORT
DP_TBTPB_ML_P<3>DP_TBTPB_ML DISPLAYPORT DP_85D
TBT_A_D2R1_AUXDDC_PTBTDP_RXTBTDP_85DTBT_A_D2R_1
TBT_A_D2R1_AUXDDC_NTBT_A_D2R_1 TBTDP_RXTBTDP_85D
DP_INT_ML_N<3..0>DISPLAYPORTDP_85DDP_INT_ML
DP_INT_ML_P<3..0>DISPLAYPORTDP_85DDP_INT_ML
DP_HDMI_TBT_AUX_NDP_85DDP_HDMI_TBT_AUX
DP_HDMI_TBT_AUX_PDP_85DDP_HDMI_TBT_AUX
DISPLAYPORTDP_85D DP_TBTSRC_ML_C_N<3..0>
TBT_SPITBT_SPI_45S TBT_SPI_CLKSPI_TBT_CLK
HDMI_IG_CLK_C_PHDMI_CLOCK HDMI_CLKHDMI_85D
HDMI_IG_CLK_C_NHDMI_CLOCK HDMI_CLKHDMI_85D
HDMI_IG_DATA_C_P<2..0>HDMI_DATA HDMI_DATA HDMI_85D
HDMI_IG_DATA_C_N<2..0>HDMI_DATA HDMI_DATA HDMI_85D
DP_INT_AUXCH_C_PDP_85DDP_INT_AUXCH
DP_INT_AUXCH_C_NDP_85DDP_INT_AUXCH
DP_INT_AUX_PDP_85DDP_INT_AUXCH
DP_INT_AUX_NDP_85DDP_INT_AUXCH
DISPLAYPORTDP_85D DP_TBTSRC_AUXCH_C_P
DISPLAYPORTDP_85D DP_TBTSRC_AUXCH_C_N
TBT_SPI_MISOTBT_SPITBT_SPI_45SSPI_TBT_MISO
DISPLAYPORTDP_85DDP_HDMI_TBT_ML DP_HDMI_TBT_ML_P<3..0>
DP_HDMI_TBT_ML_N<3..0>
DP_85DDP_HDMI_TBT_ML DISPLAYPORT
TBT_B_R2D_C_P<1..0>TBT_B_R2D TBTDP_TXTBTDP_85D
DP_B_LSX_ML_P<1>DISPLAYPORTDP_85DDP_B_LSX_ML
DP_B_LSX_ML_N<1>DISPLAYPORTDP_85DDP_B_LSX_ML
TBT_A_D2R_P<1>TBT_A_D2R_1 TBTDP_RXTBTDP_85D
TBT_A_D2R_N<1>TBT_A_D2R_1 TBTDP_RXTBTDP_85D
DP_TBTPA_AUXCH_C_PDP_85DDP_TBTPA_AUXCH
DP_TBTPA_AUXCH_NDP_85DDP_TBTPA_AUXCH
DP_TBTPB_ML_N<1>DISPLAYPORTDP_85DDP_B_LSX_ML
DP_TBTPB_ML_C_N<1>DISPLAYPORTDP_85DDP_B_LSX_ML
DP_TBTPB_ML_P<1>DISPLAYPORTDP_85DDP_B_LSX_ML
DP_TBTPB_ML_C_P<1>DISPLAYPORTDP_85DDP_B_LSX_ML
DP_TBTPB_ML_C_P<3>DP_TBTPB_ML DP_85D DISPLAYPORT
TBT_B_D2R_C_P<0>TBTDP_RXTBTDP_85DTBT_B_D2R_0
TBT_B_D2R_P<0>TBT_B_D2R_0 TBTDP_RXTBTDP_85D
TBT_B_D2R_C_N<0>TBT_B_D2R_0 TBTDP_RXTBTDP_85D
TBT_B_D2R_N<0>TBT_B_D2R_0 TBTDP_RXTBTDP_85D
TBT_B_D2R_C_P<1>TBTDP_RXTBTDP_85DTBT_B_D2R_1
TBT_B_D2R_C_N<1>TBT_B_D2R_1 TBTDP_RXTBTDP_85D
TBT_B_D2R_P<1>TBT_B_D2R_1 TBTDP_RXTBTDP_85D
TBT_B_D2R_N<1>TBT_B_D2R_1 TBTDP_RXTBTDP_85D
TBT_B_D2R1_AUXDDC_PTBT_B_D2R_1 TBTDP_85D TBTDP_RX
TBT_B_D2R1_AUXDDC_NTBT_B_D2R_1 TBTDP_85D TBTDP_RX
DP_TBTPB_AUXCH_C_PDP_85DDP_TBTPB_AUXCH
DP_TBTPB_AUXCH_C_NDP_85DDP_TBTPB_AUXCH
DP_TBTPB_AUXCH_PDP_85DDP_TBTPB_AUXCH
DP_TBTPB_AUXCH_NDP_85DDP_TBTPB_AUXCH
TBT_B_R2D_C_N<1..0>TBT_B_R2D TBTDP_TXTBTDP_85D
DP_TBTPA_AUXCH_C_NDP_85DDP_TBTPA_AUXCH
TBT_A_R2D_P<1..0>TBT_A_R2D TBTDP_TXTBTDP_85D
TBT_A_R2D_N<1..0>TBTDP_TXTBTDP_85DTBT_A_R2D
DP_TBTPA_ML_N<1>DP_85D DISPLAYPORTDP_A_LSX_ML
DP_85D DISPLAYPORT DP_A_LSX_ML_P<1>DP_A_LSX_ML
TBT_A_R2D_C_P<1..0>TBT_A_R2D TBTDP_TXTBTDP_85D
DP_TBTPA_ML_C_P<3>DP_TBTPA_ML DISPLAYPORT DP_85D
DP_TBTPA_ML_C_N<3>DISPLAYPORTDP_85DDP_TBTPA_ML
DP_TBTPA_ML_P<3>DP_TBTPA_ML DISPLAYPORT DP_85D
TBT_A_D2R_C_N<0>TBT_A_D2R_0 TBTDP_RXTBTDP_85D
TBT_A_D2R_C_P<0>TBT_A_D2R_0 TBTDP_RXTBTDP_85D
TBT_A_D2R_P<0>TBTDP_RXTBTDP_85DTBT_A_D2R_0
TBT_A_D2R_C_P<1>TBT_A_D2R_1 TBTDP_RXTBTDP_85D
TBT_A_D2R_N<0>TBT_A_D2R_0 TBTDP_RXTBTDP_85D
TBT_A_D2R_C_N<1>TBTDP_RXTBTDP_85DTBT_A_D2R_1
DP_TBTPA_ML_N<3>DP_TBTPA_ML DISPLAYPORT DP_85D
DP_TBTPA_ML_C_N<1>DISPLAYPORTDP_85DDP_A_LSX_ML
DISPLAYPORT
DP_85DDP_A_LSX_ML DP_TBTPA_ML_P<1>
DISPLAYPORTDP_85DDP_A_LSX_ML DP_A_LSX_ML_N<1>
DP_TBTPA_ML_C_P<1>DISPLAYPORTDP_85DDP_A_LSX_ML
<BRANCH>
<SCH_NUM>
<E4LABEL>
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AREA_TYPE SPACING_RULE_SETNET_SPACING_TYPE1 NET_SPACING_TYPE2
TABLE_SPACING_ASSIGNMENT_HEAD
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
87 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
D
SIZEDRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AREA_TYPE SPACING_RULE_SETNET_SPACING_TYPE1 NET_SPACING_TYPE2
TABLE_SPACING_ASSIGNMENT_HEAD
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
AREA_TYPE SPACING_RULE_SETNET_SPACING_TYPE1 NET_SPACING_TYPE2
TABLE_SPACING_ASSIGNMENT_HEAD
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
LINE-TO-LINE SPACINGLAYERSPACING_RULE_SET WEIGHT
TABLE_SPACING_RULE_HEAD
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
LINE-TO-LINE SPACINGLAYERSPACING_RULE_SET WEIGHT
TABLE_SPACING_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
MINIMUM LINE WIDTH
ALLOW ROUTE
ON LAYER?
LAYER MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
AREA_TYPE SPACING_RULE_SETNET_SPACING_TYPE1 NET_SPACING_TYPE2
TABLE_SPACING_ASSIGNMENT_HEAD
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
LINE-TO-LINE SPACINGLAYERSPACING_RULE_SET WEIGHT
TABLE_SPACING_RULE_HEAD
LINE-TO-LINE SPACINGLAYERSPACING_RULE_SET WEIGHT
TABLE_SPACING_RULE_HEAD
AREA_TYPE SPACING_RULE_SETNET_SPACING_TYPE1 NET_SPACING_TYPE2
TABLE_SPACING_ASSIGNMENT_HEAD
TABLE_SPACING_ASSIGNMENT_ITEM
MINIMUM LINE WIDTH
ALLOW ROUTE
ON LAYER?
LAYER MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
TABLE_SPACING_RULE_ITEM TABLE_SPACING_RULE_ITEM
ELECTRICAL CONST SET
PHYSICAL
NET TYPE SPACING
Camera Net Properties
Memory Bus Spacing Group Assignments
Memory to Power Spacing
Spacing Rule Sets
Memory Bus Constraints
MIPI Interface Constraints
Memory to GND Spacing
I149
S2_2OTHERMEM TOP,BOTTOM=6x_DIELECTRIC ?S2_2OTHERMEM * =4x_DIELECTRIC ?
S2MEM_2GND*S2_MEM_*GND
MIPI_85D * =85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF=85_OHM_DIFF =85_OHM_DIFF
=4X_DIELECTRIC ?*MIPI_2OTHER
=6X_DIELECTRIC ?*MIPI_2CLK
S2_MEM_45S * =45_OHM_SE =45_OHM_SE =45_OHM_SE =STANDARD=STANDARD=45_OHM_SE
S2_MEM_85D * =85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF=85_OHM_DIFF
* =2x_DIELECTRIC ?S2_DQS2OWNDATA
S2_CMD2CTRL * =2x_DIELECTRIC ?
S2MEM_2OTHER TOP,BOTTOM=10x_DIELECTRIC ?
S2MEM_2PWR TOP,BOTTOM =4x_DIELECTRIC ?
S2_CMD2CTRL TOP,BOTTOM=4x_DIELECTRIC ?
?
=10X_DIELECTRICTOP,BOTTOMMIPICLK_2OTHER
?=8X_DIELECTRICTOP,BOTTOMMIPI_2CLK
?=6X_DIELECTRICTOP,BOTTOMMIPI_2OTHER
S2_DATA2SELF TOP,BOTTOM=4x_DIELECTRIC ?
TOP,BOTTOM=4x_DIELECTRIC ?S2_DQS2OWNDATA
S2_CMD2CMD TOP,BOTTOM =4x_DIELECTRIC ?
S2MEM_2GND TOP,BOTTOM =4x_DIELECTRIC ?
S2_CTRL2CTRL TOP,BOTTOM=4x_DIELECTRIC ?
S2_CMD2CMD * =2x_DIELECTRIC ?
S2_CTRL2CTRL * =2x_DIELECTRIC ?
S2MEM_2PWR * =2x_DIELECTRIC ?
S2_MEM_CMD S2_MEM_CTRL * S2_CMD2CTRL
S2_MEM_DQS*
** S2MEM_2OTHER
S2_MEM_DATA*
** S2MEM_2OTHER
S2_MEM_DATA*
=SAME * S2_DATA2SELF
S2_MEM_PWR S2_MEM_* * S2MEM_2PWR
S2_MEM_PWR
** DEFAULT
S2_MEM_DQS0 S2_MEM_DATA0 * S2_DQS2OWNDATA
S2_MEM_CMD ** S2MEM_2OTHER
S2_MEM_CTRL ** S2MEM_2OTHER
S2_MEM_CLK ** S2MEM_2OTHER
S2_MEM_CMDS2_MEM_CMD * S2_CMD2CMD
S2_MEM_CTRL S2_MEM_CTRL * S2_CTRL2CTRL
S2_MEM_* S2_MEM_* * S2_2OTHERMEM
MIPI_DATA CLK_MIPI * MIPI_2CLK
MIPI_DATA
** MIPI_2OTHER
=7X_DIELECTRIC ?*MIPICLK_2OTHER
S2_MEM_DQS1 S2_MEM_DATA1 * S2_DQS2OWNDATA
S2_DATA2SELF * =2x_DIELECTRIC ?
CLK_MIPI ** MIPICLK_2OTHER
S2MEM_2GND * =2x_DIELECTRIC ?
S2MEM_2OTHER * =6x_DIELECTRIC ?
SYNC_MASTER=J44 SYNC_DATE=08/12/2013
Camera Constraints
MIPI_CLK_PCLK_MIPIMIPI_85DMIPI_CLK_S2
MIPI_DATAMIPI_85D MIPI_DATA_CONN_PMIPI_DATA_S2
S2_MEM_DQS1 S2_MEM_DQS1 S2_MEM_85D MEM_CAM_DQS_P<1>
MEM_CAM_DQS_N<1>
S2_MEM_DQS1 S2_MEM_DQS1 S2_MEM_85D
MIPI_CLK_NCLK_MIPIMIPI_85DMIPI_CLK_S2
MEM_CAM_BA<2>S2_MEM_CMD S2_MEM_CMDS2_MEM_45S
MEM_CAM_BA<0>S2_MEM_CMD S2_MEM_CMDS2_MEM_45S
MEM_CAM_CS_LS2_MEM_CTRLS2_MEM_45SS2_MEM_CS
MEM_CAM_CLK_NS2_MEM_CLK S2_MEM_CLKS2_MEM_85D
MEM_CAM_WE_LS2_MEM_CMD S2_MEM_CMDS2_MEM_45S
MEM_CAM_RAS_LS2_MEM_CMD S2_MEM_CTRLS2_MEM_45S
MEM_CAM_CKES2_MEM_CTRLS2_MEM_45SS2_MEM_CKE
MEM_CAM_CAS_LS2_MEM_CMD S2_MEM_CTRLS2_MEM_45S
MEM_CAM_ODTS2_MEM_CTRLS2_MEM_45S
MEM_CAM_CLK_PS2_MEM_CLK S2_MEM_CLKS2_MEM_85D
MEM_CAM_BA<1>S2_MEM_CMD S2_MEM_CMDS2_MEM_45S
MEM_CAM_DM<0>S2_MEM_DATA_0 S2_MEM_DATA0S2_MEM_45S
MEM_CAM_DQS_P<0>S2_MEM_DQS0 S2_MEM_85D S2_MEM_DQS0
MEM_CAM_DQS_N<0>S2_MEM_DQS0 S2_MEM_DQS0 S2_MEM_85D
S2_MEM_PWR
PP0V675_MEM_CAM_VREFDQ
MIPI_CLK_CONN_NCLK_MIPIMIPI_85DMIPI_CLK_S2
MIPI_CLK_CONN_PCLK_MIPIMIPI_85DMIPI_CLK_S2
MIPI_DATA_S2 MIPI_85D MIPI_DATA MIPI_DATA_N
MIPI_DATAMIPI_85DMIPI_DATA_S2 MIPI_DATA_P
S2_MEM_DATA_0 S2_MEM_DATA0S2_MEM_45S MEM_CAM_DQ<7..0>
S2_MEM_DATA_1 S2_MEM_DATA1S2_MEM_45S MEM_CAM_DQ<15..8>
MEM_CAM_DM<1>S2_MEM_DATA1S2_MEM_45SS2_MEM_DATA_1
MIPI_DATA_CONN_NMIPI_DATAMIPI_85DMIPI_DATA_S2
PP1V35_CAMS2_MEM_PWR
PP0V675_CAM_VREFS2_MEM_PWR
S2_MEM_PWR
PP0V675_MEM_CAM_VREFCA
S2_MEM_CMDS2_MEM_45SS2_MEM_A MEM_CAM_A<14..0>
<BRANCH>
<SCH_NUM>
<E4LABEL>
116 OF 120
75 OF 78
31 32 68
32 68
31 32
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31 32 68
31 32
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31 32
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32
31 32
31 32
31 32
31 32
31 32
32
32 68
32 68
31 32 68
31 32 68
31 32
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31 32 www.rosefix.com

Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
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NOTICE OF PROPRIETARY PROPERTY:
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PAGE TITLE
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IV ALL RIGHTS RESERVED
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SIZEDRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
SPACINGPHYSICAL
NET TYPE
ELECTRICAL CONST SET
SMC SMBus & Charger Net Properties
SMC Constraints
SYNC_DATE=08/12/2013SYNC_MASTER=J44
SMB_45S SMBUS_SMC_1_S0_SCLSMBSMBUS_SMC_1
SMB_45S SMBUS_SMC_1_S0_SDASMBSMBUS_SMC_1
SMBUS_SMC_3_SCLSMBSMB_45SSMBUS_SMC_3
SMBUS_SMC_5_G3_SDASMBSMB_45SSMBUS_SMC_5
SMBUS_SMC_0_S0_SDASMBSMB_45SSMBUS_SMC_0
SMBUS_SMC_2_S3_SCLSMBSMB_45SSMBUS_SMC_2
SMBUS_SMC_2_S3_SDASMBSMB_45SSMBUS_SMC_2
SMBUS_SMC_0_S0_SCLSMBSMB_45SSMBUS_SMC_0
SMBSMB_45SSMBUS_SMC_5 SMBUS_SMC_5_G3_SCL
SMBUS_SMC_3_SDASMBSMB_45SSMBUS_SMC_3
<BRANCH>
<SCH_NUM>
<E4LABEL>
117 OF 120
76 OF 78
14 32 36 39 43 68 72
14 32 36 39 43 68 72
36 39 43 63
36 39 51 52 68
36 39 62 68
34 36 39 68
34 36 39 68
36 39 62 68
36 39 51 52 68
36 39 43 63 www.rosefix.com

TABLE_SPACING_ASSIGNMENT_ITEM
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
124578
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D
87 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
D
SIZEDRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_ASSIGNMENT_ITEM
PHYSICAL_RULE_SETAREA_TYPENET_PHYSICAL_TYPE
TABLE_PHYSICAL_ASSIGNMENT_HEAD
PHYSICAL_RULE_SETAREA_TYPENET_PHYSICAL_TYPE
TABLE_PHYSICAL_ASSIGNMENT_HEAD
AREA_TYPE SPACING_RULE_SETNET_SPACING_TYPE1 NET_SPACING_TYPE2
TABLE_SPACING_ASSIGNMENT_HEAD
OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
MINIMUM LINE WIDTH
ALLOW ROUTE
ON LAYER?
LAYER MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_ASSIGNMENT_ITEM
TABLE_PHYSICAL_ASSIGNMENT_ITEM
PHYSICAL_RULE_SETAREA_TYPENET_PHYSICAL_TYPE
TABLE_PHYSICAL_ASSIGNMENT_HEAD
TABLE_PHYSICAL_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_ASSIGNMENT_ITEM
TABLE_PHYSICAL_ASSIGNMENT_ITEM
TABLE_PHYSICAL_ASSIGNMENT_ITEM
TABLE_PHYSICAL_ASSIGNMENT_ITEM
TABLE_PHYSICAL_ASSIGNMENT_ITEM
TABLE_PHYSICAL_ASSIGNMENT_ITEM
TABLE_SPACING_RULE_ITEM
OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE
TABLE_PHYSICAL_RULE_ITEM
OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE
TABLE_PHYSICAL_RULE_ITEM
OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE
TABLE_PHYSICAL_RULE_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
MINIMUM LINE WIDTH
ALLOW ROUTE ON LAYER?
LAYER MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
AREA_TYPE SPACING_RULE_SETNET_SPACING_TYPE1 NET_SPACING_TYPE2
TABLE_SPACING_ASSIGNMENT_HEAD
TABLE_PHYSICAL_RULE_ITEM
MINIMUM LINE WIDTH
ALLOW ROUTE ON LAYER?
LAYER MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
LINE-TO-LINE SPACINGLAYERSPACING_RULE_SET WEIGHT
TABLE_SPACING_RULE_HEAD
TABLE_SPACING_RULE_ITEM
LINE-TO-LINE SPACINGLAYERSPACING_RULE_SET WEIGHT
TABLE_SPACING_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
LINE-TO-LINE SPACINGLAYERSPACING_RULE_SET WEIGHT
TABLE_SPACING_RULE_HEAD
DDR3 Loaded Segment Constraint Relaxations
ELECTRICAL CONST SET
NET TYPE
SPACING
ELECTRICAL CONST SET
NET TYPE
PHYSICAL
SPACING
Allow 0.127 mm necks for >0.127 mm lines for ARD fanout.
Alternate diffpair width/gap through BGA fanout areas (95-ohm diff)
DP, SATA, HDMI, PCIE CONSTRAINT RELAXATIONS
J44 Specific Net PropertiesJ44 Specific Net Properties
Alternate single ended and differential impedances between devices.
PHYSICAL
=2X_DIELECTRICSENSE * ?
*THERM =2X_DIELECTRIC ?
AUDIO *
=2X_DIELECTRIC ?
0.3 MM0.3 MM
ANL_AUDIO_WIDE =1TO1_DIFFPAIR 0.1 MM 0.1 MM10 MM*
ANL_AUDIO * 0.1 MM 10 MM 0.1 MM0.1 MM=1TO1_DIFFPAIR 0.1 MM
?
=STANDARDGND *
=45_OHM_SE=1TO1_DIFFPAIR =45_OHM_SE =45_OHM_SE 0.1 MM 0.1 MM*THERM_45S
PCIE_* GND_P2MM*GND
GND_P2MMGND *CLK_PCIE
GND GND_P2MM*USB
*
PWR_P2MMSB_POWERCLK_PCIE
DIG_AUDIO =1TO1_DIFFPAIR* =1TO1_DIFFPAIR =1TO1_DIFFPAIR 0.1 MM0.1 MM=1TO1_DIFFPAIR
=45_OHM_SE=45_OHM_SE=1TO1_DIFFPAIR =45_OHM_SE 0.1 MM 0.1 MM*SENSE_45S
0.090 MMDP_85D ISL9 0.075 MM
CPU_27P4S BOTTOM 0.230 MM 100 MIL
SATA_* GND_P2MM*GND
MEM_72D * 100 MIL0.090 MM
0.090 MM
100 MILMEM_40S*
PCIE_85D * 0.090 MM 10 MM
PWR_P2MM * 0.20 MM 1000
PCIE_85D BGA P65_BGA
CLK_PCIE_85D BGA P65_BGA
HDMI_85D BGA P65_BGA
DP_85D BGA P65_BGA
MEM_72D BGA_MEM MEM_85D
MEM_40S BGA_MEM MEM_45S
USB_85D
TOP 0.100 MM 500 MIL
GND_P2MM * 0.20 MM 1000
PWR_P2MMSATA_* *SB_POWER
THERM_45S * THERM_45S
* 0.070 MM 100 MILMEM_45S
PWR_P2MMSB_POWER*USB
DIG_AUDIO * DIG_AUDIO
ANL_AUDIO
* ANL_AUDIO
1TO1_DIFFPAIR * 1TO1_DIFFPAIR
MEM_85D TOP 0.100 MM 6.35 MM
MEM_72D
BOTTOM 0.127 MM 6.35 MM
MEM_85D
* 0.090 MM 100 MIL
SENSE_45S * SENSE_45S
0.090 MMUSB3_85DISL10 0.075 MM
USB3_85D
TOP 0.100 MM 500 MIL
PCIE_85D ISL10 0.075 MM 0.090 MM
SYNC_MASTER=J44 SYNC_DATE=08/12/2013
Project Specific Constraints
CPU_VCCSENSE GND_P2MM*GND
AUDIO_DP_SPKTWT SPKRCONN_R_OUT_PDIG_AUDIO AUDIO
AUDIO_DP_SPKTWT SPKRCONN_R_OUT_NDIG_AUDIO AUDIO
SENSE_DP_CPUVR CPUVR_ISNS_NSENSESENSE_45S
CPUVR_ISNS_R_NSENSE_DP_CPUVR SENSE_45S SENSE
SENSE
CPUVR_ISNS1_PSENSE_45S
SENSECPUVR_ISNS1_NSENSE_45S
SENSE_DP ISNS_HS_COMPUTING_NSENSESENSE_45S
SENSE_DP SENSE_45S ISNS_LCDPANEL_NSENSE
AUDIO_DP_AMPSUB AUD_SPKRAMP_RSUBIN_NAUDIOANL_AUDIO
AUD_LO3_R_PAUDIO_DP_AMPSUB AUDIOANL_AUDIO
AUDIO_DP_AMPSUB ANL_AUDIO AUDIO AUD_LO3_L_N
AUD_SPKRAMP_LSUBIN_NAUDIO_DP_AMPSUB AUDIOANL_AUDIO
AUDIO_DP_AMPSUB LSUBIN_PAUDIOANL_AUDIO
AUDIO_DP_AMPTWT SPKRAMP_LIN_PAUDIOANL_AUDIO
SENSE_45S
SENSE_DP ISNS_HS_OTHER3V3_PSENSE
SENSE_DP SENSE_45S ISNS_LCDPANEL_PSENSE
SENSE_DP_TBT ISNS_TBT_PSENSESENSE_45S
ISNS_LCDBKLT_PSENSE_DP_LCDBKLT SENSESENSE_45S
SENSE_45S
SENSE_DP ISNS_CPUDDR_NSENSE
SENSE_45SSENSE_DP SENSEISNS_CPUDDR_P
NC_ISNS_CAMERANSENSESENSE_45S
AUDIO_DP_SPKTWT SPKRCONN_L_OUT_NDIG_AUDIO AUDIO
SPKRCONN_SR_OUT_NAUDIO_DP_SPKSUB DIG_AUDIO AUDIO
AUDIO_DP_SPKTWT SPKRCONN_L_OUT_PDIG_AUDIO AUDIO
AUDIO_DP_SPKSUB DIG_AUDIO AUDIO SPKRCONN_SR_OUT_P
AUDIO_DP_SPKSUB DIG_AUDIO AUDIO SPKRCONN_SL_OUT_N
ANL_AUDIOAUDIO_DP_AMPSUB AUDIO RSUBIN_N
AUDIO_DP_AMPSUB ANL_AUDIO AUDIO RSUBIN_P
AUDIO_DP_AMPSUB AUD_SPKRAMP_RSUBIN_PAUDIOANL_AUDIO
AUDIO_DP_AMPSUB ANL_AUDIO AUDIO AUD_LO3_R_N
AUDIO_DP_AMPSUB LSUBIN_NAUDIOANL_AUDIO
AUD_SPKRAMP_LSUBIN_PAUDIO_DP_AMPSUB AUDIOANL_AUDIO
AUDIO_DP_AMPTWT ANL_AUDIO AUDIO SPKRAMP_RIN_N
AUDIO_DP_AMPTWT ANL_AUDIO AUDIO SPKRAMP_RIN_P
AUDIO_DP_AMPSUB ANL_AUDIO AUDIO AUD_LO3_L_P
AUDIO_DP_AMPTWT ANL_AUDIO AUDIO AUD_SPKRAMP_RIN_N
AUDIO_DP_AMPTWT ANL_AUDIO AUDIO AUD_SPKRAMP_RIN_P
AUDIO_DP_AMPTWT AUD_LO2_R_NAUDIOANL_AUDIO
AUDIO_DP_AMPTWT AUD_LO2_R_PAUDIOANL_AUDIO
AUDIO_DP_AMPTWT SPKRAMP_LIN_NAUDIOANL_AUDIO
AUDIO_DP_AMPTWT ANL_AUDIO AUDIO AUD_SPKRAMP_LIN_N
AUDIO_DP_AMPTWT ANL_AUDIO AUDIO AUD_LO2_L_N
AUDIO_DP_AMPTWT ANL_AUDIO AUDIO AUD_SPKRAMP_LIN_P
AUDIO_DP_AMPTWT ANL_AUDIO AUDIO AUD_LO2_L_P
SENSE_DP ISNS_TPAD_PSENSESENSE_45S
ISNS_HS_OTHER3V3_NSENSE_45SSENSE_DP SENSE
SENSE_DP_CPUVR CPUVR_ISNS_PSENSESENSE_45S
SENSE_DP SENSE_45S SENSEISNS_HS_OTHER5V_N
THERMTHERM_DP_CPU_D2 THERM_45S CPUTHMSNS_D2_N
THERM_DP_CPU_D2 THERM_45S THERMCPUTHMSNS_D2_P
THERM_45S THERMTHERM_DP_CPU_D1 CPUTHMSNS_D1_P
SENSE_DP_CHGR_CSI CHGR_CSI_PSENSESENSE_45S
SENSE_DP_CHGR_CSI CHGR_CSI_NSENSESENSE_45S
SENSE_DP_CHGR_CSI CHGR_CSI_R_PSENSESENSE_45S
SENSE_DP_CHGR_CSI CHGR_CSI_R_NSENSESENSE_45S
SENSE_DP_CHGR_CSO CHGR_CSO_NSENSESENSE_45S
SENSE_DP_CHGR_CSO CHGR_CSO_PSENSESENSE_45S
SENSE_DP_CHGR_CSO CHGR_CSO_R_PSENSESENSE_45S
SENSE_DP_CHGR_CSO CHGR_CSO_R_NSENSESENSE_45S
SENSE_DP_TBT ISNS_TBT_NSENSESENSE_45S
SENSE_DP_LCDBKLT ISNS_LCDBKLT_NSENSESENSE_45S
NC_ISNS_CAMERAPSENSESENSE_45S
ISNS_HS_COMPUTING_PSENSE_DP SENSE_45S SENSE
ISNS_PP5VS0_NSENSE_DP SENSESENSE_45S
THERM_DP_CPU_D1 THERM_45S CPUTHMSNS_D1_NTHERM
CPUVR_ISNS2_PSENSESENSE_45S
SENSE_45S
SENSE_DP ISNS_1V05_S0_NSENSE
CPUVR_ISNS_R_PSENSE_DP_CPUVR SENSESENSE_45S
NC_ISNS_DDR_S3NSENSE_45S SENSE
SENSE_DP_CPUHIGAIN SENSE_45S SENSEISNS_CPUHIGAIN_N
SENSE_DP_CPUHIGAIN SENSE_45S SENSEISNS_CPUHIGAIN_P
SENSE_DP_CPUHIGAIN SENSESENSE_45S ISNS_CPUHIGAIN_R_P
SENSE_DP_CPUHIGAIN ISNS_CPUHIGAIN_R_NSENSESENSE_45S
THERM_45S
THERMTHERM_DP_TBT_D1 TBTTHMSNS_D1_P
THERM_45S THERMTHERM_DP_TBT_D1 TBTTHMSNS_D1_N
SENSE_45SSENSE_DP ISNS_HS_OTHER5V_PSENSE
CPUVR_ISNS2_NSENSESENSE_45S
SENSE_DP ISNS_SSD_NSENSESENSE_45S
SENSE_DP ISNS_SSD_PSENSESENSE_45S
SENSE_45S
SENSE_DP ISNS_1V05_S0_PSENSE
NC_ISNS_DDR_S3PSENSE_45S SENSE
AUDIO
AUDIO_DP_SPKSUB DIG_AUDIO SPKRCONN_SL_OUT_P
ISNS_PP5VS0_PSENSE_DP SENSESENSE_45S
ISNS_PP3V3S0_NSENSE_DP SENSESENSE_45S
ISNS_PP3V3S0_PSENSE_45SSENSE_DP SENSE
ISNS_TPAD_NSENSE_DP SENSESENSE_45S
CODEC_HS_MIC_PAUDIO_DP_MIC AUDIOANL_AUDIO_WIDE
HS_MIC_PAUDIO_DP_MIC AUDIOANL_AUDIO_WIDE
AUD_CONN_SLEEVE_XWAUDIOAUDIO_DP_MIC ANL_AUDIO_WIDE
AUD_CONN_SLEEVEAUDIO_DP_MIC AUDIOANL_AUDIO_WIDE
AUD_CH_HS_GNDAUDIOAUDIO_DP_MIC ANL_AUDIO_WIDE
ANL_AUDIO_WIDE
AUD_HP_PORT_REFCHAUDIO_DP_MIC AUDIO
AUD_CONN_HS_MIC_PAUDIOAUDIO_DP_MIC ANL_AUDIO_WIDE
AUD_HS_MIC_PAUDIO_DP_MIC AUDIOANL_AUDIO_WIDE
AUD_HS_MIC_NANL_AUDIO_WIDE AUDIOAUDIO_DP_MIC
AUD_CONN_HS_MIC_NANL_AUDIO_WIDEAUDIO_DP_MIC AUDIO
AUD_HP_PORT_REFUSANL_AUDIO_WIDE AUDIOAUDIO_DP_MIC
AUD_CONN_RING2ANL_AUDIO_WIDE AUDIOAUDIO_DP_MIC
AUD_CONN_RING2_XWANL_AUDIO_WIDEAUDIO_DP_MIC AUDIO
AUD_US_HS_GNDANL_AUDIO_WIDE AUDIOAUDIO_DP_MIC
HS_MIC_NANL_AUDIO_WIDE AUDIOAUDIO_DP_MIC
CODEC_HS_MIC_NAUDIOAUDIO_DP_MIC ANL_AUDIO_WIDE
PP3V3_S0SB_POWER
PP3V3_S5SB_POWER
GNDGND
<BRANCH>
<SCH_NUM>
<E4LABEL>
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46 48
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40
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42 52
42 52
42
40 58
42
40 42
41
43
41 54
41 57
41
41 55
42 43
42 43
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23 43
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41 54
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41 55
48 50 68
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59 60 61 65 68 www.rosefix.com

Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
124578
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87 6 5 4 3
C
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NOTICE OF PROPRIETARY PROPERTY:
PAGE
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PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
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SIZEDRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AFP://KISMET.APPLE.COM/KISMET-PROJECTS/J44
<RDAR://COMPONENT/XXXXXX> J44 HW EE SCHEMATIC | PROTO 0
Change List:
Useful Wiki Links:
Schematic Design Wiki - https://hmts.ecs.apple.com/wiki/index.php/Schematic_Design
<rdar://component/497587> MobileMac HW | Schematic
<rdar://component/497590> MobileMac HW | Investigation
<rdar://component/497588> MobileMac HW | Layout
MobileMac HW Radar:
<rdar://component/497589> MobileMac HW | Architecture
Kismet:
<rdar://component/497585> MobileMac HW | New Bugs
Other Info:
<rdar://component/497591> MobileMac HW | Task
Page Allocations - <rdar://problem/11791318> 2012 Schematic Page Allocations
Schematic Conventions - https://hmts.ecs.apple.com/wiki/index.php/User:Wferry/SchConventions
Reference
SYNC_MASTER=J44 SYNC_DATE=08/12/2013
<BRANCH>
<SCH_NUM>
<E4LABEL>
120 OF 120
78 OF 78www.rosefix.com

Circuito eletrônico da placa J44 4G_820-3536.pdf

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Circuito eletrônico da placa J44 4G_820-3536.pdf

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