CLOCKED RESET DOMINANT SR-LATCH

SR latch, Latch, reset latch, set latch

1. DEPARTMENT OF ELECTRONICS & COMMUNICATION
ENGINEERING
TOPIC
CLOCKED RESET -DOMINANT SR -LATCH
S UBMI TTED BY
G AN ES HK UMAR . P(21 3 04 01 3)
PONDICHERRY UNIVERSITY
ChinnaKalapet, Kalapet
Puducherry -605014

2. Outlines
•Introduction
•SR-Latch
•Operation of the S-R latch based on the inputs applied
•SR-latch NAND and NOR circuit & truth table
•Gated S-R Latch
•Gated S-R Latch circuit & truth table
•Usually, the NAND implementation of S-R is in the active low type
•Behavioral rules for a basic cell
•Model of Simulink SR-latch
•Result
•Advantages & Disadvantages
•Application

3. Introduction
A latch is one of the basic memory elements that store information in a digital
system. One latch can store 1-bit of information. The outputs of a latch are
constantly changing according to the inputs as long as the latch is enabled. In
other words, the content of a latch changes immediately when the inputs change
when it is enabled. When a latch is not enabled, the latch holds the value that is
stored.
Here we will talk about two different kinds of latches: an SR-Latch and a D-Latch.
The differences between them are the number of inputs and how they change
the state.

4. SR-Latch
An asynchronous latch that works based on applied set and reset signals
without relying on control signals is referred to as S-R Latch.It produces two
outputs that are labeled as Q and Complement of Q. These gates are
constructed by using the universal gates NAND or NOR.
The gate constructed by using cross-coupled NAND gates is of active Low
type S-R gate. The active-low can be converted to high by including the
inverters at the inputs.By using two cross-coupled NOR gates one can
produce an active high S-R gate

5. Operation of the S-R latch based on the inputs
applied
When SET = HIGH, Q=1. When RESET = HIGH, Complement of Q=1
(i.e.,Q=0).
When SET=RESET= LOW, there is no change evident in the latch state. This
state is also referred too as the prior state before the application of inputs.
when SET=RESET=HIGH. The outputs Q and complement of Q may be high
or low. The situation of the gates is unpredictable during such inputs. This
type of state is defined as Indeterminate or Invalid state. This leads to the
‘Race Around Condition’.

6. SR-latch NAND and NOR circuit & truth table

7. NAND Gate NOR gate
Truth Table

8. Gated S-R Latch
Generally, an S-R latch designed its behavior is sensitive to the inputs. To
make it more flexible an S-R Latch circuit is made synchronous by adding the
property of enable signal.If the Enable signal is HIGH then the operation is
performed based on the inputs applied and the change in the output is
detected.
If the applied Enable signal is LOW. Then the inputs are ineffective and no
change in the output states is detected. The enable signal used may also be a
clock signal.

9. Circuit Truth table
Gated S-R Latchcircuit & truth table

10. Usually, the NAND implementation of S-R is in the
active low type
•when ENABLE=1, the circuit is enabled. The S and R inputs behave in the
active HIGH manner.
•when ENABLE=0, the latch maintains the previous outputs in spite of the
change in the inputs of S and R.
•In the gated latches the signals applied for is Enable, Control or it might be
Clock.

11. Behavioral rules for a basic cell
•When just SET is active, Q is driven to '1' and QN is driven to '0’;
•When just RESET is active, Q is driven to '0' and QN is driven to '1’;
•When both SET and RESET are active, Q and QN are both driven to '0' (NOR
cell) or '1' (NAND cell);
•When neither SET or RESET are active, the output is determined by the logic
value “stored” in the feedback loop.

12. Simulink SR-latch

13. Result

14. Advantages Disadvantages
i.The latches designed by using
logic gates accommodate less
space.
ii.The non-sequential behavior of
the latches leads to stealing the
cycle to complete the operation
when it is required.
iii.These are known for responding
to the inputs applied and they
are quick by nature.
iv.It requires less amount of power.
i.There are certain disadvantages
of latches.
ii.Due to the level sensitivity, the
analysis of latches in the circuit
gets complicated.
Advantages & Disadvantages

15. Application
➢These circuits are known for storing the information in the form of bits.
These are known as memory elements.
➢The usage of pulse latches follows the same behavior of flip-flops but good
enough to generate a quick response.
➢In the two-phase synchronous systems to avoid the transit count, the data
latches (D-Latches) are used.
➢It is widely used to store the data and the codes for computations.

16. Thank you
FOR YOUR ATTENTION