Clocked Sequential circuit analysis and design

The presentation covers clocked sequential circuit analysis and design process demonstrated with example. State reduction and state assignment is design is also described.

1. Clocked Sequential Circuit: Analysis and Design
Learning Objectives:
1.To learn analysis of Synchronous Sequential Circuits
2.To learn Design of Synchronous Sequential Circuit
3.To learn State reduction and Assignment in design
4 April 2019 1
Dr NaimR Kidwai, Professor, Integral University,
LucknowIndia, www.nrkidwai.wordpress.com

2. Analysis of Clocked Sequential Circuit
4 April 2019
Dr Naim R Kidwai, Professor, Integral University,
Lucknow India, www.nrkidwai.wordpress.com
2
Outputs&stateofaclockedSequentialcircuitisfunctionofinputsandpreviousstate.
Analysisofclockedsequentiallogiccircuitconsistsofobtaining
•statetable: Alsocalledtransitiontableconsistsoffoursections;inputs,
presentstate,nextstateandoutput.
•statediagram:Graphicalrepresentationofstatetable.Astateisrepresentedbya
circleandtransitionbetweenstatesisrepresentedbyadirected
line.Inputandoutputvaluesofthetransitionisputonthedirected
line
•stateequation:Specifiesnextstateintermsofpresentstateandinputs.Output
equationisalsodescribedintermsofpresentstateandinputs

3. Analysis Steps
4 April 2019
Dr Naim R Kidwai, Professor, Integral University,
Lucknow India, www.nrkidwai.wordpress.com
3
State&outputequation
•Assignvariablenamestoinput,outputs,flipflopsinputandoutput
•DetermineFF’sinputequationsintermsofinputvariableandpresentstate.
•Determinenextstateequationofflipflop’susingFFcharacteristicequation(state
equation).Determinecircuit’soutputifany,intermsofinputvariable/presentstate
(outputequation).
StateTable
•Listallbinarycombinationofinputsandpresentstates
•ListnextstateofFF’sandoutputsusingstateequationandoutputequation.
StateDiagram
•MarkFFstatesandconnectthemwithdirectedlinestonextstatewithinput/output
valuesontheline.Eachrowofstatetablecorrespondtoadirectedline.

4. Analysis : Example
4 April 2019
Dr Naim R Kidwai, Professor, Integral University,
Lucknow India, www.nrkidwai.wordpress.com
4
D
AA A
Y
D
BB B
X
CLK
ExamplecircuithasoneinputX,twoDFFwithoutputsA&BandoneoutputY.DQ
XAD
BXAXD
n
B
A



1 FF; D ofequation sticcharacteri Using

s;FF' Input to  
equation;Output

equation; State
1
1
XBAY
XAB
BXAXA
n
n






5. Analysis: example
4 April 2019
Dr Naim R Kidwai, Professor, Integral University,
Lucknow India, www.nrkidwai.wordpress.com
5
00
01
11
10
1/0
1/0
1/0
1/0
0/0
0/1
0/1
0/1
State Table
input
Present
state
Next stateOutput
XA BA
n+1B
n+1Y
00 0 000
00 1 001
01 0 001
01 1 001
10 0 010
10 1 110
11 0 100
11 1 100 
 

equation;output State/
1
1
XBAY
XAB
XBAA
n
n






6. Design Steps
4 April 2019
Dr Naim R Kidwai, Professor, Integral University,
Lucknow India, www.nrkidwai.wordpress.com
6
•Fromtheworddescriptionandspecification,deriveastatediagramofthecircuit.
Reducethenumberofstateifpossible
•Assignbinaryvariablestothestate.
•Obtainstatetablefromstatediagram
•ChoosethetypeofFFtobeusedandfillthebinaryvaluesatFFinputforeachstate
transitionusingFFexcitationtable.
•DerivetheFFinputequation.FFinputandcircuitoutputarefunctionofinputsand
presentstatevariables
•DrawthelogicdiagramusingFFinputequationsandcircuitoutputequation

7. Design Example: Sequence Detector
4 April 2019
Dr Naim R Kidwai, Professor, Integral University,
Lucknow India, www.nrkidwai.wordpress.com
7
Designasequencedetectorwhichdetectsthreeormore1’scomingtoaninputline.
Ondetectionofpersequence,a‘1’isgenerated
•Letinitialstateofcircuitiss
0
•Ifinputis‘0’,stateisunchanged
•Ifinputis‘1’,statechangestos
1(a‘1’hasarrived)
•Ifstateofcircuitiss
1
•Ifinputis‘0’,statechangestos
0(a‘0’hasarrived)
•Ifinputis‘1’,statechangestos
2(a‘1’hasarrived)
•Ifstateofcircuitiss
2
•Ifinputis‘0’,statechangestos
0(a‘0’hasarrived)
•Ifinputis‘1’,statechangestos
3(a‘1’hasarrived)
•Ifstateofcircuitiss
3
•Ifinputis‘0’,statechangestos
0(a‘0’hasarrived)
•Ifinputis‘1’,stateisunchanged(a‘1’hasarrived)
s
0
s
1
s
2
s
3
1/0
1/0
1/1
1/1
0/0
0/0
0/1
0/0

8. Design Example: Sequence Detector
4 April 2019
Dr Naim R Kidwai, Professor, Integral University,
Lucknow India, www.nrkidwai.wordpress.com
8
00
01
10
11
1/0
1/01/1
1/1
0/0
0/0
0/0
0/0
State Table
inputPresent stateNext state
Input
conditions
Outpu
t
XA BA
n+1B
n+1T
A T
B Y
00 0 00 0 0 0
00 1 00 0 1 0
01 0 00 1 0 0
01 1 00 1 1 0
10 0 01 0 1 0
10 1 10 1 1 0
11 0 11 0 1 1
11 1 11 0 0 1
LetinputisX.Torepresent4states,2FF’sarerequired.LetTFF’s
hastobeused.Stateassignment:s
0→00,s
1→01,s
2→10,s
3→11
Statediagram
Excitation Table of T FF
Q
n Q
n+1 T
0 0 0
0 1 1
1 0 1
1 1 0

9. Design Example: Sequence Detector
4 April 2019
Dr Naim R Kidwai, Professor, Integral University,
Lucknow India, www.nrkidwai.wordpress.com
9 
    
 XABAXY
BABXBXBABXBAXT
BAXAXBAXT
B
A






7,6,,
6,5,4,3,1,,
5,3,2,,
WritingT
A,T
B,andYasafunctionofX,A,Bin
SOPformandsimplifyingusingK-map
T
AA A
Y
T
BB B
X
CLK

10. State Reduction and Assignment
4 April 2019
Dr Naim R Kidwai, Professor, Integral University,
Lucknow India, www.nrkidwai.wordpress.com
10
StatereductionaimstoreducenumberofFF’sbyreducingnumberofstates,while
keepinginputoutputrelationshipunchanged.
Step1:Makethereducedstatetable
a
0/0
b
d
f
g e
c
1/1
1/0
1/1
0/0
1/1
1/1
0/0
1/1
0/0
0/01/0
0/0
0/0
PresentState
Next State Output
X=0 X=1 X=0 X=1
a a b 0 0
b c d 0 0
c a d 0 1
d e f 0 1
e a f 0 1
f g f 0 1
g a f 0 1

11. State Reduction and Assignment
4 April 2019
Dr Naim R Kidwai, Professor, Integral University,
Lucknow India, www.nrkidwai.wordpress.com
11
Step2:Findequivalentstateinreducedstatetableandremoveoneofthem
Twostatesareequivalentif,theygivesamesetofoutput,gotosamestateor
equivalentstateforinputs
state‘e’and‘g’areequivalent.Rowcorrespondingto‘g’isremovedintable
andstate‘g’isreplacedby‘e’elsewhere
PresentState
Next State Output
X=0 X=1 X=0 X=1
a a b 0 0
b c d 0 0
c a d 0 1
d e f 0 1
e a f 0 1
f e f 0 1

12. State Reduction and Assignment
4 April 2019
Dr Naim R Kidwai, Professor, Integral University,
Lucknow India, www.nrkidwai.wordpress.com
12
Step3:Repeatthestep2ifanyequivalentstateisfoundagain
state‘d’and‘f’areequivalent.Rowcorrespondingto‘f’isremovedintable
andstate‘f’isreplacedby‘d’elsewhere
PresentState
Next State Output
X=0 X=1 X=0 X=1
a a b 0 0
b c d 0 0
c a d 0 1
d e d 0 1
e a d 0 1

13. State Reduction and Assignment
4 April 2019
Dr Naim R Kidwai, Professor, Integral University,
Lucknow India, www.nrkidwai.wordpress.com
13
Step3:Repeatthestep2ifanyequivalentstateisfoundagain
state‘c’and‘e’areequivalent.Rowcorrespondingto‘e’isremovedintable
andstate‘e’isreplacedby‘c’elsewhere
PresentState
Next State Output
X=0 X=1 X=0 X=1
a a b 0 0
b c d 0 0
c a d 0 1
d c d 0 1
Step4:Ifnoequivalentstateisfound,statereductioniscomplete.Assignbinaryvalues
tostatesandimplementthecircuit.
Finalreduceddiagramisshowninfigure,whichhasfourstatesie.Require2FF’s
a
0/0
b
d
c
1/0
1/1
0/0
1/1
0/01/0
0/0