CMOS Image Sensor Design_h20_3_photodiode_pixels_1sep2020.pdf

CMOS Image Sensor Design_h20_3_photodiode_pixels_1sep2020

1. IN5350 –CMOS Image Sensor Design
Lecture 3 - Light detection and 4T pixel circuit
principles

2. Course project
•Project size / scope: 40-60hrs total
•Schedule: see next slide
•Grade: Project report counts 25% of final grade (exam counts 75%)
•Topic&fieldis flexible/optional. Some suggestions:
–Analog design (e.g. SNR modelling, design&simulatepixel array
and readout circuits, HDR sensor design, GS sensor design)
–Digital design (e.g. RTL design: readout timing and/or ISP
functions such as BLC, DPC, LENC, CI, TM, JPG)
–Algorithm design (Matlab/Python: ISP, AEC, AWB)
•Oblig. deliverables: (i) Project plan, (ii) Project report, (iii) Presentation
•For access to nanolab in 5
th
floor email your name, username, and card
number to Olav Stanly Kyrvestad<
[email protected]>
•All SW (Cadence, Matlab, etc) available on all machines at IFI, as well as
via remote login from external computer
2

3. Project schedule
Task/milestone Start Finish
Chose topic and define scope 1-Sep 8-Sep
Create project plan (tasks, milestones, schedule) 8-Sep 15-Sep
MS1 –project plan approved by Johannes 15-Sep 22-Sep
Study literature on the topic (include summary in report)22-Sep 29-Sep
Design implementation&simulation 29-Sep 13-Oct
Write up prelim report (increferences, design, results)13-Oct 20-Oct
MS2 –submit preliminary report to Johannes 20-Oct 20-Oct
Design/simulation (fine tuning) 20-Oct 27-Oct
Write up final report (inclreferences, design, results)27-Oct 3-Nov
MS3 –Presentation and discussion 3-Nov 3-Nov
MS4 –submit final report to Johannes 10-Nov 10-Nov
Exam 18-Nov 2019
3

4. References
•Obligmaterial are these slides and the accompanying exercises
•Recommended books
–Physics of Semiconductor Devicesby Simon M. Sze and Kwok
K. Ng(Oct 27, 2006)
–Solid-State Imaging with Charge- Coupled Devices (Solid- State
Science and Technology Library)byAlbert J. P.
Theuwissen(Mar 31, 1995)
•Recommended online sources
–Excellent PN junction literature on Wikipedia
–http://pveducation.org/pvcdrom/pn- junction/conduction- in-
semiconductors
4

5. Camera signal chain
01/09/2020 5
Photodiode
This section

6. Valence band
Conduction band
Intrinsic silicon
01.09.2020 6
Si atom density: 5x10
22
cm
-3
p
i= n
i≅10
10
cm
-3
at 300K
p
i: intrinsic hole concentration (thermally generated)
n
i: intrinsic electron concentration (thermally generated)
Electron energy, E
E
C
E
V
E
g=1.12eV at RT

7. Photoelectric effect in Semiconductors
01.09.2020 7
-
-
-
-
-
E
g
Conduction band
Valence band
+ + + + +
νh
E
v
E
c
Condition for detection :
Band- gap in Silicon:
λ
cut-off≈ 1,1 um
Photon energy (Joule) :
λ
ν
c
hhE ==
g
Eh≥ν
JE
g
19
108,1
−
⋅≈
gE
hc
≤
λ
Cut-off wavelength in Silicon :
Energy level

8. Photon absorption in Silicon
Si Si Si
Si Si Si
Si Si Si
Electron
e-
Hole
•CMOS image sensors detect light by generating electron- hole pairs
•Accumulatedelectrons are converted into a proportionalvoltage
(theholes aredrainedto GND, iedo not contributeto signal out)
h+
01.09.2020
8
νh

9. Photoelectric effect remarks
•Occurs in both intrinsic and doped silicon (cf
photodiode)
•Normally one photon creates one electron, only.
–Excess energy goes to heating
–High-energy particles, e.g. X-ray, can create multiple
electrons (as well as damage the Si crystal structure)
•Other semiconductors with smaller bandgap
energy (e.g. SiGe , PtSi) can detect longer
wavelengths, i.e. in the IR spectrum
01.09.2020
9

10. Quantum efficiency (QE)
01.09.2020
100%
QE (%)
Ideal response
Wavelength (nm)
Losses due to
reflections, etc.
Cut-off wavelength
in Silicon
•QE: probability of photon detection, i.e. N
elec/N
phot
•Determines light sensitivity
50%
0%
300nm
1100nm
Typical Silicon detector
10
Visible spectrum

11. QE remarks
•Photo- generated charges outside the depletion
layer do not experience any electric field.
Hence, they tend to diffuse in all directions and
may get lost through recombination
•Depending on wavelength, photons can go
several microns deep into silicon before being
absorbed by a Si atom
•Therefore, the larger the depletion layer width
(read: low doping concentration) the better the
QE
01.09.2020
11

12. Absorption of light in Silicon
12
Φ(x)=Φ
0????????????????????????????????????(−????????????????????????)
Φ(x): photon flux, α: absorption coefficient (cm
-1
)
x: distance from silicon surface (cm)

13. Absorption of light in Silicon
(intensity versus depth)
13
ϕ(1/????????????)=1/e=0.37
Light penetration
depth, 1/α
Ref: J Nakamura, ch- 3

14. QE dependent onSi thickness, ielength
ofopticalpathin silicon
14
100%
QE
Wavelength
Normal substrate
thickness(3-5um)
50%
0%
300nm
1100nm
400nm 700nm
Thicksubstrate
(>10um)

15. N-type silicon with Phosphor donors
01/09/2020 15
N
D: dopant concentration
n
0: free electron concentration
n
0≅N
D
From n
0p
0= n
i
2we get p
0
≅n
i
2/N
D
Electron energy, E
E
C
E
V
E
F
E
i
qɸ
Fn<0
????????????
????????????????????????≈−????????????
????????????????????????????????????
????????????
????????????
????????????
????????????
????????????
????????????=
????????????????????????
????????????
≈26mV at RT

16. P-type Silicon with Boron acceptors
01.09.2020 16
N
A: dopant concentration
p
0≅N
A
n
0≅p
i
2/N
A
Electron energy
E
C
E
V
E
F
E
i
qɸ
Fp>0
????????????
????????????????????????≈????????????
????????????????????????????????????
????????????
????????????
????????????
????????????
????????????
????????????=
????????????????????????
????????????
≈26mV at RT

17. Electric field = ∫(Chargedensity)
01.09.2020 17
Total charge density (⍴) is sum of all contributions:
????????????=????????????(????????????−????????????+????????????
????????????−????????????
????????????) (1)
Gauss’s law:
??????????????????
????????????????????????
=
????????????(????????????)
∈
????????????
(2)
where ℇ(y)=electric field in y-direction
????????????(????????????)=charge density in y-position
∈
????????????=permittivity of silicon=k
s∈
0=11.9 x 8.854E-14 F/cm

18. PN junction
01.09.2020 18
Zero bias Forward bias Reverse bias

19. Reverse biased PN junction
01.09.2020 19

20. Reverse biased PN junction
01.09.2020 20
????????????
1=+????????????(????????????
1????????????)????????????
????????????
????????????
2=−????????????(????????????
2????????????)????????????
????????????
????????????
1=−????????????
2
????????????
1
????????????
2
=
????????????
????????????
????????????
????????????
Using Gauss’ law, the electric field is the integral of charge
density divided by permittivity. Thus:
ℇ
????????????????????????????????????????????????=
????????????????????????
????????????????????????
1
????????????
????????????
=
????????????????????????
????????????????????????
2
????????????
????????????
Integrating the field gives the voltage. Thus:
????????????
1=
ℇ
????????????????????????????????????????????????????????????
1
2
=
????????????????????????
????????????????????????
1
2
2????????????
????????????
????????????
2=
ℇ
????????????????????????????????????????????????????????????
2
2
=
????????????????????????
????????????????????????
2
2
2????????????
????????????
????????????
????????????=11.7????????????
0
????????????
0=8.85�10
−12
????????????/????????????
N
D
N
A

21. Reverse biased PN junction
•Let
•where V
Ris the reverse bias voltage
•Combining with previous page we get
•where d
1+d
2is the total depletion width of the
reverse biased PN junction
01.09.2020
21
????????????
????????????=????????????
1+ ????????????
2=????????????
????????????+????????????
????????????
????????????
1+????????????
2=
2????????????
????????????
????????????
�
????????????
????????????+????????????
????????????
????????????
????????????????????????
????????????
�????????????
????????????

22. One-sided (n+p) step junction
01.09.2020 22
????????????
????????????>>????????????
???????????? ????????????
2>>????????????
1
From above this implies
????????????
2>>????????????
1
????????????
2≅????????????
????????????
This means the potential drop appears almost entirely on the p side.
????????????
2=
2????????????
????????????
????????????????????????
????????????
????????????
????????????

23. PN junction light detector (Photodiode)
01.09.2020 23
Depletion region
+
-
e-h+
++++++++
++++++++
++++++++
++++++++
++++++++
++++++++
++++++++
-------------
-------------
-------------
-------------
-------------
-------------
-------------
N-type P-type
VFD
VRST
VRST
Exposure
time
V
FD
Low light level
Medium light level
Bright light

24. CMOS devices
G
DS SDB B
p-substrate
n-well
P+ P+ n+ n+
G
PMOS NMOS
01.09.2020
24

25. Pinned photodiode
0V
p-substrate
n-well
P+ p+ n+ n+
01.09.2020 25
Floating diffusion
output node
Surface pinned to 0V
Fully depleted after
reset operation, i.e.
at start of light
integration
FD
Transfer gate
TG

26. Potential well diagram
TG
01.09.2020 26
RST
V
DD
1.8V
2.8V
3.0V
2.0V
PD FD
Vpin = photodiode pin
voltage, i.e. when n-
region is fully depleted

27. NP photodiode
27
P-doped silicon substrate
N-doped
photodiode
Gate
hυ
e-
e-
e-
e-
e-
e-
e-
e-
Capacitive
output node
translates photon
charges (e-) into
proportional
voltage drop
(∆V)
hυ hυ
hυhυ
hυ
Photons
C
G
Source follower
Vout
∆V
Floating
diffusion
(FD)
Problem: thermally generated (dark) electrons in Si/SiO
2interface
(e.g. I
dark=1-10nA/cm
2
)

28. Si –SiO2 interface (crystal structure
mismatch)
01.09.2020
28
+
-
E
v
E
c
electron
hole
Si/SiO2 crystal mismatch lead to
interstitial energy levels that electrons
use as stepping stones to reach E
c=>
dark current noise
E
d1
E
d2
E
d3
E
d1-3: crystal defect states

29. Pinned photodiode
29
P-sup
N-doped
photodiode
Transfer
gate
Floating diffusion
node (FD)P+ doped
surface
layer
(pinned at
GND)
absorbs
any dark
electrons
SiO2

30. Camera signal chain
01/09/2020 30
Photodiode
This section

31. Readout of pinned photodiode
01.09.2020 31
RST
V
RST
V
DD
M
rst
M
sf
M
sel
ROW
COL
TX
M
tx
RST
ROW
V
FD
T
int
V
COL
V
1V
2
N.A.
TX
PD
FD
M
cs
Vbias

32. Small-Signal Capacitance of reverse
biased PN junction
01.09.2020
32
C
j
+∆Q
-∆Q
∆V
R
+
-
If the reverse bias is increased by a small amount, then the
depletion region width must increase on both sides. Hence, charges
must flow on both sides of the diode.
Operating
region

33. Small-signal capacitance of reverse
biased PN junction
01.09.2020
33
∆????????????
1=+∆????????????∆????????????
2=−∆????????????
????????????
????????????=
∆????????????
∆????????????
????????????
????????????
????????????=−
????????????????????????
2
????????????????????????
????????????
????????????
????????????′=
????????????
????????????
????????????
??????????????????
????????????=−
??????????????????????????????
2
????????????????????????
????????????
????????????
????????????
′=2????????????????????????
????????????????????????
????????????
2????????????
????????????+????????????
????????????????????????
=
????????????
????????????
????????????
2
One sided: ????????????
2
′=−
2????????????????????????
????????????????????????
????????????????????????
2
????????????
2=????????????
????????????+????????????
????????????????????????

34. One-sided step junction small-signal
capacitance vs reverse-bias voltage
01.09.2020
34
Note: CMOS pixels use reverse biased diode capacitance (aka
floating diffusion node) to convert photon charge into voltage.
Above voltage dependency can sometimes cause non- linear
response.

35. Camera signal chain
01/09/2020 35
Photodiode
This section

36. Introduction
•SF used in almost every digital camera that
exists; used in both CMOS and CCD sensors
•Widely used also in general ASICs as a voltage
buffer which can drive large capacitive loads
•Widely used due to its small size (only one
transistor inside pixel) which maximizes
photodiode area
01.09.2020
36

37. SF in 4T pixel
01.09.2020 37
RST
V
RST
V
DD
M
rst
M
sf
M
sel
ROW
COL
TX
M
tx
RST
ROW
V
FD
T
int
V
COL
V
1V
2
N.A.
TX
PD
FD
M
cs
Vbias

38. NMOS source follower
01.09.2020 38
M
cs
Vbias
M
sf
Vin
Vout
D
G
S
D
G
S
B
B
•Both devices in saturation
•Mcsacts as a fixed current
source (I
DSset by V
bias)
•Fixed I
DSimplies that V
GSof M
sf
is fixed. Thus, V
out‘follows’ V
in
keeping a constant V
GS
•V
SBof M
sfis not zero => body
effect applies
VDD

39. Small signal equivalent circuit of SF
01.09.2020 39
g
mv
gs
g
mbv
sbv
gs
v
out=v
sb
v
in
r
02
r
01
????????????
????????????=
????????????
????????????????????????????????????
????????????
????????????????????????
=
????????????
????????????
????????????
????????????+????????????
????????????????????????+
1
????????????
01
+
1
????????????
02
????????????
????????????=
1
????????????
????????????+????????????
????????????????????????+
1
????????????
01
+
1
????????????
02

40. SF remarks
•M
sfsources current, M
cssinks current
–Asymmetric drive capability
–Check both rising and falling edge settling
•Acts as a level shifter where Voutequals Vin
minus approx. Vth
–
For PMOS: Voutequals Vin plusVth
•To keep M
csin pinch- off (saturation), V
outcannot
go too low => limited useful voltage swing
–Typical requirement: allow max 1% deviation from
the linear (straight line) curve
01.09.2020
40

41. For hand calculations of devices in
saturation use:
01.09.2020
41
????????????
????????????=????????????
????????????????????????
????????????????????????
????????????
????????????
????????????
????????????????????????−????????????
????????????????????????=2????????????
????????????????????????
????????????????????????
????????????
????????????
????????????
????????????
????????????
????????????=
1
????????????????????????
????????????
Assume:
g
mb<<g
m
????????????=0.1V
-1
????????????
????????????????????????
????????????????????????=400uA/V
2