CMOS integrated Fundamentals technology .ppt

CMOS (Complementary Metal-Oxide-Semiconductor) is a widely used digital logic technology that employs both NMOS and PMOS transistors to implement logic functions with very low static power consumption. In a CMOS inverter, the basic building block, the PMOS transistor connects to Vdd and conducts when the input is low, while the NMOS transistor connects to GND and conducts when the input is high, ensuring that only one transistor conducts at a time in steady state. This complementary arrangement provides sharp voltage transfer characteristics, high noise margins, and full-swing output signals. CMOS logic gates are formed by combining PMOS pull-up networks and NMOS pull-down networks according to the desired logic function, e.g., NAND, NOR. The main advantage of CMOS is its extremely low static power consumption and robustness, while dynamic power, which depends on switching activity, load capacitance, supply voltage, and frequency, dominates at high speeds. CMOS circuits are scalable and suitable for high-density VLSI designs, making them the standard technology for modern digital electronics. CMOS (Complementary Metal-Oxide-Semiconductor) is a fundamental technology in digital VLSI design that uses both NMOS and PMOS transistors to implement logic circuits with very low static power consumption. The basic CMOS inverter works by connecting a PMOS transistor to Vdd and an NMOS transistor to GND, with their gates tied together as input and drains connected as output. When the input is low, PMOS conducts and NMOS is off, pulling the output high; when the input is high, NMOS conducts and PMOS is off, pulling the output low. This complementary action ensures that ideally no direct path current flows in steady state, resulting in negligible static power dissipation. CMOS logic gates are constructed using pull-up PMOS networks and pull-down NMOS networks, arranged in series or parallel depending on the logic function, such as NAND or NOR. CMOS circuits offer high noise margins, full-swing output voltages, and strong driving capability, making them robust and reliable. Power dissipation in CMOS is primarily dynamic, proportional to the load capacitance, switching activity, supply voltage squared, and operating frequency (
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𝑡
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). CMOS technology is highly scalable, enabling dense VLSI integration, and forms the backbone of modern digital electronics, including microprocessors, memories, and ASICs. Furthermore, advanced CMOS techniques, such as adiabatic logic and low-power design strategies, focus on reducing dynamic power while maintaining speed and robustness. Scalable, enabling dense VLSI integration, and forms the backbone of modern digital electronics, including microprocessors, memories, and ASICs. Furthermore, advanced CMOS techniques,

1. 1
AGENDA
Study of IC Technology
MOS Transistor Theory
Inverters
Building Logic Circuits with CMOS
MOS Capacitance Estimation
Power Dissipation in CMOS
Stage Ratio
CMOS Dynamic Logic
Scaling of MOS Transistor Dimensions
CMOS Processing Technology
Sense Amplifier

2. 2
Study of IC Technology
 IC Technology
 Microelectronics Technology
 Feature Size

3. 3
IC Technology
• Depending on the no. of transistors to be fabricated IC technology
can be categorized as
• The important factor in achieving such complexity is scaling down
of the feature size.
Integration levelYear No. of transistorsDRAM Integration
SSI 1950s Less than 10
2
MSI 1960s 10
2
 10
3
LSI 1970s 10
3
 10
5
4K, 16K, 64K
VLSI 1980s 10
5
 10
7
256K, 1M, 4M
ULSI 1990s 10
7
 10
9
16M, 64M, 256M
SLSI 2000s Over 10
9
1G, 4G and Above

4. 4
IC Technology
Integration of a large function on a single chip provides:-
• Less area/ Volume and therefore, compactness
• Less Power consumption
• Less testing requirements at system level
• Higher reliability, mainly due to improved on-chip interconnection
• Higher speed, due to significant reduced interconnection length
• Significant cost saving

5. 5
Microelectronics Technology
P CMOS
Micro Electronics
Active Substrate
Silicon GaAs
Bipolar
TTL ECL
(Good Resistors)
Fast
Current : Majority None thro’
gate
Current : Majority + Minority
thro’ base
Inert Substrate
MOS
N

6. 6
Two basic technologies used for manufacturing IC’s are
• Bipolar
• MOS
• Bipolar : The main technology is low-power-schottky TTL
Disadvantage: High power dissipation.
Used for SSI and MSI.
• MOS : LSI technology uses MOSFETS since these can be packed
in small area.
• P-MOS Technology : It uses P-MOSFET ’s.
Mobility of holes - 240 cm
2
/v*sec
Holes are majority carriers & hence this is relatively slow.
• N-MOS Technology : It uses N-MOSFET ’s
Mobility of electrons -650 cm
2
/v*sec
Since electrons are majority carriers this technology is
faster than P-MOS.
• CMOS Technology : It uses combination of P-channel
and N-channel MOS.
Microelectronics Technology

7. 7
CMOS Technology
As shown above PMOS transistor is formed in a separate n-type region
known as n-well.
p–type body
n well
n+n+ p+ p+
S G D D G S
NMOS PMOS
Polysilicon
Gate Oxide
Thick SiO
2 (Isolation) SiO
2

8. 8
Attributes Of CMOS Technology
• Wide supply voltage range from 3 to 15 volt.
• Voltage required to switch gate is fixed percentage of V
DD
.
• Packaging density : Requires 2n devices for n input gate
• Fully restored logic level : Output settles at V
DD
or V
ss.
Therefore
called as restoring logic.
• Characteristics of CMOS technology lies between that of P-MOS
and N-MOS. It is faster than P-MOS but slower than N-MOS.
• Mainly used in systems that require portability or less power
consumption.
• It needs more processing steps as compared to N-MOS or P-MOS.

9. 9
Comparison - CMOS and Bipolar
Technologies
Unidirectional
devices
Bi-directional
devices
 Direction
HighLow Fan-out
LowHigh Packaging density
LowHigh Noise margin
LowHigh Input impedance
HighLow
 Static power dissipation
BIPOLARCMOSFACTORS

10. 10
• BI-CMOS TECHNOLOGY :
• It combines both bipolar and CMOS transistors on single substrate.
• MOSFET’s have limited driving capabilities while bipolar transistors
provide higher gain and better high frequency characteristics.
• The output drive capabilities of CMOS gate can be enhanced if
output stage is BJT.
• Used for implementing high performance digital systems.
• GaAs ( Gallium Arsenide ) TECHNOLOGY:
• Silicon MOS technology is main media for computers, but the
speed requirements for Supercomputers which are suppose to
operate at 10 BFLOPS (Billion Floating Point Operations per
second ) uses gallium arsenide technology.
BI-CMOS Technology

11. 11
Feature Size
Typically L = 1 to 10 µm, W= 2 to 500 µm and the thickness of oxide layer is in
the range 0.02 to 0.1 µm.

12. 12
N-MOSFET
layout
• Value of gate length (L) is called as feature size of manufacturing
technology.
• Thus feature size is function of IC technology.
Feature Size

13. 13
Year Vs Feature Size
<1  (sub micron
process)
1990s
< 2 1980s
5 1970-80
7 – 10 1970
FEATURE SIZEYEAR
Currently Feature size is in the range 0.25  to 0.15 

14. 14
• How many devices that can be fabricated on a 4 inch silicon wafer
with 5 technology ?
• N = No of devices = r
2
/ (5 X 5 
2
) = 3 X 10
8
N
• Thus 1/10th decrease in Feature size increase the Device
count 100 times.
DEVICE COUNT

15. 15
MOS TRANSISTOR THEORY
 Structure of MOS transistor
 Operation of enhancement NMOS

16. 16
Cross-sectional View of a Typical
N-MOSFET
• Central region of device consist of a Metal-Oxide-Semiconductor
• Subsystem made up of a conducting region called the gate [M],
on top of an insulating silicon dioxide layer [O]
• p-type silicon [S] epitaxial layer on top of a P
+
- substrate.
• n
+
regions constitute the drain and source terminals
• It has four terminals viz. Gate-G, Drain-D, Source-S and
Substrate-B.

17. 17
• p
+
regions constitute the drain and source terminals
• It has four terminals viz. Gate-G, Drain-D, Source-S and
Substrate-B.
Cross-sectional View of a Typical
P-MOSFET

18. 18
•For P-channel MOS substrate is of N type and source, drain are
formed with P type material.
•For N-channel MOS substrate is of P type while source & drain
are formed with N type material.
•Gate is polycrystalline silicon electrode and is insulated from
substrate by thin layer of silicon dioxide SiO
2
•Since the gate is insulated, MOSFET’s are also called as
Insulated Gate Field Effect Transistors ( IGFET )
•It is a voltage controlled device, the current through channel is
controlled by voltage applied to gate.
•MOSFET’s can be configured either as
Enhancement type MOSFET OR
Depletion type MOSFET
Metal Oxide Semiconductor
Field Effect Transistor

19. 19
Enhancement NMOS
• Lightly doped p-type material forms substrate
• Highly doped n
+
regions separated by substrate form drain & source
• When gate voltage V
GS = 0, drain current is zero.
• Since the gate is insulated, any positive voltage applied to
gate, will produce electric field across substrate.
Source
Drain
Gate
PMOS
Gate
Drain
Source
NMOS
G
D
S

20. 20
• This field will end on induced negative charges in p substrate.
• These negatively charged electrons, which are minority carriers in p
substrate, form an inversion layer. Current flows from source to drain
through this induced channel.
• More the positive voltage, More is the induced charge & hence more
current flows from source to drain.
• This is also called ‘Normally Off ’ MOS, since drain current is zero for
zero gate voltage.
• CMOS integrated circuits use enhancement type transistors only.
Enhancement MOS

21. 21
Enhancement MOS Cross-Section
Channel
Region
p-type substrate
(Body)
n+ n+
Source (S)
Gate (G) Drain (D)
L
Body (B)
Oxide (SiO
2)
Metal

22. 22


• In Depletion MOS structure, the source & drain are diffused on
P- substrate as shown above.
• Positive voltages enhances number of electrons from source to
drain.
• Negative voltage applied to gate reduces the drain current
• This is called as ‘ normally ON ’ MOS.
Depletion Type MOS
G
D
S
NMOS
Source
Drain
Gate
PMOS
Gate
Drain
Source
NMOS

23. 23
Operation Of N-MOS Transistor
• Depending on the relative voltages of the source, drain and gate, the
NMOS transistor may operate in any of three regions viz :
• Cut_off : Current flow is essentially zero (also called
accumulation region)
• Linear : (Non saturated region)-It is weak inversion region
drain current depends on gate and drain voltage.
• Saturation : It is strong inversion region where drain current
is independent of drain-source voltage.

24. 24
Cut-off Region
• With zero gate bias (V
GS=0) , no current flows between source
and drain, only the source to drain leakage current exists.
• Current-voltage relation : I
DS
= 0 V
GS
< V
T
p-type substrate
(Body)
Source (S)
V
DS
=0
n+
n+
n+
n+
V
GS
=0

25. 25
Linear Region
• Formation of Depletion layer
• Small positive voltage applied to gate causes electric field to be
produced across the substrate
• This in turn causes holes in P region to be repelled. This forms
the depletion layer under the gate.
V
DS
=00  V
GS V
t
p-type substrate
(Body)
Source (S)
n+
n+
n+
n+
Depletion Layer

26. 26
Linear Region
• Formation of Inversion layer :
• As the gate voltage is further increased, at particular voltage V
T
,
electrons are attracted to the region of substrate under gate thus forming

conduction path between source and drain.
• This induced layer is called ‘inversion layer’. The gate voltage necessary

to form this layer is known as ‘Threshold voltage’ (V
T
).
• As application of electric field at gate causes formation of inversion
layer, the junction is known as field induced junction.
V
DS=0V
GS > V
t
p-type substrate
(Body)
Source (S)
n+
n+
n+
n+
Inversion Layer

27. 27
Linear Region
•When V
DS is applied, the horizontal component of electric field (due
to source-drain voltage) and vertical component (due to gate-
substrate voltage) interact, causing conduction to occur along the
channel.
•When effective gate voltage (V
GS - V
T) is greater than drain
voltage, current through the channel increases. This is non
saturated mode. I
D = f (V
GS,V
DS)
V
DS
< V
GS
- V
t
V
GS
> V
t
p-type substrate
(Body)
Source (S)
n+
n+
n+
n+
Inversion Layer

28. 28
As V
DS
is increased, the induced Channel acquires a tapered shape and
its resistance increases with Increase in V
DS.
Here V
GS is kept constant at value > V
T
Saturation
V
DS
= V
GS
- V
t
V
GS > V
t
p-type substrate
(Body)
Source (S)
n+
n+
n+
n+
n- channel

29. 29
Saturation
•When V
DS > V
GS – V
T, V
GD < V
T, the channel becomes pinched- off &
transistor is said to be in saturation.
•Conduction is brought by drift mechanism of electrons under the
influence of positive drain voltage and effective channel length is
modulated.
p
V
DS
> V
GS
- V
t
V
GS
> V
t
p-type substrate
(Body)
Source (S)
n+
n+
n+
n+
n- channel

30. 30
N-CHANNEL MOSFET
Cut- off Region (V
GS < V
T)
I
DS  0
Linear Region (V
GS
 V
T
) & (V
DS
< V
GS
- V
T
)
I
DS
= 
n
[2.(V
GS
– V
T
) V
DS
– V
DS
2
]
Saturation Region (V
GS
 V
T
) & (V
DS


V
GS
- V
T
)
I
DS
= 
n
[(V
GS
– V
T
)
2
(1 + V
DS
)]
 is an empirical constant called as ‘channel length modulation’
MOSFET Drain Current Equations
 = k W/L;
called as gain
factor of the
device

31. 31
P-CHANNEL MOSFET
Cut- off Region (V
GS
> V
T
)
I
DS
 0
Linear Region (V
GS
 V
T
) & (V
DS
> V
GS
- V
T
)
I
DS
= 
p
[2.(V
GS
– V
T
) V
DS
– V
DS
2
]
Saturation Region (V
GS  V
T) & (V
DS 
V
GS - V
T)
I
DS
= 
p
[(V
GS
– V
T
)
2
(1 + V
DS
)]
 is an empirical constant called as ‘channel length
modulation’
MOSFET Drain Current Equations

32. 32
Where  = k W/L; called as gain factor of the device
k

= 
ox
/t
ox
called process transconductance parameter
t
ox
= Thickness of the gate insulator
L = Length of channel

ox
= Permitivity of gate insulator
Linear Region
Since 
n
= 2
p
=> k
n
= 2k
p
thus

n = 2
p

33. 33
Drain curve for NMOS operated with
V
GS> V
T

34. 34
I
D-V
DS characteristics
CUTOFF REGION

35. 35
I
GS
= 0
I
S
= I
D+
-
+
-
IV characteristics of NMOS
Transconductance curve

36. 36
INVERTER
 Static Load Inverters.
 CMOS Inverter.
 Switching Characteristics of CMOS Inverter
 Noise Margin

37. 37
Static Load Inverters
• When I = 1, inverter dissipates static
power
• Switching point of inverter depends on
ratio of R to R
ON
(on resistance of NMOS
device.)
Resistor load (passive)
• Static load inverter are Ratioed logic gates where logic levels are
determined by relative dimensions of composing transistors.
• Transfer function of inverter varies with load.
1]

38. 38
• Load is enhancement-mode NMOS device. Static power
dissipation occurs when I = 1.
• Output swings from nearly 0V to (V
DD – V
T(n)

)
• Using a transistor as a load tends to require much less
silicon area than a resistor.
• V
OL
can be close to 0V, depending on ratio of R
ON
of two
enhancement devices.
Active - Resistive Load
Enhancement NMOS
2]

39. 39
• Load device is always on, looks like a load resistor. Dissipates
static power when I = 1, V
GS = 0V always
• V
OH = 5V; VOL nearly 0V, depending on ratio of R
ON_dep to
R
ON_enh.
• Depletion-mode devices were used before it was economical to
put both p-type and n-type devices on the same die.
Active-Resistive Load
3]

40. 40
• As shown above PMOS device is acting as static load.
• Here also the load device is always on (conducting).
dissipates static power when I = 1.
• V
OH = 5V; V
OL nearly 0V, depending on ratio of R
ON-P to R
ON-N 
Active - Resistive Load
4]

41. 41
Characteristics of CMOS Inverter
R
in
= 
R
out =0
Noise Margin = V
DD
/2
Gain = 

42. 42
Characteristics of CMOS Inverter

43. 43

Actual Inverter Characteristics

44. 44
•V
IL represents the maximum logic 0 (LOW) input voltage that
will guarantee a logic 1 (HIGH) at the output
•V
IH represents the minimum logic 1 (HIGH) input voltage that
will guarantee a logic 0 (LOW) at the output
V
OH
= V
DD
V
OL
= 0
V
TH
= f ( R
ON-n
,R
ON-p
)
V
TH
= V
DD
/2 if R
ON-n
= R
ON-p
Inverter Characteristics

45. 45
Resolution of Gate Output Level
• When we join P and N switches, both will attempt to exert a logic
level at the output.

• For inverter with independent control of inputs, the possible levels
at the output of the pull-up and pull-down are as shown below
pull down
output
pull up
output
Combined
output
0 Z 0
Z 1 1
Z Z Z
0 1 crowbarred

46. 46
CUT-OFF LINEAR SATURATION
NMOSFET
V
GS
< V
T
V
IN
< V
T
V
GS
 V
T
V
IN
 V
T
V
DS
< V
GS
– V
T
V
OUT < V
IN - V
T
V
GS
 V
T
V
IN
 V
T
V
DS
 V
GS
– V
T
V
OUT  V
IN - V
T
PMOSFET
V
GS > V
T
V
IN
> V
T +
V
DD
V
GS  V
T
V
IN
< V
T
+ V
DD

V
DS > V
GS – V
T
V
OUT
> V
IN
– V
T
V
GS  V
T
V
IN
> V
T
+ V
DD
V
DS  V
GS – V
T
V
OUT
 V
IN
– V
T
Voltage Relation for Regions Of
Operation Of CMOS Inverter

47. 47

n
/
p
Ratio
• The ratio ßn (gain of NMOS) / ßp (gain of PMOS) determines the switching
point of the CMOS inverter.

48. 48
Switching Characteristics of CMOS Inverter
t
t

49. 49
• The switching speed of the CMOS gate is limited by time taken to
charge and discharge the load capacitance
t
t
Switching Characteristics of
CMOS Inverter

50. 50
Calculation of Fall Time
• Fall Time : The time required for output to fall from 90% to 10%
of its steady state value.
T
fall
= R
fall
* C
LOAD
R
fall = k * 1/β
n
T
fall
 3 C
L
/V
DD
β
n
• k is a constant that depends on threshold voltage and V
DD.
•

k = 3 to 4 for values of V
DD
= 3 to 5 volts & V
T
= 0.5 to 1 volt.
• The gain factor = 
n

ox
/t
ox
W/L

51. 51
Calculation of Fall Time
t = RC time constant
exponential formulas, e
-t/RC

52. 52

• Rise Time : The time required for the output to rise from 10%
to 90% of its steady state value and is given as
T
rise = R
rise * C
LOAD
R
rise
= k * 1/β
p
T
rise  3 C
L
/V
DD β
P
• Thus to achieve high speed circuits, the load capacitance should be
minimized.
• Lowering the supply voltage on a circuit will reduce the speed of
the gates in that circuit.
Calculation of Rise Time

53. 53
Calculation of Rise Time
Exponential rise time

54. 54
•Higher capacitance ==> more delay
•Higher on-resistance ==> more delay
•Lower on-resistance requires bigger transistors
•Slower transition times ==> more power dissipation (output stage
partially shorted)
•Faster transition times ==> worse transmission-line effects
•Higher capacitance ==> more power dissipation (fCV
2
power),
regardless of rise and fall time
Calculation of Rise & Fall Time

55. 55
•For equally sized n and p transistors β
n
= 2β
p
Hence T
fall = T
rise /2
•To equalize the rise and fall times of an inverter I.e T
rise = T
fall
must have ß
n = ß
p
•This means, that channel width for the p-device must be increased
to twice of the n-device. Hence if Lin = Lp then W
p= 2*W
n
•Thus ß
n
= ß
p
provides equal current source and sink capabilities.
•Thus equal charge and discharge times
Calculation of Rise & Fall Time

56. 56
Delay time : It defines the response of gate for change in input.
•Is measured between 50% transition points of input and output
waveforms.
•Gate displays different response times for rising and falling
waveforms.
•T
plh
Defines response time of gate for low to high output
transition
•T
phl
Defines response time of gate for high to low output
transition
•The overall propagation delay is average of these two
T
D = (T
phl + T
plh)/2


Delay Time

57. 57
CMOS Inverter - Summary
• CMOS inverter uses actively driven P-channel transistor is used as
pull-up drive.
• It allows maximum logic voltage level swing.
• Eliminates the static power dissipation as no current flows from
V
DD to ground in steady state.
• Number of transistors is 2N.
• It is ratio-less logic I.e.
• Output logic levels are independent of ratio of pull-up and
pull-down transistor sizes.

58. 58
CMOS Inverter - Summary
• Resistance of N-channel transistor is R
n
α L
n
/W
n
* K
n
• Resistance of P-channel transistor is R
p
α L
p
/W
p
* K
p
• But μ
n
= 2 μ
p
, hence β
n
= 2 β
p
.
• Hence in order to achieve symmetrical operation(equal rise &
fall time ) we must have
(L
n
* W
p
)/ (L
p
* W
n
)= k
n
/k
p
=2 Thus with this sizing N & P
transistors have equal I-V characteristics.

59. 59
Noise Margin
V
OH(MIN)
V
IH(MIN)
V
OL(MAX)
V
IL(MAX)
Output characteristics Input characteristics
Logic High
Output range
Logic low
output range
Logic High
input range

Logic low
input range

60. 60
• Determines the allowable variation in input
voltage of gate so that output is not affected.

• Is specified in terms of two parameters

• Low noise margin - NM
L
= V
IL(MAX)
- V
OL(MAX)
• High noise margin - NM
H
= V
OH(MIN)
-

V
IH(MIN)
 
Noise Margin

61. 61
Inductive Coupling Capactive Coupling Power & Gnd Noise
 
Noise in Digital Integrated Circuits

62. 62
If V
in is very noisy signal. Passing this signal through a symmetrical
inverter (Vinv1) would lead to erroneous values. Raising the
threshold to (V
inv2) yields correct response.
Noise in Digital Integrated Circuits
Response of standard Inverter Response of standard Inverter
with modified V
inv

63. 63
Effects of β
n/
β
p
CMOS inverter Noise margin
Noise in Digital Integrated Circuits

64. 64
Building Logic Circuits With CMOS
 MOS TRANSISTOR AS SWITCH
 SERIES & PARALLEL CONNECTION OF SWITCHES
 COMPLEMENTARY LOGIC GATE DESIGN
 TRANSMISSION GATE
 LOGIC DESIGN WITH TRANSMISSION GATE
 CMOS TRANSISTOR SIZING

65. 65
• P-MOS source is tied to V
DD
, used
to pull signals up.
Controloutput
G= ‘1’D=‘0’
G= ‘0’ D=‘Z’
ControlOutput
G= ‘0’D= ‘1’
G= ‘1’D=‘ Z’
MOS Transistors as Switch
• N-MOS source is tied to ground,
used to pull signals down

66. 66
Why N-MOS Transistor
Produces Weak ‘1’?
• Apply logic’1’ to Gate and Drain
• at time t = 0 ;V
GS= V
DD
• Capacitor starts charging and V
GS decreases as the source voltage
approaches its final value
• Decreasing V
GS
reduces the channel charge, while a smaller V
DS
indicate a reduction in the drain- source electric field.
•The Source will stop increasing in voltage when V
GS
reaches V
t
• at t   ;
V
out
= (V
DD
- V
t
) = V
max
(Known as threshold voltage loss)

67. 67
Why N-MOS Transistor
Produces Strong‘0’?
• Apply logic’1’ to Gate and logic’0’ to Source
• at time t = 0 ;Assume V
C
= V
DD
• NMOS transistor will begin to discharge capacitor and continue until
drain terminal reaches a logic’0’
•at t   ; V
C = 0V
The transistor is strongly conducting with large channel charge but
there is no current flowing since V
DS = 0V.

68. 68
Why PMOS Transistor
Produces Weak ‘0’ ?
• Apply logic’0’ to Gate and logic’0’ to drain
• at time t=0 ;Assume V
C= V
DD
• PMOS transistor will begin to discharge capacitor
•at t   ; V
C
= V
t
Since the transistor must maintain
min ( V
SG
) = V
t
for the conducting channel to exit

69. 69
Why PMOS Transistor
Produces Strong‘1’ ?
• Apply logic’0’ to Gate and logic’1’ to source
• at time t=0 ;V
GS= V
DD
• Capacitor starts charging and continue until drain terminal
reaches a logic’1’
• at t   ; V
C = V
DD
The transistor is strongly conducting with large channel charge but
there is no current flowing since V
DS = 0V.

70. 70
MOS Transistors as Switch
SWITCH G INPUT (SOURCE) OUTPUT(DRAIN)
N - Switch
X Z
V
DD STRONG 0
V
SS
WEAK 1
P - Switch

X Z
V
DD
STRONG 1
V
SS WEAK 0
I/P O/P
G=1
G=0
G=0
G=0
• Thus NMOS transistor produces active low logic at output.
• While PMOS gives active high logic at output.
Gate
G
D
Drain
S
Source
Gate
G
D
Drain
S
Source

71. 71
Series Connection Of Switches
• If N switches are placed in
series Y=‘0’ if A & B are ‘1’.

•Thus yields an AND function.
Y = A * B

• If P switches are placed in
series Y=‘1’ if A & B are ‘0’.
•
• Thus yields an NOR function.
Y = /A * /B

72. 72
Parallel Connection Of Switches
• When N switches are placed in
parallel Y=‘0’ if either A or B is ‘1’.
• Thus yields an OR function.
Y = A + B
• When P switches are placed in
parallel Y=‘1’ if either A or B is ‘0’.

• Thus yields an NAND function.
Y = /A +/B

73. 73
Complementary Logic Gate Design
A CMOS gate is combination of two networks as shown below
PUN
PDN
Y= /F
V
SS
V
DD
I/P
I/P
• Pull Up Network (PUN) consists of
P-MOS transistors. Thus implements
the logic function F

•Pull Down Network (PDN) consists of
N-MOS transistors. Thus implements
the logic function /F.

74. 74
CMOS NAND Gate Design
• PUP network consists of two parallel P-MOS transistors
• PDN network consists of two series N-MOS transistors
WHY ???

75. 75
CMOS NAND Circuit

76. 76
NOR Gate Design
PUN = /A * /B PDN = A + B

Y = /(A + B)

77. 77
NOR Circuit

78. 78
AND Gate Design
POORLY DESIGNED AND GATE !!!

79. 79
AND Gate Design
Instead use this !

80. 80
Designing Compound Gates
• To implement the function F = /((A+B+C)*D)
• PDN will provide 0’s of function F.
• Hence equation of PDN is (A+B+C) * D.
• For PUN network will provide
1’s of function F
• Equation for PUN is (/A*/B*/C)
+/D

81. 81
Transmission Gate
• By combining an N-switch and P-Switch in parallel perfect
transmission of both ‘1’s and ‘0’s is achieved.
• When I=0 both N & P devices

are OFF
V
IN


V
OUT
X Z
• When I=1 both N & P devices

are ON
V
IN

V
OUT
V
DD
V
DD
V
SS
V
SS

82. 82
Transmission Gate
• Schematic icons for transmission gate
Most widely used

83. 83
Transmission Gate Characteristics
2:1 multiplexer
Y = SA +/SB
• This implementation will need total 6 Transistors
• 4 Transistors for two pass gates
• 2 Transistors for inversion of S
• Thus transmission gate logic uses less gates than the design
with normal gates.

84. 84
Transmission Gate Characteristics
But it has got Demerits !
• It is non restoring logic output levels may or may not settle at V
DD

or V
SS
(as it passes logic level at input to output ) where as CMOS
gates provides restoring logic.
• It has no drive capability, drive comes from original A, B inputs
What about CMOS gate?
• Transmission gates provide no isolation between input and
output.
•Then Why & Where Transmission gates are used ?

85. 85
Logic Design Using Transmission gate
2:1 Multiplexer Y = SA + /SB
A

B S Y
X 0 00(B)
X 1 01(B)
0 X 10(A)
1 X 11(A)
• When S= 1, S1 is ON and S2 is OFF. Hence input A is connected
to the output.
• When S= 0, S1 is OFF and S2 is ON. Hence input B is
connected to the output.

86. 86
• Multiplexer may also be constructed using logic gates
• However these implementations are larger and consume more
power than a transmission gate implementation
Comparison of
Multiplexers
4
Transmission Gates
12 Why ?Static CMOS Gates
Transistor Count Design Style
2:1 Multiplexer

87. 87

EN I O
0 X Z
1 0 1
1 1 0
Tristate Inverter
Total 6 transistors !

88. 88
EN Q
1 D
0 Q
old
D LATCH Positive level sensitive
How will the circuit function ?

89. 89
• When EN = 1, switch S1 is closed and S2 is open.
• Hence Output-Q follows Input D
D-LATCH With En = 1

90. 90
• When EN = 0, switch S1 is open and S2 is closed.
• Hence,
• Output-Q is isolated from Input D.
• Output retains the value of D at the falling edge of EN [ WHY ???]
D-LATCH With En = 0

91. 91
D-LATCH with Asynchronous Reset
• How to implement asynchronous clear?

92. 92
Edge Triggered D - Register
• By combining two latches in master-slave arrangement, edge
triggered register can be constructed.
• For positive edge triggered first latch(master) is negative level-
sensitive latch

93. 93
Rising Edge Triggered D Register
How will the circuit function ?

94. 94
• When CLK= 0 , S1 and S4 are closed /Q
m
follows D, and Q is
stored in the inverter loop.
D-register With Clk = 0

95. 95
• When CLK= 1.
• S1 is open and S2 is closed
Hence /Q
m
LATCHES the value of D, that existed on the rising edge of CLK.
[ Does it remind you of set-up hold and Metastability]
• S3 is closed and S4 is open,
Hence Q gets the value of /Q
m
[ I.e. the value of D on the rising edge of CLK].
• Q is isolated from changes on D input.
D-Register with CLK = 1

96. 96
• In case of negative edge triggered register master is positive
level-sensitive latch.
Edge Triggered D-Register

97. 97
Guess The Functionality ?

98. 98

99. 99
CMOS Transistor Sizing
 DESIGN REQUIREMENT
 TRANSISTOR SIZING
 LOGIC RESTRUCTURING
 CONDUCTOR SIZING

100. 100
CMOS Transistor Sizing
Design requirements

•Speed: -
In many state-of-the-art design, especially contemporary
microprocessor, speed tends to be the dominating
requirement.
• Power: - In portable applications such as mobile telephones,

PCs, etc., minimizing power dissipation is crucial.
• Area: - Circuit area is often the prime concern, as it has direct
impact on die size and hence the cost.

101. 101
CMOS Transistor Sizing
• Symmetrical drive capability of CMOS allows comparable
transition time for output voltages irrespective of direction of
transition.
• Primary effect of sizes of pull-up and pull-down transistors is
on equivalent resistance of transistors in conduction state.
• To obtain symmetrical characteristics at output rise and fall time

should be same which says R
N
= R
P
• Resistance of N-channel is given as R
N  L
N
/W
N
*K
N
• Resistance of P-channel is given as R
P  L
P
/W
P
*K
P

102. 102
Sizing of NAND and NOR Gates
• In case of NAND gate equivalent pull-down resistance is twice that of
either pull-down alone R
DN
= Rn
3
+ Rn
4
= 2* L
p
/W
p
* K
p.
•

103. 103
Sizing Of NAND and NOR Gates
• In case of NOR gate the equivalent pull up resistance is twice that of
either pull up alone R
up
= Rp
3
+ Rp
4
= 2* L
p
/W
p
* K
p
• Hence for NOR gate K
n/K
p = 5 will give symmetrical output ??
• NOR gates require greater silicon area than NAND gate for symmetric drive
operation.
• Hence NAND gates are always preferred than NOR

104. 104
Logic Restructuring
• Gate delay of large fan-in gate can be improved by manipulating logic
equation, I.e. restructuring logic
Consider 8-input AND gate

105. 105
Conductor Sizing
• ELECTROMIGRATION: - Direct current flowing on a metal wire over a
substantial time period causes a transport of metal ions, ultimately causing
the wire to break or short to another wire.
Rate of electromigration depends upon temperature, crystal structure and
current density ( current per unit area).
Keep the current below 0.5 to 1mA /um normally prevents electromigration.
Current density for contact periphery must be kept below 0.1mA /um.
Signal wires normally carry alternating current are less susceptible to
migration.

106. 106
Conductor Sizing
•POWER AND GROUND BOUNCE: - Ohmic voltage drops can occur
on power conductors degrading VDD and ground levels leading to
poor logic levels  reduction in noise margin of gates  incorrect
operation of gates.
This degradation of supply voltages is termed as “power bounce”
for VDD and “ ground bounce” for the GND lead.

107. 107
Conductor Sizing
POWER AND GROUND BOUNCE can be minimized by: -
• reducing the maximum distance between supply pins and circuit
supply connections using a finger shaped power distribution network.
• Providing multiple power and ground pins.
• Using low resistively metal.
Finger-shaped network With multiple power & ground pins

108. 108
Switching speed of MOS system strongly depends on
the parasitic capacitances associated with
MOSFETs and interconnection capacitances.
Total load capacitance on the output of a CMOS gate
is the sum of
 Gate Capacitances (C
g
)
 Diffusion Capacitances
Gate capacitance :- C
G
= bulk + overlap capacitance
C
G = C
GB + C
GD + C
GS
C
G
= C
OX
W L
eff
MOS Device Capacitance Estimation

109. 109
MOS Device Capacitance Estimation

110. 110
MOS Device Capacitance Estimation

111. 111
MOS Device Capacitance Estimation

112. 112
MOS Device Capacitance Estimation
Diffusion Capacitances
Voltage dependent source and substrate and drain-
substrate junction capacitances, C
sb
, C
db
. These
junctions are reversed-biased during normal operation

113. 113
Where Does Power Go In CMOS
Power dissipated in a CMOS circuit is categorised as follows,
• Static dissipation :
Due to leakage currents
• Dynamic dissipation :
Due to charging and discharging of internal & load capacitance.
• Short circuit dissipation :
Due to short circuit path between V
DD and GND during switching

114. 114
Static dissipation is due to,
• Leakage currents in the reversed-biased diodes formed between

the substrate (or well) and source/drain regions.
• Sub threshold conduction, also contributes to static dissipation.

Sub threshold leakage increases exponentially as threshold
voltage decreases.
• Total static power dissipation is given as
p
static= Σ
n
leakage current * V
DD
Where n is the number of devices in a CMOS Circuit.

Static Dissipation

115. 115
Static Dissipation
LOWER BOUND ON THRESHOLD TO PREVENT LEA KAGE

116. 116
• During low to high transition part of energy drawn from supply is
dissipated in PMOS. While during high to low transition stored
energy on capacitor is dissipated in NMOS transistor.
• Dynamic power dissipation gives measure of this energy
consumption
Dynamic Power Dissipation
V
DDV
DD
S
G
G
S
GND
C
L
Charging Current
V
in
V
out

117. 117
Dynamic Power Dissipation
• The average dynamic power consumption for input frequency of
F is P
dynamic
= C
L
* V
DD
2
* F
• Power dissipation is independent of device parameters
• This can be reduced by decreasing C
L
, V
DD
or F

118. 118
Short Circuit Dissipation
• It is the DC power consumed during switching.
• A direct current path from V
DD
to ground exists when both N

and P transistors are conducting simultaneously during
switching.
• Short circuit consumption is given by
P
sc
= I
mean
* V
DD
•Short- circuit power depends on W/ L ratios of the transistors
• Greater the rise-fall time of the signals, larger is the power
consumed.

119. 119
Short Circuit Dissipation
Input switching waveform & model for short circuit current.
• I
peak is determined by the saturation current of devices, hence is

proportional to the sizes of the transistor.

120. 120
Impact of Rise/Fall Times on
Short-Circuit Currents
• Power dissipation due to short circuit current is minimized by
minimizing the rise and fall time of input and output signal.

121. 121
Stage Ratio
- The object is to maximize the speed with minimum area overhead.
- Option I will be slow, since Gate1 will not have drive capability to drive the
large inverter.
- In Option II, we have a chain of inverters of increasing size (by an order of a)
- Gate I will be fast, since it drives a minimum sized inverter (Inverter 1)

122. 122
Stage Ratio
•When It is desired to drive large load capacitances such as long
buses, I/O buffers and off-chip capacitive loads.
•This is achieved by using a chain of inverters where each
successive inverter is made larger than the previous one.
•The ratio by which each stage is increased in size is called ‘ stage
ratio’.
•The signal delays encountered in driving the off chip load directly
from a minimum sized inverter is unacceptable.
•The optimization to be achieved here is to minimize the delay
between input and output while minimizing the area and power
dissipation.

123. 123
Stage Ratio

124. 124
• Inverter 1 is a minimum- sized device.
• Subsequent inverter device sizes increase by a factor of ‘a’
• Delay of each stage is ‘a * T
d
’, where T
d
=delay of minimum sized
inverter driving an identically sized inverter
• Hence total delay ( delay through the n stages ) is n * a * T
d

• Cg is load of first driver which is minimum- sized device
• If C
gN
is the load capacitance of the N
th
inverter then C
gN
= C
g
* a
N
• To guarantee that none of capacitances internal to the chain of
inverters exceed C
load
[ why ?? ] we must have C
g
* a
n
= C
L

here n = N +1
I.e a
n
= C
L/
C
g
Stage Ratio

125. 125
Hence a = [C
L/
C
g
]
1/n
Total delay = n * [C
L/
C
g
]
1/n
* T
d
The optimum value of n is
n
opt
= ln [C
L/
C
g
]
• Now optimum value of a i.e a
opt
can be calculated as;
a
n
= C
L/
C
g
a
ln [CL/ Cg]
= C
L/
C
g
Taking natural log of both sides we get a = 2.7
• But the actual stage ratio is given by
a
opt
= exp[(k+a
opt
)/a
opt
]
Where k = C
drain/C
gate
• For 1µ process k = 0.215, hence a
opt
= 2.93
• For 2.5µ process k = 3.57 which gives a
opt
= 5.32
Stage Ratio

126. 126
CMOS Dynamic Logic
 Dynamic Charge Storage
 Clocked CMOS Logic

127. 127
Dynamic Charge Storage
• Since the node is capacitive, we model it as a capacitor ‘C’
that can be used to hold a charge.
The logic’1’ is given at input V
i and control. The voltage across
the capacitor increases to
Vmax = (V
DD
- V
t
)

128. 128
Dynamic Charge Storage
Initially, Vs was at Vmax indicating that a logic 1 was stored
on the capacitor.
However, since leakage currents remove charge, Vmax cannot
be held and Vs will decrease in time.
Eventually, Vs will fall to a level where it will be incorrectly
interpreted as a logic 0 value.
Because the stored charge will leak away over time, this
circuit is termed a dynamic storage circuit.

129. 129
Dynamic Charge Storage
• Since a transmission gate consist of a parallel NMOS and
PMOS combination, reverse junction charge leakage will occur
whenever a TG is used to hold charge on an isolated node.
When the TG is OFF, both transistor are in cut-off and two
leakage paths exit, one through each device.
The leakage current I
Rp
through the PMOS adds charge to the
node, while the NMOS current I
rn removes charge from the
node.
Disadvantage :- requirement for dual polarity control signal
additional PMOS in TG.

130. 130
Dynamic Charge Storage
• The pass transistor can discharge the inverter gate to 0V to
give a good low logic level. In this case, the inverter output is
high and PMOS feedback transistor is OFF.
The pass transistor can pull the inverter input voltage high
enough to force the inverter’s output to a low logic voltage.
This low voltage turns on the PMOS feedback transistor,
thereby pulling the inverter input to the upper supply voltage
and holding it there.

131. 131
Dynamic Charge Storage
• Advantage
Area efficient compared to the static storage circuit.
Simplicity of the required circuitry.

132. 132
Clocked CMOS Logic
 C
2
MOS
 Precharge Evaluate Logic
 Domino CMOS

133. 133
C
2
MOS
 The clocked transistors are placed in series with
the p-channel and n-channel transistor of a
standard inverter.
The layout is simplified because the source/drain
regions of the two p-channel transistors can be
merged.
The output of C
2
MOS is available during the entire
clock cycle.
The load capacitor is the storage node for the
dynamic charge.

134. 134
Precharge Evaluate Logic
The path between power and ground is broken
by two series transistor. No DC current path
from power to ground will exit at mutually
exclusive times.
Minimum-size transistors can be used
throughout.
The path to V
DD is used to precharge the output
node during part of the clock cycle, and the
path to ground is used to selectively discharge
the output node during another part of the
clock cycle.
The output is taken high during precharge time
and is logically valid during the discharge
cycle.
Valid output available is less than 50% (for
square-wave clock).

135. 135
Precharge Evaluate Logic
Two phase operation determined by the clock signal 

n
– block 
p
– block
Precharge :  = 0, out = 1 Precharge :  = 1, out = 0
Evaluate :  = 1, out = F(x) Evaluate :  = 0, out = F(x)
Input change during precharge and are stable during evaluate.

136. 136
Precharge Evaluate Logic
 Advantages:
Less area
Minimum-size transistors
Large number of transistors can be placed in series within the
logic section
Faster
 Disadvantages:
 Charge sharing
 The addition of clock signals(minimum and maximum)
 Output must be stored during precharge

137. 137
Domino CMOS
P-E logic gate followed by a static inverter buffer at the output.
The buffer provides output drive capability to either V
DD
or
ground.
Domino CMOS is a non-inverting logic form
Use “keeper” transistor to maintain a pre-charged high.

138. 138
Domino CMOS
Precharge :  = 0, out = 0
Evaluate :  = 1, out = F(input)

139. 139
Scaling of MOS Transistor Dimensions
 Sub-Micron Considerations
 Scaling Methods

140. 140
Sub-micron Considerations
• When dimensions of MOS device go below 1µ then it’s behavior
deviates substantially than actual MOS operation that has been
discussed so far.
• For sub-micron range the channel length becomes comparable to
other device parameters such as depth of drain and source
junctions, and width of their depletion regions.
• Such devices are called ‘ short channel transistors ’ & represents
the deviation form ideal model.

141. 141
•These second order effects that impact on device behavior
includes
1.Variation in I-V characteristics
2.Mobility variation
3.Threshold voltage variation
4.Impact ionization- Hot electron
5.Tunneling
6.Drain punch-through
7.Channel length modulation
Sub-Micron Considerations

142. 142
• The I-V characteristics of short channel device deviate
considerably from the ideal equations.
• I
D
= {( V
GS
-V
T
)V
DS
– (V
DS
2
)/2} -----Linear region
• I
D
= (k
n
/2) W/L(V
GS
-V
T
)
2
(1+ V
DS) ----Saturation region
• The most important reasons for this difference are the Velocity
saturation and mobility degradation.
• Velocity saturation : Carrier velocity is given as;
• 
n
= 
n
E
x
= 
n
*dv/dx
• This states that carrier velocity is proportional to electric field &
is independent of value of that field, i.e it is constant.
Variation in I -V Characteristics

143. 143
• But when the electric field along the channel reaches a critical
value E
max , velocity of carriers tend to saturate( i.e carriers reach

their maximum limited velocity ).
• Current under the velocity saturated condition is
I
DSAT = 
SAT* C
ox * W (V
GS - V
DSAT - V
T)
• Thus the saturation current linearly depends on the gate-source
voltage.
• Also, I
D is independent of L in velocity saturated devices.
• Reduction in the channel length causes reduction in the electron
mobility even at normal electric field levels. This is called
‘ mobility degradation ‘
Variation in I-V Characteristics

144. 144
Mobility Variation
• The mobility ‘M’ describes the ease with which carriers drift in the
substrate material
• It is defined as ratio of average carrier drift velocity ‘V’ to the
Electric field ‘E’.
• Mobility can vary in number of ways viz :
• According to the type of charge carrier. [ WHY ??]
• Increase in doping concentration decreases mobility.
• Increase in temperature decreases mobility.

145. 145
• As device dimensions are reduced threshold voltage becomes
function of L,W and V
DS
• The threshold voltage is not constant with respect to the voltage
difference between the substrate and the source of the MOS
transistor. This is known as ‘ substrate bias effect’ or ‘ body-
effect ’.
Threshold Voltage Variation

146. 146
•As the length of the gate decreases, electric field intensity at
the drain increases.
•In sub- micron devices, the field intensity can become very
high, to an extent that electrons are imparted with enough
energy to become ‘hot’.
•These hot electrons can impact the drain, dislodging holes.
•These free holes will escape into the substrate creating a
substrate current. This effect is known as impact ionization
•This will degrade the transistor performance and can trigger
latch-up.
Impact Ionization

147. 147
• The high- energy (hot) electrons can also penetrate the gate
oxide causing a gate current.
• This can lead to degradation of MOS device parameters.
• Hot- electron effects can be minimized by decreasing the supply
voltage in smaller devices.
Impact Ionization

148. 148
Tunnelling
• The gate is separated from the substrate by an oxide of thickness
t
ox
, Generally the gate current in a MOS Transistor is zero
• When the gate oxide is very thin, a current can flow from gate to
source/drain
• This happens due to electron tunnelling through the gate oxide
• This gate-current is proportional to the area of the gate.
• This effect puts a limit on the minimum thickness of the gate
oxide
layer, as processes are scaled

149. 149
Drain Punch-Through
• If the drain is at a very high voltage with respect to source , the
depletion regions around the drain and source will meet
• This will cause a channel current to flow, irrespective of the gate
voltage, even if it is zero. This is known as punch-through
condition.
• Punch-through can be avoided with,
• Thinner Oxides.
• Larger Substrate Doping.
• Shallower Junctions.
• Longer Channels.

150. 150
Channel Length Modulation
• In the saturation region, the ideal characteristics of a MOS
transistor shows a constant current region,
i.e.drain current I
DS
remains constant, with increase in V
DS.

• This characteristics assumes that carrier mobility is constant.
It does not take into account the variation in channel length
due to change in V
DS
.
• However, in saturation, as V
DS increases, channel- length L
decreases by a very small amount such that L
eff
= L - D
L
• This decrease in L, increases the [W/ L] ratio, and hence
increases I
DS due to increase in ß.
• For long channel lengths, influence of channel variation is of
little consequence, but as devices are scaled down this
variation has be taken into account.

151. 151
Scaling Methods
• Scaling is method in which device geometries migrate to
lower sizes while still maintaining the same device
characteristics.
• This is done by scaling the critical parameters of a device
in accordance to a given criteria.
• Scaling methods include
 Lateral scaling
 Constant field scaling
 Constant voltage scaling

152. 152
Lateral Scaling
LATERAL SCALING :
- Here the only parameter that is scaled is the gate length L
- This method of scaling is also called gate- shrink
- It can be easily done to an existing mask design
- Power dissipation increases by the factor 
- Input capacitance of the transistor decreases by the factor 

153. 153
- A dimensionless scaling factor  is applied to,
• All dimensions (including vertical dimensions such as tox )
are decreased by .
• Device voltages are decreased by 
• Concentration densities are increased by 
• As a result,
• Depletion thickness d.
• Threshold voltage V
T
• Drain Current I
DS
also get scaled by the same factor 
• Since the voltage V
DD
is scaled, the electric field in the device remains
constant
• Hence, the operating characteristics of the device remain the same
even after scaling
• Power dissipation decreases by 
2
Constant Field Scaling

154. 154
• Similar to constant field scaling, except that voltage V
DD
is kept
Constant
• The current I
DS increases by the factor 
• Speed of the device increases by the factor 
• Number of transistors per unit area increases by the factor 
2
• As a result, the current density increases by the factor 
3

• Proportionately wider metal wires are required for more densely
packed structures
• Power dissipation increases by the factor 
• This will increase the need for cooling devices/ structures for the
IC
• Power dissipation of above 1- 2 Watts require specialized cooling
fins or packaging
Constant Voltage Scaling

155. 155
CMOS Processing Technology
 IC Fabrication : An Overview
 Photolithography

 CMOS Fabrication Process
 Latch-Up in CMOS Circuits
 Stick Diagrams
 Layout Design Rules
 Layout Examples

156. 156
IC Fabrication
• An IC fabrication process contains a series of masking steps to
Create successive layers of insulating, conducting and semi-
conducting material that define the transistors and metal
interconnect.
• Techniques such as oxidation, implantation,deposition are used
to build these layers.
• The starting material used for IC fabrication is silicon wafer.
Wafer is a disk of silicon, 4" to 8" in diameter, < 1mm thick,
• Wafers are very brittle, the larger the diameter, the more
susceptible to damage. Surface of the wafer is polished to a very
flat, scratch free surface.
• The single crystal silicon used as substrate is obtained from
polycrystalline silicon generally by CZ (czochralski ) process.
Controlled amount of impurities are added to the melt to provide

157. 157
IC Fabrication
the crystal with required electrical characteristics. After the crystal
has been developed several steps are involved to achieve mirror like
structure.
• Oxidation is used to deposit Silicon Dioxide (SiO2) on surface of
wafer to be used as insulting material - heat wafers inside of an
oxidation atmosphere such as oxygen or water vapor.
• To build the micro(semiconductor) devices, we need junctions
formed by N and P type region. To create these regions on silicon
wafer what we need is process to introduce impurity atoms into
the substrate.This may be achieved by using Epitaxy, Deposition
and Ion-implantation.

158. 158
IC Fabrication
• Epitaxy involves growing single crystal film (of the required
dopant) on silicon surface by heating wafer and exposing it to a
source of the dopant.
• Deposition is to evaporate the dopant onto the surface, then heat
the surface to drive the impurities in the wafer
• Ion implantation involves exposing surface to highly energized
dopant atoms. When these atoms impinge on the surface, they travel
below the surface forming the regions with varying doping
concentration.
• During fabrication of the transistors or other structures it is needed
to block some regions from receiving the dopants. Hence special
material called as mask is used to block the impurities in particular
region.

159. 159
Mask
Common material used for masks are Photoresist,
Polysilicon, Silicon dioxide, Silicon nitride.
To create mask:
(a) deposit mask material over entire surface
(b) cut windows in the mask to create exposed areas
(c) deposit dopant
(d) remove un-required mask material
•Masks plays important role in process called selective
diffusions.
•The selective diffusion involves
1.Patterning windows in a mask material on the surface
of the wafer.
2.Subjecting the exposed areas to a dopant source.
3.Removing any un-required mask material.

160. 160
Photolithography
•The Process of using an optical image and a photosensitive
film to produce a pattern on a substrate is photolithography
•Photolithography depends on a photosensitive film called a
photo-resist.
•Types of resist
•Positive resist, a resist that become soluble when exposed
and forms a positive image of the plate.
•Negative resist, a resist that lose solubility when
illuminated forms a negative image of the plate.

161. 161
Photolithography
p–type body
Substrate

162. 162
Resist application
p–type body
Photolithography

163. 163
Exposure
p–type body
Photolithography

164. 164
Positive Resist
p–type body
Etching
Photolithography

165. 165
Negative Resist
p–type body
Etching
Photolithography

166. 166
Fabrication of CMOS Devices
Technologies used for CMOS fabrications include
• N-well process
• P-well process
• Twin-tub process
• Silicon on insulator.

167. 167
P-Wells and N-Wells
• A p- transistor is built on an n- substrate and an n- transistor is

built on a p-substrate
P-well N-well
P substrate
contact[P
+
]
N substrate
contact[n
+
]
OUT
IN
G G
D S
n
+
n
+ p
+
p
+

168. 168
• In order to have both types of transistors on the same substrate, the

substrate is divided into “well” regions (Shaded region in the
standard cells)
• Two types of wells are available - n- well and p- well
• In a p- substrate, an n- well is used to create a local region of n type
substrate, wherein the designer can create p- transistors
• In a n- substrate, a p- well creates a local p- type substrate region,
to
accommodate the n- transistors.
• Hence, every p- device is surrounded by an n- well, that must be
connected to V
DD via a V
DD
substrate contact.
• Similarly, n- devices are surrounded by p- well connected to GND
using a GND substrate contact.
P-Wells and N-Wells

169. 169
CMOS Fabrication
p–type body
n well
n+n+ p+ p+
S G D D G S
NMOS PMOS
Polysilicon
Gate Oxide
Thick SiO
2 (Isolation) SiO
2

170. 170
P-type Substrate
p–type body
Silicon Crystal
Thin Oxide

171. 171
N-Well Diffusion
p–type body
n well

172. 172
Si
3N
4 Ion Implant Barrier
p–type body
n well
Si
3N
4

173. 173
N
+
Guard Ring Implanted
p–type body
n well
n
+
n
+

174. 174
P
+
Guard Ring Implanted
p–type body
n well
n
+
p
+
p
+
n
+

175. 175
Thick Oxide Grown
p–type body
n well
Thick Oxide

176. 176
Si
3N
4 & Thin Oxide Strip
p–type body
n well

177. 177
Gate Oxide Grown
p–type body
n well

178. 178
Poly Layer
p–type body
n well

179. 179
P-Channel Drain and Source
p–type body
n well
p+ p+

180. 180
N-Channel Drain and Source
p–type body
n well
p+ p+n+n+

181. 181
SiO
2 Layer Deposited
p–type body
n well
p+ p+n+n+

182. 182
Contact Openings (Cuts)
p–type body
n well
p+ p+n+n+
Contact Cuts

183. 183
Metallisation (Metal 1)
p–type body
n well
p+ p+n+n+

184. 184
The N-Well Process
• Steps in N-well process :
1. Formation of n-well regions
2.Define N-MOS and P-MOS active areas.
3.Field and gate oxidations (thinox)
4.Form and pattern poly-silicon.
5.P
+
diffusion
6.N+ diffusion
7.Contact cuts
8.Deposit and pattern metallization
9.Over glass with cuts for bonding pads

185. 185
Latch-Up in CMOS Circuits
•Latch-up is condition in which parasitic components gives rise to
establishment of low-resistance conducting path between V
DD
&
V
SS
•This results in chip self-destruction or system failure.
•Latch-up may be induced by the glitches on the supply rails or by
incident radiation.

186. 186
Physical Origin Of Latch-up
OUTINV
ss

187. 187
Latch-up Mechanism
R
substrate
R
well
Q
2
Q
1
• If sufficient current is drawn from NPN
emitter then NPN ( Q
2
)turns on when
V
BE
 0.7V.
• When NPN turns on, note that emitter
current increases exponentially with V
BE
• Current flowing through the parasitic n-well
resistors will eventually turn on the parasitic
PNP
• As PNP turns on, the NPN base current
increases and voltage drop across R
substrate

also increases, further increasing the NPN
emitter current (Q2 turns on “harder”), which
further increases the PNP base current,
which again further increases NPN base
current.

188. 188
Remedies for the Latch-up Problem
One way is to keep the p-substrate tied very closely (i.e.close
proximity) to GND (most negative supply) to reduce substrate
resistance (RS1 &RS2), and the n-well tied very closely to VDD
to reduce RW1 & RW2.
• Each well must have a substrate contact of appropriate type (n-
type for n-well).
• Place substrate contacts as close as possible to the source
connection of transistors connected to the supply rails.
• Place a substrate contact for every 5- 10 transistors
• Lay out n and p- transistors with packing of n- devices towards Gnd
and p- devices towards V
DD

189. 189
Layer
Polysilicon
Metal1
Metal2
Contact To Poly
Contact To Diffusion
Via
Well (p,n)
Active Area (n+,p+)
Color Representation
Yellow
Green
Red
Blue
Magenta
Black
Black
Black
Select (p+,n+) Green
CMOS Process Layers

190. 190
Stick Diagram
•Before the cell can be constructed from a transistor schematic it is
necessary to develop a strategy for the cell's basic layout.
•Stick Diagrams are a means for the design engineer to visualize the
cell routing and transistor placement.
•Steps involved in stick diagram construction.
•STEP 1 :
 
 
     
-> Identify each transistor by a unique name of its gate signal
-> Identify each connection to the transistor by a unique name

191. 191
Figure 1:
Schematic
and Graph
Stick Diagram

192. 192
STEP2 :
Figure.2
Euler path
Stick Diagram

193. 193
STEP2 :
•Eulers paths : A path the traverses each node in the path, such
that each edge is visited only once.
•The path is defined by the order of each transistor name.
•The Euler path of the Pull up network must be the same as the
path of the Pull down network.
•Euler paths are not necessarily unique.
It may be necessary to redefine the function to find a Euler path.
F = E + (CD) + (AB) = (AB) +E + (CD)
•Next step is to lay out the stick diagram
-> Trace two green lines horizontally to represent the NMOS and
PMOS devices
-> The gate contact to the devices are represented by vertical strips
-> Surround the NMOS device in a yellow box to represent the
surrounding Pwell material.
Stick Diagram

194. 194
Figure 3: Connection
label layout
Stick Diagram

195. 195
->Surround the PMOS device in a green box to represent the
surrounding Nwell material.
->Trace a blue line horizontally, above and below the PMOS and
NMOS lines to represent the Metal 1 of V
DD
and V
SS
.
->Label each Poly line with the Euler path label, in order from left
to right.
->Place the connection labels upon the NMOS and PMOS devices.
Place the VDD, VSS and all output names upon the NMOS and
PMOS devices
Stick Diagram

196. 196
Figure 3: Connection
label layout
Stick Diagram

197. 197
Figure 4: Stick Diagram, Interconnected

198. 198
Schematic

199. 199
Stick-diagram NAND Gate

200. 200
Stick Diagram NOR Gate

201. 201
Layout Design Rules
Minimum spacing
Minimum width
• Limitations of patterning process gives rise to
set of mask design guidelines called ‘ Design
Rules ’.

• These guidelines specify minimum line width
& minimum spacing allowed in a layout
drawing.
• Minimum line-width: Smallest dimension
permitted for any object in the layout
drawing ( minimum feature size ).
• Minimum spacing: Smallest distance
permitted between the edges of two objects.
• Violating a design rule might result in non-
functional circuit or in highly reduced yield.
• Lithographic process is used to transfer pattern to each layer of IC.

202. 202
Layout Design Rules
• Even for the same minimum dimension, design rules tend to

differ from company to company and from process to process.
• One approach to address this is to use scalable design rules.
These include
1. Lambda (  ) based rules.
2. Micron rules.
• Lambda (  ) based rules : These defines all the rules as function
of single parameter called .
• Scaling of the minimum dimension is accomplished simply by
changing the value of .
• Scaling factor lambda is foundry/silicon vendor dependent.

203. 203
Layout Design Rules
• When mapping the transistor schematic/layout to a particular
technology, the actual W, L will be calculated as:
W' (actual, microns (µ)) = W * (microns)
L' (actual, microns) = L *  (microns)
 ( lambda ) is dimensionless unit called as scaling factor.
• Feature-size independent way of setting out mask dimensions to
scale.
• For MOSIS foundry vendors, 2.0µ technology  = 1.0
1.2µ technology  = 0.6
0.8µ technology  = 0.4.
• Typically the minimum gate length is set to 2  and width is varied.

204. 204
• Micron Rules :
• Linear scaling is possible over a limited range of dimensions,
hence these rules are not used by industry. Normal industrial
practice is to deal with ‘ micron rules ‘

• Micron rules expresses the design rules in absolute dimensions
and hence can exploit the features of a given process to a
maximum degree.
• These are usually given as list of minimum feature sizes and
spacing for al the masks required in an given process.
Layout Design Rules

205. 205
Design Rules
Examples
from AMS
0.6micron
technology

206. 206
Intra-Layer Design Rules

207. 207
Via’s and Contacts

208. 208
N Transistor – Layout
Bulk
Drain
Source
Gate
Thin-Oxide

209. 209
P Transistor - Layout
n
-
Bulk Source
Gate
Drain
Thin-Oxide

210. 210
Parallel/Series Transistors

211. 211
Large MOS Transistors

212. 212
AND Gate Layout

213. 213
AND Gate - Layout

214. 214
Inverter Layout

215. 215
Inverter Layout

216. 216
4-Input NAND Gate

217. 217
Pseudo NMOS NAND Gate

218. 218
Logic Graph for F = (A+B)C

219. 219
Layout F = (A+B)C

220. 220
Logic Graph for F = /(AB+CD)

221. 221
Pass Transistor Based Multiplexer
F

222. 222
Pass Transistor Based Multiplexer

223. 223
Sense Amplifier
t
p
CV
I
av
----------------=
make V as small
as possible
smalllarge
Idea: Use Sense Amplifer
outputinput
s.a.
small
transition

224. 224
Sense Amplifier
2- D Memory Organization

225. 225
Sense Amplifier

226. 226
Sense Amplifier
The bit lines exhibit the most sensitivity to capacitance of all the
large nets, they offer the most opportunity for improvement.
By increasing the current flowing through the bit lines, they can be
discharged quickly and thus improve the switching time.
The sense amplifiers contain the current source for the bit lines. By
varying the current through the bit lines, the delay due to parasitic
capacitance can be significantly reduced.