CMOS Layout

CMOS Layout

1. Analog Layout Lecture #3

2. CMOS Layout and Design Rules

3. It is the design responsibility to determine the geometry of the various masks required during processing. The process of defining the geometry of these masks is known layout and it is done using computer CAD programs. During the layout design, the designer does need to produce the geometry of all masks because some of the masks are automatically produced by the layout program such p + and n + masks used for the source and drain CMOS Layout and Design Rules

4. The most important masks are for the active region and for gate polysilicon . The interaction of these two masks becomes the channel. CMOS Layout and Design Rules (Continued)

5. The most important masks are for the active region and for gate polysilicon . The interaction of these two masks becomes the channel. The design rules for the layout transistors are often expressed in terms of 2 l . 2 l is the minimum technology gate length. The last figure shown the smallest possible transistor that can be realized when contact must be made for each junction. When we express the design rules in terms of 2 l , we assume that each mask has a worst case alignment of under 0.75 l . Thus, we can guarantee that the relative misalignment between any two masks is under 1.5 l . CMOS Layout and Design Rules (Continued)

6. If an overlap between any two regions of a microcircuit would cause a destructive short circuit. Then a separation between the corresponding regions in a layout is 2 l guarantees this will never happen. For example, if the poly mask and the contact mask are overlapped, then the metal used to contact the source junction is also short-circuited to the poly causing the transistor to be always turned off. CMOS Layout and Design Rules (Continued)

7. Also, if the source happens to be connected to the ground, this error also short-circuits the gate-to-ground. To prevent this type of short circuits, the contact opening must be kept at least 2 l away from the poysilicon gates. Another example of failure due to misalignment is the gate that does not fully cross the active region. This misalignment causes a short between the source a the drain. Thus the design rule that poly must always extend at least 2 l past the active region. CMOS Layout and Design Rules (Continued)

8. Another design rule is that active regions should surround contacts by at least 1 l If an overlap exists between the edge of the active- region mask and the contact mask, no disastrous short occur. The circuit still works correctly as long as sufficient overlap exists between the contact and the active masks. The maximum relative misalignment 1.5 l is , having the source (or drain) region surround the contact by guarantees an overlap at let 1.5 l (the minimum contact width is 2 l ) due to misalignment is the gate that does not fully cross the active region. CMOS Layout and Design Rules (Continued)

9. The minimum source or drain junction with a contact is The perimeter of a junction with a contact is CMOS Layout and Design Rules (Continued)

10. CMOS Layout and Design Rules (Continued) Sometimes, when it is important to minimize the capacitance of a junction, a single junction can be shared between two transistors.

11. The sidewall capacitance is directly proportional to the junction perimeter. This capacitance can be a major part of the total junction capacitance (because of the heavily doped of the field implants). Minimizing the perimeter is important. It is important to note that as transistor dimensions shrinks, the ratio of the perimeter to the area increases and the sidewall capacitance becomes more important CMOS Layout and Design Rules (Continued)

12. Example If l = 0.5, For the junction J1: Junction J2: CMOS Layout and Design Rules (Continued)

13. Example (Continued) Shared Junction J3: CMOS Layout and Design Rules (Continued)

14. Minimmizing the junction capacitance is so important, An experienced designer takes before laying out important high-speed cell First is to identify the most important nodes and then to investigate possible layouts that minimize the junction capacitance of the nodes. CMOS Layout and Design Rules (Continued)

15. Example: Inverter Design CMOS Layout and Design Rules (Continued)

16. Example: Inverter Design The minimum spacing between n-well surrounds the p-channel active region is at least 3 l . The minimum spacing between the n well and the junctions of n-channel transistors is 5 l . This large spacing is required because of the large lateral diffusion of the n well and the fact that the n-channel junction became short-circuited to the n-well, which is connected to V DD , the circuit would not work Since a p-channel junction must be inside the well by at least 3 l and the closest an n-channel transistor can be placed to a p-channel transistor is 8 l . CMOS Layout and Design Rules (Continued)

17. Example: Inverter Design A single contact opening, known as a butting contact, can be used to contact both the p-channel transistor source and an n + -well tie, because both will be connected to V DD . CMOS Layout and Design Rules (Continued)

18. Example: Inverter Design Metal is used to connect the junctions of the p-channel and n-channel transistors. Normally, the metal must overlap any underlying contacts by at least l . Atypical minimum width for the first-level metal might be 2 l . However, it can be wider to 4 l as in the figure. CMOS Layout and Design Rules (Continued)

19. Example: Inverter Design For n-channel transistor: A butting contact was used to connect the n-channel source to a p+ -substrate tie and both will be connected to ground. In a typical set of design rules, a maximum distance between transistors and well (or substrate) ties is specified and the maximum distance between substrate ties is also specified. For example, the rules might specify that no transistor can be more than 100 l from the substrate tie. CMOS Layout and Design Rules (Continued)

20. Example: Wide Transistor CMOS Layout and Design Rules (Continued) Wide Transistor Parallel Transistors

21. Example: Wide Transistor CMOS Layout and Design Rules (Continued)

22. Example: Wide Transistor Node 2 has a much greater capacitance than node 1. Because it has larger total junction area and especially a large perimeter. Thus, when the equivalent transistor is connected to the circuit, node 1 should be connected to the more critical node. A large number of contacts used to minimize the contact impedance. The use of many contacts in wide junction regions greatly minimizes voltage drops that would otherwise occur due to the relatively high resistivity of silicon junctions compared to the resistivity of the metal that overlays the junctions and connects them. CMOS Layout and Design Rules (Continued)

23. Example: Wide Transistor Assume the total width is 80, length is 2 l , l = 0.5 um. Node 1 is the source, node 2 is the drain, and the device is in the active region. C j = 2.4x10 -4 pF/(um) 2 and C j-sw = 2x10 -4 pF/um CMOS Layout and Design Rules (Continued)

24. Example: Wide Transistor CMOS Layout and Design Rules (Continued)

25. Transistors in analog circuits are typically much wider than transistors in digital circuits. For this reason, they are commonly laid out using multiple-gate fingers as shown. When a precision matching between transistor is required, then not only should be individual transistors be realized by combing a single-sized unit transistor, but the finger for one transistor should be interdigitated with the fingers of the second transistor. This called common- centroid layout . It helps match errors caused by gradient effects across a microcircuit such as temperature or gate oxide thickness across the layout. CMOS Layout and Design Rules (Continued) Common- Centroid Layout

26. CMOS Layout and Design Rules (Continued) Common- Centroid Layout

27. Important Notes The outside fingers have separate second-order size effects and therefore one outside finger is used for M1 and one for M2, Inside the structure, the fingers occur in doubles- two for M2, two for M1, two for M2, and so on. This layout is symmetric in both x and y axes. Any gradients across the microcircuit would affect both M1 and M2 in the same way. This layout technique greatly minimizes nonidealities such as op-amp input offset voltage errors when using a differential pair in the input stage of op-amp, Common- Centroid Layout

28. Important Notes Current Mirror Design When current mirrors with ratios other than unity are required, each of the individual transistors should be realized from a single unit-sized transistor. For example, if a current ratio of 2:1 were desired: The input transistor might be made from 4 fingers, whereas the output transistor might be realized using 8 identical fingers. In addition, for the greatest accuracy, all fingers should be inside fingers only. Outside, or dummy, fingers would only be included for butter matching accuracy and would have no other functions. The gate of the dummy fingers are normally connected to the most negative power supply voltage to ensure they are always turned off (or connected to positive power supply in the case of p-channel transistors). Common- Centroid Layout