Combinational & Sequential Logic Circuits — A Professional Insight by Dr. G.S. Virdi

This lecture on Combinational and Sequential Logic Circuits has been prepared by Dr. G.S. Virdi, Ex. Chief Scientist, CSIR–Central Electronics Engineering Research Institute (CEERI), Pilani, with over 45 years of distinguished R&D experience in microelectronics and semiconductor device fabrication.

The presentation provides a clear and comprehensive understanding of digital logic fundamentals essential in the design of modern electronic systems. It covers key topics including:

Boolean logic and digital circuit behavior

Adders, subtractors, encoders, decoders

Flip-flops, latches, counters, memory elements

Difference between combinational & sequential circuits

Practical applications in digital systems and VLSI design

This lecture is highly beneficial for:

✅ Undergraduate & postgraduate engineering students
✅ Researchers in semiconductor and digital electronics
✅ Professionals working in electronic product design & embedded systems

A valuable learning resource for strengthening concepts in digital electronics and logic design

1. Combinational&Sequential
LogicCircuits
Dr.G.S.Virdi
Ex.ChiefScientist
CSIR -Central Electronics Engineering Research Institute
Pilani-333031,India

2. INTRODUCTION
•Indigitalcircuittheory,sequentiallogicisatype
oflogiccircuitwhoseoutputdependsnotonlyon
thepresentvalueofitsinputsignalsbutonthe
sequenceofpastinputs,theinputhistoryaswell.
Thisisincontrasttocombinationallogic,whose
outputisafunctionofonlythepresentinput.

3. •Differencebetweencombinationaland
sequentialcircuit....
•Sequentialcircuitsarethosewhicharedependenton
clockcyclesanddependsonpresentaswellaspastinputs
togenerateanyoutput.
•CombinationalCircuit–
•Inthisoutputdependsonlyuponpresentinput.
•Thesequentiallogichasmemorywhilecombinationallogic
doesnot.
•Theyemployafeedbacklooptogiveoutputbacktoinput.
Sequentiallogiccircuitsisaformofbinarycircuit;its
designemploysoneormoreinputsandoneormore
outputs.

4. •Acombinationallogiccircuitperformsanoperation
assignedlogicallybyaBooleanexpressionortruthtable.
Examples ofcommon combinational
circuits include:
adders,multiplexers,
half adders,
demultiplexers,encoders
logic
full
and
decoders.

5. •ASequentiallogiccircuitsisaformofbinarycircuit;its
designemploysoneormoreinputsandoneormore
outputs,whosestatesarerelatedtosomedefiniterules
thatdependsonpreviousstates....Examplesof
suchcircuitsincludeclocks,flip-flops,bi-stables,counters,
memories,andregisters.
•Therearetwotypesofsequentialcircuit,synchronous
andasynchronous.Synchronoustypesusepulsedorlevel
inputsandaclockinputtodrivethecircuit(with
restrictionsonpulsewidthandcircuitpropagation).
Asynchronoussequentialcircuitsdonotuseaclock
signalassynchronouscircuitsdo.
•Flipflopisasequentialcircuitwhichgenerallysamples
itsinputsandchangesitsoutputsonlyatparticular
instantsoftimeandnotcontinuously.Flipflopissaidtobe
edgesensitiveoredgetriggeredratherthanbeinglevel
triggeredlikelatches.

6. Halfadder
•Anadderisadigitalcircuitthatperformsadditionof
numbers.Halfadderhasonlytwoinputsandtwooutputs.
Thehalfadderaddstwobinarydigitscalledasaugend
andaddendandproducestwooutputsassumandcarry;
XORisappliedtobothinputstoproducesumandANDgate
isappliedtobothinputstoproducecarry.
•Byusinghalfadder,youcandesignsimpleadditionwith
thehelpoflogicgates.
CircuitImplementation
TruthTable
BlockDiagram

7. WhyitiscalledasHalf-adder?
•Thehalfaddercanaddonlytwoinputbits(AandB)and
hasnothingtodowiththecarryifthereisanyintheinput.
Soiftheinputtoahalfadderhaveacarry,thenitwill
neglectitandaddsonlytheAandBbits.Thatmeansthe
binaryadditionprocessisnotcompleteandthat'swhyit
iscalledahalfadder
HowHalfAdderworks?
•Halfadderisasimplecombinationalcircuitusedtoadd
twosinglebits.Itacceptstwoinputsandproducetwo
outputsthatisasumoutputandacarryoutput.Ahalf
adderconsistsoftwologicgates1)XORand2)ANDgate.
AndthecarryoperationperformedbyANDgatethuscarry
outputwillbeA+B.

8. FULLADDER
Thefulladderadds3onebitnumbers,wheretwocanbereferred
toasoperandsandonecanbereferredtoasbitcarriedin.It
produces2-bitoutputandthesecanbereferredtoasoutput
carryandsum.
Thefull-adderhasthreeinputsandtwooutputs.Thefirsttwo
inputsareAandBandthethirdinputis aninputcarryasC-IN.
Whenafull-adderlogicisdesigned,youstringeightofthem
togethertocreateabyte-wideadderandcascadethecarrybit
fromoneaddertothenext.
TruthTable
BlockDiagram
CircuitImplementation

9. •Withthetruth-table,thefulladderlogiccanbeimplemented.Youcan
seethattheoutputSisanXORbetweentheinputAandthehalf-adder,
SUMoutputwithBandC-INinputs.WetakeC-OUTwillonlybetrueifany
ofthetwoinputsoutofthethreeareHIGH.
•So,wecanimplementafulladdercircuitwiththehelpoftwohalfadder
circuits.Atfirst,halfadderwillbeusedtoaddAandBtoproduceapartial
SumandasecondhalfadderlogiccanbeusedtoaddC-INtotheSum
producedbythefirsthalfaddertogetthefinalSoutput.
•Ifanyofthehalfadderlogicproducesacarry,therewillbeanoutput
carry.So,C-OUTwillbeanORfunctionofthehalf-adderCarryoutputs.
•Theimplementationoflargerlogicdiagramsispossiblewiththeabove
fulladderlogicasimplersymbolismostlyusedtorepresenttheoperation.
Givenbelowisasimplerschematicrepresentationofafulladder.

10. •Afulladderisadigitalcircuitthatperformsaddition.Full
addersareimplementedwithlogicgatesinhardware.
Afulladderadds threeone-bitbinarynumbers,two
operandsandacarrybit.Theadderoutputstwonumbers,
asumandacarrybit.
•TheBooleanexpressionforafulladderisasfollows.
•FortheCARRY-OUT (Cout)bit:CARRY-OUT=AANDBOR
Cin(AXORB)=A.B+Cin(A⊕B)

11. •Abinaryparalleladderisadigitalfunctionthatproduces
thearithmeticsumoftwobinarynumbersinparallel.
•FOUR-BITBINARYPARALLELADDERisacircuitinwhich
twobinarynumberseachofnbitscanbeaddedbymeans
ofafulladdercircuit.Considertheexamplethattwo4-bit
binarynumbersB
4B
3B
2B
1andA
4A
3A
2A
1aretobe
addedwithacarryinputC
1.
•Agroupoffourbitsiscalledanibble.Abasic4-bitparallel
adderisimplementedwithfourfull-adderstagesasshown
inFigure.
4-BitParallelBinaryadder:

12. •Again,theLSBs(A1andB1)ineachnumberbeingaddedgointotheright-
mostfull-adder:thehigher-orderbitsareappliedasshowntothesuccessively
higher-orderadders,withtheMSBs(A4andB4)ineachnumberbeingapplied
totheleft-mostfull-adder.Thecarryoutputofeachadderisconnectedtothe
carryinputofthenexthigher-orderadderasindicated.Thesearecalled
internalcarries.Inkeepingwithmostmanufacturers'datasheets,theinput
labeledC,istheinputcarrytotheleastsignificantbitadder;C4inthecaseof
fourbits,istheoutputcarryofthemostsignificantbitadder;and∑1(LSB)
through∑4(MSB)arethesumoutputs.Thelogicsymbolfor4-bitparallel
adderisshowninFigure.
•Twobinarynumberseachofnbitscanbeaddedbymeansofafulladder
circuit.Considertheexamplethattwo4-bitbinarynumbersB
4B
3B
2B
1and
A
4A
3A
2A
1aretobeaddedwithacarryinputC
1.Thiscanbedoneby
cascadingfourfulladdercircuitsasshowninfigure.Theleastsignificantbits
A
1,B
1,andC
1areaddedtotheproducesumoutputS
1andcarryoutputC
2.
CarryoutputC
2isthenaddedtothenextsignificantbitsA
2andB
2producing
sumoutputS
2andcarryoutputC
3.C
3isthenaddedtoA
3andB
3andsoon.
Thusfinallyproducingthefour-bitsumoutputS
4S
3S
2S
1andfinalcarry
outputCout.Suchtypeoffour-bitbinaryadderiscommerciallyavailableinan
ICpackage.

13. •Ahalfsubtractorisanarithmeticcircuitthatsubtractstwobitsand
producestheirdifference.Thecircuithastwoinputsminuend(X)and
subtrahend(Y)andtwooutputbits,oneisthedifferencebit(D)and
theotheristheborrowbit(B).
•Aslikeadditionoperationof2binarydigits,whichproducesSUMand
CARRY,thesubtractionof2binarydigitsalsoproducestwooutputs
whicharetermedasdifferenceandborrow.Thesimplestpossible
subtractionof2-bitbinarydigitsconsistsoffourpossibleoperations,
theyare0-0,0-1,1-0and1-1.Theoperations0-0,1-0and1-
1producesasubtractionof1-bitoutputwhereas,theremaining
operation0-1producesa2-bitoutput.Theyarereferred
asdifferenceandborrowbitrespectively.Thisborrowbitisusedfor
subtractionofthenexthigherpairbit.
•So,wecandefinehalfsubtractorasacombinationalcircuitwhichis
capableofperformingsubtractionof2-bitbinarydigitsisknownasa
halfsubtractor.Here,thebinarydigitfromwhichtheotherdigitis
subtractediscalledminuendandthebinarydigitwhichistobe
subtractedisknownasthesubtrahend.
HalfSubstractor:

14. •ItperformstheoperationX–Y.Itshouldbenotedthatthe
weightoftheoutputborrowbitis-2,whiletheweightof
theoutputdifferencebitis+1.
•Thetruthtableofthehalfsubtractorisshown.The
Booleanfunctionsforthetwooutputscanbeobtained
directlyfromthetruthtableas:
D=(XY +XY)=X⊕Y
•Thehalfsubtractorbooleanexpressionsare:
•D=(X’Y+XY’)= X⊕Y
•B=X’Y

15. •Afullsubtractorisacombinationalcircuitthatperformsasubtraction
betweentwobits,takingintoaccountthata1mayhavebeenborrowed
byalowersignificantbit.Thecircuithasthreeinputsandtwooutputs.
•Inputvariablesareminuend(X),subtrahend(Y),andpreviousborrow
(Z);outputvariablesaredifference(D)andoutputborrow(B).
•ItperformstheoperationX–Y–Z.Itshouldbenotedthattheweight
oftheoutputborrowbitis-2,whiletheweightoftheoutputdifference
bitis+1.Thetruthtableofthefullsubtractorisshown.
•Thefullsubtractorbooleanexpressionsare:
•(X’Y’Z+X’YZ’+XY’Z’+XYZ)=X⊕Y⊕Z
•(X’Y’Z+X’YZ’+X’YZ+XYZ)=X'(Y⊕Z)+YZ
•
FullSubstractor:

16. •Whenthereisasituationwheretheminuendandsubtrahendnumber
containsmoresignificantbit,thentheborrowbitwhichisobtained
fromthesubtractionof2-bitbinarydigitsissubtractedfromthenext
higherorderpairofbits.Insuchsituation,thesubtractioninvolvesthe
operationof3bits.Suchsituationofsubtractioncan’thandlebya
simplehalfsubtractor.So,combiningtwohalfsubtractorwecanform
anothercombinationalcircuitwhichcanperformthistypeof
operation.Thiscircuitisknownasthefullsubtractor.
•Sowecandefinefullsubtractorasacombinationalcircuitwhichtakes
threeinputsandproducestwooutputsdifferenceandborrow.Above
isthetruthtableofthefullsubtractor,wehaveusedthreeinput
variablesX,YandZwhichreferstothetermminuend,
subtrahend andborrow bitrespectively.Thetwo
outputsdifferenceandborrowarenamedasDandBrespectively.
•Theconstructionoffullsubtractorcircuitdiagraminvolvestwohalf
subtractorjoinedbyanORgateasshownintheabovecircuitdiagram
ofthefullsubtractor.Thetwoborrowbitsgeneratedbytwoseparate
halfsubtractorarefedtotheORgatewhichproducesthefinalborrow
bit.Thefinaldifferencebitisthecombinationofthedifferenceoutput
ofthefirsthalfadderandthenexthigherorderpairofbits.

17. •BothLatchesandflipflopsarecircuitelementswhereintheoutputnotonly
dependsonthecurrentinputs,butalsodependsonthepreviousinputand
outputs.Themaindifferencebetweenthelatchandflipflopisthataflip
flophasaclocksignal,whereasalatchdoesnot.
•Aflip-floporlatchisacircuitthathastwostablestatesandcanbeusedto
storestateinformation.Aflip-flopisabistablemultivibrator.Thecircuitcan
bemadetochangestatebysignalsappliedtooneormorecontrolinputsand
willhaveoneortwooutputs.
•Latchesandflip-flopsarethebasicelementsforstoringinformation.Onelatch
orflip-flopcanstoreonebitofinformation.Themaindifferencebetween
latchesandflip-flopsisthatforlatches,theiroutputsareconstantlyaffectedby
theirinputsaslongastheenablesignalisasserted.Inotherwords,whenthey
areenabled,theircontentchangesimmediatelywhentheirinputschange.Flip-
flops,ontheotherhand,havetheircontentchangeonlyeitherattherisingor
fallingedgeoftheenablesignal.Thisenablesignalisusuallythecontrolling
clocksignal.Aftertherisingorfallingedgeoftheclock,theflip-flopcontent
remainsconstanteveniftheinputchanges.
SequentialLogicCircuits:
FLIP-FLOPS:

18. •Therearebasicallyfourmaintypesoflatchesandflip-
flops:
•SR,D,JK,andT.Themajordifferencesintheseflip-flop
typesarethenumberofinputstheyhaveandhowthey
changestate.Foreachtype,therearealsodifferent
variationsthatenhancetheiroperations.
•Eachtypecanhavedifferentvariationssuchasactivehigh
orlowinputs,whethertheychangestateattherisingor
fallingedgeoftheclocksignal,andwhethertheyhave
asynchronousinputsornot.Theflip-flopscanbedescribed
fullyanduniquelybyitslogicsymbol,characteristictable,
characteristicequation,statediagram,orexcitationtable,
andaresummarizedinFigurebelow.

19. Flip-Flops:SR,D,JK,andTFlip-Flops

20. •Thebistableelementisabletorememberorstoreonebitof
information.However,becauseitdoesnothaveanyinputs,wecannot
changetheinformationbitthatisstoredinit.Inordertochangethe
informationbit,weneedtoaddinputstothecircuit.Thesimplestway
toaddinputsistoreplacethetwoinverterswithtwoNANDgatesas
showninFigure.ThiscircuitiscalledaSRlatch.
•InadditiontothetwooutputsQandQ',therearetwoinputsS'andR'
forsetandresetrespectively.Followingtheconvention,theprimeinS
andRdenotesthattheseinputsareactivelow.TheSRlatchcanbein
oneoftwostates:asetstatewhenQ=1,oraresetstatewhenQ=0.
•Figure4.SRlatch:(a)circuitusingNANDgates;(b)truthtable;(c)logic
symbol;(d)timingdiagram.
S-RLatchusingNAND&NORGate:

21. •LiketheNORGateS-Rflipflop,thisonealsohasfourstates.Theyare
•S=0,R=1—Q=0,Q’=1
•ThisstateisalsocalledtheSETstate.
•S=1,R=0—Q=1,Q’=0
•ThisstateisknownastheRESETstate.
•Inboththestatesyoucanseethattheoutputsarejustcomplimentsof
eachotherandthatthevalueof
•QfollowsthecomplimentvalueofS.
•S=0,R=0—Q=Q0,&Q’=Q0’Nochange
•IfboththevaluesofSandRareswitchedto0,thenthecircuit
remembersthevalueofSandRintheirpreviousstate.
•S=1,R=1—Q&Q’=Remember
•Ifboth thevaluesofSandRareswitchedto1itisaninvalidstate
becausethevaluesofbothQandQ’are1.Theyaresupposedtobe
complimentsofeachother.Normally,thisstatemustbeavoided.
Continued…

22. •Anotherreasonwhywedonotwantbothinputstobeasserted
i.e.R=S=1isthatwhentheyarebothasserted,QisequaltoQ',
butweusuallywantQtobetheinverseofQ'.
•Figure5.SRlatch:(a)circuitusingNORgates;(b)truthtable;(c)
logicsymbol.
Continued

23. S-RFLIPFLOPUSINGNANDGATE

24. S-RFLIPFLOPUSINGNORGATE

25. •TheproblemswithS-RflipflopsusingNORandNANDgateisthe
invalidstate.ThisproblemcanbeovercomebyusingabistableSRflip-
flopthatcanchangeoutputswhencertaininvalidstatesaremet,
regardlessoftheconditionofeithertheSetortheResetinputs.For
this,aclockedS-RflipflopisdesignedbyaddingtwoANDgatestoa
basicNORGateflipflop.Thecircuitdiagramandtruthtableisshown
below.
•Aclockpulse[CP]isgiventotheinputsoftheANDGate.Whenthe
valueoftheclockpulseis‘0’,theoutputsofboththeANDGates
remain‘0’.AssoonasapulseisgiventhevalueofCPturns‘1’.This
makesthevaluesatSandRtopassthroughtheNORGateflipflop.But
whenthevaluesofbothSandRvaluesturn‘1’,theHIGHvalueofCP
causesbothofthemtoturnto‘0’forashortmoment.Assoonasthe
pulseisremoved,theflipflopstatebecomesintermediate.Thuseither
ofthetwostatesmaybecaused,anditdependsonwhetherthesetor
resetinputoftheflip-flopremainsa‘1’longerthanthetransitionto‘0’
attheendofthepulse.Thustheinvalidstatescanbeeliminated.
ClockedS-RFlip-Flop:

26. ClockedS-RFlip-flop

27. •JKflip-flopsareverysimilartoSRflip-flops.TheJinputisjustliketheS
inputinthatwhenasserted,itsetstheflip-flop.Similarly,theKinputis
liketheRinputwhereitclearstheflip-flopwhenasserted.Theonly
differenceiswhenbothinputsareasserted.FortheSRflip-flop,
thenextstateisundefined, whereas,fortheJKflip-flop,thenext
stateistheinverseofthecurrentstate.Inotherwords,theJKflip-
floptogglesitsstatewhenbothinputsareasserted.Thecircuit,
truthtableandthelogicsymbolfortheJKflip-flopisshowninFigure
17.
•Figure17.JKflip-flop:(a)circuit;(b)truthtable;(c)logicsymbol.
J-KFLIP-FLOP:

28. •AJ-Kflipflopcanalsobedefined as
amodificationoftheS-Rflipflop.
Theonlydifference isthatthe
intermediatestateismorerefined
andprecisethanthatofaS-Rflip
flop.
•ThebehaviorofinputsJandKis
sameastheSandRinputsoftheS-R
flipflop.TheletterJstandsforSET
andtheletterKstandsforCLEAR.
J-KFlip-Flop :

29. •WhenboththeinputsJandKhaveaHIGHstate,theflip-flopswitchto
thecomplementstate.So,foravalueofQ=1,itswitchestoQ=0andfor
avalueofQ=0,itswitchestoQ=1.
•Thecircuitincludestwo3-inputANDgates.TheoutputQoftheflip
flopisreturnedbackasafeedbacktotheinputoftheANDalongwith
otherinputslikeKandclockpulse[CP].So,ifthevalueofCPis1,the
flipflopgetsaCLEARsignalandwiththeconditionthatthevalueofQ
wasearlier1.SimilarlyoutputQ’oftheflipflopisgivenasafeedback
totheinputoftheANDalongwithotherinputslikeJandclockpulse
[CP].SotheoutputbecomesSETwhenthevalueofCPis1onlyifthe
valueofQ’wasearlier1.
•Theoutputmayberepeatedintransitionsoncetheyhavebeen
complimentedforJ=K=1becauseofthefeedbackconnectionin
theJKflip-flop.Thiscanbeavoidedbysettingatimeduration
lesserthanthepropagationdelaythroughtheflip-flop.The
restrictiononthepulsewidthcanbeeliminatedwithamaster-
slaveoredge-triggeredconstruction.
J-KFlip-Flop:

30. •Latchesareoftencalledlevel-sensitivebecausetheiroutputfollows
theirinputsaslongastheyareenabled.Theyaretransparentduring
thisentiretimewhentheenablesignalisasserted.Therearesituations
whenitismoreusefultohavetheoutputchangeonlyattherising
orfallingedgeoftheenablesignal.Thisenablesignalisusuallythe
controllingclocksignal.Thus,wecanhaveallchangessynchronizedto
therisingorfallingedgeoftheclock.Anedge-triggeredflip-flop
achievesthisbycombininginseriesapairoflatches.Figureshowsa
positiveedge-triggeredDflip-flopwheretwoDlatchesareconnected
inseriesandaclocksignalClkisconnectedtotheEinputofthe
latches,onedirectly,andonethroughaninverter.Thefirstlatchis
calledthemasterlatch.ThemasterlatchisenabledwhenClk=0and
followstheprimaryinputD.WhenClkisa1,themasterlatchis
disabledbutthesecondlatch,calledtheslavelatch,isenabledsothat
theoutputfromthemasterlatchistransferredtotheslavelatch.The
slavelatchisenabledallthewhilethatClk=1,butitscontentchanges
onlyatthebeginningofthecycle,thatis,onlyattherisingedgeofthe
signalbecauseonceClkis1,themasterlatchisdisabledandsothe
DTYPEFLIP-FLOP:

31. •inputtotheslavelatchwillnotchange.ThecircuitofFigure10(a)is
calledapositiveedge-triggeredflip-flopbecausetheoutputQonthe
slavelatchchangesonlyattherisingedgeoftheclock.Iftheslavelatch
isenabledwhentheclockislow,thenitisreferredtoasanegative
edge-triggeredflip-flop.ThecircuitofFigure10(a)isalsoreferredtoas
amasterslaveDflip-flopbecauseofthetwolatchesusedinthecircuit.
Figure10(b)and(c)showthetruthtableandthelogicsymbol
respectively.Figure10(d)showsthetimingdiagramfortheDflip-flop.
•Figure10.Master-slavepositive-edge-triggeredDflip-flop:(a)circuit
usingDlatches;(b)truthtable;(c)logicsymbol;(d)timingdiagram.
Continued…

32. DtypeFlip-Flop:
•Thecircuitdiagramandtruth
tableisgiveninfigure
•Dflipflopisactuallyaslight
modificationoftheabove
explainedclockedSRflip-flop.
Fromthefigureyoucanseethat
theDinputisconnected totheS
inputandthecomplementofthe
DinputisconnectedtotheR
input.TheDinputispassedonto
theflipflopwhenthevalueofCP
is‘1’.
•WhenCPisHIGH,theflipflop
movestotheSETstate.Ifitis‘0’,
theflipflopswitchestothe
CLEARstate.

33. •TheTflip-flophasoneinputinadditiontotheclock.Tstandsfor
togglefortheobviousreason.WhenTisasserted(T=1),theflip-flop
statetogglesbackandforth,andwhenTisde-asserted,theflip-flop
keepsitscurrentstate.TheTflip-flopcanbeconstructedusingaDflip-
flopwiththetwooutputsQandQ'feedbacktotheDinputthrougha
multiplexerthatiscontrolledbytheTinputasshowninFigure18.
•Figure18.Tflip-flop:(a)circuit;(b)truthtable;(c)logicsymbol.
TtypeFlip-Flop:

34. •Thisisamuchsimplerversionof
theJ-Kflipflop.BoththeJandK
inputsareconnectedtogetherand
thusarealsocalledasingleinputJ-
Kflipflop.Whenclockpulseis
giventotheflipflop,theoutput
beginstotoggle.Herealsothe
restrictiononthepulsewidthcan
beeliminatedwith amaster-slave
oredge-triggered construction.
Takealookatthecircuitandtruth
tableisshowninfigure.
TTYPEFLIP-FLOP:

35. THANKYOU