Computer Organisation and Architecture notes by Shivani.pdf

Pe,
— COMPUTER
| Contents ARCHITECTURE

UNE race:
Computer architecture and organization, computer generations. |
Von Neumann model, CPU organization ds In
Rogjster organization, Various CPU register... nae
Register Transfer, Bus and Memory Transfers. (A702
Arithmetic, Logic and Shift microoperations, Arithmetic logic shit

ink ol
UNIT 1

|The arithmetic and logic unit, Fixed Point representation — integer
representation, sign-magnitude, 1's and 2's complement and range....(37to4s Q.1. Whats a computer ?

Integer arithmetic — negation, addition and subtraction, multipi or

cation, division. (64106 ¡fire din the Basic function of computer. (RGP.
Floating-Point representation, Floating-Point arthmeti (621066

Hardwired microprogrammed control unit, Control memory,
Microprogram sequence = „(68108
UNIT -H

Central Processing Unit (CPU), Stack Organization, Memory

Stack, Reverse Polish Notation, Instruction Formats, Zero, One,

Two, Three- Address Instructions, x GS 02. List at least five essential functional blocks that any computer
RISC Instructions and CISC Characteristics, Addressing Modes, should possess, Describe briefly the role of each block. (R.GP.V:, June 2007)
Modes of Transfer... nti 410210122 Ans. In is simplest form, a computer consists of five functionally
Priority interrupt, Daisy Chaining. nn (1228 126 dependent main parts - input, memory, arithmetic and logic, output and
DMA, Input-Output Processor (IOP). £ M 0 18 Control units, . ‘ Es
UNIT-IV

Computer memory system, Memory hierarchy, Main memory —
RAM, ROM chip, auliary and associative memory.

Cache memory - associative mapping, direct, mapping, sel-
associative mapping, write policy cache performanco maca (1871010 ALU = The information received is either stored in the memory for later

TION,
MPUTER/ARCHITECTURE AND ORGANIZATION,
COMPUTER GENERATIONS, VON NEUMANN MODEL,

| ‘CPU ORGANIZATION

Dec. 2015)

Ans. A coniputer may be defined as an electronic machine that can solve

, Pröblems by accepting data, performing certain operations and presenting the
results of those operations under the direction of detailed step-by-step
instructions. Such a set of sequenced instructions, which cause a computer
to perform particular operations, is called a program.

Input — Input units accepts coded information from hu
(13910186 from ciectromechanical devices such as the keyboard ofa video terminal. or
from other computes over digital communication lines

an operators,

Virtual memory ~ address space, memory space, address reference or immediately used by the arithmetic and logic circuitry to perform
mapping. paging and segmentation, TLB, page faul, effective, the desired operations,

access time, replacement 7610 E

ONT manent algorithm au Memory ~ The processing steps are determined by a program stored in

Parallel Processing, Pipelining General Cor writhmetic
Pipeline, and instruction Pipeline nsideration, Arithmi “(19510211 Output Control Unit - Finally the results are sent back to the outside
Neca Coat ne world through the output unit. All of these actions are coordinated by the

Speralons Mati Mutation, and Memory nfrlcaving, a contol unit Bei dinated by th

it has been traditional to ref
thmetic and logic circuits
tion with the main control

to the

incomju as
circuits as central processing unit } Memory TO Mir
(CPU), of simply a processor. Input oe Program

and ouiput equipment is usually Gand
combined under the term input - ; Orgran

output unit (VO). Hu TS Opera IN

ization and compure, Proctor Ro
tAccumetator er AC)

0.3. Differentiate between computer orgar

architecture.
Ans. Differences between computer organization and compute, Fig. 1:2 Seoréd Program Organi

architecture are given below in tabular form —

mization. Instructions are stored in one

Fig. 1.2 shows this typelof org
other. For a meinory unit with 4096 words

S.Ne] Computer Organization Computer Architecture |
4096, If we store each

lection of memory and data in
ture mentions Le need 12 bitsito specify an address since

utes which arenstruetion code in One 16-bit memory word, we have available four bits for

(© [Computer organization mentions | Computer arc
the operational units and their |ihose system at

interconnections that realize the | visible to a programmer, or thos city a 12 bi

persil he operation code to specify one out of 16 possible operations and 12 bit

pp speisen system bue that have a dir „peeify the address of an opercud. The control reads a 16-bit instruction
impacton the logical execution on, ıhe program portion of memory. It uses the 12-bit address part of th

program Instruction to read a 16-bit operand from the data portion of memory. It then

that a

(ii) [Hardware details which are trans- | VO mechanisms, memory addressir

ecules the operation specified by the operation code. Comput

parent tothe programmer such techniques, the instruction se “ecules the operation specified by the operation code, Computers hat a

isthe memory ecology use, | andhenumberofbisusecw pa 8! procesor reiste usually assign it the name accumulator and ibe

¡control signals and interfaces [different data types which am. AC. The operation is performed with the memory operand and the content
between the computer and peri- referred to by architectural)? AC

Ipherals are referred to by organi-| attributes, | Qs. Discuss the generation of computers.

do fats chitecturel_ A Over the years, many computing dev

example, an organization design] Für\eampl&, an architectura sou by (hc humans lo solve different types of problems. All the

th raie by using a special | design) whether a computer wil flevices can be classified into five generations which refer to the phases of

jmulüply unit or by using a mecha-| have a multiply instructior A r Se ee er

eat pat en havea multiply instruction. {provement made to different computing devices resulted in a small, cheap.

Per toes st, reliable and productive computer. The technologica at in the

Feld of comptsts not only re

echnologies, but also the improvements made to the software technologies

develope!

Lo the improvements made to the hardwai

tion.
(RGRY, June 2010 (à First Generation (1940-1956) - The first generation computers
and simples way 1 organize a computers to have processor eg eised the vacuum tubes technology for calculation ay well as for storage and
Operation 10 er format wih two part. The first part specifies control purposes. So, these computers are aso called as vacuum tubes or
dares tells the cone and th second specifies an address, The Me™2Phermionic valves based machines. A vacuum tube, as showa in fig. 1.3, was
read from memory and used aa quan Operand in memory. This Operan gie glass device, which used filaments inside it. The filaments vien
data stored inthe processor ging 1 1 be operated on together Wi ated genere cletons, which eventually help in the amplification

Q4, Write short mote on stored program organi:

6 Computer Architecture

nok sa The
foe could perf

mc
rlihsesonds The
cece

deal
vacuum tt
computations
memory of il
«constructed using lector
al danand instructions were fin Gr
fhe gen from punched cards, These
ons were wren in machine and.
"serbio languages because high-level Heater
am langages were introduccd
. ration

" fagnetie disk and magnetic tape were the m
sd or rat opment made hese compu
y mag Anal anaes a
en al programme ous ple Engh words
allel neon alone multiple ob o e Buches

rain secondary stora

popular and wide!

Cathode

progr s
much Inter, These first £

nn ENIAG EDVAC ‘onpection ‘aman intervention while processing multiple jobs, resulting in faster processing,
Caan Leal ig. 1.3 A Vacuum Tube econd generation computers, an increasing usage of computers was seen in

{iy Second Generation (1956-1963) — A new electronic susy Jusiness and industry for commercial data processing applications like payroll,
ed at Bell Laboratories in 1947 y no contol. marketing and production planning. Some examples ot second
ley and Walter Brattain for which they won the ySenemtioncomputers are PDP-S, IBM 1401 and IBM 7090

itt as shown in LA is semiconductor device hats (ii) Third Generation (1964-1975) ~ In 1958, Jack St. Clair Kilby
ds incre the power ofthe incoming signals by preserving the shape ey um RobertNöyce invented the rs integrated circuit, The major characteristic
¿rg sal as re comecions which are emite (E), bae ar third generation computer systems was lus of Integrated Cie
O The base of tonto le the pate through, which te SR ICs), ICh are the circus consisting o several electronic components
ee amp sent Thesigna sent roue he base Rene Wansislors resistors and capacitors grown on a single chip of silicon
Fee ane lshaliminting wire interconnection between components. The IC technology
eae ar nor 1 mals also known as “microcletronies” technology because it made it possible
the amplified signal. The emitter of the transistorlaets agithe ou integrate tar
E of the tani a M em square) surface of lion, known as “chip” (ce fig 1.) Inia the
phe sl te excel roi Cs inant ony abut 1 twenty components. This Isle was

Pil the esc loge ce aaa a gener nern (SS) Laer ithe adancementin che
ci ANT nd gener manufacturing IC, it became posible 1 integrate up 0 about hunde

device, called transistor, was inves

number of circuit components into very small (less than $

samed small scale in

echnology came to be known as medium

generation computers

more powerful vower
‘ore reliable, less Powerful, er

circuits built by wiring electronic

and e pensive, smaller ‘omponents ly. Henc
le opens is manually. Hence, third
generation copa an the fist ‘eneration computers were more powerful,
Secondary OPPUlErS Printers, Er «cole dore reliable, less expensive, smaller and

cm leds nd operating ‘oler to operate than the second generation Fi
dering RR Ver also invented Me, ompulers.
Fig. 1.44 Transit

1.5 An Integrated Circuit

emputer Architecture um 9

rel advancement in storage ecologies allowed the construction : puters, The progress in

: 4 10 the other generation of comp 7

random deccs memory and large capacity mage reaper as compar hor prin compres, The pros t
tapes. Hance, the did generation computers spically SI and VLSI technologies led 10 the development of mieror

die) of ain memory snd magnetic ippieroprocess0

incorporates various
5 sung le tens of megabytes of data per disk drive. On the oftugomponents of a computer such as CPU,
nd genen we emergence of sandardiztin of hie nemory and VO con. on a wre SP
x operating systems, unbundling ofsofw¿Fhe computers in this generee
A cata a an nied far industry FORT leugned to have a mieroprocessr, Some
An COBOL, wich were de most popular ig dvel programming laguna storage chips and supe ie
thes dys weresandarizty the American National Standard Insitute (Ayeig. 1.6 shows the Intel PAD mero
nn and 1968 respec. They meo refered to as ANSI FORTRAN grosser chip developed Wt TE Sus
‘ANS! COBOL. The idea was that as long as these standards are followed popular later microprogessors ETS Je
Frogramwring.a FORTRAN ora COBOL programcouldborunonany comp 6, Intel 486 and Pentium The ica
an ANSI FORTRAN or ANSI COBOL compile. Additional}, some myPersonal Computer (PC) became
¡eel programming languages were introduced during the third generauhe people during this ea, 4
period. Notable among ese were PL/L, PASCAL and BASIC. John Kemenya — During the fourth generation, magnetic core memories were replaced by
Thomas Kurz of Dartmouth College introduced the concept of time-Sharisemiconductor memories, resulting in large random access memories with very
mg system. Time-sharing operating system simultaneously allows a last aggess time. On the other hand, hard disks became cheaper, smaller and
aber of users to direc acces and share the computing resources in a manrargerin capacin Parallel, in addition to magnetic tapes floppy disks became
that each usr guts the ilusion that no one else is using the computer. This very popular asa portable medium. Another significant development during the
number of independent, relatively low-spodounh generation period was the spread of high-speed computer networking,
1y connected to the main computer. Until which enabled multiple computer to be connected together, to enable them to
emputer manufacturer sod their hardware along witha the esociatedsoftwaommunicate and share data. LANs became popular for connecting several
sel ot charge parts forte sofware they provided to customers. Howevdozen or even several hundred computers within an organization and WANS
thesination changed in 1969 when IBM and other computer manufacturers begbecame popular for connecting computers located at larger distances. This gave,
to price their hardware and software products separately. This unbundling fise to network of computers and distributed systems. Some of the examples of
software from hardware gave users an opportunity to invest only in software fourth generation computers are IBM PC, IBM PC/AT, Apple and CRAY-1
= value. The development and introduction of minicomputers (9) Fifth Generation (1989-Present) - The different types of modern
ok pisc during the third generation period. The computers built until the digital computers come under the categories of fifth generation computers. The
anime syiems, which only Very large companies could afford fh generation computers are based on the ultra large scale integration (ULSD
ly available minicomputer, the PDP technology tra allows almost ten million electronic components to be fabricated
igital Equipment. Corporation (DEC). It confirmon one small chip. The ULSI technology helps in increasing the power and specd
computer fr businessandscientfe appicativof the microprocessor chips and the capacity of primary and secondary storage
corras ate as Computer mans wo had ete oa gr extent As a rel the ih genero comptes ste,
Seager ntl Some eal of itd gneatn computers are Néchaper and moe ei, as compared to he fourth generation computers
9) Fourth Generation (1975-1989) - The average number {
lecronie components packed on a silicon chip doubled each year after 196
This progress soon led to the era of large scale integration (LSI) when it 4
possible to integrate over 30000 electronic components on a single ch
followed by very large scale integration (VLSI) when it was possible to integra *0MPONenIs,
aout one milion eletonic components on a single chip. As a result
manufacturers were able to reduce the size of the computers and made the

front. the

lan

Fig. 1.6 The Intel P4004
‘Microprocessor Chip

by having a I

accompli
online terminals simultaneo!

purchase and use. The first commerci
was introduced in 1965

Q.6. Draw the Von-Neumann model of a digital computer. Explain its

‘various subsystems. (R.GPY,, June 2005, 2008, 2011)
Or

cumann model and explain the functioning of its

(R.GPV, June 2012, 2013)

Describe the Von-

Or
Draw and explain Von-Neumann model of computer and explain its
‘Subsystems, (RGP, June 2014)

ure Unit-1 11

10. Computer Ar

Or on nber of the memory accesses made by the

en by reducing the tou num
y ures the Von Neumann botenesk by proving the

cycle access to its external memory

Describe Von-Neumann model with the help of diagram.
(RAGE, June 29°"!
[CPU with fast, sing

or
is Von-Neumann model of computer ? Explain its various Explain the features of Von-Neumann model.
meer sleet reat, CSL (GPX June 2016)
vel Ans, The key features of Von-Nelimann model are as follows
Deux Von-Neumann model of computer and explain all the suhsysten (i) Data and instructions are stored in a single read write memory
a ESTI May 201 Gi) The contents of this memory are addressable by location without

Ans: Von-Neumann and his colleagues began
the design of a new stored-program computer in
1946, known as the IAS computer, at the
Princeton Institute for Advanced Studies. The
TAS computer is the prototype of all subsequent
general purpose computers. The general structure
of the IAS computer is shown in fig. 1.7. It
consists of

cgard to the type of data contained there.
(iii) Execution occurs in a sequential fashion (unless explicitly

modified) from one instruction to the next.

Arlhmeie
conteur un]

Veumann and Harvard
(R:GPV, Dec. 2009)

Main Memory

© 0.9. What is the difference between Von.
= computer architecture ?

1.7 Structure of th" ans. fn a Von-Neumann architecture, program and data are stored in the
JAS Computer same memory and managed by the same information-handling subsystem. In
(6) A main memory that stores both data and instructions, the Harvardarchitecture, program and data are stored and handled by different
(6) Anaritmeticand logctniK(ALU capable ofopeatingon bina de HbSYStEMS. This is he essential difference between the two architectures

ii) A contol unit that 5 the instructions in In the original “Harvard computer”, built in 1944 and for which the

ne inno cn med, progama tsk andthe nl tsk

iv) Input and output (VO) equipment operat trol Were suficently different to result in wo different storage technologies. Today

(Ge) Input and output (VO) equipment perla bye contour of computers are Von-Neumann architecture because of the

0.7. Draw Von-Neumann architecture. What is meantby VoneNeumarefficiencies gained in designing, implementing, and operating one memory
honteneck ? (R.GE Y, June 2009, Dec. 20lsystem instead of two.

Ans. Von-Neumann Architecture fRefer 10 Q.6: However, in some niches, particularly certain embedded appli

the program is more-or-less hard wired, task requirements are such that the

Harvard architecture can provide distinct operational advantages, Under certain

conditions, a Harvard computer can be much faster than a Von-Neumann

computer because data and program do not contend for the same information

pathway, and storing the program in an immutable read-only memory can

=

Von-Neumann Bottleneck — A computer's performance is also strong
affected by other factors besides its instruction set, especfally the time require
to move instructions and data between the CPU and main memory M and to
lesser extent, the time required to move information between M and 1/O device

It typically takes the CPU about five times longer obtain a word from !'
fines ie fi sleonie gomputers, despite strenuous efforts by cites @.10. Discuss CPU components and functions,
CPU-M speed disparity has become such a feature of standard (Von-Neuman sn BE E
computers that is sometimes referred 10 as the Hon-Newmann bortlenvek, RIS i) The register set which stores | © Fo] "Uinta
Computers usually limit access to main memory to a few load and stos intermediate data used during the execution of
the instructions. Fig. 1.8 Major Parts of CPU

instructions, other instructions, including all data processing and progra”

12 Comguror Arctocture
The atithmetic logie unit that performs the required mi
eperations for executing the structions
{iy The conto! unt that supervises the transfer of information amy
she testers and msiucts the ALU as to which operation o perform
“The CPU performsa variety of functions dictated bythe type of instruct
stich are incorporated the computer. Sometimes, the computer architec,
‘computer structure and behaviour as seen by the program,
à language instructions. This includes the instruction y
+ instruction formats, and the general organization oft
where the computer designers and the compu
chine is the part ofthe CPU associated with ¢

‘which uses machi
addressing mode
CPU registers. The boundary
programmers see the same

instruction set
From the designer's point of view, the computer instruction set provid

the specifications for the design of the CPU. Design of a CPU is a task that
large part involves selecting the hardware for implementing the machi
instructions. The computer programmer who programs in machine or assem
language must be aware of the register set, the memory structure, the type
data supported by the instructions, and the function that each

performs.

E gg Eg

REGISTER ORGANIZATION, VARIOUS CPU REGISTER
I

Q.H. What is register ? (R.GRK, Dec. 201

Ans A sita oop of pop wit ech lp 0oPlgpable
one bit of information.

0.12. Write short note on general register organization,
Ans. Memory locations a Tor storing return addresses, pari
products, pointers. counts during multiplication. Men
me consuming operation in a eompuler so such applications
time consuming. tis more eficicntand convenient to contain these intermedis
vals in prec The registers Communicate with each other
only for performing various microoperatin but also while direct data transfer
Forseven CPU registra bus ogniaton shown in ips 19
In fig. 1.9, the output of each register is connected to wo multiplexers!
form the two buses A and B. For specific bus the selection times in €
allege hese one the input data, The A and B buses forms I"
inputs to a common arithmetic logic unit, The operation choose in the AL!
Geteminos the arithmetic or logic microopertion that i 10 be performs
Mierooperation result is availabe for output data and also goes into the inP

of all the registers. A decoder selects the register which ge

from the output bus. The de
hence providing a transfer path between the data in the output bus and the

inputs of the selected destination register.

Unit-1 13

Vel

EE} sun y

EE]
Decoder

SELD

Oupat

Fig. 19
the information
‚oder activates one of the register load inputs,

“The control unit that operates the CPU bus system directs the information
flow through the registers and ALU by selecting the various components in
the system.
June 2010)

0.13. Write short note on computer registers. (R-GRV.

Ans. Computer instructions are stored in consecutive memory locations
and are executed sequentially one al a time. The control reads an instruction
from a specific address in memory and executes it. It then continues by reading
the next instruction in sequence and executes it and so on. This type of
instruction sequencing needs a counter to calculate the address of the next
instruction after execution of the current instruction is completed. It

le a register in the control unit for storing the instruction

necessary to prov
code after it is read from memory. The computer needs processor rc
for manipulating data and a register for holding a memory address, The register
are listed in table 1.1 together with a brief description of their function and the
number of bits that they contain.

14 Computer Architecture

Table 1.1 List of Registers for the Basic Computer

Register | Number register Nam Function
ul A blind ae
DR 16 | Data register Holds memory operand
aR 12 | Address register | Holds address for memory
ac 16 | Accumulator Processor register
iR 16 | Instruction register | Holds instruction code
PC 12 | Program counter | Holds address of instruction
TR 16 | Temporary register | Holds temporary data
INPR | 8 | Input register Holds input character
ouTR | $ | Output register | Holds output character

ums 15

ve The program counter keeps track ofthe adress ofthe istration
sae next, Therefore, it holds the address of
het intern o be fetched fom the me

fn is to be executed n
y contains t
as been fetched, its content is

tuted sequentially. For a jump
npsto the memory location

whic
location whiel
‘Afieran instruction ha
is are modified, and program jt
4 instruction to be executed next

(R.GRN., June 2008)

ns are normally ex

assuming that instru
ion its content

inst
«which contains the desire

9.17. Define the memory address register.

Or
Write the function of miemors address register in computer sysery
RGP)

Dec. 2005, May/June 2006, Dec. 2013)
ans, Memory address register holds the address of the instruction or data
n ‘Central processing unit (CPU) transfers the

The memory unit has a
bits. Twelve bits of an instruction word are needed to specify the address à

-apacity of 4096 words and each word contains] to be fetched from Ihe memory
‘address of the next instruction fi

‚m the program counter (PC) to the memory
itted to the memory

an operand. This leaves three bts forthe operation part of the instruction any address register
à bit to specify a director indirect address. The data register (DR) holds i, through the add

From memory address register, itis ransmi
ress bus. Sometimes, i is also called simply address register.

‘operand read from memory. The accumulator (AC) registers a general-purpos
processing register. The instruction read from memory is placed in th
instruction register (IR). The temporary register (TR) is used for holdin
temporary data during the processing, The memory address register (AR) la
12 bis since this 1s the width of a memory address. The program cont
(PC alo has 12 ir and hold ie adres ofthe net instruction ere
om memory after the current instruction is executed. The input registe
(INPR) receives an 8-bit character from an input size. The oliiput regi
(OUTR) tide n crac foram ut device, a A

0.14, Write down differen types of registers used by CPU also expla
‘the general register organization with the help of didgram.
(RGP V June 2015
Ans. Refer 0 Q.13 and Q.12. oe) "
0.15. Define the accumulator,
‘ %
Write the function of accumulator in computer system.
a (R.GBX, Dec. 2005, May/June 2006, Dec. 2013
ims. The accumulator is register It holds one of the operands prior 1

the execution of an instruction, and re
n. and receives the result of most of the arithmeti
donne 1e result of most of the arithmet

(R.GPV, June 2008

2.16. Explain program counter.
a a =
Write the function of program counter in computer system.
(R.GPY, Dec. 2005, May/June 2006, Dec. 201%)

(RGR, June 2008, Dec. 2011)

118. Write the function of instruction register in computer system.
¢ (R.GPY, Dec. 2005, May/June 2006, Dec. 2013)
Or

Define he instruction register. (R.GPY, June 2008)
“Ans. Contains the 8-bit opcode instruction being executed. This register
lds an instruction until it is decoded. Some computers have two instruction
registers so that they can fetch and save the next instruction while the execution

of the previous instruction is going on.

Q.19. What is the function of memory data
system ?

register in computer

(RGP, Dec. 2005)
Or

Define the memory data register.

(R.GPY, June 2008)

Ans. Memory data register holds the instruction code or data received
from or sent to the memory. It is connected to data bus. The data that are
written into the memory are held in this register until the write operation is
completed, Hence, the flow of data from the CPU to the memory or from the
memory to CPU is always through memory data register.

NUMERICAL PROBLEMS

Prob.1. The following program is stored in the memory unit of the
basic computer. Show the contents of the AC, PC and IR (in hexadecimal),
at the end, after each instruction is executed. All numbers listed below ure
in hexadecimal -

or Architecture ‘ines a

Location Instruction Pron 3 À diet computer has a common bus system or 16 register ef
7 CLA 12 bin each. The bus is constructed with multiplexers —
ou ADD 016 (i) ow many selection inputs are therein each mutiplese
012 (ii) What size of multiplexer is needed ?
e (ti How many multiplexers,are there in the bus
u (RGP, Dec. 2011, 2012)
oe aoe Sob (i) There are total 2* = 16 Tegisters
ons BUN 013 ‘Therefore, 4 selection fies arémccded to choose one of 16 register
016 c1as (ii) 16% Imuliplexef is needed
017 93C6 (ii) 32 multiplexers, one for each bit of the registers
Sal.
Tocaion| Taxation | Content of AC | Content of PC [Comentofin] | REGISTER TRANSFER, BUS AND MEMORY TRANSFERS
| oo | aa 0000 on 7800
016 0.20. Write short note on ‘register transfer language”.
om | ADDO16 or 1016 1 (RGP, June 2004, 2008)
012 | Bunons cas 014 4014 “Whe. Asesiser transfer language is he symbolic notations used to des
03 | AUT sist 014 7001... | the mieroopertion transfers among register. The term regler sans
017 lc implics the availability of hardware logic circuits which can perform a stated
014 | ano! sins as 0017. | miersoperation and transfer the result of operation of the same or another
ms | Bunon sist 013 11013 | register and the word ‘language is borrowed from programmers, whe apply
a Gas | this term 10 programming languages. Register transfer language (RTL) is a
5 conventional tool for describing the internal organization of digital computers
wee in concise and precise way. Thus, a register transfer language is a system for
(CIAS)=100 0001 1010 0101 AND, ‘expressing in symbolic form the mierooperation sequences among the registers
(93C6)¢= 1001 0011 1100 0110 fa digital module, The register transfer language is believed to be as simple
1000000: 1000 0100 ‘as possible, therefore it should not take very long to memorize. It can also be
a employed to facilitate the design process of digital systems.
Prob.2. A digital computer has a Common bus system for 8 registers of A A d
bits cach. The bus s constructed MSI sisters Q.21. Explain the process of register transfer and write down the basic
ted with multiplexers. symbols used for register transfers.
(i) How many selection inputs are there in each multiplexer? en i
Gi) What size of multiplexer is iplexer ? “Ans, The information transfer from one register o another is represented
e liplexer is needed ? in symbolic form by means of a replacement operator. The statement
(Gi) How many multipexers are there in the bus ? GES

oe (R.GPV, Dec, 2009)

Sol. (i) There are total 23 = 8 register shows a transfer of the content of register RI into register R2. The above

sisters si i

Tl. rin rar efit slat one of @ mer SEP anise ete hat to comen of Hd ep Sy Me oe of
(i) 8 1 multiplexer is needed RI However after the transfer, the content of source register RI does not
(i) 8 multiplexers, one for each bit ofthe registers.

change.

18. Computer Arehtcctoro

specifi fer implies that circuits à
ús ofthe source register to the inputs ofthe destina
fer has a parallel load capability. Usa,
only under a predetermined cont,

Fe statement d

jut re transfer may take plas
Jenoted by means of an ifthen statement.

rah = 1) then (R2RI)
tsa control signal produced in Ihe control section. Sometimes, ii
from the register transfer opere,

condition, This can be

where P
‘convenient to separate the control variabl
ty specifying a control function. A control function is a Boolean varia
o Lor 0. in the statement, the control function is designated a,

whieh is equs

oe af LM
| ey |

Fig. 1.10 Transfer from RI to R2 when P

Fig. 1.10 depicts the block diagram of information transfer from R 1)
R2. Register R2 has a load input which is activated by the control Variable ?
Here, it assumed that the control variable is sy
lock as the one applied to the register

chronized with Ihe'sam:

tis sh
shown in timing diagram of fig. 1410 (b) that PS aétivated in th
aml section by the iung edge ofa clock pulse at time t Next posit
‘ston of th lok atin + finds the oad input ative and then, tht
date Inputs of R2 are loaded ito register in parallel At time + 1, Pay £0
Sic ces etarra plage with every clock pulse anion
ile rena able 1.2 shows the Basie symbols of the register

Table 1.

Basic Symbols for Register Transfers

E T Description — Examples —
me serial amples
A Denotes a register — — RE FE
| (and mineral) | ie

| Parentheses () | Denotes
Arrow 4

Sey ucToopera
“pe nierooperations | R2 RI, R1 <- R2

Com

unit-1 19

capital letters, and numerals may follow
ister by specifying the range of bits or
ister, parentheses are used.
. A comma,

tere estes are represented by
the teens To represent a part ofa
obo mame 10 a portion of 1
by tng à transfer of infomation and he di
Ar shows ta or moe operas which ar execu at he same
is wed er at exchanges the contes of to register during one
fi ls provided tha T = his dented bythe tement as ven

below

«cion of transh

the same

Fi RIE RI, RI < R2
gered flip-flops, are used (0 make this

Registers, having/edgest
‘simultaneous operation possible
0.22. Defiñe control funetion.
Ans, À control function is a Boolean va
the statement, the contro! function is desi
P:R2RI
‘This indiedtes that transfer operation would be executed by the h
nly ifP = 1

(RGP. Dec. 2008, June 2013)
viable which is equal to 1 or 0. In
ated as given below ~

0.25. Define three state buffer. (R.GRW, Dec. 2008, June 2013)

“Ans. A bus system can be constructed with three sta
multiplexers. A three state gate is a digital circuit that shows three states. Two
of these states are signals equivalent to logic 1 and as in a conventional gate
and the third state isa high impedance state. The high impedance state behaves
like as an open circuit, which means that the output is disconnected and does
not have a logie significance. Three state gates may perform any conventional
logic, such as AND or NAND. However, the one of most commonly used in
design of a bus system is the buffer gate. The graphic symbol of a three state
buffer gate is shown below —

gates instead of

Normal.

orp y= Airc =
Tigh Impedance IC

Contra

Inu

Fig. 1.11

0.24. Draw and explain the implementation of 1-bit register.
(Ri Dec. 2014)

Ans. The implementation of one bit register is shown in fig. 1.12. The:

triggered D flip-flop is stored the 1-bit data, which is connected to the
common bus through tri-state buffers.

architecture

20 Comm

unit=1 21

Ey s—]

ieee

Fig. 1.12 1-bit Register
The input D and output Q are connected through input tri-state buf
respectively. If Rig is active, the control signal R
Enables the input tri-state buffer and the data from common bus is loaded in
the D Mio in synchronization with clock input. This is implemented us,
AND gate (see fig. 1.12). The control signal R y is activated to load data fro
Q output ofthe D Mip-flop onto the common bus by enabling the output 1

and output tri-state but

sate buffer

The bus contention problem oc
buffers are active at a time. To avoid bus contention no more than one oups

buffer may be inthe active state at any given time.

1s when two or more output trissat

0.25. Draw and explain the organization of a CPU showing th
connections Benscen the registers to a common bus. (R.GRV., Dec. 201)
Ans. The basic computer mainly contains a control unit, a memory ux
and eight register Paths must be offered to transfer information from
to another and between memory and registers. If connections 8
made between the outputs of each register and inputs of the other regis!
umber of wites will be excessive. A more efficientapproaeh to transfe
tion in a system with many registers is to use;a common bus
1.13 illustrates the connection of the registers and/memöry of the bes:
mon bus. The outputs of memory and seven registers at
ed Lo the common bus. At any given time, the particular output that
chosen for the bus lines is determined from the binary, value of the selecto
variables 5, S, and So. The number along.cach output shows the decime
equivalent ofthe required binary selection, For example, the number along I
output of IR js 5. The 16-bit outputs of IRare kept on the bus lines when S:
5, Su = 101 because this is the binary value of 5. The lines from the como"
bus are connected to the data inputs ofthe memory and tothe inputs of ec}
register. During the nex clock pulse transition, the particular register who“
load (LD) input is enabled receives the data from the bus. If the memory wit
input is activated then it receives the data from the bus. Ifthe read input ©
activated ad 8,8, = 11 hen he memory places its Lit ouput nt 1

the

do NACL
A A à

tp INRCLR,

ub

do,

ick

Fig. 1.13 Computer Registers Connected to a Common Bus

rs AR and PC have 12 bits each since they hold a memory
ts are set to 0's when the contents of AR
Or PC are sent to the 16-bit common bus. When AR or PC receive information
from the bus, only the 12 least significant bits are transferred into the register.
DRAC, IR and IR have 16 bits each. The input register (INPR)
“output register (OUTR) have 8 bits each and communicate with the
1 bits in the bus. The 16 lines of the common bus receive
ive registers have thre

Two register
address. The four most significant bi

Four re
and t

eight least signific
information from the memory unit and six registers. Fi
CLR (clear), INR (inerement) and LD (load). The increment

control inputs
ing the count input ofthe counter, Two registers

operation is obtained by enabl
have only a load input.

“The input data and outpt
bus, however, the memory address is connected to AR. Thus. AR mi

be used to specify a memory address. By employing a single re

ut data of the memory are connected to the common
st always
ter for the

22 Computer Architecture
the need foran address bus that would have been require
ler can be specified for the memory day

ster can receive the day

address, we remove:
‘otherwise. The content of any 1
input during a write operation. Likewis
KR memory afer a read operation except AC. The 16 inputs of AC copy,
fam an adder and logie circuit that contains three sets of inputs. One set yy
Tech inputs come from the data register (DR). Another set of 16-bit inpu,
from the outputs of AC, which are used to implement registe,
operation lke sift AC and complement AC. The inputs from DR ang
AC are utilized for arithmetic and logie microoperations like OR DR 10 AC qy
{Ad DR to AC. The result of the operation is sent to the AC and the end cam,
sat of the operation is sent to flip-flop E. À third set of 8-bit inputs come from

the input register.
0.26, Explain the different types of registers
Explain how these registers are connected 10 a common bus.
(R.GPV, Dec. 2012

used in a basic computer

Ans, Types of Registers ~ Refer 10 Q.13.

Connection between the Registers and a Common Bus ~ Refer to Q.25,

0.27. Why address and data bus are multiplexed ? (R.GPV, June 2016)

Ans. The address and data bus are multiplexed to reduce its numbers
pins. Since we do not require address and data at the same time, we can have
2 common bus for address and data. To select a memory location, we need

address first, when the location is selected after that we have to transfer the
data with that selected location.

0.28. Write explanatory note on system bus. (RGP, May/June 2006)
Or
Explain common bus system archiectut@ with the help of diagram.
ae (RGPY, June 2015)
An A typical computer system has a number of buses at various levels
to fiiliat the transfer of information between components: The CPU contains
4 number of internal buses for transfering information between processor
registers and ALU. À bas which connects major components in a multipro
system, such as CPUs, 1OPs, and memory, is known as a system bus.

so a shee memory multiprocessor system, the processors request

mm memory or other common resources through the system bus. I?
o 1 the bus, the requesting processor may
ri the sytem bus. he requesting proceso must wait In addition, th
702655075 may request the system bus atthe same time. Then, arbitraion

no other processor is currently usin

uml 23

n for the shared sources,

formed to resolve this multiple contentios
stem bus structure for multiprocessors

ee =

must be pet
Fig, 1.14 depiets the sy

oo [crc] fro

Controller

tem mn [ru] [ten

sytem te} Lo [or e | (TU =

I I I
Tao

Taco Ba
Fig) 1.14 System Bits Structure for Multiprocessors
tains approximately 100 signal lines. Functionally,
“data, address, and control. Furthermore, there
ly power to the components. Data

Atypical system bus co!
these lineSiare of three types ~
‘are power distribution lines which suppl
lines provide a path for the transfer of data between processors und common
memory, Generally, the number of data lines is a multiple of 8, with 16 and 32
being most common. Address lines are employed to recognise a memory address
fr any other source or destination, such as input or output ports. The number
‘Gf address lines determines the maximum possible memory capacity in the
system, As an example, an address of 24 lines can access up to 2°4 (16 mega)
words of memory. Data and address lines are terminated with three-state
buffers. Data lines are bidirectional, permitting the transfer of data in either
direction. Address buffers are unidirectional from process to memory

“The data transfers over the system may occur in two ways ~ synchronous
‘orasynchronous. To control the information transfer between units, the control
lines provide signals. Timing signals specify the validity of data and address
information. Command signals indicate operations to be performed. Typical
control lines are transfer signals such as memory read and write, acknowledge
of a transfer, interrupt requests, bus control signals such as bus request and
bus grant, and signals for arbitration procedures.

0.29. Explain and draw a diagram of a bus system that use multiplex
k registers of n-bits each to produce an n-line common bus.
(R.GPV, Dec. 2008, June 2012)
Or
Draw und explain the bus structure for the data transfer between registers
and the common bus. (R.GRY. June 2013)

stor Architecture

ns. Abus system will multiplex k registers of n-bis each to produce y,

"on bin, The number of multiplexers needed to construct the by

Unit-1 25

bia number of bits in each register. The size of each multiplexg, — y,
Re serons e le, a common bus fy ps |
ce ais a nes. For example common hu soe =
cages 16min one foreach lin in waa =
Se cams aight dt pt Ins andre cet
a Register 1-7 Bt
DT Be
CAES
TH
xe bad ote ba [Pa Register, 1 =D}

| | Hi TT EAT

+4

bind [

Regier? Melero

Fig 1.15 Bus System fork Registers
The consracion of a bus system fork register showin I 1.15
ter has n bits, numbered 0 through n= 1. THE bus consists of 0.

dex 1 mulúplescrs each having k dat inputs, O thr € number of
seen Ines wl be Such ht 2 under

030. Draw a common bus system wit is
hoc Bus system with Your registers with the help of

(R.GPY, Dec. 2011)
Ans. Abus sirutur composed of

se sel af st of common lines, one for each

Con ass ooh which binary information is tantemed on a atime
onto! signals determine which rite” pe bus during ac
an ich register is chosen by the bus during each

Pina eier ans. The muliplosr let he source regir whee

binary information
"Y information is placed on the bus. The construction of a bu

four register is illustrated in fg. 1.16 system for

4130
Common Bus
ig. 1.16 Bus System for Four Register

sure, each register contain four bits numbered from 0 to 3. The bus

ME
ta inputs from 0

consists of a four 4 x 1 multiplexers each containing four dat
10 3, and two selection inputs Sy and Sy. In fig. 1.16, we use labels to show
the connection from the outputs of the registers to the inputs of the multiplexers
to simplify it. The diagram shows that the bits in the same significant position
in each register are connected to the data inputs of one multiplexer to form
‘one line of the bus. Thus MUX O multiplexes the four 0 bits of the register,
MUXI multiplexes the four 1 bits of the register and so on. The two selection
lines Sp and $ are connected to the selection inputs of all four multiplexers.
The selection lines select the four bits of one register and transfer them into
the four-line common bus. The 0 data inputs of
all four multiplexers are chosen when S¡Sp = 00
and applied to the outputs that form the bus. This
causes the bus lines to receive the content of
register A because the outputs of this register are
connected to the 0 data inputs of the multiplexers,
Ina similar way, register B is chosen if S,Sq= 01
and so on. Table 1,3 shows the register which is
selected by the bus for each of the four possible
binary value of the selection lines,

le 1.3 Function Table

_ T Register

26 Computer Arcade

NUMERICAL PROBLEMS

Probes Represent the following conditional control statement by y,
eier transfer statements with the control functions.
Pe 1) then (Ry By else if (D = D then (Ry — Ry
(RGPS:, Dec. 2007, June 207,

Sol. PER «
PO:R¡ CRs

Prob$, Show the hardware that implements the following Statemen
include the logie gates for the control function and a block diagram for th
Binary counter with a count enable input.

ayTy +Ty+ y TAR AR HI

(R.GPV, Dee. 2013,

Sal, The hardware implementation (block diagram) ofthe given statemen
is shown in fig. 1.17

ao

1

a ou En
EA] Binary Co
Counter

Fig LIT

Proh Show the Mock digram o the hardware i
piel vee. an, à

RyRy, RR,
‘Sok Fig. 1.18 shows the block di
ic block digeram of the hardware
the given register transfer statement, à
i

that implements

Guck

Fig. 1.18

Unit = 27
Prost, Design a hardware circuit by using common bus architecture

1 implement the following register transfer languages —

Ps dp eA
9 : 42 -4s
RA CA
8: Aye dpa As

‘Ag are one-bit register
à by using common bus architecture to implement
1.19.

where Ap Ay Aw
Sol. Hardware circuit

YY Y
e a eed Bak PL u
Pr 2

Fig 109

Prób.8. Consider the following register transfer statements for two 4-

bitregisters RI and R2-
aT: RI RI + RD
XTERI ER?

Every time that variable T = 1, either the content of R2 is added to the
content of RI if = I or the content of R2 is transferred to RI if x = 0. Draw
a diagram showing the hardware implementation of the two statements.
Use block diagrams for the two 4-bit registers, a 4-bit adder and a quadruple
2 10 1 line multiplexer that selects the inputs fo RI. In the diagram show.
how the control variables x and T select the inputs of the multiplexer and
the load input of register RI.

Sol. The hardware implementation of the above given statements is shown
in fig. 1.20,

4

Fig.

28 Comer Bree oe e

prob. Show the hardware implementation or the following stem

The registers are 4-bit in length. 4 ee ONS, k
7 $ (METIC, LOGIC AND SHIFT MICROO! 2
Tj:4 ER, | ARITHMET rTMMETIC LOGIC SHIFT UNIT

ok,

Le DEA 0.1. Write short note on microoperations. "(RG June 2010)

Sol. The conditions are represented through the following tryy or
= Explain microoperations. (R.GRY., Dec. 2007, 2011)
a s zs or
LCD LE BE BU BU mus Define microoperation, À. {R GR, June 2004, 2005, Dec 2008. HM.
June 2012, 2013)
J ofojofo|=|=[o |
0 Ans. A microoperatiomis a basió operation performed on the information
opa poj Jefa stored in one or more registerso The result obtained after the operation may
ofifofol Paja place the previous binary information ofa register or may be put into another
' register. Shift, count, clear, and load are the examples of mierooperations. A
ololifolilolt Counter with parallel load can perform the microoperations increment and
ofolofr food. À bidirectional shift register can perform the shift right and shift Left
Lt microoperations In a digital computer, the internal hardware organization is
‘The condition statements are ~ best defined by specifying —
(6) Set of registers it contains and their function

ABER (i) Sequence of microoperations performed on the binary

Seht, information stored in the registers.

enacts (i) Control that initiates the sequence of microoperations
BE the bloc Mr In a computer, the sequence of microoperations can be specified by
E nl pik dagen showing te karéwar implementation regis a een solana ‘words, but this procedure generally involves a

i. 1.2 lengthy descriptive explanation. Itis more convenient to adopt an approp

= symbology to describe the sequence of transfers between register:

P various arithmetic and logic microoperations associated with the
DE ET The use of symbols instead of a narrative explanation provides a
. ur VA ns » and concise way for listing the microoperation sequences in registers and the
u. control functions which initiate them,
BI à 1, 0.32. What are the various categories of mierooperations ?
3 Ans, Microoperations are classified into four categories ä
te N () Register transfer microoperations transfer binary information
I from one register to another.

Gi) Arithmetic microoperations perform arithmetic operations on
ren numeric data stored in registers

30 Computer Architecture

Logic microoperations perform bit manipulation operation,
stored in registers.

i
non-mumeric da
(ix) Shift mierooper

ia registers
0.33. Explain arithmetic microoperations.

tions perform shift operations on data sy,

Ans. Addit
arithmetic miervoperation

subtraction, increment, decrement, and shift are the by,
"An add microoperation is specified by the statemen

R3 € RI + R2
It states that the contents of register RI are added to the contents
eviser R2 and the sum transferred to register R3. The hardware implementa,

ods three registers and the digital component that perfor:
ion. Other basic arithmetic microoperations are given

the addition oper
table 14

‘Table 1.4 Arithmetic Microoperations

eae | Description
PRECRISRI | Contents of Ri plus R2 transferred to R3
RERI-RZ | Contents of RI minus R2 transferred to R3
Wek Complement the contents of R2 (1's complément)
R2Ri=1_ | 2°scomplement the contents of R2 (negate)
RSG RI-R22 1 | RI plus the 2°s complement of R2(subrraction)
j are Rist

| Inerement the contents of RI by one

the contents of Rb

In general, subtraction is impleme on
on. Instead of using the minus 0;
2 following statement

ted through complementation as
subtraction is specified +

Re IR Ran

's complement of Rand addin,
¡Us come and adding 1 to it generates 1
iding the contents of RI to the 2's complement of R2

2. Increment and deren
Scat Rt Be teeta oe meras smb

equivalentto RI

Im most computers, the mult

séquence of add and shift mierooy
quence of subtract and shift m

ipliction operation is implemented wit!
erations, and division is implemented with
nierooperations,

Unit-1 31

L microuperations ? Enlist the

0.34. What do you understand by Io

various logic mierooperations.

nes OR mieroopen

ex este bythe atmen!
PAL RUD R?

croapttion ioe exe on he individual bits of

Special symbols ar used

nto dingue

olen funtion. The

operations are the microoperations which specify binary
UF bits stored in registers. In these operations, each bit
(ely and treated like binary variables. As an
tion with the contents of two registers

i specifies a logic mi
the registers provided
for the logic mierooperation:
from the corresponding symt

the control variable P
$ OR. AND, and complem
bolstemployed to express Bot
symbol v is usedifo represent an OR mierooperation and the symbol À to
asen an AND mierooperation. The complement microoperation is the
as the Ps complement and uses a bar on top of the symbol which
designatesthe register name. Iwill be possible to differentiate between a logic
‘nicrooperation and 4 control or Boolean function by using different symbols,
‘Another reason for adopting two sets of symbols is to be-able to distinguish
he symbol + when used to symbolise an arithmetic plus, from a logic OR
“operation. When the symbol + takes place in a microoperation, it will represent
fan arithmetic plus, and when it occurs in a control or Boolean function, it will
denote an OR operation. As an example, in the statement
P+QiRIR2+R3, REC RSVRE

the + between P and Q is an OR operation between two binary variables of a
control function. The + between R2 and R3 denotes an add microopera
The OR mierooperation is denoted by the symbol v between registers RS and
Ré.

Sixte

different logic operations can be performed with two binary
variables, which can be determined from all possible ruth tables obtained with
two binary variables as depicted in table 1.5. In this table, each of the 16
columns Fy through F represents a truth table of one possible Boolean function
for the two variables x and y.

Table 1.5 Truth Table for 16 Functions of Two Variables

32 Computer Architecture

Uni1 33
The frat column of table 1.6 represents these 16 Boolean func, i
Ce tr om, Te 1 og meer tiron A ven
iiained froma these functions by replacing variable x by the binary gy. RL<-shl RI
vr A and variable y by the binary content of register B. Bont R2e-shr R2

Cancons Jste in first column of table 1.6 represent a relationship bey
variables x and y. The logie:microoperations listed in seq,
column denote a relationship between the binary content of wo regia
and B. 1

Table 1.6 Sixteen Logie Mierooperations

Transfer B

eration | Name a

.
| clear =

| AND |

| |

| F<A8B Exclusive OR

| | Feav OR

i | FeAvB NOR
Exclusive NOR

Complement!

Complement A.
|

(R.GRY, May 20

toyfänsfer the data serially. Y
tole ef or the right. There are th

NAND
Set wall!"

Fall ls

235. War are she various shift microoperations 2
Or .
rite short note on skip miérooperations ?
Ans. Shift miroopertions ae used
ts ofa register canbe shite
types oF shits
@ Logical shin
Gi) Circular shit

(ii) Arithmetic shin.

( Logical Shift ~ A logical shif is one which transf

input. The symbols fers 0 throof
‘put. The symbols shl and shr are used for logical shiftleft 4

the serial

se wo mierooperaions which specify 1-bi shift the Tet of the content

AR and a it shift fo the right ofthe content of register R2
Oe al shi the it ansferedf he end position through the serial
input i assed 10 be 0

or rotate operation circulates

(ii) Circular Shift Acircular shift
the bits of the register around/the two ends without loss of information.
‘This is done by connecting the serial output of the shifl register to its serial
input. The symbols if andicir are used for the circular shift eft and right,
respectively. Table .7 shows the symbolic notation for the sh
microoperations.

“Table 1.7 Shift Microoperations

Eymbolic Designation Description
PREM | ShiftlettregisterR |
ReshrR | Shiflright register R |
Recil R Circular shiftleft register R |
| R<-ashi R Arithmetic shifl-Jeft R

(iii Arithmetic Shift - An arithmetic shift mierooperation shifts
signed binary number to the left or right. An arithmetic shift-left multiplies a
signed binary number by 2, while an arithmetic shif-right divides the number
by 2. Arithmetic shifts must leave the sign bit unaltered since the sign of the
number remains the same when itis multiplied or divided by 2.

Q.36. Discuss in brief about logic and shift microoperations.

(R.GPY,, Dee. 2017)
Ans, Refer to Q.34 and Q35.

0.37. Explain different microoperations with example.

(R.GPV, June 2016)
Ans. Refer to Q.33, Q.34 and Q.

‘oultiplerer. the data are selected wit
inputs to the multiplexer are A,

Init 35
34 Computer Archtectun pas

(0.38. Explain arithmetic logic uni ln detal a
Inacnd of using the individual registers to perfor, AME

Input systems uses Various Storage rep,"

One stage of ALU unit shown in fig.

‘Table 1.8 Operations of the ALU

Ans
rnicrooperations directly

mon ALL, The data of particular register are Kepa ig
sara ef he common ALU o perfor a mierooperaion. Then, the af Operation Select es naci
sat san apron and eu is rando à destination o 513: | 51 ] So | Gn
Fee rata cra so that the entre register transfer ope, | St toto Transfer A
er og the ALU and into he destination rege 0 | 9 | 5 | 0 | 1 EN
fom the sue uring one clock pulse period. Oftenly. eg} © | 9 | 9 | 9 | 0 ‘Addition
can be performed ore china sparc nt but sometimes itiepm | © | 0 | 0 | 1 | £ Add with cary
nl 6 0 Subtract with borrow
ral o} 0) 1 | Gey Subtraction
aus en ET opoj1 Fade
> lí Theo Decrement A
s o | o | il | % Transter A
à : AND
À of 1 fo] où *
s i E (la OR
CT one ia o Leal, MO [> XOR
eee Loi o let | = ‘Complement A
Acid i fof at] = Shift Right A into F
LCL er Lee y hal 1 » |» Shift Ich À into F
T |, 4 ogee
Gut eux ni 0.39. What do you mean by logic microoperation ? Explain any four
Ly 2 of logie microoperations. Draw one stage of logie unit with its function
One Stage re table. (R.GBV., May 2018)
E mo a Ans. Refer to Q.34 and Q.38.
7 ora 0.40, Explain why each of the following microoperations cannot be
‘| 7 executed during a single clock pulse —
A id RE MPC]
Fig LB AC ACH TR
1 DR <-DR + AC

of an arithmetiologic shift unit. NÉ y |
iris are combined into one ALU US Pee a sequence of microoperatons tha will perform the above
s. Here the subseript rep RES

to both the arithmetic ei

figure, the arithmetic, logic and shift

mon selection variables tsa stage. Inputs

rn bath he arihmet ut an igi cire. Inputs So? (R.GRY., May/dune 2006)
operation. A+ | multiplexer at the OU Ans. (IR MIPC)
arithmetic output in E, and a logic output in H ln ©

h inputs S, and $,, The other wo ¥ Ho

+ PC cannot provide address to memory. Address must be transferred

for shift righ e sb to AR fi
left operatio Tight operation and Ay . Fo Ÿ st
neo The Output carry C,,, of a given arithmetic singe must! P
connecte wo the input carry C oft arithmetic stage n ARE PC

next stage in sequence. The input (1°
Fit sage is the input carry Ca which eave The ne

: of REM
in Which provides a selection variable MARY

36 Computer Architecture
(i) ACE ACH TR
Mere, add operation must be done with DR. Transfer TR 10 DR fi
DReTR
ACH AC + DR
ii DR + DR + AC
addition is transferred to AC (not to DR). To save vat
be stored temporarily in DR (or TR). ‘|

Here, res
AC its content rm

AC © DR,DRe-AC
AC AC+DR a —
É ARITHMETIC ‘AND LOGIC UNIT, FIXED POINT
ee REPRESENTATION INTEGER REPRESENTATION, SIGN- -
MAGNITUDE, 1'S AND 2'S COMPLEMENT AND RANGE

0.1. Discuss the arithmetic and logic unit (ALU).

Ansi The arthinetic logie unit (ALU) of a compu
where the actual execution of the instructions takes place during the processing
Speralon, That fs itis also responsible forall calculations performed and all
comparisons (decisions) made inthe ALU. The data and instructions, stored in the
primary storage prior to processing, are transferred as and when needed. 10
ALU where processing takes place. Intermediate results generated in the ALU are
{emiporaily transferred back to the primary storage until needed at a later time
Data may move from memory to ALU and back again to storage many times
before the processing is over. There are number of arithmetic and logic operations
that a computer ean perform. These are add, subtract, multiply, divide and logic
operations or comparisons such as less than, equal to or greater than

xr system is the place

Fig. 2.1 shows, in general terms, how the ALU is interconnected with the
rest of the processor. Data are presented to the ALU in registers and the
results of an operation are stored in registers. These registers are temporary
storage locations within the processor that are connected by signal paths to
the ALU. The ALU can also set flags as the result of an operation. The flag
values are also stored in registers
within the processor. The control unit Carat
provides signals that control the “tai
operation of the ALU and the pes
movement of the data into and out"
ofthe ALU. Fig. 2.1 ALU 1/Ps and O/Ps

2.2. Write down the functions performed by ALU.

Ans. ALU (arithmetic and logic unit) is the part of the CPU which

n ofthe CPU which performs
arithmetic and logic operations. Generally, an ALU performs the following

Arithmetic
Logi Unie

Regine.

38 Computer Architecture Una-n 39

ad loge operations sins hardware elements that perform typical operations such as

fy Subtraction gi unit contains hard iat operations such à
eo Be I ta ara sine ALO une pa
es ) Logical OR o aional elements such as gates, multiplexers. and a 4-bit parallel ade
42) oe i Se For this approach, first an arithmetic unit and a logie unit are

(viii) Complement (logic: OT; a -ombined to obtain an ALU.

(5) Le or right shif dhe content ofthe aecumalator cam be shit, The key elemento this system ia bit parallel adder. The millones
Ay Char he conet fe accumulator orca tag cn be made Sec ther Y OF TNS. By ince the selection input (Sq) also
ALU does not perform other mathematical operations such as exponer. 0, js po input carry (Cire Fllowingesulis

logarithmic, trigonometric and floating-point operations. These operations; “rg, = 0 then FER plus Y

performed by special purpose math processor called floating-point unit (FP Ve F = X plus Y'plus 1

(ii) Logical exclusive-OR ral en they are €

fet or

Modem microprocessors contain an FPU on the microprocessor chip ity X minus Y
fie, an on-chip FPU). For the second’, a wworfunetion logic unit, as shown in fig. 2.3 is designed.
Discuss the design of ALU. From this figura itcan be Seen that when Sy = 0, the output G = X AND Y; otherwise
or the ouputG = X@ Y. Note that from these two Boolean operations, other operations
Take un example and explain the design of arithmetic and logic un suchas NOTand OR can be derived by the following Boolean identities
(R.GRK, June 201. ve x
Ane. Fi xORy=x 0 y Oxy

tionally, an ALU can be divided into two segments ~ E
arithmetic unit and the logic unit. The arithmetic unit performs typical arithme:
‘operations such as addition, sublraction, and increment or decrement by

“Therefore, NOT and OR operations can be obtained by usingadditional hardware
‘The outputs generated by the arithmetic and logic units

and the circuit of

Ce te penado volves ey Designed orage integral MA es 108 à 5 0 felines as shown SE 2-4
an however, an arithmetic unit must handle 4-bit binary coded decim yo Lux | te 5 sux
a numbers and floating-point numbers. Therefore, this unitmust incltk >— lea EE | le ”
necessary electronics to manipule these data types. As Iheiname implies. 5 5
7 ” 5 Darst,” At) A HP,
Ll, ni
ET _ ET
ra TD =
=p mux pil MX Le
eat ED, ss 6— fe
PEN DH: Em DA ul
FTTI À 1
5 y
AS Fig. 23 Organization of a Logic Fig. 2.4 Combining the Outputs
Seren. Unit Generated by the Arithmetic and

Fig. 2.2 Organization of an Arithmetic Unit

Logic U

Computer Architecture

From this organization it can be seen that when the select line 5, «
er select outputs generated by the logie unit: otherwise, thd
à unit are selected. The select line, S is referred to as the
pue since selects the derived mode of operation. A complete block
schematic ofthis ALU is shown in fig. 2.5

— |
Unie A
| He
‘Select [$ T
we

.5 Schematic Representation of the Four-functions ALU
‘The truth table illustrating the operation of this ALU is shown in fig.

Skalen |
een) ee Comm

NON LTS a

CO ECTS EXE
+ Boolean AND,

TP Fade OR,

Ans. lo the fixed-point number repres

6 the binary or decimal point is at the A

E E nal point is at the extreme right of the computer we

inal numbers are postive or negative integers, he radix print as

to bea! the extreme le. then all numbers are pose or negative fractions
’onsider that you have to multi y

that you ultiply 23.15 and 33.45. This will

ren nie 5 x 3345. The result will be 7743675, The decimal po!

laced by the user to get the correct result, which is 774.3675. $°

11 numbers #
integer or BCD numbers are refer
ofitain no information regarding

binaty point. The binary or decimal poit!
or let OF the number.

itp

Uniti 41

entation system, the user has to keep track of the radix

as
ns binary number sytem, arta

e nary mumber 11010101, equivalent

a ey do nohave ih benef of minus ig and prod or

er aaa end Procsig Onl ina dits and 1 ae

re oe pune Te represen 15 snlaifoan if Weare

swith the digi

ae from 0 10 255 (2°).

0.6. Discuss sigitemagnitude representation in brief.

Ans. There are varibus ways to represent negative as well as positive
integers. All of them involve treating the most significant (Ief-most) it in
the wordas asign bit. The number is positive if the left most bit is O and
the number is negative ifthe left most bit is 1. Sign-magnitude representation
is one ofthe simplest type of representation that uses a sign bit. The right
most n — 1 bits hold the magnitude of the integer in an n bit word. For
example

+36= 00100100
-36= 10100100
Sign-magnitude representation has some limitations. First, addition and
subtraction need a consideration of both the signs of the numbers and their
relative magnitudes to carry out the required operation. Second, there are two
representations of (+ 0 and ~ 0). That's why sign-magnitude representation
is rarely used

0.7. What is 1's and 2's complement representation ?

Ans. (1) 15 Complement Representation - One's complement is specific
type of representation of binary numbers. If each 1 is replaced by 0 and each
O by 1, the resulting number is known as the one's complement of the first
number, Both the numbers are complement of each other. If one of these
numbers is positive then the other number will be negative with the same
magnitude and vice versa. For example (01101), represents (+13)19 whereas
(10010); represents (- 13)10 in this representation.

This method is widely used for representing signed numbers. In this
representation also, MSB is 0 for positive numbers and | for negative numbers.

42 Computer Architecture
(i) 2% Complement Representation -TW0"s complement y
umber can be calculated by adding L to one's complement of y
number. For example. 2 complement of O101 is 1011. Since O10) yo $
{Sy therefore LOI represents (~ Sha in 2% complement repnae
in this representation ifthe MSB is O the number is positive
MSB is 1 the number is negative. One thing important in 2's
that the 25 complement of a number is the number itself

Tak,
the pe

na
whereas

$ complene,

8. What are he diferent wars of representing a signed rampe
shat isthe best was of representation ? Why (RGPY, Dec. an

dn hear ars ways freprsennga signed number fl u

= Refer 10 QS =

Integer Represent:

Prol

Prob.2. Convert the following numbers with the indicat

imal.

Unit 43

convert hexadecimal number (F3) yg into decimal number.
TERRE (RGPV, June 2014)
DER x 16Ù+ 3 » 16°
5164 3x1
403 (2410

bases 10

@ (12121); (i) (4310)5 (R.GPY, June 2015)

(2, ERES

Sien-magnitude Representation — Refer to Q.6. Sol. (i)
Ys and 2's Complement Representation — Refe AA =
sentation — Refer to Q.7. E IRSA 4 1x5140% 50
Thebest way of representation is 2 complement because 2's complen, À 4x 125+3:25+5+0
notation isnot very simple to understand hut its advantage is that then = 500 +75 +5
Singe notation for zero. which is very convenient when the computer «e = 68010 ei

to test for a O result Also, itis ver

arithmetic addition operatic u

straightaway gives the correct result,
Hence, 2's complement notat
numbers inside a computer.

tion is generally used to represent sie

Fraps * complement of a number ? (R.GBY, Dec, 20
the Rp omplement can be formed by leaving Al least sj
replacing 1's by Osma no owrorder O'S andirst Minchanged and $

Q.10. Explain 28 complement method of subtraction

of binary numb
(RGPV, June 20!
er is equivalent to À
tract 0010 (2 decim’

en
ts. The tion of 74 o
seen o e number Sur
from O101(S decimal, Ihe
Sum willbe DO! (en

= 0011 (3 decimal).

lement of a numb

uppose, we want 10 sub

:cimal) 0010 (2 decin™ (_g5;

stand for posi

(4112) th
tra)

Probi3! Determine whether the following 2's complement notations

‘or negative numbers. Give their values in decimal numbers.
Gi) om
(iv) 01010101

@ 01110000

i 10001111
(RGPV, Dec. 2017)

Sol. (i) 01110000

f the LSB bit is O, then number is positive. Since 01110000 represents
efore 2's complement of 01110000 is 10010000 representing

0
non
Ifthe LSB bit is 1, then number is negative. Since 11001111 represents
io, therefore 2's complement of 11001111 is 00110001 representing
Mo:
Gi 10001111
IF the LSB bit is 1, then number is negative. Since 10001111 represents
ho therefore 2's complement of 10001111 is 01110001 representing

(iv) 01010101
Ithe LSB bit is O, then number is positive. Since 01010101 represents
dio, therefore 2's complement of 01010101 is 10101011 representing
o:

4 Comautor Architecture ae

TIGER ARITHMETIC ~ NEGATION, ADDITION an

2,8 shows the Mlowchart fo
jig 28 shows the Mowchas
‘SUBTRACTION, MULTIPLICATION, DIVISION O two binary ben I AC and BR reg)
obtained by adding IN In s
esis 1th
0.1. Define arithmetic processor oc
called arithmetic processor, The data type assumed 10 reside in prog mus he same sign
definition ofthe instruction. An arithmetic instruction can specify bin.
decimal dat, and in both case he data may be in fixed-point or Noatng,
form. Integers or fractions may be represented by fixed-point num,
Sepa numbers may be represented in ether signed-magnite or sg
complement representation. If only a binary fixed-point add instructn
‘arithmetic operations for binary and decimal da A

in fixed-point and fa Vic Overton

Point representation, it would be more complicated. Go
212 How de jo perform negaon of an integer? Cc eg and Sabre Nam
dim. The negation ofanintgessimpleinsign-magnitude representa isa A Flobchart for the Algorithms of Adding and AUTEUR À

and carried out by inverting the sign bit. The negation of an integer in! in Signed-2's Complement Representation

‘complement can be carried out with the following s i ‘ >
ith the following rales cedure for addition and subtraction for fx

im of adding and subtract
tation. The sum is
je last

ters. If the exclusive-OR of ae

Q.14. Describe the pro

seb hb oF the integer inclui offener Explain y we of fomehart (RG: Dec 2004, 2006)

(i) Treating the result as an unsigned binary integer, add 1 plain the hardware for signed-magnitude addition and subtraction

va E ¡Give the flowchart for add and subtract operation Oftwo signed: with block diagram. (RGP, Dec. 2007, June 2013)
lement dat. Explain the logic ofeach operation. (R. GR Ve Dec 2 or o |

Ans The addition of two number in signed. Derive an algorithm in flowchart form for the addition and subtraction of

of adding the numbers: 2's complement form cons

withthe sgn bi
scl ua Mn is. A mutant posi

“fixed point binary numbers insigned-magnitude representation with subtraction
done by a parallel subtractor (E, A <A - B). Show one stage of the adder-

hte tem a o nee ha ec St wih ét on ASC). LER, Jae 208
The overflow can a Oc occurs, E à

the ne ca D db ping Le Show the hardware to be used for addition and subtraction of wo
En sd decimal numbers in signed-magnitude representation. Indicate how an
i gardware imple overflow is detected. (R.GPY, Dec. 2008)

in fig. 2.7. The lefimost A E Rocco me m
“a Write down the algorithm for addition and subtraction with signed-
magne data Als daw We fowehart (GP, June 2011)

re complementer and AC Roger à

is an overflow, ther raw, rt to explain how addition and subtraction of fixed
rerio Hipp Visto ando ZI 27 Hardware o Se, Dr omar explain how adn and subtraction of uo fica

is discarded, À Complement don op Point numbers can be done, Also draw a circuit using full address for the
it same (R.GPV, Dec. 2013)

‘Subtraction

46 Computer Architecture

Ans. The signed-magnit

upon the
listed in first column of te

Table 2.1 Addition and

every arithmetic calculations. I we
sce Gnd at there are eight different conditions to consider, den Así
sign of numbers, and the operation performed. These con Deng

fe 2

numbers are familiar because th
1d or subtract two num

N
nA

traction of Signed-magnitude Numb
n

$ Ada Subtract Magnitudes
rperation | Magnitudes

= When 4 > B | WhenA<B | When ar
A) CB) HA+B) 1
A) + (-B) HA-B) | -(B-A) HA
CA) (Br 4A-B) | +(B-A) a ol
(A) + €-B) (A+B) ) {A-B)
(AB) «a-B) | -@-a) E
A8) | «a+ B a AB)
(a GB) | (A+B)
(a) cm qua | kta | anny

stated as follows -

different, then fi

from A and make

the two magnitudes and a

the larger. Choose the sign
larger agninde han ober.
from A and make the sign of th

for different signs in the

gísters: Now. let A and B be

‘wo magnitudes and attach the sign of

from the iarget. choose the sign of the res
complement of the sign of À if A <B,

ch the si
B are identical, compare the magnitude.

subtraction al

Hardware Implementation —
writhmetie operations with hardw:

are that the tw
the two registers th

The algorithms for addition, subtraction derived from the table 2.1 cant

Addition Algorithm ~ When the signs of A and B are identical, add,
A to the result. When the si

est compar fag ha
compare magnitudes and subtract the sinaller munte
sult to be same as A ¡FAS B ort

iw
i o magnitudes are equal ractl
the sign of the result positive, a

ofA to the result the signs of A.
ud nd subiractihe smaller number fa
he result be same as the number which o
80 Majes are equal then subiractÉ
The two algorith one
rithms are similar exe,
oon ilar except for the sign comparison. TH
frien sein e addon grit soe?

lgorithm and vice versa,

ls necessa

cessary for implementing the 8
'0 numbers, be stored 1*
iat hold the magnitudes ©

“na

two flip-flops that hold the corresponding
‚red to a third register. A
A So. Nand A, form

and B, be the
ration may be transfer
It is transferred into A and

sand A,
result of the opeı
the res

‘he num
s. The ;
obtained if
nulator register

Jam of the hardware for implementing the
tions. It consists of registers A and B and sign

y adding A to the 2°s complement of
ced 10

2,9 shows a block

Fig
addition or subtract

n operation
Subtraction is done by

ny i ransferred 10. Mip-op E where it can be chos

itudes of two numbers,

flip-flops A, and
B. The output car
“obtain the relative magn!

A Wa) [rs
(ave) beds the overlo bit El
hen A and B are added, THE Eu
Mon of À plus B is done °F stat

1

Parallel Adder

through the parallel adder. The
S (sum) output thejadder is [E

Input Carey

given to theinput of the A 3
pies sopa o je 29 nr fr Signed Mide
PAL os ss Addition and Subtraction

upon the state of the mode
control M. The M signal is also applies
Os the output of B is transferred to the adder, the in]
‘output ofthe adderis equal tothe sum A +B. When M = 1, the I’s compl
fof B is applied to the adder, the input carry is 1, and output S = A+B +I
‘This is equal to subtraction À ~ B (i.e.. A + 2's complement of B= AB)

.d to input carry of the adder. When M
put carry is 0, and the
nent

Hardware Algorithm - Fig. 2.10 shows the flowchart for the hardware
algorithm, The two signs A, and B, are compared by an exclusive-OR gate. IF
the output of the gate is 1, the signs are different; if it is O, the signs are
identical, For a subtract operation different signs dictate that the magnitudes
be added. Foran add operation identical signs dictate the magnitudes be added.
Microoperation EA <A + B is used for adding the magnitudes, where EA isa
register that combines E and A. After addition, carry in E constitutes an overflow
if vis set to 1. The value of E is transferred into the AVF (add-overflow flip-
flop).

I the signs are different for an add operation or identical for subrract
itudes are subtracted

operation, the two magnitudes are subtracted. T
byadding A to the 2's complement of B. No overflow will take
cleared to 0. À 1 in E indicates that A 2 B and the number in A is the correct

place iFAVF is

1 cor rase

unt-n 4
nun ste deposito oi nee zn

zero. A in E indica AB. In this case, itis necessary to take ei signs are In O, and Boy respectively.
fe A ica 7 pin an bdne ih coon fe yap and
ect enn an tess ve mic ee tae

gh product willbe stored

‘When AB; the sign of the results the complement ofthe original sign Wincea double“

Ya registers À an

(4 Q, Registers A and E are ER

"is sot to a number equal 10 ARTEN

resul is obtained in register A and its sign in A,. The value in AVF provi Neared nd SC an ‘a Non
iles umber of bits o

: 2 si ‘the multiplier. Since an es
werflow indication. The final value of E is immaterial nd mast be sed il si the

‘ord will be occupied by the
will consist off

hen. it is necessary to complement A, to obtain the current sign, Th

ads Operation

den ine bit of w
‘and the magnitude
a Now, the Jower-order bit OF the

act Oper

ura tsa, no
meng uliplican in i
= = e e present partial product in A.
and Fes te rest
_ Añer that, register EAQ is shifted to right,
Ase, SLA ind gives new partial product and sequence
inde gsremented by one. This
moe o oun pete uni SC equal zero
E if SC = 0, them process stops, and the
IN orme Als shied it Q with
Fes 2 AA holding the most significant bits and Q Fig. 2.11 Flowchart of Multiply
me holding the least significant bits. Operation

0.17. Explain how multiplication of two ixed-point binary numbers
in sign magnitude representation Is carried out and give the hardware
implementation for multiplication.

Ans. Multiplication of two
done with paper and per

«ed-binary numbers in signed-magnitude is
cil by a process of successive shift and add operations,

=
ou mel

For example,
F210 ich go a à
-10 Flowchart for Addition and Subtraction Operatl an ulplier
IS Esplin sign-svagninie, 1 M3 perations ay
‘hele range foreighebireguem > MAS complement numbers wit 00000
Ans. Refer to Q.6, Q.7 and Q.14, (R.GRY., May 2018 ¡de a
2.16. Explain hardware algori 342 10010 Product
rithm for multiplication. Inthe example, if the multiplier bit is 1, the multiplicand is copied down,
Ans. Algorithm for mui _ otherwise zeros are copied down. The numbers copied down in successive

(RGRY, June 2003)

plicacn of ts , June 2005) ines are shifted of ber
sis esl \ ne position to the left from previous number. A!

ixed-point binary numbers are added and their sum forms the des If oth the re ‘he

shown in fig. 2.11
ig. 211. Inia, the map
the multiplier is à
plier is in Q and multplicand in B, an? Same sign, the sign of product is positive, else it is negative

y Arcteture

unit-1 St
process of multiplication, some chang,

rial compute. Firs, instead of peo O

for multiplying binary integers

ovides a method

a à are ps. Bo loa I de operates on the fact that strings of
many an ina number as he ae | 7 complement ent aon, apres Me Di
comsement fo provide an adder forthe suma "ene mtn require no addition A} anda wing

1 2% to weight 2” can be |
tion of the multiplier bits and shitting
added to the partial

1o

ively accumulate the partial produtos
instead of siting the mltipticand to the Je, the part

tothe right. which sets the partial product and the multi
relative positions. Third when the corresponding bit of tye

pam bit wei
Sing. the multplicand may b
ue or left unalired accord

mt un
grin ei
is 1 product. Before shifting. 4
4 fom the parón

ine pa
the maroduct, subtract’
ss Other ie need to addall zeros to the partial product, since it walt Spowing rules

on partial product dogs not change

when the multiplier bit is

C (Te para product ds
| enticalto te previous multiplier Bl a
== SG) van ena gant TT rios o Vs ine me
T mount mul is ado the partial product upon enews
EE ei us 1) in a string of 0's in the multiplie
ame Fe et pen inasinge10s tem
a craneo + Tis ogg Mes for bio positive or neptive multi WA
= | % mnlemeat representation, This is because a negative muliplir e a
zo Lac andthe last operation willbe a subtraction of the appropriate
3. ate QRegister ici
ann 72 Hardware for Mu Operation he hardwärempiementnion of Booth algorithm requires the register
Ne 212 shows the hardware ic iguration shown in 2.
ct ts plein of muliply per UE M shown in fig. 2.13
Tatty neon eng ends sin Q, The sequence coute, Ce Ce ]

equal to the num
ented by | after forming

is deere
content of the cour

r of bits inthe multiplet. 7
each partial produet, Af

ctreaches Tompienenerand
the mali zero, the products formes ara Adder On net
Sepa Gann me al Be ES
edo ne 0 FA register. Multiple à nA
"nieht. This shift will be iplier and partial prod a HH canter
a sath of oca el Ne by statement “Shr BAQ" a HI
ha fate Sted the nos signifi most signifcantposition of Fig. 2.13 Hardware for Booth Multiplication Algorithm
une hi ne bit of te paral mn OSI A, andOisshifid® Fig 2.14 shows the flowchart of Booth algorithm for multiplication of

bits one position to thee suet is shifted

the igh into Q, pushing signed-2's complement numbers. Register AC and appended bit Qs + ı are
nun Et intl cleared o 0 and SC is set to number of bis inthe multiplier (n). The

lain Booth’ go
ert Yor mp of mo sued pasoo Omi in Q and Q 1 are checked and ifthey are equa 10
ican a ean Olean that he rt in a ting of 0's as been encountered, Ifthe two
E Same 200, a ts are equal to 10, it means that the fist 1 inthe string of 1's has been
in detail Booth’ » encountered. First case requires the addition of the multiplicando the partial
ei re ar q ad Pin A En equi surco ofthe mula rm the
i im and its hard“ partial product in AC. When two bits are equal the partial product does not
Esplin Bon arm wig ©" GRE, June 20 Change. Since the addition and subration ofthe mulipicand follow each
pt, Dee, 101 Sr over cannot occur. The next step is to shift right the partial product

RG.

Describe i
implementation

$2 Compute Arniectire

Matty

tipica a BR
aile a OR

ac to
Grete
seen

ACC ACHE

ACC ACER

unit= 53

roduc ato et yors ean be done with one microoperation by
dar at once, This is a fast
Rs

Ir
Ll

PRES

Fig. 214 Flowehart for Booth

and the epi. This is an ri
fs AC und QR tothe right and leav

a ur 1d leaves the sign biLinAC unchanged.

Of Booth algorithm for

decremen

AT

os

RACE QR)
scesc.
330 =
End

Multiplication Algorithm

metic shift right (asht) operation wt

iedntimes. Fig 2.15 shows a numerical exar
Shows the step-by-step multiplication oft

Saben.
me

EU “ST à

a ye

hh
Fig. 2.16 2-it by 2-bit Array Multiplier

Consider the multiplication of two 2-bit numbers as shown in fig, 2.16
‘The multiplicand bits are xy and xp, the multiplier bits are ÿ and yp, and the
product is 732922 First partial product is formed by multiplying yo by x1%
‘The multiplication of two bits such as yo and xp produces a 1 if both yo and xo
bits are 1, else it produces O. Since itis identicalto an AND operation, thus it
can be implemented with an AND gate, The first partial product is formed by
two AND gates, Second partial product is formed by multiplying yi, by xy Xo
and is shifled one position to the left. These two partial products are added
withthe help of two half adder (HA). Generally, there are more bits in the
paral products and it will be necessary to use full-adders to produce the sum
In this process, the least significant bit of product does not go through an
adder since its formed by the output ofthe first AND gate.

‘A combinational circuit binary multiplier with more bits can be constructed.
Abit of multiplier is ANDEd with al bit of multiplicand in as many levels as
there are bits in the multiplier. Output in each level of AND gates is added in
parallel with the partial product of the previous level to form a new partial
product, At the last level AND gates produce the product. For j multiplier bits

and kmultiplicand bits, we require jx k AND gates and (j~ 1) k-bit address to
produce the product of j + k bts.

1 do

54 Computer Architecture

(420, Design an array multiplier that multiplies two 4.

Use AND gates and binary adders. RGP
Or
and explain the circuit diagram of 4-bit by.

Draw

Ans. We consider a multiplier circuit hat multiplies a bi de
ou bis with a number ofthree bis. Let (he multiplicand be represas
bb andthe multiplier by 38% Since k= 4 and j = 3, we need ias
gates and two 4-bit adders to produce a product of seven bits, Fig
shows the lo; am of this multiplier. ig:

Vis set and the op
vero

Unit 55
un divide overflow Mip-lep
vurely. JA < B no divide
2d by adding B 10 A

id stored in A. IF A 2 B, the
‚tion is terminated premal
dividend is restore

pits of the div

cecurs so the value of

piste operation

vide Magnituder

E MERO
A COTA CARA
spel el] ty
Ú E Act
Added = Tyree
ait Adee ae
Sam and Output Carry
DE
ied Rad
csi der
Sam aed Ostpt Car
eh et
Pi. 217 +84 by si My pig =
by bi Array Mallo Fig. 2.18 Flowchart of Division Operation

0.21. Draw the fowch
bina mann a flowchart and explain how division mo fice pe
merde renom enr
GP, I 2
Le x Y, June 2004, 2
and explain the Roweharı for hardware aid

re divide operation.

(RGP, Dec. 20

e di

Ans. Fig. 2.18 shows th
shows the fk
is in Band dividend in A and
Part of quotient, SC
quotient, Since
Will be occ

‘occupied by the
divide overflow condition

The division of given magnitudes starts by shifting the dividend in AQ to
the left with the high-order bit shifted into E. Ifthe shifted bit into E is 1, we
know that EA > B because EA consists of a 1 followed by n — 1 bits while B
consists of only n= 1 bits. Thus, B must be subtracted from EA and I inserted
into the Q, for the quotient bit. Because register A is missing the high
bitofthe dividend, its value is EA 21. Adding to this value, the 2’s complement
of B results in

(Ar

1) 4Q8-1-B)= EA-B

If we want E to remain a 1, then the carry from this addition is not

transferred to E. If the shif-left operation inserts a 0 into E, the divisor is

56 Computer Architecture
+s complement value and the carry jg

subtracted by adding its 2
; therefore Q, is set to |

io ETRE, st means that A 2 B
je ies that A<Band he original number is restored by adding 5 4
ae eave 40 in Qu This process is repeated again with ys
the partial remainder. Áfcr times, the quotient m
nainder is achieved in register A.

Vu
1

ane
sa
inner ande
aime died

(022 Eolien hardware nd flowchart for dion a
of two feed point binary numbers in signed magnitude repres nist |
D de dde ee enon an

Or
Explain he algrti for division of signed magni

manta lg ‘fo sion of signed magnitude data, Wy,
e sra Ter rimplening don
sonar Eros amen sc
seh i212 Reser EAQ ino Saf ih O isn
Quite press ot Tenumealeumplein ie 219ehs
se ypc, The dor tre inte Bester and the do
x dues ringe Aan The dividend shied ot
aa dir br dis? scompemen ake Theis
sorte apni aiilin TE ins iat
ken edi an par ean shies o
ol Eso, it signifies that A < B so the quotient it
Thea fst alo ste e ur
rt ie he pleased aie ro
int bits are formed, Liste that whl

remade
eosin and en

se
ao a

tr Shisot Ay

Me TS
UML, Da bat ete
a o ing

Un M Mac enter

Sein Rae severe gn vet
Het, SN an te ete 1100

oder < D:

So a

Fig. 2.19 Example of Binay
Flowchart for Division Algoı

entering

Dh
"> Division with Digital Hardware
rithm ~ Refer (0 Q.21.

die o
Le
epphan or equal 10 the
"Brite sg, er that a dh
and sig of the remainder in A, i the same, ser hem or

"e detected when a
{pan be DV

unit- 57

ice as long as the divisor. the

mes pros overflow condition

bide ero Ma a allows ANE ett
A igh-order half bits of the aio beta edo re

à division Di

NUMERICAL PROBLEMS

Q and SC during the

sisters A, Es
(multiplicand) and

sed, Shen tat contents le
sip ‘of two binary numbers LIT

(RGR, June process of mulipeation num
a 101 (multiplier) included.

The signsiare not i

‘Sot Ta shows the procedure of multilealon.

Table 2.2

ipheand B= 1111 LE A o [sc
Mullplier in | 00000 | 10101] 101
¡Qu *h add B wi
First partial product o | mu
Shin right FAQ o | om | noi! 100
{Qn =0:shif right FAQ o | oo | itor} on
Qu= Had B jui
“Third partial product 1 | one

Shin richt EAQ o | on | one | 010
Qu = 0: shift right EAQ o | or001 | rom] 001
Qq= Hada B unt

Fifth partial product ı | Deo

Shift right EAQ o | von | oror | 000
Final product in AQ = 1010001011

Prob.S. Multiply (- 710 with Go by using Booth multiplication.
Give the flow table of the multiplication.
Sol. The step-by-step multiplication process using Booth’s
the given numbers is shown in table 2.3. Here,
BR = 11001 (-7) {2°s complement}
BR+1=00111
QR= 00011

algorithm for

Unit- 1 59

Table 2.3 rithm
«able 24 Multiplication of 6) * (4) with Booth Algorith
f ae EA wc | or BR = 11010 AC OR | Qu | SC
O en | Den | BR + 1= 00110
| intially ‘90000 | 00011 a oo | ooo | © | 10
1] 0 | Sabwact BR} 00111 ashr 00000 | omıo | 0 | 100
| vom ake ‘0000 [00001 | o | on
00011 | 10001 subtract BR Ht
ry ashe 00001 | 11000 sr domo | 00000 | 1 | oro
opa Add BR 11001 AR 11010
nom 11101
ash 11101 | 01100 asht oz] 10000 | o | 001
ojo at uno | 10110 ashe um | 01000 | o | om
ojo ashr m | oon 24)
EN resi the ropbstep muliplication process using Bann

cd nati.
i ert e ¡ne following binary numbers are multi?
Probá. Draw the required register confl algorithm Mie, he fol

iplic d register configuration to carry ı s.pig register that hold signed numbers — ,
rutin nig Bots maple arin a Jen A ES UD (819 «€ 19. (RAR: June 2009
Sr Me nendı.sp mitipicaion proces using Booth algorithm for

Sol, The required e the given binary numbers are shown below

ster configuration to carry out multiplication 4

‘Booth algorithm is given below ~ i) (+ 15) * (+ 13) = + 195 = (0011000011);
BR-O1111 ¢+ 15)
BR Reger Sue Conner BR + 1 = 10001 15)
so) OR = 01101 (+ 13)
Table 25
Tangier BR = nm ; asp
CE ACER RER | One| se
ital om ON ET
9 as 1 | 0 | Subtract BR 10001
= LT toon
Sy rey ashr am | somo | 1 | 100
er o| 1 [aan out
ont
Fig. 2.20 i a ashr 00011 | Hol o on
Multiplication of (6 Subtract BR 10001
24, °F 6) and (4) using Booth algorithm is given in 1 A Tom,
re ven in ashe moro | ono: | 1 | oro
Her, BR = 11010 (-6) fin 2% 1] 0 | ashe mor | coro} 1 | oor
+ 2 complement) of 1 [Kor mt
00110 . 1100
00100 (+. ahr como | ooo | 0 | 000
100 (+4) TS

60 Computor Architecture ancl Gt

‘ O111101)2% co
(in 159 € 1) = 195 = (10 mplemen plication of 5 + (- with Booth Algorithm
R= OUI (15) Tate 27 Magen Qt ET
5) sles : si
Qù = 10011 6-13) E Tan | aa | ac | er | Om | 5
Table 2.6 Lee Pas 000 Toro 0 TOT
= a ashr 00000 |onon | 0 | 100 |
es [ers ee ac Der Tas Tool | canoe | non | po
Bis 0001 lo A |
i Tit Goo | toon | 6 = no à pon]
1 | 0 nent 10001 el à acabe — |_00101 |
THOT o y
air 11000 | 11001 | 1 | ag oo0on | oir | 0 | oo
fu fat ano | onoo| 1 nio subBR |) LN
of 1 | aaor ou T1100 | |
on | ashe ho | oo 1 | oot
ashe oo | 1omo | o [a ashi au [ooo | 1 | 000}
ol 0 fas wo | to | o 5 of multiplication using Booth method.
Prob. Explain the process of multi
1] 0 | Subtract BR 10001 jolve - 5x2 Booth method. (R.GPV, May 2018)
; 10011 ‘Sol Mottipliation using Booth Method - Refer to Q.18.
a moot Vino | à | om "SES o 010
Pe x MOT >, ale 0
rob, Explain Booth's multiplication algori La TO
jun i tion algorithm. Show th a
tp malpcaon proces using Boo algorithm to mally thé 0000000
5) and (-13) in Binary. eel “efi 00001 0 x *«
Sol. Booth’s Multiplicti A AGP Vg Bec. 111 1 0 x xx
alt Apr = Rees 8, AAA co
mine Prob. Using 8 is 25 complement integer, show how t perform the
sable fo ot algorithm for multiplications Give the faction operation 18 — 16. (R.GPY, June 2017)
bl for register contents used in implemenling ponen Give the So Binary representation of given integer are following hi
rt used in implementing Boone algorlıhm fort SP Binary ion of given integer are following here
konn So (18) - 00010010
Sol. Boots Algorithms — Rete 19 “GBP Dec. 2 (1), - 00010000
Now, multiplication of 5 + Gis Using 2's complement notation to transform 18 — 16 into 18 + (- 16).
lable 27. shows te sep o BN GEN algorithm is shows Pin number 16 is converted into 2's complement
the multiplier in QR is negative end ge HOES x ( 6) 00010000

10-bit product appe

sit 'e multiplicand in BR is E
isthe originals eA and OR and ind in BR is positive. Î

bitoFthe multiple... "Eve. The final value of Qr

Here,
BR= 00101 (+. 18
BR+i= 11 ve 2's Complement
01-5) of 16
QR=

11010 (- 6 pr
sa
complement} Ai:

62 Computer Architecture Unt- 63

Ke, Dec. 2015)

(E POINT REPRESEI = i y it and why we use it? (Re
¿NTATION, FLOAT = y What is the parity-bit and why it
FLOATING PON ETT METI STING Boy 7 ana bi called a parity bis added to cach data word, Te
us N ie tear oreo oe oma te
ir ic "mal Fede (odd party). When a single error or an odd number
Tapia aig po representation With example, e (ven po) rd CR re code word chan
GE, Das, for oc DE AREA atthe resiving end and violation of the
“an Na epi oan ts posible o represent range gary of he code Word AES RAR DER te
cnc By sina xed binary raged pasty He mete rs
e he representation of numbers wih a fractional compo:
el. Bu this approach has limitations such as very large numbers cam bers ?
nek sented nor an very smal factions. Also, the nctional part of the qu Y 1928 PO a
1 division could be los. By using scientific notation, one gets ike ns. A fraction with 4 nonzcto, 5 diia sid be somal ir a
en ba prod 436 © 1010 an Normalized numbers are gery Pr nrmlized
SOUS con be reel 456 % 10" In above reghere is only one noxmalized Für, whereas there are Any a
seu lie decimal point toa convenient cation and use the exp.
¡Ooh that deck pene Many hghlevelprogammine ee, A foalng-otaenumber Wpormalized when the most grifos digit of
have fying floating point numbers. The general way to gehe mantissaismonzerö. Regardless of where the position of the radix point is
u floating-point number is real declaration which is in contrast with fassumed 10 be in the mantissa, the number is normalized only if its leftmost
pein number which re specified by an integer declaration statement. dig ze: For instance, the 8-bit number 00110110 in binary form eno
„Frag point number ina computer register consists of two fieänomalizdbecauseafthe o leading 0's. By shifting the number two positions
stds ale i) Sandanespanent E. Teo par lo tad carding te ding Oso oh 101 00, bo
sained from multiplying S times a radix B raised to Ihe valve benorinalized. The two shifts multiple the number through 4 (27). The exponent
ds
or must De subtracted by 2 0 achieve the same value for flotin

in the code word.

35. What is mean by normalization ? Why do we do normalisation

‚point number.
The base Bis implicit and ne For floating-point number, normalized numbers provide the maximum possible
cunts aie Bis plc and need not be stored because iis the\sameopretision. A zero cannot be normalized because it does not have a none

21 shonsa pia ti aie
SRE Doi ati ar ED ly prod Rai poi hy a ir he mats ad

Stones à pp
pao y e Ÿ | oint representation isa must for scientific computations because
io = e scaling problems involved with fixed-point computations. Although,
- ina Jarithmetic operations with floating-point numbers are more difficult than
snow gum Format arithmeli operations with fixed-point numbers and their execution takes longer
Sol "ME mare complex hardware

EN us 0.26. What are basic operations of floating-point arithmetic ? Explain.
041100012" wo a e Ans, Arithmetic operations with floating-point numbers are more

M1 11000 18000000e00eoda00 compli y 4

ETES

ted than with fixed-point numbers and their execution takes longer
and requires more complex hardware. In addition or subtraction itis
Recessary to ensure that both operands have the same exponent value, Thos,

‘alignment of the radix points is required before adding or subtracting the

mantissas. Table 2.8 summurizes the basic operations for floa
> rates the basic operations for floating-point

=1 61101011 soro0o100000000
ep noc

94 Computer Architecture
‘Table 2.8 Floating-point
Arithmetic Operations

Arithmetic Operations

Floating-point Numbers

xr Be +Y,)x 8%

200

Y 2
K+Y= (03 x 1022 40.2) x 10% = 0.23 x 103 = 25

X-Y= (03 x 1023-02) x 103 = (0.17) x 109 =
NY 0.06 x 105 = 6000
X-Y= ( LS «10! = 015

Considering the sum othe following Noating point numbers
‚8372400 x 102
+ „1580000 x 101
An above example its necessary thatthe two exponents are equi:
rats can be aed. We can either shif the fist number three posi
or shift the second number three positions to right. When the mantisse
El in register, shifting to the left causes a loss of most significant dí
ig he ight assassin gis, Fis method 9°
an error while the second method only reduces the accuracy, Thus; the 5%
need is preferable. Multiplication and division are more! ¡straight forwars
Problems arised as the result of these operations arc given below

un 9 Strifcan Under In theprocess of aligning signifi”
dis fon off the right end ofthe sgificand, Thus, some form of ru
(i) Significand Overfiow S
same sign may result in a can out of

fixed by realignment. is

{ily Esponent Overfow- A,

ssible exponer Les

Possible exponent vals. In some syst
he minal” Esponen Under.
the minimum possible exponent val
small 10 be represented and it may

The addition of two significands o!
f the most significant bit. This €”

exponent exceeds tne mani”
is may be designated as + 0)
Anegatve exponent means itis le

le. This means that the number
be reported as 0,

27. Explain it
sabracion 5

A
(operation, the tw
by the ALU.
the process
operatic

ce

von Next if either operand is Zeroy

unit 65

the addition and

withthe hep of flomchers how
Jody Le PV, June 2004)

out of floating-point numbers. (Ri
Or

carried

‚n and subtraction of float

and explain flowchart for addit

ee x u herz (R.GPV. June 2005, 2012)
ee NY) oi MBC psp slit rando
Ais Heck for zeros (ii) Align the mantissas
a {iv) Normalize the result.

O. Add or subiract the mantissás

A hat is shown in fig222. For the addition or subtraction

al ow operands must be transferred lo register thal will be use

ca e or subırction ae identical except fora sign change o

by changing the sign of subtrahend, if it isa subtrac
i the other is reported as result

pics

Monti
dios

Fig. 2.22 Addition and Subtraction of Floating-point Numbers

66 Computer Architecture

et phase ise manipolte he numbers that The WO expo
my beacon ying iter the smaller mg
Sa shin te larger number tothe le, Because ether y
‘asl an the loss of digits, it i the smaller number that is shifted;
hate lost are therefore of anal significance Aliments
neh magnitude portion of significan right | digit and incre
the exponent unt the 10
sre te the sigificand, then the other number is reported as resul,

Next the two significands are added together, taking into accoum ÿ

Msg die the result may be zero. Also there i possibility of sig
‘exponent is incremented. The exponent overflow could occur as a res,
Gould be reported andthe operation halted. Next phase normalizes th
Normalization consists of shifting significant digit is non zero. Each shift
a decrement of exponent and thus cause an exponent underflow. At the
the result may be rounded oft and then report

Pera

ch

0.28. Explain the multiplication and division algorithms for flows
Point numbers with their respective flowcharts

Ans. Mukipliation and division in floating-point arithmetic are n
simpler than addition and subtraction

Floating-point Multiplication — A flowchart for multiplication of:
floating-point numbers is shown in fig 2.

ET]
er

Report
Orca

Report
Undertion

a
[Senden

2.23 Floating-poir Zr
ating point Multiplication (Z Xx Y)

exponents are equal. If this process gives

ma or
The multiplication algorithm can be subdivided into four parts —
mec er zeros i) Ade exponent
ply te mans (1) Normalize the rods
. reported as th rel The ext se
rer operands 0,0 is report ose
Fir fl ens. ey a stored in ised fom the exponen au
i add D ie bis, Ths, the Bis value must be subtracted oy
sold ha est of operation could be either an exponent overflow or
don TH op would reported ending the algorithm.
le exponent of the products within the Proper range the next step is
cda The muipfeen is peromed he same 03
per, yeae dela wih snag
nd wil be double the length of the mutes and
reer og ground Arte prise
einai and r0Unded
nain pont Division =
Me 22.

‘The flowchart for division is depicted in

Aad
Bias

Ye ae
vertan

Report
nderflow

lg. 2.24 Floating-point Division (Z <= X)

The algorithm is subdivided into five parts ~
(Check for zeros. (i) Initialize registers and
iy Align the dividend, (iv) Subtract the exponents.
(9) Divide the mantissa.

aluate the sign.

unit 69
or)

65 Computer Ara

y fist step is testing for

0. f the divisor is zero, an q,
et to infinity. A dividend of O, results in y "à sail
1 infinity: O, results in g | gar. Explain th

hardwired control unit in detail. (RGP. Dec. 2

i dep, he divisor exponent is subtracted from the dividend exp! Or
" 7 Or
divided asin fixe pr and eplai sica hardwired control uni. (Ke GB, Dec. 2015)

0.29. Hove is multiplication of floating-point number achie,

(R.GBV, June 4, design of hardwired control unit.

rite in detail about the
(R.GPV, Dec. 2017)

Ans. Refer 10 Q.
‘ans. When the control signals are generated by hardware using

NUMERICAL PROBLEMS conventional logic design techniques th jontrol unit is said to be hardwired.
A diagram of hardwired contro! units shown in fi 2.25. This control
Prob.12. Represent the number (+ 46.5);9 as a floating poin prit may De based on the use of a.counter driven by a clock signal, CLI

a 2 ie a normale fection want has 16 bie pie enices consol FSS et determined by the following

Lilien (RGRV, Dec. 2007, June ¿y miormaion=
| (i) Contents ofithe control counter

di) Contents of the instruction register
(i) Contents of the condition code and other status flags.
‚als representing the state of various

‚Sal The binary equivalent of (46,519 is calculated as follows —

By status flagsywe mean the sigs
tions of the CPU and various control lines connected to it

CLK [Contr sep
Que ‘Counter

ies]

46=101110
oot Status
ea : =
„Te mat ros mania fas 16 Bnd he expone: : er
b1011 1010000
110111 01000000
pee titrant 011 pa
some bit exponent Fig. 225 Control Unit Organization

nen

un dr win some ng to sts of anal wi, we

ROAD sequence | i start by giving a simplified view of the hardware involved, The decoder-
à encoder blo > i it which

2 hati men by hate mn, since lock in fig 2.25 sa combinational cit which produce the

seth stl spas Ol? RGR, Dec, re control outputs, depending onthe stat ofall its inputs. By separating

logic design techniques ate generated by hardy © decoding and encoding functions, we obtain the more detailed. block

the conta unt said a gi on est" gr a Be 2

70 Computer Architecture

Control Sep
Counter

7] Condition
Codes

2 | encoder
peer |

Crees
Fig, 226 Separation ofthe Decoding and Encoding Function
Tue step decoder provides separate signal ine foreach step ot
inte contol squene. Likewise, the ouput of
Ariston decoder has separate ine foreach
main insmucon. casar any insruction
loadin he IR, on ofthe output ines INS, 10
INS set and al other ines are et 10
AN np signal tothe encoder bock in ig,
2.26 should becombized to generate the individual
conto! signals Vg, PCa. Add, End and so on
Structure of the encoder à exemplified by the
iit shown F227, a implement logis
Zn = Ti + TÇADD + TBR N
A means that he con
turn on during time lt,
sinon, and soon. This pon

ano BR

Zia
Figo 2.27 Generatiot
the Zn Control Sie

'gnal Zu, that enables the input to register
for all instructions, during T for an X
of the Z;, function has been compiled &
takes place during the fetch Phase. Likewise, 5 ar N

End

the End control signal,

MADD STEBR + TN TARA +

I Sara

Sock diagram.

+ gpical microprogrammed control unit

Umit 71
the End signal can be used to start a new instruct

2.28 shows One control step counter to its starting

by resetting the

CT

2.28 Generation of the End Control Signal

‚med control unit with
(R.GPV, Dec. 2008)

Fig.
0.32. Explain different sections of microprogran
Or

With the help of a neat diagram and example, explain the working of

(R.GRV, June 2009)
Or

With the help of block diagram,
sroprogrammed,control unit.

describe the organization of a
(R.GPV, Dec. 201)

Or

wn esplin union microprogram control ui block dagram.
=. ns ds (R.GPV,, Dec. 2012)

‘Ans, The block diagram of a typical microprogrammed control unit is

shown in fig. 2.29.

Reset

f

SE
Lords e

Control Memory (CM)

Miceoprogram

ranch] Conta | Control Memo
Canon) Ken | Kanon | Da Biter”
ome Field Field (CMDB)

<n

Contra Susto
Fig. 2.29 Block Diagram of Microprogrammed Control Unit
A summary of the use of various components included in this organization

24s given below —

… (Control Memory Buffer Register (CMBR) - Control memory
er register functions the same as the memory buffer register of the main

72 Computer Architecture
isa latch, and serves

unit = 7:

asa buffer for the microjn,

sd in microprogrammed

cory, Typically, each microinstruc: er, á dea
eve from the control memory TYP! Iruction y, Jain various branching techniques use ed
tes À ess Ee one 2007
= ara rm
ei "ns. A variety ofapproaches have been taken for dealing with conditional
| "Selen. es -
5 ei i er tultipte Streams — A simple pipeline suffers a ty for a
sn condon selected chose the extemal condition 1 be y O Mm goce tm imo apie ions to ch

She output ofthe multiplexer (MUX) is connected o the load inpu os,

Hi ton
O mer MPC. he mieroprogram counter (MPC) wil ba er,

low the pipeline to fetch both instr
Paso streams. There afe two problems with this approach

as ofthe pipeline an

micro x ing use of

pci in he branch address field of the mieroins oo e a) ‘with mllplepipelins thereare contention delays For acess:
e lea condon is false, then mieroprogram coun, ie regir and lo MEMO

point he net milan 1 bo exeeuted. So this rangement ge ‘oy ‘Additional bach insfctions may enter the pipeline before

Conditional branching. The contol function field of the mieroinstrucin CP cision iresolved ach such instruction needs an additional
hold the control information in an encoded form. he orignal bra

(ii) Microprogram Counter (MPC) — The microprogram (ii) Prefetchi Branch Target ~
(cyte teres of the next eoinaruction tobe executed gos TI) ol ran DT

itis loaded from an external source to point to the start ovine the branch This target is then saved un
E he starting address A ÓN is taken, the target has already been prefetched

i) Eo Buffer - Aloop-bufferisa small, very-high-speed memory
ind containing the n

When a conditional branch is
ched, in addition to the instruction
the branch instruction is

microprogram to be executed, From then on, Ihe microprogram counter 1%
is incremented after each instruction fetch, andthe instruction fetched is
tothe Son memary buffer register (CMBR, If branch arcs by he struction fetch. stags of et

‘encountered, then the microprogram counter (MPC) will be ue most recenly fetched instructions, in sequence. [a branch Is 0 be taken, the
ro loaded Wh ware first checks whether the branch target is within the buffer. Iso,

contents ofthe branch address field of the microinstruction that is held A
control memory buffer register (CMBR). ruction that is held instruction is fetched from the buffer.

hi) External Condit a (iv) Branch Prediction - Various techniques can be used to pred
nal ds se don Select AUX = This MUX ehooseS)ewhether a branch will be taken. Among the more common are the following
area condos gering be contents off cog 6) Predict never taken
Bote nn ts gir specified (b) Predict always taken
en fam, An enon Ind sho iria, thai (e) Predict by opcode

1e cost is reduced. (d) Taken/not taken switch
(e) Branch history table.

‘The first three approaches are static. They do not depend on the execution
„history up to the time of the conditional branch instruction. The later two

Ans, Refer to Q38 and Q.32. (R.GPY, June approaches are dynamic. They depend on the execution history.

0.34. Discuss in brief mi ‘The first two approaches are the simplest. These either always assume
ani A nc ae a menge,
(R.GPV, June 2005, ‘Hor they always assume that the branch will be taken and always fetch from the

eo? et ee understand by microprogrammed control ? ES
of microprogrammed control organization.

Explain hardwired, mlcroprogrem [bos
pprogrammed control unit sg, Ti inal static approach makes the decision based onthe opcode of he
Ans: Refer to Q32 and Q31 (RGB, June branch instruction. The processor assumes that the branch will be taken for

Certain branch opcodes and not for others,

74 Computer Architecture Unt- 1 75

Dynamic branch strategies ater
qe Maty of conditional branch instructions in a prop Sequence

to improve the accurae
pire fmicrooperation. The main advantage of microprogrammed control
i ‘once the hardwired configuration is established, there should

ding Ow more bits can be associated with each cond es ae fact that
aa that riet the recent history of the instruction, aN ed rte aa WHERE :
refered to as a taken/not taken switch that directs the processor hy it Possible to have a Hardwired Control Associated with a Control
‘raniculr decision the next time the instruction is encountered, ne Hndeired one, by definition, does not contain conte MEE
0) Delayed Branch is posibleto improve pipeline per avg fared Conlon Mp rane ®
y automatically rearranging instructions within a program fim Gy The principal advantages of the! Use of mictoproet

) I's both cheaper and losserror prone to implement
for

(23h. Belen the dienen beneen hatred control ang | i) A bardwived control gpg comin comple sie
op mme como, 1 le pasible to have a hardvired control anequencng trough (he madmierößgeftionh ofthe Iran cycle
with a control memory ? Write in short. = 19) The decoders und sequencing logie unit of a microprogrammed
(RGN, Dec. 2004, May/June 2006, Dec ¡ono! unit are very simple pieces of EE
or EN advantages of Hardwired and Microprogrammed Control —
Digerniae beween bardived control unit and microprogney, 0) The pricipal disyantaes ofa mieroprogrammed aná, as
Cates (R.GRV, June 2005 il be somewhat slower than a hardwired unit of comparable technology.
ne or A e oprogramming is the dominant technique for implementing
raise ariel ed megane conto! uns hin io tores IC ds ed DH RR,
certs and demerits. GEV. Tunes A RISC processor, with their simpler instruction format, typically
ordre comet wad Oh de se hardwired control units.
set oa ak faster than microprogrammed control M, 0%), The microprogrammed approach in greater detail.

2 = (R.GPV, Dec. 2013, Juned, 0.37. What is the need of a control unit in a computer ? What is
fferentate hardwired and mi Wärdiired control unit ? What are its advantages and disadvantages ?
mer end denen acd and mieroprogrammed contr! uni, En = Ss

ch of them, (R.GRY, Dec. 2010)
Ans Different (RGPY, June} 3 wi
ee lem Ans, Need of a Control Unit in a Computer ~ The control unit is used

Hardwired Control and Mic
ate two major types of cool pal Microprogral''to control system operations by routing the selected data items to the selected
M0 Meere (à los zation = processing hardware at the right time. The responsibility of a control unit is
Have content TOO COL to drive the associated processing hardware by generating a set of signals
et named tins sb sisi witha master loc, Thi synchron sabios
is more advanageou as comport implement control Topic, Hardwired oe time reference for system analysis and design.

(ol logis plane RCE Hardwired Control Unit - Refer to Q.31
Advantages and Disadvantages — Refer to Q.36.

0.38. Whatis microprogramming and microprogrammed control unit?
(RGB, Dec. 2014)

Y an Miro a men of contol ni ein in which the
ds ithe sgn x gen nal sein and sequencing informo stored in a ROM or
e demonio RAM al acom! mem The cota sigas tb ave at any ine
cana ene orton en amon 18,3 rise, tat ed rom cetro memory in
og nformato RG he same vayan instruction i fetched from main memory. In aio,

Computer Arentactore

setioncxplicidyorimplicily specifies the next micro
the necessary information for mign

he used, thereby providing

Micropre alleredrelatvely easily y altering the conten

eer has nieroprogramming yields contol units which
than ht e col memory nd ls access cree
fi ee
Mol tctione fonconttol memory: These disadvantages have disco
the use of microprogremming in RISCs and other high-speed pro
her chiparea and circuit delay must both be minimized. Microproge:
es o be used in such CISC as the Pentium and 680 x 0.
A control unit whose binary contol variables are stored in y
called a microprogrammed control unit mene

0.39. Draw the functional block diagram of control unit of,
‘computer, (R.GPV, June}

Ans. Fig. 2.30 shows the functional block diagram of the control
rn

Instruction Register IR)

Li HT + r 110
EN ther tps
CEE wi
THT 5
TA ce
NN Dame

Increment UN
ment INR)
Gear

Gee

More

hardwired counterparts. This Dexibilüy is obtained at yo oun

Unt-n 7

coer ae represent BY the symbols D thigh Dy. The subse
st ne
fe imtrctión is shied to Mio denotd bythe symbol
code. Bit § e applied to the control logic gates. The 4-it sequence
Bits 0 howe nbiary fom O through 15. The spas ofthe counter are
6 timing signals To rough T's.

ans (SC) can be incremented or cleared synchronously
counter is incremented to provide he sequence of timing
Tecoder, Ones in a while, the counter is cleared 0.

decoded int

Sequence €
Most of the time,
signals out of 4 * 16 d

% Sang the next active timing signal 10 be To,

0.40. Write short note'on control memory.
(R.GRY, Dec. 2012, May 2018)
Or
Explain the term control memory
(R.GRY, June 2008, Dec. 2008, June 2011)
_AnsoAfiemory that is part of a control unit is referred i as a control
memory, The control memory isa concise description ofthe complete operation
‘ane control unit It defines the sequence of microoperations to be performed
during eachjeyele, and it specifies the sequencing of these cycles.

Qui. Explain the term pipeline register. (R.GPV, Dec. 2007)

‘Ans, The control data register holds the present microinstruction while
the next address is computed and read from memory. The data register is
Sometimes called pipeline register.

0.42. Explain the term control address register. (RGP, June 2011)

Ans. The control memory address register specifies the address of the
ricroinstrction and the control data register holds the microinstruction read
from memory. The microinstruction contains a control word that specifies one
‘or more microoperations for the data processor.

0.43, Define microinstruction.
(RGP, June 2004, Dec. 2008, 2009, June 2012)
or
Explain the term microinstruction. (R.GP, Dec. 2007, June 2011)
Ans, Each word in control memory contains within ita microinstruction.
The microinstruction specifies one or more microoperations for the system.

0.44. Describe a ypical microinstruction format. What are the considerations
in the design of a microinstruction format ? (R.GPV, June 2002)
Or

Write short note on microinstruction format.
(RGRY., Dec. 2006, June 2008)

78 Computer Architecture

nen 70
or
ieroinstruetion Fields
What is microinstruction format ? Explain differ, «able 29 Binary Code and Symbols for Microfatruet :
microinstruction. mann. DIE PONT Tr] [Fi [open | Sr]
or 1 pe E {nor
Explain in detail various fields of microinstruction Sor, [00 | came |ao | Jo ACEACHDR [ADD
A a. “lg | ACEACHDR | A À |
mul GPK, Dec à 001 ac 0 | carac | ow} acco CuRAC |
Ars Fig 231 shows te merinstucton code format for iy. | 010/ACHO 5 laincac | Jam ac«-aczı HINCAC
memory. The 20 bits of te mierinstrction are divided into four gy 011 | AC AC + | peragt ihe, ACE DR DRTAC |
parts = he tre Geld Fl, F2 and P3 specify mierooperation [10 | ACH DR Bee 4 NE oi |prrar
computer the CD field chooses status bit conditions: the BR fields | 01 | AR DRO-10)| DI Dice PERAR |
the type of branch to be used; and the AD field contains 7 FCTAR: |

a branch a4 | 110 | AR + PC
The address field is seven bits wide because the control men MARI DR.
128 = 27 words. =

Ware | [111 | Marie DR RITE |

vun a
=p Condition | Symbol [Comments
E IES DE | 2 7 175 | Microoperation [Symbol | [CD Condition T5 er |
ejeje [2 ater Ber on ai] o (ade
mac ncopr|xor || | brane
AS: Mkreperato Hels | ac x |,
E Cin Branch o10| Ace2Ac com lor [oras | sente
os Sign bit of
AD Ado Pa orlacesirac > [sHL leas | s Pe |
ic 100|AC«shrAC |shr |}10 [AC(S lac
Fig. 231 Microinstruction Code Format MR [cre Ae se |
Microoperation IN as ie
cache raise avi] ino tre fields of bre eat 110! PC AR ARTPC nac |
se Tne na SE Be even dint mirogpetns wb 1 noc
microinstructi $3 Bives total of 21

RSR
'Perations are used, oné or : ame 7 erm
ra CAR © ADI condi
Each microopeaton ig

FRS AR à con
re À é ” CAR + CAR + lit if condition = 1
designate the Source register, hi,

fe letters, First two let >, if condition = 0
the thi d CAR CAR + Lif com 1
Vers designate he destination eg, et IMSS à T and the at? 10 [RET [CAR < SBR(Return from subroutine) |
The CD

60 |
Id consists of two bi lu [map |CAR(@—5)< DRU1-14). CARLO) 0 |
domos which ee sed ine nodo to speciy ours | a

ion register

in table 2,9, ic 1
tata references Da tal First condition is always a | 5. Define microprogram.

used in conjunction with?

» Explain the term microprogram. — (R.GRY, Dec. 2007, June 2011)
"ext microinstruction as si

Ans. A sequence of microinstructions constitutes a microprogram,

20 Computer Architecture

Unit- 8

0.46, Def (R.GPY, June 2004, Dec. 2008, 2009, yyy, Draw and explain the micropros ee
hol "ration. pe

peter Fe De Write a brief note on microprogram sequencer, (R.GRV, J 2

‚Ans. is same as microprogram.

À arr sequence hears selon pr of he
is immed control unit. The purpose of a microprogram rs
= rs econo me Sat a min maybe
Explain ih term sequencer GRY, une 3 dencoued. Te next- adress atin une der mois
Ans. The next address generator is sometimes called a Topropiddress source 10 be loaded = EC mu ee M
sequencer amine the ares sequence hat is read fom cap aes source is Buddy tenon ade I
memory: The address af the next miroinsruction can be specified ins equence rveives from the Pi

ass, depending on he sequencer inputs. The functions of a micropro EE |
a Load

Sequencer are incrementing the contol address register by one, loading
the contol address register an address from control memory, Y
muxa En

247, Define heierm microprogram sequencing. (RG, Jung

transfen
address to start the control opera!

anextemal address, or loading an ini

0.48, Define he term microinstruction sequencing. (R.GPV, June 2h

Ans. Microïnstuetion sequencing gets the next microinstruction f
the control memory

Mux? [rest

So] seca ek CAR
a Ci

0.43. What are the major design considerations in microinstrucs

sequencing ? (RGB, Dec, 2013, Al

Ans: Thee are two concerns involved in the design offa microinsin
sequencing technique — the

size ofthe microinstruction atid. the adées
Enero ine. The first concer is clear, Minimizi the size the cos
Cory decreases the cost o that component. The second concern is
desi to execute micrinstrutins a fasta possible.

Conan

y Y

co BR ap

2.50. What is the
internal structure and

Purpose of microprogrami'sequencer ?
working in detail.

Or
Amieroprogramseguencer une
the block diagram of or A

252 ck Diagram of Micrapragram Sequence fora Control Memo

(GRY, Dee ™ 232 shows ine block diagram ofthe erro suene The
i trl memory is included in the diagram to show the interaction between
se u od to it In this circuit, (wo multiplexers
evt th he age and de mem atache I ii

x the sequencer,
Operations which are required to ix

ess from one of four soure

Are used. The frst multiplexer chooses an address fro

7 pement the call and return Je il el e second multiplexer

Subroutine micro instrucions,— call and return and ros into à control address register (CAR). The second mull

Or (RGP, June Bes the value of a chosen status bit and the result of the test is ae one
a it € circı fr ıtrol address register (CAR) provides
Dek diagram, explain the working princi jcePut logic circuit. The output from cont
Program sequencer, Se working principle of ri

3 rol address register
je adress forthe contol memory. The content of contol a
Zune 2009, Dee. 20102643) remets and given o one ofthe multpleer inputs and the

Or

ge Computer Architecti7®

sine register (SB), ther ee inputs 10 Mullen my i
wi tine register (SBR), and from an external source whieh «agi TS it can be obtained as -
saute “the diagram shows a single subroutine register, hy nd sh
i have a register stack about four 10 eight levels den? So= llo + NT
iveat the same time. In con L= Hot
N sn be implemented with three AND gates, an OR gate,

MS

sequen
ange, a number of subroutines can be

and

Sala Sack ponte. a push and pop operation stores and retrieves nn The circuit ca
res during the call and rum microinsructins. men

Draw the format of ajmicroinstruction and explain how a

‘The condition (CD) field ofthe microinstruction chooses one of
Kol, ©
7 (GRY, June 2010)

tits inthe second multiplexer. In case Ihe bit chosen is equal to 1, they wleroprogram sequencer works.

‘arable sequal Is otherwise, its equal . The T value together uy, Mis ion Format Referto Q.4.
no bits from the branch (BR) field is applied to an input logic cies .
partcularsequence,theinat og will determine the typeof operations I"
are avilable inthe wit. The typical sequencer operations are — ing 9.52. Compare horizontal ad y
branch or jump, call and return from subroutine, load an external ayadvantages and disadvantages.
Pushpa stack, and the adress sequencing operations. The sega Ans, Comparison between horizontal and vertical enganizalions are 98
can provide upto eight address sequencing operations with three input fellows —

‚program Sequencer = Refer to Q.50.

‚ertical organization. Give their
(RGP, June 2013, Dec. 2014)

In the input logie circuit of fg. 2.32, 4 :

vot ee ween i] on
Sy. Sy and L Variables Sp and S choose one of the sr

addresses for contol adress reg 0 and Sy choose one of he, horizontal organization, there | In vertical organization, there is
sales eer CAR) able ems melo 00, | ec ocn tve |sienifcan encoding of he

in subroutine register 2
tne register (SBR). The binary values of the two selection Vari

decide te path inthe mulipexer information control information
‘Table 2.10 Input Logie Truth (i) | When higher operating speed is | When slower operating speed is
ie Truth Table for Mieroy A
2 able for Microprogram Sequence desired, itis considered to be | desired, itis considered to be useful.
= Input MUX 1 Jy Load SBR en
eld
. Ihr 5 % L Gin | Iutas a considerable ability to | It has a limited ability to express]
Ara [ooo ho À express a high degree of para- | parallel mierooperations.
loss [NP in
o
0.1 o 1% 9.0 0 (iv). | Formats of horizontal organiza- | Formats of vertical organization!
tol 19% à: 1 Sion are long. are’ short,
1
1 ler. + E o Following are the advantages and disadvantages of horizontal and vertical
1: 4 0 Organizations.

lo are similar to the bit al

dera fun e bl vals i he BR el, (6) When operating speed of computer is an important factor and

state Bit val à Shen the
pa Stated function mn sl. Bit values for Sy and Sí ere parallel usage ofa number ol resources is permitted by the machine
bis e neded str Dr Pi he multiples Sit, he horizontal organization approach is preferable,

subroutine register (5 call mir
islet (SBR) is iroinstruction (BR =
BR) is loaded w fraction (ER: (i) The vertical organization approach is suitable when operating

ith the incre ot
x provided incremented value of £ speed of
Provided thatthe satus bit condition hited th y ‘Peed of computer is slower and less bits are needed in the microinstruction.

puter rt
sy Te considerable factor is vertical approach ;,

Te pelle hardware needed to handle the exec 1%

ition q

NUMERICAL PROBLEMS

can be divided imo subfields to specify 46 microoperation, 1° mer

Imierooperatins can be specified in one microinstruction ? "|

(R.GPY,
x „(MERK De) CENTRAL PROCESSING UNIT (CPU), STACK ORGANIZATION,
_ Sol Since Fi ofS bis can speci 31 (= 2° 1) mieroopera, ‘MEMORY STACK, REVERSE POLISH NOTATION,
‘field ofits can specify 15 (=2*- 1) mierooperations, therefore 9jy INSTRUCTION FORMATS, ‘ZERO, ONE, TWO, THREE-

ADDRESS INSTRUCTIONS

specify 46 mierooperations.

One misinstuton an specify S11 (= 22 — 1) mierooperatom 9.1, What is CPU?

ns. Té part ofthe computer which performs the bulk of data processing
Called the central processing unit (CPU). I is responsible for
functions of any computer system. It is referred
1 major calculations

operations
are andeontolling the

Lee he bran ofthe computer. In a computer system, a
fh comparisons are made inside the CPU.

0.2. Explain how CPU communicates with input/output devices.

‘Ans. The communication between CPU and input/output devices is
implemented using an interface unit. In a computer system, data is transferred
fiom an input device to the processor and from the processor to an output
device. Each input and output device is provided with a device controller, which
isused to manage the working of various peripheral devices. Actually, the CPU
communicates with the device controllers for performing the 1/0 operations.

Deve
ee non
Deve
cru Data Bus IE
[concer | [Sins T rm |L pote |
Rae | Poser

Fig. 3.1 CPU to HO Devices Communication
seine computer system, the interface uit works as an intermediary
between he processo andthe device controller of various peripheral devices.

€ interface unit accepts the control commands from the processor and

86. Computer Archiooture

jey can be easily underst
interprets the commands 50 that they can st00d,

rons or convaing be input and output operations. The
Pois commusicaton involves two important operations

um-m 87
by they
REÍ q, pln stack organ
Prose’ fos, Astorage device that stores information like manner that the item
is, oe ye first item is known as stack. Stack is the useful feature of
nes Ha gal computers, stack is essentially a memory unit with an address

wit penn hb e CPU od he data fom an ip, Tear ch my cout ony Sick poten a estes sit de

st which holds the
dera wasfering the dal from an pnt fis o the stock because is value alway pois a the OP out
Lorean man inp res os ys where the tray itself may be taken out or

nee Ciara tier ae contrary lo a stack of Way a vor
the data bus which transfers single byte of data at a time, me rte ann of wordt sts ee
oc ea gt Po ae ean eh of ee rene
cot dt is oi at he at resent on dodo da he sk ep THe eri of een a Di
(iD Ar acelin the dt y the data register ofthe ima Sno cn be thought OF abe eo pst an em on PPT
va ses ua acid ga ough the device control burs sol or pappedän complet stack, These operations ae sim by
sclnosledgemen othe input device, showing that the data is received, inrementing or decreenting the slack points reise.
the input device disables the data valid signal Register Stack)— Stack can be organized as a collection of a Fine
(1 The Mn ito the sas register is set to 1 because de uber of meron words r register or i an be placed in a pasion ort
FE Ge Re organization of 64 word register stack is shown in Fe
FPE à the CPU issues an VO read signal to the data regie 32. Stack pointersegister SP contains a binary number whose value is equal
(00 Thad phos ey ec te es of te word that eurent on tp ofthe sack, Tee items
(5) The data register then places the data on Wefineed in the stack - A, B and C in that order. Item C is on top of the
pits ‘When the data is reine, Ge CPU ends en potes ba so that Ihe coment of SP is now 3. The stack is popped by reading the
en tote Showing tha the dats hee Deca NER memory word at address 3 and decrementing the content of SP 10 remove
doin Pesa of adn re ace a hance iw hen sack pointer holds address 2 item B is now on top ofthe stack.
Be tin ing the data from Pr sack is pushed by incrementing SP and writing a word in the next higher
bus conse Y emit dt hat cedo be tanséredonte® nc Me Sk insert a new item. Item C has been read out but not
ata register of the interface unit. physically removed. This does not matter because when the stack is pushed a

(o Teceua
adress 10 The CPU also ket the adress ofthe utp de eg on the dee “written in ts place

tion in detail.

WO reared last i th

(i) The CPU then 0.4. What do you mean by memory stack ?
on be dae he cp wich wit pS
stats register is elo | ole data, showing that fag” Explain how a stack is implemented in the memory system of ©
(iv) Now, the computer, (RGP, June 2017)

da reis
control o ht gist issues ada ac sé
ie accepted signal hrouß® Ans, The implementation of a stack in the CPU is done by assigning a

, Portion of memory to a stack operation and using a processor register as a

stack pointer. A portion of computer memory partitioned into three segments
Program, data and stack is shown in fig. 3.2. In the program, the program
Sounter PC points at the address of the next instruction. The address re
AR points at an array of data

the device conte of te sag
vali Te ouput device ne
Signal to the CPU throu; te

the data a def
aa ben recieved, nn a ites lata and sends an acknow'e!

face unt, showing that ho de

16 comcuter citer

Fig 3.2 Block Diagram ofa 64 Word Stuck
The three registers are connected 10 a common

‘from the stack. From fig is

ress bus AR
memory. SPis edo pop orpus fm m
ee it is clear that the initial value of SPiis #)
ste tk ons vera freer oc elit dé
A ales ede bread
te sain: ied ue 300 Ni
25 Dies photon io y
Ins. The method of y
en pa non ae

to write an expression
@® Infix Notations —

operand then he express à
‘expression to add two numbe A

When
fh the operators exist between
er A ad expression, For example

a 1 Wren in infix notation a5

1e Operators are written before 1
the prefix notation or prefix PO
add two numbers A and B is wit

pression is called

notion. For example, he expression to

in prefix notation as —

+AB

unit 69

rattons = When the operators are writen after e
so known as reverse

qui postfix No

ee a | called postfix or suffix notations Itis al ,
EJ opens un. For example, the expression 10 "ada two numbers A and Bis
Prone polish vas ystfix notation as —
de us if ic ix and postfix
Wr plain PUSH and POP instructions. Differentiate infix and pos
PP al in me POETA
a ere notion e best i e register pair
(Operands wn PUSH Instruction - PUSH instruction is used to store register pa
pu ‘Syntax — PUSH Reg. pair, à ae
i The contents of the register pair esignated in the operand are copied
E to ihe stack in the following sequence ‘The stack pointer register is
|: En ha location. The Sack ponte register ie decremented again and
i fe Example? PUSH, B

suppose P contains 34 and C contains
34
“the PUSH Binstruction makes the follo

56
wing changes in memory as shown

sia ar decremented by 2
rae een sp 2 = 2000 2 = 1998
Ceres [Pa |
| 2000 34
EM

L

POP Instruction — POP instruction is used to extract data from stack
and to store in register pair.

Syntax - POP Reg, pair

The contents of the memory location pointed out by the stack pointer
register are copied to the low-order register (C, E, L. status flags) of the
operand, The stack pointer is incremented by 1 and the contents ofthat memory
location are copied tothe high-order register (B, D. H, A) of the operand. T
stack pointer register is again incremented by 1

Example: POP B

Suppose B contains 00 and C contains 00 and stack pointer = 1998

00 00

ang POP B instruction makes he following changes in register shown

top of stack is incremented by 2.

90 Computer Architecture

ie. new top of stack = SP + 2 = 1998 +2 = 2000

| 1998

Difference between Infix and Postfix Notation — Refer to Q.5

0.7. Explain how he evaluation of posifix expression takes place

a stack,
or
Hu an algorithm to evaluate a posi expression using suitable

Ans, Once the expression is converted to postfix, we no longer reg
tomer he preceden lc The expression may be evaluated y see
from left to right. We push the operands in the stack and evaluate when,

eros an operator using the top two operands from the stay
pushing back the result the operation onto the stack so that it
für use as an operand ofthe next operator.

an algorithm to evaluate an expres

be avala

sion given in postfix fo

clear the stack

While not end of input
if ymb is an operand

Push onto the stack
else

t

POP two operands from the stack
Result opt symbol op

+ Push result onto the stack

symb

retum(pop stack)

For example
‘expression

98+

= next input character

Suppose, we ba
have to evaluate the following por
#24.

Unit-1 91

ok ou gti wil tis input we cn show the onen of
ieee wath and ear ech anf ps we.
E Table 3.1
Sabet [opt | opt | Rest | Sack
5 5
H 3.8
fo fen |e
3 13
3 ten
2 1382
a IE PES
Men fice
2 11,2
la Ye | [ou
mu ls 3

“The result Of this postfix expression is 3. The size of stack keeps varying
<s the operands keep coming and going from the stack
(0.8. Write short note on instruction format. (R.GPV, June 2017)
Ans. An instruction format is usually shown in a rectangular box
‘symbolizing the bits of the instruction as they appear in memory words or in
‘contol register. The bits of the instruction are partitioned into groups known
as fields, The most common fields in instruction formats are ~
(i) Anoperation code field that indicates the operation to be performed.

i) An address field that shows a memory address or a processor

register

(ii) A mode field that designates the way the operand or the effective
address is determined,

25. Define instruction code with its two parts. (R.GPV, June 2014)

Ans: An instruction code is a group of bits that instruct the computer to
Berform a specific operation. Its divided into two paris. The most base par
isa pean natn code is operation part. The operation code of an instruction
2 toup of bits that specify operations like add, subtract. and so on.
The operatic

£ ration part of an in
Performed, This oper
hee OF in memory. Therefore, an instruction code must specify
the operation b
ation but also the registers or the memory words where the operants

Ar be found, as wel
{be found as well a the

truction code specifies the operation to be
tion must be performed on some dat stored in processor
not only

register or memory word where the result is 19

92 Computer

0.10. har is an insirution ? What are the diffe

insraction ? te Ben

ae tonmaniunesthestoreddataanda sequence ye de has pres

ovale a pa mea, an insucton consists of two pun “es operation code encountered
& 0 ld di) Addr ©. e a memon

gone bit to specify the addres

ta jo for direct
ey

The opcode field specifies how data is to be manipulated, Th,
may reside within a CPU register or in the main memory. The pump
wes Me so indicate the data address. When operations require à re
untar sired into two or more addresses, the address fiend rn ah be fost UR (oe
‘Fare tan one adress. For example, consider the following instruc: "pi on or to

ns nk in reader nn
Opeodefekd address field Send by t

Assume that this computer uses Ry as the source register ang sui The OU ed
and Fperation or test performs

the destination register. The precedin
he ton rez e preceding instruction then adds ı! e
OF CU res Road Ry nd ac sum in eii Ko Then
ypes of instructions supported by a computer vary from one cars,
ne com,

eference instruction, 12 bits are used to specity an address

dress and to 1 for indirect address,
ference instructions are ideffificd by the operation code 111 witha
15) of the instruction, This type of instruction specifies an
‚Fihe AC register, Sineesan operand from memory is not
used to specify the operation or est Io be executed.
ction does not fequire a reference to memory and
the operation code 111
her 12 bits are used lo specify the type of input-output

“The instructions for thejcomputer
Table 3.2 Basic Computer Instructions

Uniti 93

sists of 16 bits. The operation code (opcode) part ofthe
its and the mean ing of the remaining 13 bits is determined

bit)

with a 1 in the leftmost bit in the

are given in table 3.2

to another and depend primarily
pend primarily on the architecture of a particular mac “Hexadecimal Code
Q.11. Write down the ir di 27 did
down the instruction formats of a basic computer Simbel [r=] r=1 Description
adds or (RGRY, June xp [ORR | ox | AND memory word wo AC
raw the basic computer instruction form ADD, | box | 9xxx | Add memory word to AC
reference, and iparoupuz ppe of n formas for memory reference MDR | dex | Axxx | Load memory word to AC
Me bj hen (RGR, une STA | erx | Boor | Store content of AC in memory
tein brief different pes of instructi BUN | 4xxx | Cxxx | Branch unconditionally
ells tsi her us insu formas. GRVa Dec SA | Sex | Dex | Branch and save return address
reference, regres ere has thee instruction code, formats, — men 18Z | xxx | Exxx — | Increment and skip if zero
Er “ence, and input-output instruct > Oh CLA 7800 | ClearAC
: ruction. Theséiare sb} CIE TRE
Sn a CMA 7200 Complement AC
E pwede | aa CME 7100 ‘Complement E
re IC IM. CR 7080 | Circulate right AC and E
(0) Memory-re ses hd 7040 | Circulate left AC and E
ie Nat, eference Instruction INC 7020 Increment AC
> 0 7010 Skip next instruction if AC positive
7008 | Skip next instruction if AC negative
pan (poode = 111,10) 7004 Skip next instruction if AC zero
(6) Register-geferenoe Inn 7002 | Skip next instruction if E is zero
a Instruction alt computer
Input character to AC
Output character from AC
Once 0
(e) Img i Skip on input flag
E Put-oupu Instruction Skip on output flag
Fig. 3.4 Instructic = Interrupt on
‘tion Formats of Computer Interrupt off

4 Computer Archtectura
aruction format ? Explain various instruc,

9.12. What

Ans Refer to QS and Qu!

How many references 10 memory are needed
erand into a processor register ? Gi

(R.GPF, May/June 2006, pee

instruction re

instaetion to bring an op
example of each npe.

Ans Insom case. its convenient tots the address bits of y?

al operand. If the second pay

code not as an address, but as il

frsraction code specifies an operand, then it is said that the instruction?

immediate operand. If the second part specifies the address cor
iy mad ress OF an op pean in a computtiontype in

then it is said thatthe instruction has a direct address. There is also

pry called dec adres, where the bis in the second
s in the second pan Jos nthe instruction of fig, 3.5 (Cs 1350.

instruction specify an address of a memory word in which the addres
operand is obsined, Inthe instruction code, one bit is used to dis
between a direct and an indirect address.

Todemonsrat his configuration, let us consi ct
ne ,letus consider the instruction codes

12-bit address, and an indirect address
m d an indirect address mode bit denoted by 1. For a4

RGPY, Jen. the inst

(213, What is me difference between a direet and indir, Fc
‘4

"eat legs gina EN

unit - mt 96

union is identified as a direct address instruction. The open
D instruction, and the address partis the binary equivalen: Of
fe operand in memory at address 457 and adds it 1 the
Me Infig, 35 (since the mode bit (D ofthe instruction in address
oF A ented as an indirect address instruction. The address Por the
dol 300. Therefore, the contro goes to address 300 to find the
ie operand, where 1350 is he adress of the operand. Then, the
Sound in address 1350 is added to tHe content of AC
"ue indirect ares instruction aque uo Feferences o memory to fetch
and, Fist reference is ru toed the Adress of the operand; the
Ps for the operand ise Eee addres is defined o be the address of
struction or the target address in a branch

geiles a0

finds th

ton. Herce he efecto address in the instruction of i> 5 (b) is
A direc address instructionineeds two references to memory ~

(Y) „Reädinstruction (ji) Read operand.
On ie ter hand, an indirect address instruetion needs three references

3.5. This instrction code consists of a 3-bit operation lo MEMO

O, Readinitruction (ji) Read effective address (ii) Read operand.
Examples of Direct addressing are ~

nt and for an indirect address, it is 1. Fig, 3.5 (b) sil
astncton Is kept in address 22 In memory Singeihellf (0 [SIA [24001 | Store the content of the accumulator in me
memory location 2400H.
pre o|n fo Read the data from the port.
mw | 02 Instruction in the code form.
(6) Instruction Format iy [Loa | 25014 | Get data in accumulator
Mene
OIE ha Examples of Indirect addressing are ~
FE EE © Jrx1m 25008 T Load H-L pair with 2500H
MOVA,M Move the content ofthe memory location whose
+ coo mor address is in H-L.
Hur Halt
1359 [Hom] i] LxtH, 25004 | Load the H-L pair with 2500H
ADDM Add the content of the memory, whose address}
js in H-L pair to the content of the accumulator,
Hi Halt
iy [LXIH,2500H | Load H-L pair with 2500H
SUBA,M Subtract the content of the memory, whose]
10) Direct Address adres slo H-L pair, to the content of the
Fig. 3.5 Demonstration Woe ca HT Hal

ct and Indirect Address

28 Computer bce
it and explain the execution of regiter-referenco i,
(utd Write andesp = 00

explain the control functions and microoperations fa y,

reference instructions
Fire Rogserreference instructions are identified by the coy

D,- 1 and =O. In these instructions, bit O throug

reused to specify one of the 12 instructions. These 12 bits are ay

(0:10. The control functions and microoperations for the regist

instructions are given in able 3.3.

cution of Register-reference Instructions

Table 33
DIR = v(conmon wallreiterrferenee instructions)
in B [iin IR(O 13) hat specifies th operation]
sce Clear sc
on acee Clear AC
Ge Eco _ ClearE
au aCe Compleme
cue EcE Complement
cr ACESMACACIIS) EE AC (0) Circulate ga
1 ACHSIACACO)+E, E«-AC(IS) Cireulate le
er Dem
m PACS) 20 en(PC PC +1) Skip if ps
Su INACOS = D then(PC€ PC= 1) Skip
2: Dd (PC € PC +1) Skip if AC 2
KC PC +1) Skin eo
+ Sia statstop filon) Halt compe

‘These instructions are excel
tions are executed with the clock transition assüciate

onl fenton eures the Boolean funcion?
Snips iy pron Tecmo ion ue pe
Big the symbol B, 1 bi of Ree a Ee À
instructions anna B; 1 bit OF IR. Exteution of a register rete
opted tie rer
Ste a Tesh hee Sen cor (SC) Fe cleared!
it seven re xt instruction with Ging signal Ta
ciel shi an ren Scion pr la, compl
mictooperationsion the AC or E repites

next four instructions i st rence W
ction cause a skip of

pe pol the next instruction in sequen

stated condition is fu uction is obtain

-ments must be ide
AC (15)=0, the!

‘onditions,
Posie and when AC 15) Mie ha sign bit in
al the MODs of the regie EVE"

(AC = 0). The he register are zero, if
The HLT isc cine, wen te coment of AC

Stop flip-flop $ and sio"

Sequence counter fom ca
so om coming, Te à
"OP he operation af compen? Pop mst bese

11 of the instrug ate
ai
m

tions.

15, Explain input-output instrw
tod output instructions are required for trans o
Geister. for checking the flag bits, and for controlling the
y Imp instructions contain an operation code 111 and
Pe the control when D; = 1 and 1 = 1. R bits of the
Med city the particular operation, Control functions
struction e pulcoutput instugtions are given in table 3.4

Table 3.4 Input-output Instructions

d

PU common to allfiputeoutpalinstractions)

RO N Clear SC

NP peur AC(O- Pie INBRGFGI <0 Input character |
OUT Bio : UTR ACUUË 7),FGO +0 Output character
Ser By: MHÉCFGI El) then PC PC +1) me |
SO pe FORGO = 1)then( PC<-PC+1) Skip on output Mag
Ion PB IEN@1 mens eames)
TOR, Ré : _IEN + 0 Interrupt enable oT

The insriiions are executed withthe clock transition associated with timing
Sigal Ty Fach contro function requires a Boolean function DIT, (designated by
tbo p). Control function is distinguished by one of the bits in IR (6-11). By
allocating te symbol B, 1 if IR, al control functions can be represented by pB, for
ls 6 through 11. When p = DIT = 1, the sequence counter SC is cleared.

0.16. What do you mean by zero, one, wo and three-address instructions ?
Give suitable examples. (RGPY, May 2018)

Ans. For the instructions ADD and MUL, a stack organized computer
oes ot use an address Field. However, the PUSH and POP instructions require
address field o specify the operand that communicates with the stack. The
Program for A = (X + Y) * (P + Q) will be written as

PUSH X Tex
PUSH YTS ¥

ADD ToS (X + Y)

PUSH P ToS CP

PUSH Q We

ADD ToS <- (P + Q)

MUL ToS «+ (X + Y) * (P + Q)
Por A MA] © ToS

evant required to convert the expression into reverse polish notation to
“Sluate arithmetic expressions in a stack computer. The name zero addres

ane Unit 99
this ype of computer because of the absence of an ag
given o this ype of & res y

font instructions. k

the comput

tructions use an implied accumulator reg) te NUMERICAL PROBLEMS
rvevumulator contains de result of all operations. The pr mn e many operations this code can perform ? ,
eu a en Renae treuen?
A Te MIX] ie (RGP, June 2014)
STORE T MMeAC Gi No. of memory logátiong 21224096 ,
fe co Ara igital h jemory unit with a capacity 0)
putas prok.2 A ser instruction code format consists of
wT ACASO ss u, is e yd es ofr cm of
STORE A MIAJEAC She bits for the operation part ai 1

indirection bid). Dro instructions are packed jemory word

it i ie packed in one mem
irection mode bit). Two instritctions are pac memory word
bit nstrhction register. Iris available in control unit. Formulat

Tis the temporary mem

y location address for keeping the intern:

: on ion for this computer
ce i executing instruction for 4
cedure for fetching and mf mW. Decl
In commercial computers, two address instructions. are the most come Pr yy (GRR De:2007)
The progam forA=(X Y) * (P+ Q) wll be writen as
MOY RIX REE MIX] o ar me iaa |
ADD ORLY RIERA siete ‘
MOY RP REM 1 u
ADD RO Re REE MQ) ame [opcoce 1 [naar ı | Opcode 2 | Addren?
MUL RUE RIERI=R2 } 4
MOV ARI MIAJERI 5
Here, first symbol pees Lt
symbol listed in an instruct n is assumed tbe de:
source andthe de

and the destination where the resul
_ Computers with thre.
field to specify either a proce

It of the operation is ransfer Fig. 3.6
ress instruction formats Can use each al!

Procedure for Fetching and Executing Instructions —
Me een ge D m from memory to IR and then
fora N ©) i be wrinen sg Be. Ti {Real 40 double instruction frm memory to TR and 1
RX, Y increment PC
400 ge MT Wi) Decode opeode 1
Mu HR (ii) Exccute instruction 1 using address I
The advant RI #2

a (iv) Decode opeode 2
Latine arithmetic e ¥) Execute instruction 2 using address 2
the binary ded instruction en cion GON. The à Eee oh ola i ee 1
SANS 100 many bits to specify three ade 1) Go back to step x D
2217. Diseuss the following wi examples di Prob.3. The memory unit of a computer has 256 K words of 32 bit
(0) Zero-address instruction ~

co fields. An operation
uch. The computer has an instruction format with 4 fiel
mputer has an i 1 de ser

(ei One-address instructions Feld a mode field 0 specify one of seven addressing modes, a register add
Field 10 specify one of 69 processor registers and a memory address. Specify
Destruction e number of bits in each field ifthe instruction
e ee gen (RGPK. June 2015)

(id Two-address instructions,

Ans. Refer to QG RGRY, Dec 1

100 Computer Archtacturo
ol The instruction is of 32 bits long, in which the address y ae
e y The instruction format is given below —

which are determined as a
Kr 28 x 210 = 218 bytes 1 7 6 18
Therefore,
A 1 | Opeode [Reiser Address
Address bits = 18 [ ¿e
‘To specify one of seven addressing modes, mode bits required 2019 +.
\ «ii Data = 32 bits
N Address = 18 bits

To specify one of 60 proc
Register bits are required —

prob. Write a program toevaluate the arithmetic statement ~
ps Sade Date n=0)
6052" => x=6 Q4R=S
ñ
Opcude bits = Total bits (Address bits + Register bits + Mode hie 9 773
=32-(18+6+3) >

(i) Two-address instructions
Gi) Onezaddress instructions

a (ii) Zero-address instructions.
5 A (R.GP.V, Dec. 2010)
The instruction format is given below — Sob i) The pfogram to evaluate the given arithmetic statement by using
O inéaddres instructions is as follows —
Ta MOV RL x RI Mix}
cua nd sobres memory ant wih 256 mods OO RE RC RL Ma
10 specify one of . 'ress, an operation code, the register eode| > oe
Weft rain end enedirespat~ oy FMB Ro RRC REM
code pa many bits are there in i L 2, +R
de Part and the address par ? the opetation code, the res A ee
Gi) Drave the instruction |
rene word format and indicate the numbe ps a Bee un
(ti) How many bi 2, 2 R2+M
memory ? y bits are therein the data a 2 DIV RILR2 RI RUR2
and address inputs of a ai en
y ; MIX} <
Sot (i) The RGB, June 2 i) The program to evaluate the given arithmeti statement by using
5 € instruction is of 32 Ge, June 2 4, gram to evaluate the given arithmetic statement by using
18, which are detemined an 32 is Tip in which the address bis!” ASS instrutions is as follows
Therefore, 256K = 28 x 210 = in LOAD x AC © Mix]
ae a ad bess y AC < AC - Mb]
ies bi 18 bi | ADD 2 AC < AC + MF]
ie code 6 . STORE 7 MIT] < AC
ect bit 1/25 bits LOAD m AC © Mim}
32-25 = 7 bits for opcode Mu. n AC & AC * Mi

404. Computer Arctechre

RISC and CISC.

1. Write comparison between

si (RGP. a y
se Poe conto ales are - CMA, RAL. RAR cie.
E REC asc Bei operand. Example :
ae = 3 TE must the address field of an indexed addressing moi
[an Tim RISC. the clock rae is 50-150 |In CISC, the clock rate 57 rake it the same as a register indirected mode instruction:
| MHz in 1993. MHz in the year 1992, action be 10 neers =
iy [Simple instructions taking one [Complex instructions essing mode, theaddress fi
fe oe re, 1, nds dre mode, Mc
A CE ern ne
À Gv | Few inseuctins may refer memory Most ofthe instruction ma, ches pa |
Y fo read the effective ad :
| Icons re exe ari gc I
ise mode s ‘Address part of instruction + Conte

0.22. Campare RISC and CISC characteristics. (R.GP.V, Dec. à
Ans, Refer 10.020 and Q21

9:23. Write short note on addressing modes.

Ans Th

(R.GPV, Dec. M

aléressing mode ofih instuction determines ne way the pe

sm execution. The addressing mode specifies ant

adress field of te instruction before the oe

e d. Addressing mode techniques are used in computer
“e purpose of aermodiing ne or both of the following provisions

(8 Toprovide programming versatility tothe user byprovidina

A: pines 1 memory counters fo loop control de ul
and program relocation. ¡dla |

(i) To dee
instruction

ase the number of bits in the"addressing)field ch

G24 Define implici and register addréssipg mode with example

(RGPY., Dec. 2007, *
In register addres
SER Tho opcode species the a”
tion to be performed. Example is
Move the content of register B to resist}
‘The insruction inthe code form.

Penn nee m
wtp MONA ee

vii DK ra om OO
for register a hat MOV operation, the next three bits 111 are the bina"
A and the lst three bits 000 are the binary codo for regis

Ans. Register Addressing Mode -
‘operands re inthe general purpose regs
oF the register in addition o the opera
MOV A.B
e
in this example, the opcode

re address

em
CPU register oa
ehe warn tothe ec ars, Th inden register
Pa CPU reser that contains inde
Trt addressing mode register in
Pano aressng ld must not bo

egister indirect mode

sio

rted by 8085
0.26. What are the different addressing modes supported 8:
co Eau ccc with examples (RGN. June 2009)

or
Explain with an example, how effective address is cateulated in different
rodri mon 6 mart, Dee. 2010

Explain withthe help of examples the addressing modes of a base
San he help of exon ear, June 2011)

o:
Explain various addressing modes with te help of example.
y an PRGPY, June 2012)
Expt 2 des with pl
plain the various types of addressing modes with an example. |
N (GRY, June 2013)

Or

Briefly explain all the addressing, modes of computer instructic
aaah TR GP, June

2014)

or
hat are diferent addressing modes ? Explain each of them.
(RGP, June 2017)

106 Computer Architecture
he instruction determin,

ins, The addressing mode of the inst it

A te selected during program execution. The addressing mod .

0 the address field of the instruction

mode techniques

‘operands
à rae for interpreting or modify
13 is actualy referenced. Addressi

te prin aly ming one or bol ll

(i) To provide programming versatlity to the user by pro

such facilities as pointers to memory, counters for loop control indexi,
ta, und program relocation x
(i) To deere

instruction,
‘Types of Addressing Modes —

(0. Inherent or Implied Mode - No operand address is expis
specified in the instruction. Generally, some specific registers are assume
‘the operand address and the destination of result

Example — All the S-bit MPUs provide this mode of addressing à
instruction consists of only one byte long code. A few typical instru
with the format of fig. 3.7 (a) are given below —

MPU

PRET re peration
[8085 CMA * Wea)
Lomo | Ana B |WEW+®)

(ii) Immediate Addressing-In this
‘operand is contained as a part of
immediately following the opco
‘dressing is fast in processing be:
address followed by the operand

mode of addressing, the 2
the instruction itselfyin one or two PA

cause it doesnot involve fetching of ope”,
from the memory,
Example ~ Almost al 8-bit Mi

PUs provide this addressing mode.

Hex Code
| Cas

gerd a

de as depicted in fig, 3:7:(b). Immel? of

Unit-m 107

je Because ofits simplicity and fenibiity this addressing mode
all MPUS,

[Hex Code | Operation]
BA 3301 | (4) (1033) |

BB0133 | (A) <- (1033)

T ‘ode

w
e inttion
fetch opera

de

Hex Operation

[pu] Mi “Hex Code | Ö on 7
|-LDA addr | A6 9F 2000 | (A) < 2000) |

that required for addressing a memory location. |
Example — The 8085 and the Z80 MPUS have extensive use of register

MCE
Tacaro
| tthe sss bits specify the register} |

meo —
(o)

Unit 108

> orcas [i ap Registrindirect Addressing - Conceptually same as ini
x (vi “ister is used to contain the addres ran. The register
sabe 2 by the operand addres before reiterandtet addressing
= ie led PACE, ie ize of he adden le one or

2 abel: eit pi is required to hol an ares ss dep i

Mas fe 370

= Operation ]
e u a (EA) (CN |
emery Lp (Meg) O1L10%ss |

mp BE > pe

(vin Paged Addressing=In this mode, the memory space is logica
Ser ide into a number of Blocks called pages. Generally, ih p
esters ik stor is used to hold the

T rel

MPUS, A special register called
fuse number and the instruction provides an offset. The offset provides the
0 | Tires within the page with reference to the starting address of the page. The
eciveaddress is produced by the concatenation ofthe page-register contents

‘pede ae Oreode [x Index Mens inthe higher order part and the offset in the lower order part of the address as
Be} Pa rr] E O
Teste] ee] ret
| ier pop Oper MPU | Mnemonic | Hex Code | Operation
1 6800 | ADI 9833 TA) E (A) + (0033)
| 6502 (AVE (A) + (00F9)

ena lid Indexed Addressing ~ In this modo, a fixed base address
{tent is specified as a part of the instruction. Then, an offset from the
elites is specified in a special register known as index register, The
| mare address generated by adding the constant with the:contents of the
* register is depicted in fig. 3.7 (h)
Example

_Mnemonie | Hex Code e |
> @ DA 174F,X | BDAF 17 | (AMO |
83.7 (a) inherent i | Loa a: | 03 | (a) (0012) |
Ae eat) meta ta ehem wh
Indirect adver eet resi, le) Regio Mages (iA ier y 0) Based Addressing ~ Another addressing scheme NTN AO A
10 Bar Paget Address ty Meccan Ree eer MERE effective address isknown 25 The address
resing Relative aged Address | econ OES is exactly the same as in the case of indexed SAME
Tressing le g with the offset provides

‘Fa register culled based register is add

410 ‚Computer Architecture

st of the instruction to obtain the effective addres

as a pa SS 8S depig,
fie 370

Example -

{MPU T Mnemonic

Pao TID a=

sv | ADD _ASIS.x

(8) Based-Indexed Addressing - Based-indexed addressing yyy,
I Mexibiliy by using two registers, an index register and a base regi, |
sencrating he effective address. The contents of the base register any
index register are added together to generate the effective address. fs
indexed addressing permits run-time computation of both the base adie
and an offSet to an item of a data structure.

Example -

[eu
8
5509

[ Mnemonic |

ex Opcode |
[EDAB.Y | AGA

Operation —]
[aa]

i

(xi) Indexed Indirect Addressing — In this mode of addressing
address generated by indexed addressing holds the address of the opera
re are two possibilities as follows

; (8) Previndexed Indirect =
the base address to form an indirect address:
is the effective address,

In this case, the offset is added,
the content of the indirect addr

|
In this cases the base address!
the offset is added to the content of the indir]
address, |

Example - }

(0) Post-indexed Indirect À
used as an indirect address

address to get the effective

PTE pet —|
Fee for sity Hie

= le [Operation
| 604.x) [BD OF FR
[sm [ups aan |

are co tn |
A6 9823
(sth Relative Addvesing

Ale (+23) 31
address is generated by adding
sed signed displacement avai
fig. 3.7 (j).

— In this mode of addressing, the enti
the current value of the program counter | |
T

iluble asa part ofthe instruction as depicted

mom
a —

3808 1fZ=0 continu, |

HZ =10PC)}< (PC) +08 |

s | F008 1fZ=0 continue, |

ld dal liz-iwocwo+ |
ae ing=The slack pointer register is used to specify
(xi) Stack papales oom de A on ah hare

cause no expli
pesesary. Further

rented as each
jon (STORE), the conten

remented
‘ore, the stack pointer (SP) is automatically incre
spor each memory access using slack addressing. In PUSH
fs of a register can be stored into a memory

pa snd the SP is decremented by onc or two. Likewis,
Hem ed y the SPand the SP is :
son ponte contents ofthe memory location pone by the (SP)
ro ae) can be rad ino a register andthe SP is incremental by
(ent as decided by the size of operand.
sample
(MPO]Mnemanie| Binary Code] Operaion |
SS (EA
ä (SP) 2) (HD)
| (SP) (SP)-2
La.
SHA loonoio |«SPr<<
6s00 [pu Haar

927. Wie down diferent modes of dat trar sane 201)

pi 2 Explain each mode in
le e are the different modes of data transfer ? EHEN
or

Explain the following modes of data transfer mary access

ren (i Direct me
(0 Program controlled (i) Imerrup driven RER Zune 201

Or
irte three modes of data transfer and exp!

1 of them
tain any one of HEM yy

(RGP, June

or
Explain the different modes of data tr
"ter and 1/0 devices.

sn the central

ane ete Dec 201)

a amed VO is
Exphin the tree ways of data transfer 10 and from periptery Programmed VO
RGR Ne control of the CPU. I
my ds the ex:

gan VO device
etween two progra

onnected to the VO device. The HC
access 10 OA data transfer from an Y/O
ngedsihe CPL to execute Several instructions, including an
a word frompthe UO device to the CPU and a store

ims using programmed 1/0, the CPU, main memo
ri somminieate viahesystem bus. Address lines o
SN An VO device is Connected lo the bus via an VO port, which

pectivepis an addressable data register, hence making it

sterring data between th

Ans. There are three modes of

ent LO devi

> Programmed LO
ed YO
ss (DM

til) Interrupt init

pero

pes

result of instructions writ
vis initiated by an instruction
d from a CPU register and periph
to transfer the data to or from memory,
control requires constant monies
a data transfer is initiated, the CRL 10 dv
ice to see when a transfer can again be mag fon the CPU'S Pers
fueren from a main memory location
hinesya technique known as memory
address space to VO p
data to be fetched from or ston
made the ad

inst n

and CPU. Trunsterring data
peripheral by the CPL
required 10 monitor the inter

In programed LO method, the CPU remains in a program loop uni
caesthatit is ready for data transfer, This isa time-consuming prom
busy needlessly. When the interface determina
a transfer, generates an interrupt request 1 king instruction wh
te detecting te extemal intenup signa, the CPU momentarily ssp As X automatically nu
processing branches toa service program to process the LO wanstagl MO por. These nory load and store instructions :
ily performing Pl dan words to or rom VO por: no special 10 Isaias 7
is between GPU an@lperipheleny| The essential structure ofa computer with tis typeof VO ARE
PU alps ni, Th contol nes READ and WRITE nich area
The CPU initial tapster Hl CPU when processing a memory roh nn, NINN ©
1 address and’the number of wor} 3 her a memory ac roo
utc thetasks. Wh PCT 1
cmory Cpeles through the memory bus | As
‚pemory contrller/ihe DMA transfers the | READ
el mor access operator" | taire LE
y 0 ias peo à ty "| |||]

'mory transfersiare infrequent po
inffequen« compared to proces lina = feed

Memory

napped VO is used to
A memo

Inmany mac

bak tothe

Pil merely de

than processor, LO me
S85 to memory,

2.28. What do ye i

Ans. Referio Q27, Rammed YO? RGPY, Dec. 20101 ER

0.29. Explain in 5 | 7 om

92 Espa shor programmed 10 and irene VO.,| P34 Programmed 10 with Shared Mero ont

L a OPK, June 2009 ho Wann eet 10-mapped

Write short notes on 4 Ng organizatic cted in fig. 3.9, sometimes known a8 ©
memory mapped VO and VO ma en ion depicted in fig. 3.9, e. In this scheme, a memory“

ei, ty and VO address spaces ar separe cool fine wich

ne
RGPY, Dec. 2006, 2009 | Fe instruction activates the READ M or WR

114 Compt

does noreste LO devices. The CPU must execute separ
“ the READ 10 and WRITE 10 lines, which cause y.
dressed HO port and the CPU. An 1O que

fhe same address bit pattern withoy, ©

HE HO ing

ferred beiween the ad

mors location can cons

Dae
tro
mesos || aranıo :
mara] | | mm) fe
Von
I | [ (ba

|
Ls

" dorer] [io Fez

+ 19 Programmed 1/O with Separate Memory and
1/0 Address Spaces (1/0-mapped 1/0)

When the CPU executes an 1/0 instruction such as IN or OU
addresses VO port is expected o be ready to respond to the instructor
the HO device must transfer data to or from the CPU-IO data bus wit:
specified period. The CPU must know the VO device's status to prevent ili

of information or an indefinitely long VO instruction execution time so | éMbled or disabled by exccuti
transfer is caried out only when the device is ready. With programme‘ msdable interrupt has higher priority as com hemos
the CPU cane roganmed test the 10 dec its before iio e mae and nonmaskabie mier ars ace
processor will service the nonmaskable in

ally used as a power failure interrupt.

VO data transfer Frequently, the status is specified by a single bit af infos

that the LO device makes available on a continuous basisyfor exampk|
setting flip-Nop connected to the data lines at some VO port.
To determine the status of an VO device, the CPU must perfor

following steps —

|

lo determine if the device is ready °F

(1) Read the status bit of the VO dev
i) Test the status bit
transferring data
(ii
transfer.

Interrupt Initiated VO -
The extemal d

ite,

Af not ready, return (os (); otherwise, proceed with weil

vice is connected 10 4 pin known ash NTP}
complcies the current instruction and: re

nc
progr

The ©

Hype address in

Im
i bed esi
Denken

vam. An example ofinterrupt

em de

ep is typi

saves at least Ihe contents of the "i.

ve
ve subroutine

m is written by the
temal device desires

anputer automatically oad an adress into the program counter

Uni 115

ike program known as the interrupt service routine

eeute this
y 19 ex

The
N, that is
astruction

my he same in n
a end or a subroufine
m ly, this instruction Toads

the program

der and thenstho computer

es cxerutingthe main

redepicted inyfig. 3.10.

there Are three types of interrupts ~ exter

Exieinal interrupts are init

Intemal interrupts or traps are activa
over, division by zero, or execution of
din the same fashion as external interop
Many processors include softw
est instructions is executed. the processor is ner
Snilarly to extemal or internal interrupts. Software intern

nr =
Groner

aio
e | :

sio | [Dr

ces such as A/D converters. E
felino two types ~ maskable and nonmask;

Fig. 3.10 Computer A/D Converter
Interface via Interrupt VO

mertupts, aps or

rupts.

the interrupt pins of the com
al interrupts can fü
de. A maskable interrupt is

instructions such as À
pared to the maskable interrupt

pt first. The nonmaskabl

ed internally by exceptions
‘an illegal opcode. Traps are

fare interrupts or system calls. Wh
' pied or

all used to call the operating

030. What is he most effe
() Programmed VO (ii) Interrupt

Justify your answer.

lui,

Ans. There are three techniques for HO operations
¿nta are exchanged between the processor and th
‘executes a program that gives it direct contre
Sensing device status. sending a e

int in the following =
iated VO (ti) DMA

of the
command. 3

pt instructions are

ib programmed
fe 110 module. The
LO operation.

515. Computer Architecture

fering the data. When the processor issues a commang y,
ve. iret ai ul he operation is complete. Ifthe pre
faster than the VO module, this is wasteful processor time. With i.
driven WO, the processor issues an 1/0 command, continues 1 +
he instructions, and is ineropted by the VO module when the jn}
finished its work. With both programmed and interrupt 1/O, the proc, |
responsible for extracting data from main memory for output ang
dita in main memory for input. The alternative is called as direct py,
access (DMA). In this mode, the 1/0 module and main memory cy,
data diectly, without processor involvement. Obviously, the DMA
most efficient technique,

0.31. Explain the drawbacks in programmed VO and interrupt a

(R.GPY, Dec 3
Ans, nteraptdriven JO, though more efficient than simple progra.
VO, sil demands the active intervention of the processor to trans J
between FO module and memory. and any data transfer must traverse a
through the processor. Thus, both of these 1/0 forms suffer
drawbacks ~

©) The speed with which the processor can test and seni
its the LO transfer rate.

wo.

device

Mi) The processor is coupled in managing an 1/O transfer'ker
instructions must be executed for each VO transfer.

0.52. Hovis
completely

interrupt driven LO better than programined 1/02 Dis
‘how the various signals are exchanged during 1/0,

(RGP, May/June 2006, Dec.
Ans. The problem with programmed Os that thepfOcesSor has to
3 Jon time for the VO module of concer t bepeady for ether recep
the can ion oF ta, The processor, while waiting, mst repeatedly inter

ihe status ofthe VO module. As atesut the level of the performan
miro system is severely degraded

Awallernative

is forthe processor ist issue an YO command 10 7%

> some other useful work, The VO module then in 4

hen itis ready to exchange data W
execute the data trans

processor. The processor then
resume its former processing,

Interrupt is more effici
seedless Waiting. However,
ime because every word of

fer, as before, am

ent than programmed LO because it eli
lerrupt VO still consumes a lot of. proc
data that goes from memory to 10 mot!
‘must pass through the processor. !

om VO module to memory

‘M, and sends an acknowledgement signal to device 1

re to th

fom yy), The final act isto restore the PSW and program
the stack.

u

ae
en 1
T Process Interrapt
Kamen
= a
T Restore 014 PSW
a ,

hardware events occur a
e device issues signal to the processor.
(i) The device issues an interrupt signal wis
(ii) Processor finishes his current execution and responding to th
eu

ctermines that there is
Ei The processor tess for an inept, determine ha hee
(6) The processor now needs o prepare to transfer contro tothe
I aut by saving information needed to resume he cure prog
Be point of interrupt. The minimum information required is

Preessor (PSW) and location of next instruction to be executed.

Lion

counter with the entry
pond to rapt
PSW relating 10 the

(1) The processor now loads the program
ofthe interrupt-handling program thet will res
(vi) At this point, the program counter and
Fed program have been saved on the system stack
(il) The interrupt handler next processes the in |
(il) Now saved regi ieved from the stack a

ná
saved register values are à
tape counter val

418. Computer Architecture

ue i the Base advantage of using interruptiniy

(0.33, What isthe bo ng Irena
ker nr ander program control without an iterran 0. gat
ivi oe eo (RARE, Dec. 2008, Im al nn
Me ME FE const

O memory

Un en
ages and Disadvantages — Interrupt LO je more ef
y 10 because it eliminates needless waiting. F
nes a lot of processor tim = every word od
to VO module or from 1:0 module to m

Meter interrupt

Ans. Refer 10 03
5 i tart explain the int
34, With the help of suitable flowchart expl terruptin
RGB, June $
sith programmed VO is thatthe processor has |
he LO module of concem to be ready for either revs i
ih 40 mae of aces os Tat he | prop Esplin various aliments Areas mode branch pe
transnesian of data. The processor, while waiting, must repeatedly ie À Pré. n ; relie ñ
the sinus of te HO module. As resul, the level of the performance y yiasucton i stored in memonyat añ address equivalent to decimal 780
‘entice system is severely degraded branch is made (an equivalent 10 decimal 500.

Analtgmauive forthe processor to issue an VO command to am
and hs o tado some other useful work. The VO module will then ine
the prosesor to request service when iis ready o exchange data wand
processor, The processor then executes the data transfer, as before, any (ii) Determine the relative address value In binary using 12 bits

resumes its former processing. why must the number be in 2's complement ?
Let us consider how this works, first from the point of view of hr in PC
orimput the LO module receives a READ command from the proc PO a teint de TE ee Jen tue
me UO model then proceeds o read data in from an associated perito) ele te binary value of 500. Then show that the binary value in PC
Once the data are in the module's data $ pls ihe relative address calculated in part (ii) in equal to the binary value
signals an interrupt to can CE
control line, The module VO Module Le
dl its data are requested by the Sol. Addressing Modes - Refer to Q.26.
Processor. When the request is made, the Read Status Poe. tnterrap N
odule places is dat on the data bus and is slice BO
ready for another 1/O operation. From. li (i) Relative address = 500 - 751 =~ 251
the processor's point of view, the ‘action for |
mput is as follows, The processor issues à, ‘
READ command, Ithen goes off ond dees
amet ds Ach end ech stan
ele, the processor checks Toman
When the interrupt from Tu,

(i) What should be the value of the relative address field of the
insraction (in decimal)?

, Dee. 2009)

The relative address value in binary using 12 bits is
ror

Condit 251 = 000011111011

-251= 111100000101
Ru Word

© VO maduro | » | "ne E : ¿causo the relative address of
men nena ne te JO plas PE aa umber must be in 2's complemen heen he
Abeustigrent program and Processes the T | ‘a

fterrupt. In this case, the processor ine Wad
the processor reads =

the word of data from the LO module and eh

Stores it in memory. It then restores ine

contest of the program it was working y

and resumes execution, en

Fi 312 shows he us oir
incrpivo
for reading in a black of data. E

Doro
"111100000101
(000111110100

Se lastra il
Fig. 3.12 Imerruprdrive”? À

=

ic addressing made ? An instruction is sto

Memory
code mode 1
Opeode mode |

PC 300

so

Le ieetive address isthe | Indirect addres
Mes par of the instruction | Rel

“00 and the operandito be | Indexed
std into AC 15.800. In | Register indirect
immediate mode, the se i

seed ofthe insiftction is taken asthe operand rather than

sis loadedino AC. T

effective address in this case

Prob. Mot E +
e res td ur location 301, The address fie has st wel” jy Direct ade
sin Uprocesor rier RY conan the number 200. Evaluate en, i espera
waren Fahr addressing mode ofthe instruction és ‘ i Relative addres
AS | Ue) Register indirect addressing mode,
(its Register Imliret (R.GPE.. Dec. 2005)
fix) Relative ga Te above given data 2
(93. Inden with RI as the index register A a mee
: (RGP, June yf ge sake of convenience Be. Ti | Cons
Sol: Addressing Modes ~ Refer to 026 EN A € E e of AC

600
300

90 |
700

address, the

1. In the indirect

ande. the effective address is stored in memory at address 500. So,

the relative mode,

the

02

00 = Gor

sore Uhh At memory address 200,060 word ingffhktion, Wind te ACH

Stored Stats os sent bloc 201 the ad
con 3 ttn We he ens
rent memory locations as shown ahead - |

— Memory

the content of PC is 200, whe te oy
ef PC is 200, while the contes of reis i“
ress are in decimal mut
‘address for the following addre™

five address is 800 and the operand is 300.

fixe address is 500 + 202 = 702 and the operand is 325. In the index
“ele effective address is XR + 500 = 100 + 500 ~ 600 and the oper
Adress Memory
LEFT) zoo Pre]
20 TED
Km 2 [ima
co
so EJ
se ”
= =
Fig. 3.13

422 Computer Architecture

Unie 123

16900 Ie register mode, the operandi in RT amd 409s joug,
ess mths case. ln the register indie
is 400, equal to the content of RI and the open nt

the computer at the same time,
jorty first

There is ne e pie ont

forthe addressing modes.

The Fi ig method is used to recognize the highest peony source

ne tection bce ar

he program which takes care of interrupts stars mth har

Mi pl te inert sure ee. The roi of ac
mined er ih hy aes Fs he i

2.38. What do you mean by interrupt ? When a device interrup,. Ves source is tested and if its interrupt Signal ison, control branches to a
2 de an by interrupt levice interrup y, et

me does the processor determine which device issued the interr, routine
tas a j ed the imterzupa y es oy. Henge Ae nil service routine for al interrupts bas à

aa O 8 Program contra gy ROE sible service routines. Particular service routine reached belongs to
a leviee among all devices which interrupted the computer.

for this source, Otherwise, the next-lower-priority source is

external or internal generated request. Control returas to the original pu) Stes PHO

OY the software method also ha

The herder proces or rosin an nterup is sa jardwareprioiy ert ul can be used speed
«secan af stone, The ste of the CPU u eal ae

¡ce cycle (when the interupt occurs) is determined from ~ the conte jardware priority-interrupt unit accepts interrupt requests from many
Sleeper hehe 1 pee aps
Serio sas conto, Tis sate of CPU is pushed into a ment acs on intr request o the compar kasd on hs determination
and the beginning address of the service routine is transfe rogeBiinterrupt source has its own interrupt vector to access its own service
maux. Te beginning adress ofthe service routine is detemined ys} ee ess, Hence, poling isnot needed because al the decision ac
hardware. The service routine must then determine what caused the intemfpstblshed by the hardware priority interrupt unit. The establishment of
and proceed to service it & dnare priority function can be done by either a serial or a parallel connection
interrupt lines. The serial connection is also called the daisy chaining method.

0.37. What is the role of a priority interrupt ? (RGB, June 2016)

Ans. Refer 10 Q.36.

2.36. What is meant by,

‘priority interrupt ? Explain the procedures
‘tabling the priory sima a cdas

E A |
plain priority interrupt and polting inéontexttinterrupt nie)

0.38. What is the basic advantage of priority interrapt over a nine
el be ithout u mask
(RGRV., Dec. 8 Pry system ? 15 it possible 10 have a priority interrupt without a 7
‘44 p # (RGR, June 2008)
short note on priority interrupt,

ERES, NTRA aR rn
tidus Bourne Sptem hich establishes a priority ost] Ste wih each device being able 10 originate an inierupt rc
Sram Mich condo io be sevice et we pt syste ist ey he see fe a
et ave simultaneously. The system can ls determine FC Blo the poscihiiy that several sources will eg
uns arc allowed to. inte 7 ee „a ultane. of stem &
erupt the computer while another inte uly. The priority interrupt stem e
(net er while another int] rey. The priority interop
ig src. Higher rary eu inl ar qu or Ho mine ch condon
if delayed or interrupted, could have e OR requests arrive couts
Fret interrupted, eau ave serous resus. Devices with high ts arrive simullaneousl

iv high priority and slow devices receive low priori 1] sm possible o have a priority inerapt without a =

124 Computer Architecture Pe:

149, Explain the process of handling an interrupt that occ, pie during the interrupt is shown
(GPS: Dee, 209, arg 2 anime ine instruction at address 288. A this sme, he rm

Ans. The was ha the inferrptis handled by the computer can pe ye gg in PC. The Programmer has previously placed an input
flowchart of fig 3:14. An interrupt Mip-lop R is inclu” 56 5m in memory string from address 1120 ands BUN TT

that shows what hi

Bis ce P

nes When R =0, e computer goes through an instruction eye en ga a address 1. This is shown nai 315 (a)
the este eof be struct exce TEN is checked by the omg nn tro reach ining signal and nds hat» pos
indes hat the programmer does not want fo use the interrupt, gf y pe inte syele, The content ol DEBSS) is stored in memory lo
unies withthe next ismacton cycle, IFIEN is 1, control checks pu piace se10 land R is cleared 00 Atthe beginning ofthe next ins
et tion that is read from memory sin address} since thi

ee ls
bis. Co Mag are 0. indicate hat nether be input nor the output foe he int m
are ready for ransíer of information. In this case, control continues va Wen of PC. The branehyinstruction at address 1 ca
5 a feat input-output Service program at address 1120. This prog

tet insroction ey. er lags set 10 | while IEN = 1, flipNop Reese '
Tati col de esc pase cone checks the vals OR. ase fags determines which lag is et. and then ware te regie
gee ip enter rk im en io eyed A put information, Once this is done, the instruction ION is executed
- Fro andthe program eur tothe location where vas items
{esis showmiin fig. 3:15 (0)

eration Ce Interrupt Cele bh. Y Be
Mer i. N PC=1[0 BUN 12
Y Store Return Adres NOT 1
intocaton®
i MO PC
ord Main 15 Main
wet I reer ES
| Branch to Location 1 Î
Pel
in me
vo o
a | F Program Program
Ren
CNO O
(6) Before Interrupt (6) After Inierrap Gn
‘ Fig. ion of the Interrupt Cycle
Fig: 3.14 Flowehartfor Interrupt Cycle | m Fig. 3.15 Demonstration of the Interrupt Cycle Be
The interrupt eye is hard Vi of: What do you understand by program interrupt ? Draw do
i y hardware implementation of a branch and char far j eS er

tess available in PC is ont
FE tet when the program returns 1%
hich it Was intemupted, This location may be a pro 241. Write short note on parallel priority interrupt

register, a momory stack, or a specify
-mory loc: i >, Specific memory location. Here, we choo" fou this method, a regie: a cn
oc, cn at adress Oa the pce RP o ene eis whose i

‘ontrol then inser om each device is use y is established acco
Control then inserts address | into PC and clear TEN ce that 007 device is used. Priority is establish

x bit i à ee
‘nleraipfions ean occur until the odo A the register. In addition to the interrupt register,
ur uni the interrupt request from the lag has been SP Mask register which is used to control the status

specific location where it can be foun, es lors Gas ea 090:

instruction

¿y bythe interrupt
fing so he position

the circuit may
interrupt

428 Computer Architecture

vaguest The mask register can be programmed 10 disable joy | ath
SEE wie a Hgher-prioriy device i being Serviced, In agua! Ager
a iy hat permis high prirty device interrupt he frst position

‘establishing pr
Th

wer-priority devic
pt last in the chain. E

de are connected serially

e priority, which is ke

Poner priority device is being serviced. Howes de three ey 5
SP sho the prono for a pie of four ite gone Pen de un
has an iru register whose individual Bits are se by seat dome wal deves and forms a wit

aulearedby program instructions. The highest prioriy ven o ep

ik because tis a high-speed device, The next priority is given thes JE eve Sa jables the int

followed by a character reader and a Keyboard. The mask register pr
ber of hits as the Soreerupt ;

pert are
ea i

ae ha pei van [en By enabling he interruntaekngw lle he, C dstoan
essen wi [oman request, Ti Signal feed by device 1 ts PU (pinyin
signal passes onto the nent device through the PO

rt snowed
Te nunonly vice | is no requesting an im
erp blocks te acknowl

is | ga igh PO output Ten proceso town
vmiptyeetor address (VAD) into the data bus for the CPU to use during the

bitin the mask register by
means of program Printer
instructions. Each interrupt gear] y
bit and its corresponding

mask bit are connected to

ep pt. When

signal from the

Kestonrd 3

an AND gate o generate the

reap cycle
four inputs to a priority u 4 Processor Dat Bus
encoder. In this manner, an m
interrupts identifico only if 1H 4 YAD van sans
its corresponding mask bit Dake! Dei? Poke

a Dil ie ? to es

The priority encoder 3 INTACK
produces two bits of the from CPU terrapt Request
vector address. that is Rd | ru
transfered to the CPU Fig. 3.16 Priority Interrupt Hardware Servant timer INTACK

the con, an Iterut tha is not masked takes place, another, output
he encoder sets an interrupt status Mipalop IST. Interrupt enable fir‘
{EN can be set or cleared by the program to provide an overall conto
ihe intemupt system. Outputs of IST ANDed with HEN! provide a o0
Ce a a CPU. nero! ached INTACK sign fe
U enables the bus buffers in the output re ector addres "4
es put register and a vector add

Fig. 3.17 Daisy-chain Priority Interrupt
PO output o inform

A device having a 0 in its PI input produces à 0 in its it
“ower-priority device that acknowledge signal has been blocked. A device.
cagan interna ving in Pina late aks
Ken by placing a 0 in its PO output. When device does not have pending
Fig mos itsends the acknowledge signal to the next device by placings} i
apa. Hence, the device wth PI | and PO = Dis the one withthe

42. Write short note om datsy-@haining priority

(RGR, Dec. 2004. 2006, Mer Fi wich is requesting ca ie q, and he device places is VAD onthe
i | vesting an interrpt, and the de AD on he
Esplin daisy chaining priori wt ne ane sar e highest prri He”
Plain daisy chaining priori interop, (RGR, Dee FR hich ee sin rangement the highest ihe CPU. TRE
' i eeeives the interrupt acknowledge sit

Briefly explain daley-chaining priory ; the devices fom the ise poston. te lower iss priori

x prior method of imerrapt wh Theives spé dates wien

Gt June emo must be cade vin sede: SR NE

Explain day-chaÿ se sane -chaining arrangement is shown in fig 3.18. Th

18 priority for data transfer. (R.

126 Computer Architecture
mask register can be programmed to disabl
de iron vie is eine serviced,

vide a facility. that penmits a high priority device
were device bin serviced

Fig 2.6 shows the priority logic for a system of four intern,

{thas an inerrapt register whose individual bits are set by externa)
and cleared by program instructions, The highest priority is given to hoo
‘isk because itis a high-speed device. The neat priority i given to
followed by a character reeder and a keyboard, The mast i
same mumber of bis as the

I ove
evied In gi")
inept

request. The
interrupts whil

Interrupt

interrupt register. It is Raper
passe setorreset any guy Ty

Bi m inc mash register by

means of program Petr
A y

bit and ls corresponding ‘
mask bit are connected 10 Mesboard—| 3

an AND get generate the

four inputs to à priority u

K register pn

haining me lishing,

iced serially: The devic

Ineruptare conne

fist position,
which is kep

owed by lower-priority

the device

henveen three devices a

is imerrupt 5
fate and enables the Merrupt input in th
Y are pending. the intermupline remains in the
Pare identified by the CPU, This is &
e request This signal received by device 1 at its PI (pois in)
he acknowledge signal passes onto the next device through the PO
ey out) ouput only if device 1 is not requesting an in When
pret rasa ending interrupt. it blocks the acknowledge signal from the
vice by placing a 0 in the PO output. Then, it proceeds to inset its own
pt vector address (VAD) into the data bus for the CPU to use during the

se?

mps cycle.
Processor Data us

u Peery encoder 3 INTACK À
pepa: Interrupt Acknowledge AA

Fig. 3.16 Priority Jmertiipe Hardware
ne Ue an ier at ot masked uk :
Encoder sets an interrupt status flip-flop IST::Interrupt enable fi!
he iterapt system. Outputs of IST ANDed ith TEN provide a €
Pe ehh CF emana INTACK sina
U enables the bus bullers in the output po a vector
is kep into data bus €. Pda

$ placey another out}

i

42. Witte short note om dais haine priori
RGP, Dec, 2004, 2006,
Explain de; chaining priory inerrupe arn, pee
Res : or
explain daiy-chaining prior method of interrap +
GRY, June
Explain de i je +
Plain daisy-chaining priority for data transfer. (RGP?

“Via ty

pr

sh bus

Fig. 3.17 Daisy-chain Priority Interrupt
A device having a 0 in its PI input produces a 0 in its PO output &
Frexlwer priority device that acknowledge signal has been blocked. A device
Ssingan interruptand havinga | in its Pl input, will intercept the soa
¿y ne a0 ins PO oupu Wien dev dos ne Fed
Si sends the acknowledge signal tthe next device by placinga ini
E Tad PO 2 Os the ne wi ie high
WY Which is requesting an interrupt, and the device places is VAD on ds
sce quae daisy-chain arrangement, the highest PHY 70%
her „ch receives the interrupt acknowledge signal from The

She device is from the first position, the lower is its cane
device sts its RE

inform

Ces

CPU. The

AU th devie
Ine ar logic that must be included within each devio WR
Sy-chaining arrangement is shown in fig. 3.18. The d

choeurs
Une 129

| jah, INPUT-OUTPUT PROCESSOR or)

or inverter, a circuit which provides ih.
When PI = 0, both PO and the

mern

Are equal to 0, respective ofthe value of RF. When PI= ae
den PO = À and abled. This condition m N rite short note on DMA. June 2005, 2
when PG 2 and à in aD m u rl

scknowledge signal so the next device through PO, When PI > Pa
the device ie sotive. This condition enables the vector address forte À
by placing a in PO. Mere, ts assumed that each device has it

west addross. After asuficiemt delay, the RF flip-flop is reset tye

the CPU has received the vector address,

paris DMA ? (RGPT,, June 2016)
ns The dts transfer between Alfät storage device such as magnetic
a memory is often limited bythe speed ofthe CPU. Removing the cP
ba path and letting the peripheral device manage the hs
pam could improve the speed oßfransfr. This transfer technique ic knoe
Feet memory access (DMA), The CPU is idle and has no control of the
any buses during DMA transfer. To manage the transfer directly between
E10 device and memory. a DMA controller takes over the buses

Y

E | or aa

del Priority Out 7, What is a DMA transfer ? Explain in detail h is
Fr: D 20 À 947. Wha Is ‘plain in detail how this is
trom Dove rmplished, (RGR, June 2013)

rls PRET FO Fam) ani Refer to 0.460

ae ‘TheCPU may be placed in an idle state in a variety of ways. One common.

= Le E derrota tug sed ou

vertes 1} 0 1 hagais Fig 3.19 shows two control signals in the CPU that facilitate the

‘am Ini te om. MAMI Te bcs guest (BR) inp is wed bythe BMA controle

Fi. Oe Stipe of the Dalyrchan Prov are, EE CPU to reliquis contol ofthe buses. When ths np is entre,
DFU terminates the execution ofthe eurent insrutin and pl

ta bus, and the read and write Ines into a highimpedance

‘open cireuil, which means
ificance, The

the

2.43. Explain polling and daisy-chaining methods for estab
Priority interrupt, RG PV June

Ans. Polling ~ Refer 0 Q.36.
Daisy-chalning Method ~ Refer io Q.42.

impedance state behaves like a
4e output is disconnected and does not have a logic
"activate the bus grant (BG) output to inform the external DMA that the
nse inthe high-impedance state. The DMA that originated the bus requ

Tew take control of the buses to conduct memory transfers witho
or intervention, When the DMA terminates the transfer, it disables the
routs line. The CPU disables the bus grant, takes control ofthe buses,
"ums 10 its normal operation.

QM. hy sp M.
2 rior handling desired in interrupt controller? Y
do the different priority schemes work ? GRY, June À

Ans. Refer 10 Q.36, Q.ilfand Q 42.

ind. hat do you mean Bic $ Explain the vario ine
ng techniques (RGRK, Dec. 2008, June À

hme inert Refer 10 Q.35. co aus ee Address Bs
Interrupt Handling Techniques oh — {un sgh tmpetnee
Aécliniques are '& Techniques ~ The various interrupt bi aus Le mon E
cm Sa Ru
@ Polling - Refer to 0.36, oat a rope rat [hu
Le ene

te tz Priorigy Interrupt = Refer to Q41 =
D Datsy-haining Prior
D Daig-chaining Prlority— Retos to Q 42 Fit. 3.19 CPU Bus Signals for DMA Transfer

139. Computer Arentecture Uni 495
the DMA cakes cont! of he Bus system, Ht com
E ee can be made in several way
Ih ane memo; The anse can be 35.
sil te Mek sequence omsisingoFa number of memory worg UE
hurt wile the DMA controller is master OF the my =

‚essor sends HLDA (hold acknowledge’ back tothe DMA

(a THe bus is disabled. The DMA controle places the curent
LB register, such as Ihe address register and counter onthe
fs ems a DMA acknowledge to the peripheral device. The

lt,

usé a blo

dia vansmssion
andere. An sltemutive technique called crcl stealing alloys y

me data word at a time, after which it must aye

ia coins mignon
ds mode of mansfer is needed for Jast devices such as magnetic «YP pos and Sac the DMA transfer.
anna be Sopped or slowed down Until an nu RR qalereomPICH a

ie, remit between the interrup initialised VO and direct

se Dil (RGPS:, Dec. 2011)
acces

intl to tri

e het the CPU. The CPU merely delays its operation for ya, e exe inialised VO, a programisues an 1O command and ten
¿sete to alow the dret memory VO transfer o “steal” one mem sp execu, unl its inte by the TO hardware to siga ened of
y foie 0 he other hand, in dire memory access a specialized 10

48. Differentiate been WO program controlled transfer y
anf. (R.GRE, Jind mi
Ans. With programmed LO, data are exchanged between the pug 9. Explain wile suitable
and the LO module, The processor executes a program that give y oler. e
contro of the LO operation, including sensing device status, son do ou mean hy initiation of D

diagram the working principle of DMA
(R.GRY, Dec. 2008)

controller ? How does

wi command, and transfering Ihe data % e

jor work ? Explain with suitable block diagram.

In direct memory access (DMA), the VO module and main „pl toller work EN (RGPK, Dec. 2009)
exchange data directly, without processor involvement

249. Why are read and write control lines in a DMA cos

Aidireconal ? Under what condition and for what purpose are they

Or

ln vetas example the working principe of DM Aconote
a É (RGP, June 2012)

inputs? Under hat eondon an for ha purpose are they waded or
RE ba? > Desana explain ypica block diagram of DMA. (RGP, Dee 2014
o

An. When the CPU communica e i 7
a ammnicats with hDMA onl Dar with e help of block diagram. (RGN. Jane 2017

and write ines are used ci 3
re used as inputs fom the CPU to IhelDMA controle 5

When the DMA controller communicates with memory: he va, 4% Te block diagram of a typical DMA contollris shown in fig. 320.
‘Ft lines are sedas cups from the DMA 19 memory. [le unitcommunicates with the CPU via the data bus and control lines. In the

Thus; the read and write lines aredirctionalina/DMA contrlkt | Mlewpey<——— — —

Ares Bu Butlers

50. Why di À
RR BI iy ies DMA have pririg over the CPU wien bot ref Du tay [Dates
7? Explain. (RGPY Dec. 2006, 2007, Junt Butters

Ans, The CPU can vai
cherie ui t for iching instructions and data {rom | mus
y | da len

den Renter

Set ns
Werd Coan Retr

251. Explain he responsibil i
PE a fi Pensibiliies of a wpical DMA controll. | ey
Mets oF typical DMA controller are asf"

fi) The VO devices reques ni
line ofthe controller chip. PMA operation through the DNA

Gi) The controller ap
CPU re Mi activates the CPU HOLD pin, ee
Fig. 3.20 Block Diagram of DMA Controller

ager

DMA Rea
DAA amuse 1 0 Poke

12. Conipirtr Archiociurs

en bythe CPU through the addres blocks of date necd 10 be
DMA, the kegiwets are chosen by the C Sus by ince ed 10 be
{REDS (DMA sees) nd RS (eter sele inputs. The RD eae? MW unit may be provided to enabe
{ge ina te BG 8 a) oat e cc rk hs
en A registers through the data b my,
an amant withthe DMA reiner hough us ton the CPU. This approach calle des À
sr wre othe DMA ress JPG 1, then CPU as ring Se fa li Gamo registers MO ares or
and the DMA can communicate directly withthe memory by "Up lee ou sr, one fr nara

nit 133

‘wansferred at i

Branson of à bg de

k OF data
Without continuous

address inthe address bus and activating the RD or WR cone nny ass cores conan Gem] € Word coun Aho
prescribed handshaking procedure the DMA communicates wi Fe ea cua pe aa ston be primed
peripheral through the request and acknowledge lines fe mo complex devo en D es arr

DMA controller has three register an address register, a word count o be needed o e E Sis coller ri
‘anda vonurol register. To specify he desired location in memory, the ag e Pt for initial Program contr
contains an address. The address bits go through bus buffers

into the acer gented 10 the bus and allocated unique addresses,
‚Ars est i increieted aller cach word at is transfered 10 nate 10 device interface

Anne of words be tened are kept inthe word count register Tig PO Fig 3.2 uate an example of a DMA controller used in conjunction

5 decremented by one afer each won! transfer and intemally tested for ef gah two HO devices, a disk drive and a high-speed printer. In suc

a era specify conto register. Inthe DMA aletas far i said to provide two DMA channels, The registers required to

reas onic reiten. Heoce the CPU can read from or ur hie befiemany addtess the word ‘count, and so on are duplicated, so that

DMA registers under program control via the data bus, As betised with each device. In addition, a connections also provided
Fix the OMA is initialized by the CPU, After that, the DMA

pivgafrexcichannel between the DMA,
gontinves to tansfer data between memory and peripheral unit uni à

Senierandone ofthe VO devices, [Dr
HOSS transfer. Basically: the initialization process is a program cons Tp initiate a DMA transfer of
FO instructions, which include the address for choosing particular DMA,

tatrcen the disk and the main
DMA by sending the following information ir

ol. py
ith the Ber
ers must be

they should be
as in the case of any

ase the

Highspeed]
The CPU inutiatizes the

A. O Memory ade
cei the mode of wafer auch ead err (), Memary adres
start the DMÁ transfer, |
The starting address is pre in the

trate
Bey, à program writes the pa, T
the data bus | flowing information into the T
nr ang address of the memory blo where dane à the DMA channel
Available (for ead) or where data are to be stored (for write) nid othe disk - cre Neer)
Gi) The word count, which is the number of words inthe memory 4

Fig: 3.21 Two-channel DMA Controller
de _ (il Address of data on the disk ;
Na un ee (iv) Function to be performed (Read or Write
d in the word cou register, and the control intonation in ih Then, the DMA. las ceeds independently to implement the
Jen es Income CPU stp communicin Jj, o specified I ne comes o he dk ait chen in
34 What a Dita à po in the status register of the DMA controller, The status Peer
"ar is a DMA scheme of data transfer ? Discuss is 0 au conzin information indicating whether the transfer occured cores

(RGB, De "Peers vere enn unter
Ans. Reter to Q.46, Q.47 and Q.33. A
0.55. What ls a DMA com

ested the
afi {til the DMA transfer is occuring the program cee and
"roller ? How it transfers data in a © Hoga Sano! continue However, the CPU can be used o execte anales
tem? White in shart. (RGPY, Jun” am When the DMA transfers completed, the CPU o
or Ae ae ht requested the tana. ste rspunbiiy of epering
ie requested the sto tar anale I
Fra between memory al D aaa e cc str aer

y B sen requested to do
(R.GPV, Dé E Fa yet which initiates the DMA operation when re

Explain how the data
ing DMA controller.

184. Computer Architecture
ter the transfer is completed, the DMA contro

ering |
ob pra A anal on the bus, known as pue lah

he

mens nl
ip The conti activates this signal atthe amo timo yy
Fey it in is EU rege. À

feces the main memory atthe same time, poet
a OMA comoller ry to acces he main mem oe
A us special seul called the bus arbiter is provided to coordina
aes tal devices requesting memory transfers, The arbiter impo

arity system. Memory accesses by the CPU and DMA control, a

Tmiensoven with top priority given to transfers involving synchronous y.

spon peripherals like disk and tape drives. Considering that in most cat bs

majority of memory access cycles, the DMA contri

CRU generates 1

Tee real Ananas taie Allemaively the DMA ra
re tht ren o e mal many to inate a bloc ol
"ito een. Tiss eed 1 a bert mode,

0.56. What are the different methods of DMA transfer ? Explain

AGP. if

actual process af direct memory access. June 2
or

What are the different ppes of DMA techniques ? Explain the k
principle of DMA. (R.GPY, Dec.

‚Ans. There are three basic types of DMA, which are as SOlIOW8,

(1D: Bloch-tansfer DMA ~The DMA controller Chip takes tl
from the computer to transfer data between the compater memory ad!
device. The CPU has no access to the bus until the transfer is compl
During this time. the CPU can perform intemal operations that do not et

bus, This method is popular with microprocessors, Using thistechnique, Po
of data can be transferred,

i) Cycle Stealing DMA — Data transfer between the com”
nory and an VO device occurs "ona word-by-word basis. Typically *
CPU is generated by ANDing an INHIBIT signal with the system clock "|
ne frequeñey as the CPU Elbck,

Interleaved DMA - The DMA controller chip takes 9°
bus when the CPU is mot using it, For example, the CPU does 1]
the bus while incrementing he program counter or performing an ALU oF
‘The DMA controller chip identifies these cycles and allows transfer 4]
between the memory and YO device. Data transfer take place over a Po
time for this method
Also, refer to (9.5.

systen

Haras seing” memory eyes from the CPU enge

Une 135
are different modes of data transfer >

what 5 Explain the DMA
O ra Wht men tes i
sro? (RGPK:, Dec. 2012)

odes of Data Transfer — Refer to 0,56
ps.

0% piagram of DMA Controller — Refer 0 0.5.
Bi Transfer ~ Refer to 0.56 (i
Bloc

st pra the lock diagram of DMA anse in computer stem and

M je CPU is communilled Wthe DMA by the data bus and address

man interface unit shown infig. 3.2. activates he RS line and
e DMA has itn address. The CPU can initialize the DMA by the
pin. arts the transfer between the peripheral device andthe menor.
are DMA is teotived the Stat control command, The DMA controler is
5 ne BRline ithe peripheral device transmis a DMA request, nfrming
A torelingush the buses. The CPU outpuls with it AG ie, informing

FM orbs ar diable Then the DMA ps th
me aw mes

RD WR Address D

ead Contra]
Write

tal

Data Bos
{addres ae

Select

| TEEN DMA Acknowledge}
[DM acom
bs Ps
[RS Direct Memory Peripher
pear oe
LCR ES |_owa nesses |

clar Are
ee eier in ie odes, initiales the WR or Rp ,
es visgeto the peripheral device, Inthe DM sex
a ae idieconal The direction of transfer"
os. The RD and WR a output line from the Daya
er Ber U peris read or wre operation fr the data pe

‘communicate with the ine

ths lee read if the peripheral device is received a DMA chu

Therefore the DMA manages te read or write operations and the ag

Then the peripheral device is communicate,

ed fr be
Sy de ass for cc anse bet

CPU is momentary disabled.
(0.59. List the features of 1OP.

3049. The Inte! £089 isu general purpose LO system built on a single y
chip. co independent 1/0 channels with DMA capabilities are provides
EN

operations, The 8089 is

el Attention

mal DMA registers when BG is equal ig „7
Tp wor inthe ata bus (or rte) or receives a word from g,

the two devices wh

(RGRY, Dec. y)
Ans, The bisie features of an 1OP can be illustrated by using th yt

‘contains $0 different types of instructions for performing efficie

‚clorm ther processing tasks, such

h as arithmetic to
in das E
de translation.
and ©
in Mer WAIT, ATTENTION nage
parameter re 102
SETUP: Setup OMA contrae

10 program execetin,
Send command (9) 6 LO devi

SEND: Tam rds
[omo tt FR
E dts the goo SPN
tor Progra End 10 program ten ge SETUR
EIT Pic erminte Sams tO,

end:
Bo WATT,

DMA Acknowledse

Taterrupt Request
Attention.

dircely compatible with the
Intel. $086 and 8088 16-bit
‘microprocessors. Fig. 3.23
Shows a typical 8086/8089
configuration block diagram.

Figs3.23
2:68. What is the function of Input! Output Processor) ? Es
rt lll 3:
or
(GEN, Dre, 2003, Magic 2006, Da
ÉS

Write short note 0

What is an IOP ? Ex
CPU and FOR
Ams. The input-output
control methods An
‘access capability that communicates with 1/0 devices. In this config”
the computer system can be divided into a Sao and a nun
Progessors comprised of the CPU and one or x
care of input and output tasks, relieving the CPU
involved in VO transfers. The JOP is similar tou
10 handle the dewils of VO processing, Unlike ty
setup entirely by the CPU, the
JOP instructions are specifically designed tof

Processor (10) isa logical extension of

from the housekeepit#®
CPU except that it isd

tate LO transfers. Furtbe”

plain sl procss Sfeommtunicaion be br
(R.GRY, June esc

IOP may be classified asa processor with direct he Entacknowledge I
ru

a
more JOPs. Each IOP Poe, the

de

SSH ot the CPU by activating an INTERRUPT
1e DMA controller that fa by =

IOP can fetch and execute its own ins" RR O.

| sf the TOP and its interaction with the CPU,

@ vom
10 Deko
Fig. 3.24 Computer Containing an 1OP (a) Block Diagram
(0) CPU-IOP Interaction
The bock diagram of a system containing an 1OP appoas in fig 3.24 (2)
PoP and CPU share access 1 a common memory (N) via the ssi as
JTcommon memory (M). stores separate programs for execution by the CPI
be lOP:itals contains a communication regen {OCR fer passing information
ts frm of messages between the two processors. The CPU can pce there
rater ofan 1O task, for example, the addresses ofthe 1O programs o de
te and the identity ofthe VO devices to be used. The CPU and 10P a
site with each other directly via control lies. Standard PMA or ds
“ > are used for arbitration of the sytem bus between Y
ROCF, The CPU ean atract the attention of the TOP for example «ie
San instruction like START 10, by activating the ATTENTION Hn
{OP stars execution of an JOP program whose specifica

ts the
ps umunication area. Likewise the JOP attracts
PU by nef an INTERRUPT REQUEST scan

responds to the TOP «ding
2a (6) summarizes the overall

pte an interupt handler that ypially
Program for the TOP to execute. Fig.

430 Computer Acne

compare and contrast DMA and VO processors,
(Qibl: Compare am ee
Ani. Refer 16 Q.38 and Of. nig

NUMERICAL PROBLEMS

y 256 words from a magnet
9, ti necessary to transfer 256 etd
daemon sing from address 1230, The transfer à by yen
MA controller.

MAC Give the initial values thatthe CPU must transfer to th d
controle.

(ls Give the step-o-siep
input of the first mo words.

count of the actions taken dur,

‘Sol. (i) CPU initiates DMA by transfering ~
(a) 25610 the words count register.
(6) 123010 the DMA.
Le) Bits o the control register to specify write operations
(i) (8) LO device sends a "DMA request”.
(b) DMA sends BR (bus request) to CPU.
(e) CPU responds with a BG (bus grant)
(4) Contents of DMA address register are placed in address
{) DMA sends"DMA acknowledge to VO device and en!
the write conto! line 10 memory
À Data word is placed on data bus by VO device.
(8) Repeat steps () o (g) for each data word transfered

eles. The words are assembled from a device that transmits chars
te of 2400 characters per second. The. CPU is fetching and exec
er ai an average ate of | milion instructions per second By

“ech the CPU be slowed down because of the DMA transfer ?
(R.GPV, Dec. M

{fot CPU refers to memory onlan aveFigg)once (or more) even 1

(ans
Characters arrive, ohee every 172400)

Two characters of $ bits each iles

Prob.10. A DMA controller transfers 16-bits Words 10 memory 54

are packed into a 16-bit word “|

t

R MEMORY SYSTEM, MEMORY HIERARCHY,
IAIN MEMORY = RAM, ROM CHIP, AUXILIARY AND-

# ASSOCIATIVE MEMORY

94. What do you understand by memor
das. Memory isn integral part of a computer syste ts primary Function
tual! information required by the system. Typically. a memory mit hold
sas and data. A computer designer bas 1 pay attention othe memory uit

TE ace the memory system cost i a significant ration ofthe cost of he
{Alem The system performance is largely dependent on the organization,
impact and speed of operation of the memory system.
Qh Explain the terms destructive and nondestructive memory readout
(RGN, June 2010)
Ans. In some technologies the stored information is los over period of
nées corrective action is taken, Three characteristics of memories that
da information in this way are destructive readout dynamic storage and
‘ily. In some memories the method of reading the memory destroys the
el information. This phenomenon is
) filed destructive readout (DRO),
Avis in which reading doesnot affect
E stored data have non-destructive
ad N !
Eu (NDRO). In DRO memories each

DRO
Memory

ne Per mus be followed by a wi
cha that restores the memory’s u
ara State. Ths restoration is carried 2

no Matically using a buffer register,

* 416.67 = 833.3 pace bite get fig. 4.1. The read transfers
The CPU is slowed down by ne y PREP at the addresse ay hae
™ bY no more tha Bouin ty essed (shaded) Rafe
(18333) “100 9.12% 10 o, e buffer register where iin ME
gh tide vagos mal devices Thecontets 77, 4,7 Memary Restoration in à

‘automatically written
Sriginal location.

N o he

de

Destruciive Readout (DRO) Memory

[40 Computer Architect

nit 14

aot Morlevel hierarchy of fig. da units for
rm back arom of memory Hierarchy in a comparer q a el hierarchy olé. $21) is pis f cry
“plain tn Do. Re ty ees me VAL storing in & type known as a split cache beca
Or RL, Deena ans lr Sonne ie (the Leache) and data (the De
$ E example [fig. 4.2(c)} has two cache le (te
What is memory hierarchy ? RGPF, Jun pe ir ra )] has two cache levels. hat of the
Or 2008 eg sii De $
mdr hierarchy ? And explain the i eo following relations hold betwekn adjacent memo

har ls memory hierarchy ? And explain the need for ix, Nomall) ie memory hierarchy acent memory levels

(RGRY
An Merry uns of computer form a hierarchy of diffrent me
mener iin some sense subordinate 1 the next-highest meg

the hicrrchy. The object of is organization i to obtain a good trade-of ha
tng

e abge capaci: and perfomance for the memory stem a a wie

reci Flow
Dat Pe

PL secondary
Memory

crv

[2

Ma

Secondary
‘Memory

fh i
neta PT] Male 7] secontars
so} ite Lemon |_| Nemo
af? D
Me
©

Fig 42 Common Memory
on Memory Hierarchie wth) Two, 6) Thre, and () FO?

Let us consi a
considera general “leve! system of n memory typos (Mir N

M). Fig 42 illustrates some exa
; amples with =2, ical ch
employed in these hierarchies are pea EM ”

SN

oe
Mir og pr bit Ci > Ch

access time ta, $ Laja
Storage capacity SE Say
trenes in cost ness me, ad capacity between and, cn
des ofmagnitude- Gonsdeabe system eos ae dette
ale CPU from the differences, therefore almost aways ses a
pensive memory space and rarely sees an access time

nee and inex
ato? Mp he first (highest) level ofthe memory hierarchy
fu and other processors can communicate directly with My only, My

sn.

Etica with Mz and so on. Consequenty, for the CPU 10 rend
an eld in some memory level My needs a sequence of data transfers
ca My = Mis Mica: Mi Mia 37 Ma Mi Mas
eM,

Ancxeption is permitted inthe ease of cachos; the CPU is designed to
pes the cache level (s) and go directly to main memory. Generally, all the
heßmaion stored in M at any time is also stored in M; ut not vice versa

Wileerecuinga program, the CPU generates a steady stream of memory
Ds Ar any time, these addresses are distributed in some manne?
leg the memory hierarchy. When an address produced thats ment)

E only to M; where i # 1, the address must be reallocated 10 Mi. the

loth memory hierarchy that the CPU € This relation

jan access direct

Hess involves the wanfer of daa between los M and Mi °
ves slow process.
fora 1
‘ora memory hierarchy to work efficiently, the address produced by the

ble. This approach needs that
information can be
LU. When the desired

st must

‘ey ‘ra be found in My as often as possi
Reach cn be lo some extent predictable so that
nt before itis actually referenced by the CPU. Witt
Sot be found in My, the program gag is meen 2
Feet uni proper reaoaion of ore % done

121 Draw the memory hierarchy: RG

As Baer wfig42,Q3.

py, June 2015)

142 Somputor Arcilecture
Ä i
0.5. Drum block dlogran of memory hierarchy of comp, y dee difference between static and drmamie Ran,

AN gic ET (REPL, dune 2007

= ant Riferto Q3 E Dee ee
note on DRAM. GP, May!

6. Wa main memory Y a 0

ee wo vr, aida SIAM aa

® ing cres similar to be

may u harto the asie D flip-op, They hare
ee piel woes Ml mou ene

are popular-as level 2(L2) cache x

«dynamic RAMs (DRAMS) do not se flip-flops, Adynamic RAM

re. The memory unjt communicating directly with the Cp
a thei emo Or primary memory ish

(0.7 Give.one example for primary and one for secondary me,
RGBE, Sunt

Ivory

‚Ans. Primary Memory - RAM and ROM etc. ont ‘h offawhich eontaining one trar y
a de Sake nal We o, each of which containing one anssor ad a ty acer
Secondary Memory ~ Magnetic disks and tapes. e can be charged or discharged, thus allowing 0's an Us 1 be

lee charge tend o leak out cach singe bit na yma RAM

Me feshed or reloaded every few miliseconds to prevent the data from
ray Because externa logic must take care of the refushing, dynamic
reel more complex interfacing than that needed by static RAMs, although
any applications. this: disadvantage is equalized by their larger capacities.
Som: DRAM need only one transistor and one capacitor perbit (in contrast
sq tinsislors per bit for the best SRAM), they have a very high density
dy ra Meme spi memory are CD-ROM, WORN us or eip)- Due to this reason, min memories are easy ava bu
ie {eATRAMs. However, this large capacity has a price, i, DRAMs are slow
Q.9. Write short note on RAM. “fasaftanoseconds). So the combination of a SRAM cache and a DRAM
fit emory attempts to combine the good properties of each.
up af RAM integrated circuit chips. Originally, RAM Mas used to ree Sevealof DRAM chips exist. The oldest one stil in uses the FPM (Fast Page
random mm bl How is wood o Tea ena gail DRAM is intemal organized as «mati of bis anit works by having
Programs and dote that are subjected to change. Since the RAM e else However, FPM DRAM is being gradually replaced by EDO (Extended
‘contents are desimyed when power is turned off” fou DRAM, which allows a second memory reference nat before
A RAM chip is better suite _ pcttvious memory reference has been ended (completed), This simp!
Sige Gr one Gaetan pisar a Tor communication With the CPU. ¡fisio does ia ps do “one faster but does
such faster and more expensive ines ae GA hen needed. RAM he bandwidth healthier, giving more words per second
Baden gg Pet FP and EDO chips are saynebonos, he al nd ds
ice modes, These menorie tot driven by a single clock. In contrat SDRAM (See
ee id ES ae Galle semirandom or die! py fs and dynamic RAMS which ter byosinge
emir coa a eae head fr each track i he Tp lock. tis most oftenly used in large cashes and may
$ memory; There are important character À. chnojogy for main memory.

changing stored information F

A + nation. Far instance, a read/write memory allows PEE: Qu, py

pot aad ei e But, this results in igh 4 programs seh, fal te short noe on RON therwiso, Th
5 a relatively ineypensive ROM. Do ne ed i ys a en EE

QE. Give one-one example for semiconductor, magnetic an
memory. (RGB, June

Ans. Semiconductor Memory — There are two m .
semonducior memory ~ RAM and ROM

Magnetic Memory = Types of magnetic memory are har
disk and magnetic wpe. = rn

‚Ans. Most of the main memory in a general-plirpose Computer i

öl Ihemorieshave both sequential andre)

E

"Sb,

dei Come Achtedhre

vay eng tor expose) sue. THE only possible

Be na ROM ito els te ee chip
=” ROMs are much cheaper than RAMS when ordered in high

suns rot making te mask. They ae, however nenbie

i enge after being manufctured, nd the tumaround

plaga order endreeisin be ROM may be weeks. For making y
PA on ROM used pret, the PROM (Programmante gos
mel, APROM is similar to ROM, excep that it can be programms A
Ge et chat be tamaround time, Many PROMS contain an my
ae ide A prtiulr fase can be blow out by selecting is row ang
ep hen giving high vliage to a special pin on the chip. a

"EPROM (Erasable PROM) is te next development inthis srg
inne only be feld-progammed but also feld-erased. When the quan na
(ran EPROM isexposed to swongultrwviokt Fight for a minimum of IS
al de bits ae st to 0. I many changes are expected during mans
cesa EPROM are far more economical than PROMs because y
sel. Usui, the EPROMs hase he same organization as static RAM,
‘EEPROM (Electrical Erasable PROM) is even better than the Fi
as tah be erased by applying electric pulses to it instead of requiring
Se dans be apa 6 ulmanali ligt Alo, angen
an he reprogrammed in place whereas an EPROM has to be insert
special EPROM programmable device to be programmed. The disse
ol EEPROM is thatthe biggest EEPROMS are typically only 1/64 asi
canon EPROM and thy are ony as fs EEPROME ann
ith DRAMs or SRAMs because they are 10 times slower, 100 times

ely Tey ate only used in =
sen > tuations where er nonol

can uth con Kind of EEPROM Kashmir! Unlike EPROM
Ho) os to ultraviolet light and EEPROM which

bl, Mach memory is block erable and retable. Like EEPROM
man san te cad wit rin fein eit

0.12, Write about vari
urious pes of ROM chips.
‚Ans. Refer to Q.11 e

0.13, Write short note o
le on pes of RAM and ROM. (R.GP!
Ans. RAM Types = Refer to Q.10. :

ROM Types - Refer 10 QI

9.14. What is a memory address map ? Explain with an exe

Ans: While designing à comy ef
a computer system, designer must calculo,
amount ol memory needed for the particular application and alloc?

Univ 145

between memory am
amd processor

wry ean be estabite
th specifies the memory address af :
memory address map. This i a pict

for each chip in the system.

sn OM chips
fable wil
es js known as
sp bt address space À
ae ate witha particular exp, suppose th
se PRAM and 512 bytes of ROM. The memory ass map
“on is depicted insable 4.12 The component clara tls whe
iis employed. Hosadecimal address column assigns
valent addresses Tor @ach chip. Address bus lines ae listed
“here are 16 lines in the address bus, but the able shows
o he other 6 are not used inthis example and are taken to be
Is under the address bus lines represent thos lines hat mst
Tee address inputs in each chip. RAM chips contain 128 hytes
dress lines. ROM chip has 512 bytes and equirs 9 address
led tothe low-order bus lines lines | through 7
isessentalto istinguich
ent address. For this

coi
Nor ROM chi

ri
Pin
fecimal equi

Met
id column

pe ir
¡Dies
e. The smal
m
Feonocted 1
Taree seven a
ers are always allo
Sera Mandines | though 9 forthe ROM. Now,
Ma our RAM chips by allocating to each oie
E psclarexample, we select bus lines 8 ‘and 9 to designate four distinet bi
Prion. Hore, i is worthnotieed that any other air of unas hs.
rote for this purpose. Is clear fom the table tha the nine down
tie a memory space for RAM equal lo 2 = 512 bytes. The
aoe isatn a RAM and ROM addres i done with anther bus line
le we elec line 10 for this purpose. If line 10 is 0, (hen CPU chonses à
AN, and if this line is 1 it chooses the ROM.
“Table 4.1 Memory Address Map for Microcomputer
Address Bus

5

Hexadecimat
Address

76 54

10

RAM
RAM2
RAM
RAMS
ROM

0000-007F
0080-0081

0100-017F
0180-01FF
0200-03FF

ed from the

decimal address is achieved ron
nd pment Aas es à
ade sith group can be denote
Men S/OUPS of four bits each so that cach SOUP ated
el digit Piet hsadecimal digit denotes Ines 1310 624 ed

Tange of hexadecimal addresses for euch compo

X's associated with it.

For each
daño Each chip, the equivalent he:
mation under the address bus

316 Compras Arcee

it hot do yon
in the meer

depleted is able 4.2.

ine Memory Map Refer 10

qu

16-hir processor with 32K m,

A mieinony map tn interface to 1

understand by memory map ? For q 32)
rap sá interface to 16-bit processor

Ene, |

RGPE, Mardi, |
te 2

“Table 4.2 Memory Address Map

Component. | Hexadecimal Address Address Bus
3 1615 14 1312,
RATER) 0000 - FFF OK mx
RANGER) 2000 - 3FFF 01% x

RAMS SK) 4000 - SEFF TOR, oe
RAM ER) 6000 — 7FFF Lax xx

DECODER
PS

memory,

216. What is ausitiary memory ? a8

arin!

4 unten tar

drums and more recently optical dl The marc
are its access mode, access time, transfer rat
time to reach & f ig

poe mes
ee wale
ot “fay = E
¡a pe averaue
e ces time. In et
eo y of seek time and wransf
sa so blocks. Arecorblcc
Fram'on auxiliary
1 storage’Ssiems With thei relative advantages and

importan
= apa
orage location in mem
temory and ob
ro-mechanical devices access 1
rate. Auxiliary storm

is logically
onsists of number of words,
semory is always done to enter blocks.

ETE

IE yr. Discuss optical

mages
et rd 9 mn opted mamon a
tn ago medi Js ove be» ris nt
a high capacity secondary storage, because it can store

medium fon
Frage moni of dt ih a Tinted space An aps storage

ssf rota disk, which coated wih thin meta or some

sence tae Nah reflective Laser Dam technol is wed o
ding reading of data on the disk. Duc o this, optical disks are also known
pe disko or optical laser disks

dvantages— The advantages are as follows
N) The cost-per-bit of storage for optical disk is very low.
{i) Theuse of single spiral track makes optical disks anideal

etm for reading large blocks of sequential data such as music
(ii) Duc to their compact size and light weight, optical disks are easy

bine, store, and port from one place to another

Disadvantages - The disadvantages are as follows

{i Itisead-only (permanent) storage medium. Data once recorded,

cat be erased and hence, the optical disks cannot be reused

in, 9 TH data access sped for opie dss 1 er than magnetic

ds, requires a more complicated deve mechanism than magnetic
0.18. What are e Describe magnetic apes

‘ lat are magnetic storage systems ?

id magnetic disks with their relative advantages and distante

lefined as th
th the help of ma
net pes. mE
tens are non-volatile and

s(t Magnetic storage systems are à
“an ‘data on a magnetized medium will
Md of magnet storage systems ae ma
dks nn ge systems ae ma
vide, oppy disks. The magnetic storag® len
wp cts to store data, Da cun be ecc randomly as sels
"al. When dato is accessed sequentially the access EE a
unl to the searching point Tal si the searchin Ps ne.

fair Computer Architecture

bolis dong legs. and iF The searching point is (ar, then the acc,
‘foe la venas ben daa Is accesed randamly, the acer ioe
Magnetic Tipos iis

mas storage devite, and
tied as a backup storage.
Magnetic tape sone of the
‘most “popular: storage
rein Tor Loge. dot that
aro sequen ces and

E je rape is a A ie
en phe Fig. 4.4 Magnetic Tape Reet
sail) ly 12 inch wie tf coated on one side With an ing,
‘ata whic an be mua. The ape bon ei stored un
48.240 fet ora sl cate or cassete. tis similar o the tape ea
Ap record except chat itis of higher quality and is more durable. Like rem
Spt, Computer tape ean be erased and reused indefinitely. Old d
animales eras us new data aro recorded, in the same ares,

Advantages of Magnetic Tape —
(3 Unlimited Storage -

‘italy unlimited hecause we can
‘ur da.

The storage capacity of a magnetic te
use as many tapes as required for recon

(ii) High Data Density
2.400 feet I
bis length,

~ Atypical 10.5 inch reel ofm;
ig and is able to hold 800, 1600 or 6250 characı

it) Portability — A reel
jon from one place
from one place m another.

Cost - Cost of mi

agnetic tapa
fers per inch

‘of tape is also a convenient Way of car]
do another. It is often used for transforms

‘agnetic tape is much less as comparel®
tet dam seras devices. An aida Gs! BEAL is Ro oe oe
erased and reused: Many times, e
(©) Rapid Transfer Rate —
in exces of | milion byes pa

(0) Ease of Handling
much easier to handle,

ants. Data transfer rate for a magnetic 0*

x second,

UL takesiiuch less storage space and
Limitations of Magnetic Tape —

(No Direct Access —
ice data recorded on tape can
fetvieved serially

Magnetic tape isa sequential access des
not be addressed directly. They can onl!

lata on à pe

be e, they ar more susceptible 10
2 ig, Min cd on-line, ey ae

Units tap
y environmental Problem = Specks of ds ng nem,
Par sl can cs ae ng na ut
qin EME red in a dust free environment x
ks — Wi a Mar ik that is covered with magnetic eating
eatin. Lis a pe af Secondary memory deve ed
gin programs and files. stores information inthe fo al
red needles. These needles help in encoding s sale pure
«egin polarized in one direction represen ty 1
Moresented by 0.
disk can store/a
Ps data
EN than RAM. It's da
slo as compared
ee Sia memory. Ieallows the:
eng of dat and
sie hell of erasing
coding the data as many
del. Fig 4.5 shows
pei disk with sectors and

Fig. 4.5 Magnetic Disk Surface

cid re concentric circles on the magnetic disk, having a common
Aa canin ck record dn The rica mt ae
tiza as sector. The data stored on the osos i the form of very
‘salut, which can be read or written. The size of a sector in a magr
A ce omic ef en i
a td disk, also calle as fixed disk, can hold a lage aman of da
‘ited with large computers. floppy disk, a removable disk wi i
Es sora capacity is used with personal computers
The main advantages of magnetic disks are as follows -

(High storage capacity

ÜD Fat, ee access ath A

(i) Easily moveable from one place another

(is) Better data transfer rate as compared to magnetic 1200
(v) Low cost compared to RAM are
(6) Les prone to corruption of data as compare
Main disadvantages of magnetic disks are as
{i) More expensive than magnetic tapes ‘isan

(Ü) Not suitable for sequential access
(9) Need dust-free environment

ae ositos Arona ne 181

3 a ‚om associative memory: (R.G;
8.36 Write short note pa

Yoel is ¿onsert addressable memory ? What are its advan,

contents

indes
veo pared simultaneously with al stored word

thse thaw

¡econ E
eae) i Oe cp signal. which entes aan ira nn
or © ee pe he M e, If the same Key is used for several ent hy

5 à ith à A pio be es which data field is to be read out. As an example,

ciate merry with it hardware Organizar, „ 16% etermines whic example,

a me meer Ee Tint WN a Re ber Aa ame

ioe (RGRK, June 2005, y, about al Try are needed to compar their keys with the input hey
+ Dec pe memory

mich requires itS/OWn, match circuit The match and select

Or

Mat i associative memory ? Explain the concept of mar. Katar E ave memories much more complex and costly than
ee Or LS | eo the Di circuit for'a 1-bit associative memory cell. The
Esplaln asyociative memory with its. hardware organization, p, À fig 7 95 fip-flop for data storage, a match circuit (the Exclusive
Expicin uve memory IET Organization, pi, © arises a D, flip-flop fox a £ the flip-flop to an external data bit
(he proseiaie fo reading and writing dara in associative memory, gc! comparing the contents ofthe flip-flop to an exten
pon pte) ending from and writing into the cel, The results of à
2 asien appear ‘on the match output M, where M = 1 indicates a ach
pio Woe M asociado memory 2 in match I es no match. By setting the select line S o 1. the ne
a ML Seo. ae Md atdoradireted for bth read and write operations Now da wien
Or ue ie: enable line WE to 1, that in turn enables the
cel by setting the write ena ia
Explain associative memory wth is hardware organization, Explains WO Aue the D Nip-Dop. The stored data is read out via the Q lin
‘he deta read end write in the associative memory. (R.GPS:, June y] OR?
Fa a
What de you mean by associative memory ? Explain i Win à
are. (R.GBV., Dec Mí
Ans. Ths lie needed to tnd an item stored in memory can be rl
Considerably it sav data can he recognized for

Aces bythe coset of the data itself rather PO le
tha by an adres. memory unt actes byl ley
Content is known as an associative memory or Rohn | a
Sören nirenabe memory (CAM) Tai pe I
of memory Hs eed simulan and tn
parallel on the bass of dat em e a ;
Deren e ans of dt cone eater Ian | cis] En es
wa ess ar locaton. a word iy Ne Cre
em asc nen, ot à DL ay Fie 4.7 Asie mais M
en. The memory capable of indigenen | Temazcat : ph ik a de
ed dr be gay [Tem ak omo! ine MK is activated MK = 1) 10 fos el qe
Sd bain ae anche or F7 Eirendenty of the data stored in the D-fip-fop: MK ale AERO
Specified. The memory locates al monto Set of rin eng mm rel
{yeti Theme ae ESTE ofthe fliptiop by forcing ingle transit
Fees ath the pied coment and mars [Bat fragt about 10 transisiors Far more than the sin KR ge
reg 2 Va amie RAM cell. This high hardwan paga
in zu lock diagram afan cie mery Ont pant Memories are rarely used outside cal ie

be combiri
vociativesmemory ti

3-6. Exch unit of stored Fig. 4.6 Block Dinge

A me a
Asociativo cel he preceding type u store
fixed-length word Any sub Mem ve cells of the preceding

information i =
* associative memory arrays. A 16-bit ass

Associati

© ne acord (Bu af d-bi each, $8 depieted in
div dress vi their S lines. AL words share a con

"Gam ins fr cach Hit postion: As aresult an external
‘emai Nimuincously 10 the ith stored bit of ev

48
Mo

|

|

Va
| tek,

und 153
ls are designed so that they can 4

ll
pes be com
de as depicted in fi, 4 be comnectod o fm

1 ND les.
(5 Te reduces the time required to
es =) Tereduces the time required 0 ind the m tore

60. ye memory is capable of Finding an empty amused le
6 When à word i to be read from me
ine sor
of the word, #
e Eplain about ausilians and associative memo
2 (R.GBY, June 2017)

> an associative memo
‘oc part of the ward, is specified SD he

in perso 0-16 and Q19,
“y, Describe by means of block diagram how malipe matched words
ere ont rum an associate memory. (RLGRN, De. 2007, 2009
e maich ToBic for each word can be derived fiom the comparison
inary numbers. Fist, we neglect the key bits and compare

ith the bits stored in the cells ofthe words. Word is equal

11. Fwo bits are equal ifthe are

it the pair of bits in position j are equal; otherwise, x; 0

Fethord ito be equal to the argument in A we must have all, variables

This isthe condition for selling the corresponding match bit m, to
teHoolean function for this condition is
m; = XRO

lcoytutes the AND operation of all pairs of matched bis in a werd

Wenow include the key bit k inthe comparison logic. The requirement is

‘the corresponding bits of A, and F, need no comparison. Only

| must they be compared. This requirement is achieved by ORins

em with ki, thus —

y entes and

bl we have ki 0 and +O wen ot tase

term (x + KA) will be in the 1 state if ils pair © à

Sense Tn a brea cache AND wi a ae

fgg output of 1 will have no effect. The compat

only when ky À

atch logic for word in an associative memory ea
lowing Boolean function =

m= (xy Hk) m Ka) 63

son of the Bis bas au

now becapressed

tk

Fe Gumpader Archnectue Unit-1Y- 188
expression will be equal 10 1 its comespon uate ouput wil indicate hat ro mit cum and tht he
dl be either 0 00 1 erating on he ale wa al yor avaiable in ta. :

notes et inthe concept of ‘asile memory poe ble

07 y i
associative memory page table is aed for effective ston

yi ig £R-GPV, Dec. 2013, June 2000
got maccess memory page table is ot ecient wih respect to
‘ encrally, system With n pages and m blocks would need
rating the AND operation of ln, "ble of n locations ol which upto m blocks wil be marked
ES Ee me tread word i= EM py re and all others will be empty. As an example, consider an

‘The cin for matching one word is shown in fig. 4.9. Each col, y, Aer 1924 K words and memory space of 32 K words. In case
{60 AND ges and one OR gate. The inverters for Ay and K; are neue „ck contains 1 K words, the number of pages is 1024 and the
ir cach voli and are used forall bis in the column. The output $ 32, The memory page table must have 1024 words and ont

fac ter ne

i fe ro si

TE cer ad yl be equal to ! n
iy sub. be orginal definition of 5 the Boolean fp,

an o expressed a tallow $

isn cols ofthe same word o lo the input of à common AND fat nave presence bit equal to 1.Atany given ime, atleast 992
on ne

“riera the match signal for m; m; will be logic 1 if a match occurs ang x

uste contains all 0%, output my wi A
irespove ofthe vale ofA or the wor, This occurence must be“

empty and not in use.
etd organi te pe ube wold bs cons
Aero! words equal tothe number of blocks in man memory. As
a ie ofthe memory is reduced and cach locaton is fully utized.
e e meind done by mens asie mery th
E so es prendo oc ica

‘during martnal operation.
hs el e page number
Te el compar vi pi
e a ‘address. If a match takes place. then the word is read from
‘ceneryand its corresponding block number is extracted,
cae memory of eur word Each ny inte
menos aay soni of wo fils First he bis spec ac
E a mnt sad. sui ins
i
|

to is constitute à el for, AO
ia he block number. Virtual Pare No
des is kept in the argument >
PS Inthe argument register, [101 | tineNemter
ge number bits are compared

Argument Regier

Fit. 49 Match Logic for one Word of Associative Memory

an dt gare on ne ml a enter innere [rave Joao
Fae ae te cen sean ti ofthe mach ere mme Em, Fa |

ith won Swords ar readin sequence by applying a read si H feed out fr
ee ine ws ong Mite ee © Phecomesponding lock
dt ame ces emos du à ble ih eae rá
asked gun ele By ac Si, OY one word may OAT eae y ue, dec ed
the same word position (fase mecting Output m, directly to the read la place à Sass 110
Word wll pro (itead ofthe m register), the content of the ma y y Calo the operating | |"
2 presented automatically a tbe output lines and no speci gett’ to bring the aa

“onmand Suna is needed. Fathetmore, if words having a zero conca “EN ME rom auxiliary Pores. Biel Ne

| Fig, 4.10 Associative

rot

Memory Page Table

NUMERICAL PROBLEMS

Prob.). ove many 138 x 8 memory chips are needed ,
reis capociy of 4096 162 CRE
ok Theteguired memory capacity is 4096 * 16 and the avajlayı
‘ign is E128 à 8,

Now

> Required umber of chips = -Reawited RAM

‘Available chip capacity
512
‘Hence, 512 chips are required of 8-bit each,
Prob. A compuner uses RAM chip 0/512*8 capacity. How many y,
noce to provide memory system with 2K*32 capacity? (R.GRY, Dex
“Sol Required number of chips

1%

s ly
{U . How many chips are needed and how should

lines be connected to provide a memory capacity 1024 byte:
una) How many chips are needed to provide a memory capa
Kbytes ? Explainin words, how the chips are to be connected W the
(RGP, Dec. 2002, June 2008, Dec. i
Sol (i) 8 chips arenceded with addres

& 16% 8 = 128 chips
Probd. Given a 32 x 8 ROM chip with an enable input. Show ¥
external connections necessary to constraet a 128 x ROM with four de
RGRN., Dec AN

heir ado

lines connected inparalel
al

Shäputs Comagn to Ati Chips

|

EN

nes

rom
y

Er -

En =

owt owt
zo te

Fig. 4.17 128% 8 ROM Chip

2 Ompèrs

nie WV 187

> ine short note on cache memory.

33. Wi
Qu. GRU June 2004 Dec. 205, Mayme 204, e213

qn e operation ofenche Memory. (RGRY, Dee. 219
Be ative porns fe progam and dancin be pls ina hs
oh fa exceution tm can be significa decrease, Sicha
oi now as a cache memory hat is inserted beiween he CPU and
O emoryas depieled
an go make is
A ment effective the
nt be considerably
nan the MM. This
ismare economical
Wiese of fst memory
Lit implement the

Memory Access Control

‘and Data Paths 7

Cache

Male
Memory

Fig. 4.12 Use of Cache Memory benween
PAT the CPU and the Main Memory
Ciaceptually, the operation of a cache memory is quite simple. Memory
al éreitry is designed to take advantage of the property of locality of
‘teen Ifa read request is received from the CPU, then contents fa block
«fucmory words containing the location specified are transfered into the
écheone word ata time. When any of the locations in ths block is reference
Et te program, its contents are read directly from the cache, Genen e
Ste memory can store a number of such blocks at any given time. A REP
feaion specifies the correspondence between the MM blocks an AN
act, Ifthe cache is full and a memory word insiuction MEIN cr
in the cache is referenced, then the cache control hardware YC
‘hich block should be removed to generate space for the des La ig
‘otis the referenced word, The collection of rales For NEE
“tis he replacement algerie, ;
CPU does not require 10 know explicitly about the ahr
E not require 10 know exp me ai
Pie ‘makes Read and Write requests using‘ addresses requested
FREE MM. Memory access contol circuit} dem ee operation 3 à
coment exist In the enche, I it does, the RENT cad, ei
med on he suitable cache location. Ifthe PT ec
eet is not involved, When the operation 15 pe
u Seed in two ways. In the first technique, KON ian
Me kestion and the MM Tocation ace updated

Generally, the

existence of

= nan ste words ales

en e ise eche location and 6 merk it as pg
plop loas ibe dirty ür modified bit. The y."
ul aha) Tate, when the block con ee

Me Trac from in cache o make way fora ney

Ya clearty simpler, but it results im nn VU
rte te si, Pa te m men

ma verd
Mase geese NA hen give
men rings cack peideneypetio
Bryden open, ithe addressed word is not in the cache he,

nik ris orate request word s copied from the MM in!
ache. Then, ihe particular word requested is forwarded 19 the CPU tt
uc woid which was requested may be forwarded to the CPU af,
Rede led int he cache. Altematively. this word can be trans
eine CPU we dopn asi is read from the main memory. The latter
Lc Kiowa as load throuch. decreases the waiting period of the cy
aisé

‘Whee the dressed word in a Write operation is not in the cache,
he sofermátio is written directly into the MM. In this case, there isi
sd ventags transfering the lock containing the aldressed word to the cade
Normally, à Write operation refers o a location in one of the data areas fi
es ther than to the memory arca containing program ins
Wheh Write operations are involved, the property of locality of
of as robes in actessing dat.

fll, should be remembered that in the casó of an interleaved menor

© contiguous block transfers are very efficient. Transferringdata in blocks beta,

übe MM and the cache enables an interleaved MM unit to operate ats maxim

Posie speed. Lkiwise block transfers o the cache can take advantage ot
block pr hurt transfer mode available on most dynamie RAM chips
2.24. What are the characteristics Of eache memory ?

(RGP, June 200
Ans. Referto Q23 £
02% Differentiate berween asiociative memory and cache

(RGBF, Dec.
ie and cache memory is given bel

Associative Memory Cache Memory

“A memory unil access by content |

is called nssóriative memory.

fli). | It reduces the time: required to find
the item stored in memory.

D Here, data are accessed by its
‘content

À fast and small niemory $
sat isso
It reduces the average mem?
oe ie clea |
a

“el

poes Pe

where search tin Wise
group of date

J

5 base ch
ls base harter si
fast access timo.

js a cache memory ? Discuss the basic design of c
op, Wheat is sien of cache,
qa. (RGPH, Jane 2008)

is cache memory ? Why is implemented ? (RL Des 2019

Fn “e Memory =Referto 0.23.

ns Cast
Design of Cache = Fig. 4.13 shows the principal components of a
Pony wards are stored ina cache data memory ad are grouped
a pages calle cache blocks or lines, The contents ofthe cache’ data
soil Pus copies ofa Se of main-memory blocks, Eich cache block is
en its block address refered 10 as a
wig care knows lo what par ofthe
nace the Black belongs. The collection

page esses eurrently assigned to the cache,
<i ne noncontiguous. is stored in à
the cache tag memory ot

mple, if block B containing 4, cu os

Basic

ET

For e
ces tag memory and D, is in he cache’s
des memory:
Two general ways of introducing a
fe 414, In the Jook-aside design of fig. 4.14 (a), the cache and the main
ery are directly connected to the sy gn the CPL
cts memory acces: by placing. (real) address A, onthe memory address
tt stan.oFa read (load) or wn (store) cycle. The cache M, mme}
ampares A, to the tag addresses currently residing in is tag memory a
rats found in My. that is, a cache hit occurs, he aces 5 comple Y
4 ad or write operation executed in the cache; main memory Ma TL
led. JE no match with A; is found in the cache, that is, a cache mi
Eu then the desired ‘access is completed by a read or write operat

inc) of data By that
In response to a cache miss, a block (li dat
address A from M, to M, This transfe

Ihe ¿mall block size and fast RAM Aecess a
Aloe the eahe block be filed mas het
Implements some replacement policy such #0
Where to place an incoming block. When Deco
Feed by D, in M, i saved in Ma

Fig. 4.13 Basie Structure of
a Cache

‚che into a computer appear in

stem bus. In this de

fs, aa
seeking ad
cos pag

it: The cache |
ie

Uat es

pen À What general

f plain what Is meant by a cache
he memory ?

bet, re asedio make effective uses of cac

oe ee ecutive cache memory iss Hann

tema i a pr

E pe eine is 1288 * 32 memory. The
oy sit

ey on mony bis are therein the tg, index, ick und word

palo iy What is the size of cache memory ?

(RGRY,, June 2009)

ing Refer to Q23 and Prob.7. da

ak Espai map in él cache meman: (GV, Dec 201)
À Base characteristic of Cache memory is its fast acces time. So,

3 gmation of data from main memory to cache memory is known as

eg proces, When considering the organization of cache memory

memory a mapping procedures are of practical interest

eier ce

¡Peri PIES ENTE Asocitive mapping

ee Ain. Direct mapping

(iD Ser-associative mapping.
02. What is cache memory ? How is it organized by direct mapping ?

LGPN,, Dec. 2004)
plein RGP)
Or E
Explain the need of cache memory in the computer system. Explain
tia mapping of cache organization. (R.GPY, June 2005)

(0) Look-through
Fig. 4.14 Two System Organizations for Caches

Tig. 4:34 (h) shows a faster, bot more costly organization called a look
through cache. The CPU communicates with the cache:through a sepa
focal) bus that is isolated from the main systemibus. The system bu
available for use by other unis, such as UO controller, to. communicate
‘main memory: Henee, cache accesses and main memory accesses not involv
the CPU can proceed concurrentiye Unlike the loakeaside caso, with a lo (i) Direct mapping

through cache the CPU does not automatically send all memory request (D Setessosinive mapping.

ain memory: t does so only ier agache miss. A look through cache al“ |, Direct Mapping — Let us consider a cache

having. 128 books of 16
Ale local bus linking M; and M, to be wider than the system bus, thus speed Faget oa total of 2048 2K), ‘words, and assume thatthe main memory
‘up cache-main-memory transfers. For example, if the system data bus i

Ans Cache Memory ~ Refer 10 Q.23
Wien considering the organization of cache memory, three Iypes of
aping procedures are of practical interest
(Associative mapping

Abe by a 1Gbi adress, For mapping purposes, he man Se
bits wide and the cache block size is 128 bits = 16 bytes, a 128-bit data 6° Ji Viewed as composed of 4K blocks. In the dec ain
righ be provided to link M, dnd M, which would allow a cache block ® [SEL o e MM maps onto block k modulo 128 ofthe cae, 98 Sn
replaced i litte a single loc ce, The main disndvanage ofthe ue" Because more than one MM block is mapped a 8 Nh
rough design, besides its higher complexity and cos, is that it takes 10%" Fa son, contention may arse fr that position even REN TL ana
for Mid respond to the CPU when a miss occurs ria at example, instructions o a program may PEE

Feblock256, possibly atera branch, When por!

Most flenble cache
416 shown this organizar

and content (data) of the

tore any word from ia

in the vache

Octal number and its

ter and the associative
the address i foun, the
U. When au match takes

Fe sates fp nas —}

Pr SR a ‘ative Mapping — In the fastest ang
Eo pe rgociative memory is used. Fi 4.16 sho
ho Memory stores both the ad
mae fes i allows Any location in cache os
> e jayram shows three words presen si
: O af 15-bis is shown ag a Fiver
pa eg 17-bit word is shown aS a fou digit cal punter
mas Block Be mr address of 15-Dits is keptin the argument re
: oh ate ted alsa te CP
E Dre pein memory accessed for rar
cd À een. The address-data pair is CTU Aires (sui
id de Mesassociative, cache
pee pastores he eache is full, then an [pame
2007 a pair must beudisplace
nr a air which i reqid
e. E presently inpthe cache. The
Tai Newer ge acto what pair is replaced is [02777
Tae Mack Wael fiemiked from the replacement
A a Er di darte designer sclects for the

Bee nie method isto replace cells
Viele ache in roundrobin order
new word is requested fom

Jn canon This contttes a fin

Fig. 415 Directmapping Cache
both of these blocks must be transferred to the block-0 position in teca]
Contention is resolved by permiting a new block to overvtite the cu ya (RO) replacement policy
tesdent block: The replacement algorithm is uival forts cage, 17 (RO) replacement policy,
‘As shown in fig. 4.15. an MM address can bedivided into Vee fa, Serassociative Mapping
a nes block enters the cache, then 7-bit cache block field determines if ment
ache position it which this block must be stored. The high-order Met
of the MM adress of the block are stored in five tag bits associated w
location in the cache. As execution proceeds, the 7-bit cache block fe
sach address produced by the CPU points to a particular block loca
the cache. The tag field of that bloek.is compared to the tag el
address. IFthey match then the desired word is in that block of the cc
cease of no match, the block containing the needed word must first e"
from the main memory and loaded into the cache. Direct-mapping 1%
is easy to implement, but itis not very Nevible,

cy efor the word length is 2 (6 +
ig a bis. An index address of 9 bits
meme 512 words. Hence, the
‘che memory is $12 > 36, Since
ed of c

i

4 of cache contains two data
Sin accommodate 1024 words
set-assoviative

2:30. Explain the following mapping procedures —
(9) Associative mapping (i) Ser-associative mapping
or
Explain the terms associative and set associative mapping. twin
EEE June PS" la memory in each word of

ig. 4.16 Associative Mapping
Cache (Alt Nambers in Octal)

= Set-associative mapping Is an

er the direct mapping organization in that each word of cache ca
Ar mo or more words of memory under the same index addres. Each data
Yrtistored together with its tag and the number oftag-dat items in one word
Mess id to form a set. Fig. 4.17 shows an example of à setassos

Este organizaron for a set size of two. Each index address refers to mo data
nbd their associated tags, Each tag needs six bits and each data word has

vus
FIED)

Inder Ta}
om

oT

Fig. 417 Toor
Serassociative Cocke

» Mi win feront Papi ech
Eee cali merry a der adress O00, Likewise, he wong, y
mud 1] Astral in cache at index address 777. Wine), je o
Dave, ig index value al the adds is used o acces ? «e os weer ?
fer do ed a the CPU res is compared wäh both in, SE Me gerente between write Through and write ect,
“ile a mic lakes place. The comparison logie is donc by an Spo 045 R.GRE, Dec. 2006)
Seat logs nest Siler o an asociativo memory search je*4 aces between Write though and write bs
ite selasseritii. Since more words with the same index but dig 4
‘can resido iicach, the hit ratio will improve as the set size increases, yy
a Its the St sie increases the number Of bis in words of ga is method main memory À | tn thismethod on
‘needs mort complex comparison logic, À jated with every memory
ta setsutocinive cache, when a mis takes place and the sets gf} |e operation as Well as cache
necessary lo replace one ofthe tg data items with a new value, Moston: mon is updated in Parallel
replacement algorithins employed are - random replacement, P| contains the word at the
(EIPO). aid least recently used (LRU). The control sclects one-tags dy lari, “THe
foreplacement al andom. The FIFO procedure chooses for repiacemnch] „| ee sory always contain | Main menwryandcach
‘em which has been inthe set the longest. The LRU algorithm chong} | sanmemory alas may have diferent dat
replacement the ilem that has been leat recently employed by the Cru u [Save S388 © en Keen
adding afew extra bits in each word of cache, both FIFO and LRU cap || Sumber Of memory write Sandra
mplemented x geration in a typical program is | operation in a typical program is
less
31, Point out the difference between direct mapping technique Ms then h e
“eh + lirect mapping, technique sé" When VO device communicated | When VO device communicated
asicited mapping technique, with the help of example. (a rough DMA would receive | through DMA would not receive
Ans Refer Q29 and Q.30, most recent data. most recent data
0.32. What are the various mappi 3 His a process of writing cache | It is a process of writing cache
7. various mapping methods used With cache mens process 2 pr
organization ? Explain any one method in deta |_| tnd main memory simultaneousty.| and data is removed from cache
(RGP, Jane 2007, Dec. Mi First copied to main memory

GPK. Dec. 2015,

23, 0.29 and 030,

je Through

Or
Mee shor note on mapping techniques of cache memory.

36 Explain writing into cache in relation to cache memory

2. June M RK, Dee. 2011)
neh ech (R.GPY,, June À CA

= ext > 029 and Go ¡Ls When the CPU finds a word in cache during a read operation, the
explain any one in denn Name Alle ypes of cache mapping ¿E Memory is not involved in the transfer. However, ifthe operation is a

(RAGE, Mas ONES tere are two ways that the system can proceed.
9 Simplest procedure is to update main memory with every memo”
Types of Cache Mapping - Refer to 0.29 and Q30. maton, with cache memory being updated in parallel ii 0 me de
2,4. Wit the help of gram explain how ccna à usa in coto PEE adress Tis i calle the reir med. Ts
*Prgenizadion. Explain mapping techniques, (RGB: June 2014 M4 advantage that main memoryalvaya contain le mentor
E „is characteristic is important in systems with direc
8 tansfe A emory are wal
jgues A ES: TL ensures that the data residing in main memory
Oaenizadon, Which mapping technique nl, Ss so ln would receive
ok mapping tcl Rg tan 0 vie communicating rau DMA
" updated data,

Ans. Mapping = Refer (0.0.29

da
Explain cache memory.

used in caché memory 2

sie or al if il con reside on the same IC as Ihe cpr,
e vomputers, cashes are essential components, Un. |
"a igpen of memáry, caches are generally transparent to the
“Torsten à computers caches and main memory impleme
és M addressed directly by CPU instructions
‘Access Time and Cost The most meaningful measure or,
à memory device is the purchase price to the user of a complete i,
should include not only the cost of the information storage medium
also the cost of the peripheral. equipment required to operate the pe
{We assume that € isthe price in dollars of a complete memory sy.

ys
S bits af orig capacity. The cost € of the memory is defined ass

€ dollars bit
5

Performance of an individual memory device is primarily determing
‘The basic performance measure is the average time to read a fixed amo
information, for example, one word from the memory. This parameter sine
as the read access time or simply the access time of the memory]
tepresénted by 1,. Likewise, the write access time is also defined;
but not always. equal o the read access time

Access time depends on the physical nature of the storage medi
‘onthe acces mechanisms employed. Itis calculated from the time the me

Magnetic Tapes
Optica DKS (CD-ROMs, et.)

Magnetic Disks
lara Disks)

tq vis + K

Acces Time tg Senado)

Dyna RAM ICh

wh rh ir
Cost (Dollar)

Fig: 4:19 Access Time Versus Cost for Various Memory Technolosl™

Uat Iv 189
À sito he time at which the request
ce emirals of the memory.
hip between cost € and access time , tor some m
es is shown in fig. 4.19. The straight line A Ce ee
rogies is 4 sigh ine AB approximates
hee vite ty = 10° ande= 10s they anne
SER and cis a constant Thun, 1, = 10" à LC
O ve data of fig. 4.1 hat m = - 0.5, Thus, to de
st © must increase by about 100.

formation becomes

tions

+4", We
se ly by à

it ratiolin cache organization.
(R.GRY, Dec, 2011, June 2014)
„Kormane6 of a Cache, memory is frequently measured in erm
Ans fe ‘edt ago. TEPU refers to memory and Find the mado
uo loo to erate bi When word isnot found in cache, ts in min
sete counts a miss. The ratio ofthe number of hit divided by the
e ete to memory is the hit rato. When hit rat is igh enough
Ar or he tine the CPU accesses the cache instead of main memo
Bp acess time is closer Lo Ihe acess time of fst cache memory

nya

dtilevel memory. What is hitratio ? Obtain the expression

scribe mu
pul Des (R.GEV, May/Sune 2008)

¡ame access time in a three level memory.
A Multilevel Memory — Refer to Q.39.
Ratio - Refer to Q.40.

Eipression for Average Access Time in Three Level Memo
“the probability of finding information in a given lev

pad on the size hence it is expressed as H(S). The function H(S) is also
bornas success function or hit ratio. The quantity 1 ~ H(S) = FS) is called
i ato or failure function.
„Rnulilevel memory system information contained in
Motel by all levels L; (say 4) when j> i. Hence probability fora
Pstniss at level i~ through 1 can be expressed as
y = H(S) = HS; _ ,) = access frequency to level

2 N was observed that 1; is the access time for level i and

time from the CPU to level i then,

(say 3) is
hit at levet

level

0
effective

ti)

neds
fi

Fr 5
sit tase init of sain the average aces tim
Y system is

e T of an n level

A Et)

Int

fa

T

1) to equation Gi
T- Zus 10),
iat i
ron en lis can be simplified as
Fo Ens HS 0)

By sing indo

à that
fis known HS) = 1 (Level n contains everything)
HS) = (Level D does not exist)

1- HG) = FS)
F(SQ = 1 (because HS.) 7 0)

Te LAGS
in

n=3then

RER

T= DAS

Its the average access time of a hierarchical memory system,
0.42. Explain bit rado. Generate expression for hit ratio, Derive
expression for “effective access time (t,)” if t, and ty are aecess tine

cache and main memory respectively. hy is the hit ratio ofteache.
R.GPV, May 200)

and
- Thesefore,

Forlevel 3,

Ans. Hit Ratio ~ Refer (0 Q.0.
Expression for Hit Ratio A memory hierarchy performance is determi
bby the effective access time t, to any level in the hierarchy. Effective at
time depends on the hit ratios and access frequencies at suecessive levels
For any two adjacent levels of a memory hierarehy it ratio is a con
defined, If an information item is found in M, we call ita hit, others!
miss. Assume memory levels My and M4. ina hicrarchy, i = 1, 2. =". 7
Mo he hit ratio his he probability which an information item willbe fou"
M, It isa function of the characteristics ofthe two adjacent levels M1
My ACM, the miss ratio is defined as 1 - h At successive levels, the HI
are a function of memory capacities, management policies. and PP
behaviour. With values between 0 and 1, successive bit ratios are inde
random variables, To simplify the future derivation, consider hy = 08"
that means the CPU always accesses M, first and the access tothe OM
mE M, is always a hit
The access frequency to M, is presented as
€ 70h) (hp

er

E]

4
N
CL

Ur 471

pe probability of successfully accessing

fs and a hit at Mj. Note that there wre it

À ye oct property, the access frequence dre
Be to high level + se very
5? 4
ser levels
nor Ect Acces The ep opta ia a
res m pric. Ex time miss cum, penal mus be pat
tea i level Ut memory. The mine fave ten ke
pines he main emy and block misses the cache mem bose
pt um taster beveen thee kl Tor pg
E e time penalty is much longer as compared block miss because t, < ty
À on sed out hat cache mis mes ena
e lea pave fault is 100010 10000 times as costly asa page hit
access frequencies f, for à = 1, 2, ..... n, the effective access time

‚mis means the inner loves of Memory are accessed more ofen as

aged

Pl

‘ay can be explained as given below

Ena

memory hiearel
bay) Moto + (UB hy) gy +
BC ha) a. (I= Dy My Ai)
The ist several terms in equation () dominate. Currently the effective
esti depends onthe memory design choices and behaviour of prog
er extensive program trace studies may one estimate the ito and
fer ofı, more

043. Explain locality of reference in relation to cache memory
(R.GPY, Dec. 2011)

hit * 0

big short note on locality of reference. (R.GRY., Dec. 2006)
In. Analysis of large number of programs has shown thatthe reference
scr a any given interval of tne end to be enfind win a ev
ltd area in memory. This phenomenon is known asthe property of eat
Yen, When a program loop is executed, the CPU repeatedly refers
*ofinstuctions in memo stitute the loop. Every time 2 given
ie i called is et of insructons ae fetched m Ping
Subroutines tend to localize the references to memory for ANNE
Pen The eso al ese breton tbe ay o TE
ethic tes thar over sort internal of ine, he ares En
OP program refer 10 a few localized aras of memo FPS
remainder of memory is accessed relatively infequen'

«vat are the advert

A mener Arontecte

ru,
Stine y
is Meinoty Hierarchy ~ Refer to Q a à
a ory Over Main Memory —
stages at Cache Memory 8
Advantage fe is a special very-high-speed memory used 10 inorg,,

Gy Goa
nía by making eurent programs and date vaio
CPU sta rapid rte.
fer The cache memory is employed in computer sy
“pare or the speed differential between main memory access ite,
ser logic 3
O CPU logic i usualy faster than main memory access tm,
he teat tht processing speed is limited primarily by the speed ora

memory:
{vy technique used lo compensate for the mismatch in pen

Speeds fs to employ an extremely fast, small cache between the CPU and ma
Memory whose access time is close 10 processor logie clock cycle tine

(+) The cache is used for storing segments of programs cue
heingeseruled in the CPU and temporary data frequently needed inthe peg
«aleaatons.

0.48. What is tache ? Explain the principle of locality of refeeke
Enlist and explain replacement algorithms. (RGP, May 3
Ans. Cache ~ Refer to Q23.
Principle of Locality of Reference — Refer to Q 43.

Replacement Algorithms — If a new block is brought into the ox
‘one ofthe existing blocks must be replaced. For direct mapping there i
single possible line or any specific block, and no, selection is posite!
replacement algorithm is necessary for the associative and set associ
methods. To get high speed, this type of algorithm must be implemented
hardware. A numberof algorithm have been tried ~Four of most comme
as ~ Probably the most effective js least recently used (LRU) ~ Reple*®f
Block inthe se which hasbeen inthe cache longest with no veferene 2)
a imply iplementd ar toc associative. USE it is a
(cage in. ane referenced, is USE bi is ct to one and he US
atset i setto zero, The line whose USE bit is zero is

|

¿La block is o be rend ino the set, LRU should provide the best HMA} a

because considering that more current ef

more currently used memory places are morro
toberefeenced. Another pos soso frst-ut Replace tat hy
ie set which has been in the cache longest. As a round-robin oF Ci

‘buffer method FIFO is simply implemented. Ay ity is leas fe
it |. Another posibility is least
ed he set, replace block which bas experienced the fewest 01“

Al lng

0 agorith

is cache coherence and wi

do orden ‘portant in shaved

Problem be resolved
solved with
(R.GPK, June 2015)

je What
e lipracessor 5

Y sede controller ?

or
zis cache colerence/2 Min E it necessary ? Explain diferent
oh RGN Jane 201, Dec. 2019)
1 coherence terminology associated with multiprocessors
(RGPY, Dec, 2009)
in. A he processors share a common memory in a shared memory
sa pcm In ion, cach processor may have local mem
tog which, may be cache. The compelling reason for containing
Pa caches for each processor iso minimize the average aces time in
e mcessor. The similar information may Kept in number of copes in
aches and main memory. The multiple copies must be kep similar o
BE ie ability ofthe system to execute memory operations comet. This
cent imposes a cache coherence problem, A memory scheme coberen
Pirate returned on a load instruction is always the value given by the
hut store instruction with the identical address. In bus-oriented
suligrcessors, caching cannot be used with two or more provessors without
per solution to the cache coherence problem.
A simple approach is to disallow private caches for each processor and
Aurea shared cache memory associated with main memory Every data access
rade 0 he shared cache. This approach violates the principle of closeness
«CPU to cache and increases the average memory access time, In effect,
‘scheme solves the problem by avoiding it
For performance considerations it is required to attach
53 mess One scheme that has been used allows ons ense nd
only data to be stored in caches, Such items are called cachable, Shared
Sale dat re noncachable. The compiler must tag dats as cis cacha
Eoceno ‘and the system hardware makes sure that only e e
ced in caches, The noncachable data remain in main memos: Trt
and limits the type of data allowed in caches and introduces an extea
“Wate overhead that may reduce the performance.
A approach that permits writable data to exist in

sof memory
uses a centralized global table in its compiler The stats TATE
re oe. Each loc I recngizd 13

es can contain copies o

rt reach cobren.

pc

plain cach

a private cache to

at least one cache is

sored in the central global able.
) oF read and write (RW). All cacl

> Only one cache can contain a copy of an Ry,
5 pos fhe cache with an RW block the other gS

pren an be sey meso ang,
& eae ar by means of hardware-only scheme Mh
à centre by the hardware automatically and hay
ee tapa and higher speed. Inthe hardware soluto
N pecially designed to allow it 10 monitor all bus requ
ted OP, AN caches attached to the bus constantly monitor thes
possible we operations. Depending on the method used, they mye
2 her pda o invalidate th he eons when a math i gon
E Teva contol that motors his action is called snoopy cache co
This Hf fase à hardware unit designed 10 maintain a busavge
ais over all he caches ached to the bus.

NUMERICAL PROBLEMS

Prob The ces time of a cache memory in 100 ns and that ofl
memory is 1000 ns. If estimated that 80 percent of the memory epa
For read and remeining 20 percent fr

nb 89. An through procedure is used.

(5, What isthe average access time of the system considering}
memory read cycles ?

"The cache oberon

he
Mar

{in Whats the average access time of the “tem fo ba a
and write requests ? is iS %

1) What is the hit ratio taking ruo consideration the Write da!
(RGB, June 2002, Dec. 2005
Sab (i) 09% 100 + 0.1 x 1100 = 90.+ 110,

a
(ii) 02% 1000 + 0,8% 200 = 200-4 16 je
(ill) Hit ratio = 0.8 « 0.9 < 02 4

Prob.& A digital computer has, mer it and ace)
facet Ai @ memory unit of 64K x 16 and

ier of The cache uses direct mapping with a block |

LO How mäng bis are there y PL
els of the address pra ete in the tag, index, block and

(0) How mern bs ether andr?

the cache accommodate? yg

on

te: The hit ratio for read acam |)

Und e
16. Gx adress: Vb dt
2 binnen
O Era | Worl
=10-bitcacheaddress
® =23 bits in each word ofcache Ams,
din 3 = 256 Docks oF words cc Ans

| A two Way set associalve cache memory uses blocs of four
The main memory size is T2BK * 32.
oo D Formnlate ll pertinent information required to consruct the

qe meno
a)

"ati the siz ofthe cache memory?
(R.GPV, June 2002)

Pe.
a 2048
Forasetsize of 2, index address has 10 bits to accomodate = = 1024
jf cache
La 6) Tits ‘Obits
Tag [index]
Je Block |e Word >|
Sits 2bits
Tagl Datal

so24( Tits [32056 [7056 [32055]
(Size of cache memory= 1024 x 2 (7 + 32) = 1024 x 78 Ans,

Prob 8. A CPU has 32 bit memory address and 256 KB cache memory
cache is organized as 4-way set associative cache with cache block size
6 byes =
( What is the number of sets in the cache ?
(ii) What is the size of the tag field per cache block? à
{How many address bits are required 10 find the byte offset within
lock ?
€) What is the total amount of extra memory (in bytes required
ap bits >

tache
rte
(GRA, Dec. 2010)

(R.GPY, Dec. 2002,

June 2007, Dec. 2010, 2012, June?

tal 2 our yıes blocks,
gel There are 212 = 4096 sets, each comaiing four 16

bits oF A form the set address,

175 Comparer Architecture

in The remaining 16 bits constisue the lag

Meriory Address [16 12 3
Tag Sedes Dio

ii Te towordez 4-bit displacement identifies a byte.
yes cache Bock Nein,
RT tg memo implemented by Four 4096 » 16.5
A tion our 4006 « 6-bis RAMS from the cache data man Ray
ry

Prol. Aset acia cache consists of 64 lines, or slots, divide,

“fine sen. Mein memory contains 4K blocks of 128 words each. Shox he oer
fe

ey,

‘fain memory addresses and ag bit in cache address. (R.GR

‘Sok Main memory contains 4K(2"2) blocks of 128(27) vor.
7 bt long 5
v= 2 sets
deal

Wond= 128 = 2
The d set bits specify

4-2
Tag bits= 19-272 10
Thus, main memory address !

3 u XV ADDRESS SPACE, MEMORY SPACE,
ioe PAGING AND SEGMENTATION, TLB, PAG
¡pee ACCESS TIME, REPLACEMENT Moria

Write short note on virtual

RGP, Dec, ys.

2006, Y 2007, 2008, Dee. 2017, May 201
Explain the concept of vi by

ep of vial memory with the help of exam,

Or (RGB, June 2

Describe the conce 0

Me concept af viral memory, (R GR, Jane M

What is the use of vi
9 virtual memory in computer system ? y

(RGRM, Dec

memory is a concs

dual M e
q Nit er to construct pr
Last de al tothe totality
able. Foe the following three purposes
sae free user programs from the need to cary out
5 Carry out Storage

2 make programs independent of the configuration and
memory present for their execution: for example topemit cea
es secondary memory When the capacity of main memory sence,
wy To obtain the verylOw Access time and cost por bit at ar

ae vi a memory hierar: ‘
si memory cn D8impleméned a anexenson of paged or seen
„Nm nagement;or 38 combination of bot, Acorinl. addres
son is performed by means of page-map tables, segment descriptor
es oct
2 raging sytem. the virtual address space is divided into equals
Uam as pages Likewise the physical memory is also divided ino
Ma blocks called frames. Size of a page isthe same asthe sive ofa
‘Gut of page may be 512, 1024, or 2048 words
uch virtual address may be regarded ss an ordered pair < p,n > ina
stem, where p is the page number and n isthe word number within
BER). Sometimes the quantity n is referred to as the displacement or
ike Auser program may be regarded as a sequence of pages and a complete
“sofi program is always held in a backup store such a a drum ora disk
Ane pof the user program can be placed in any available page frame p' of
“main memory. ffa page is in the main memory a program may access the
Man

cal
ssi

Vital Address Main Memory Address

Memory

Prem for Virtual Address
otcement Gen “se
Fa A Frame
p' Page Frame a ta
Page Ins }
Mapping |
P| Algorithon
m Fr ind
¡LA
m
—
} m
I

Fig 4.20 Paging Systems in Virtual Memory Mis

hg Compinor Architecture
me, pages are brought from Secondary mem,
er pai ern Al nun ay
rere be and into phil memory aggre ig
Fa alled dye adress translation and is depicted in iS
a ing progr accesses a virtual memory location y, 22
<n prt ds ht il page pi maped 1. >
«State Then, the physical address is determined by appending yo
pai des rando en e implemented using page table, yy, |
eta he tin entry in mat tr. Kw ave op ge
Sag sual page of the viral address space x

‘Aas Reed Memory ~ Refer to Q.11.

‘Virtual Meméry — Refer 10 Q.47.

BA: Whats mia by memory hierarchy ina computer system >
¿explain hat is meant by associative memory and virtual memory ?

(RGPY, Dec, my,
= Anis. Memory Hierarchy - Refer to Q.3. A

“Associative Memory — Refer 10 Q.19.
‚Virtual Memory - Refer to Q47.
0.50. What is address space and memory space ?

“Ans. An adress used by a programmer will be called a virtual address]

the set uf such addresses the address space. An address in main mem à
¿sl a location or physical address. The set of such. locations is callos
‘memary space. Thus the address sy

‘memory pace in computers with virtual men

QSI: What is associative memory ? .

ative memory ? Explain the concept of aid

‘space and memory space in virtual memory, (RGRY, June 20
Ans. Refe 19 Q.19 and OSO.

32, What is the need of

. virtual memory in the cor syste
ter ope memory in the computer 5)

les organized in viral memory sen
(RGBF, Dec. 20
fist confronted with programs WP
‘memory. Generally, the solution ad“
lees, known a-overl

Ans. Several year ago people we
were 100 big to fit in the available

ase pit te pro eae

oe running first, ha it was done, it would call another over

erly systems were highly comple, pom wen
= Deming multiple oyrlay 854

Hone. The ovelys were placed onthe dink sed no and 06

Unit: tr

je operating system. Although the actua]
"10 be done by the programmer Spit

A ork of swapping
rk of spining the progra

3 ina
e rula thought of way to turn the complet jobover sin

nod that was devised has come
thon
med virtual memory is that

long
ai
the combined size of the progra.
ced the amount of physical memory avait

ope. ad the rest on thedisk, ASa example. | M preys
pe machine by carefully selesting which 256 10 ka m mann
es dan with pieces of the program being swapped between dik y
py as required. '
remus memory can also work in a multiprogramming system. As an
ae eight | M ptograms Canesch be assigned a 256 K paition ina >

‘vith each program operating as though it had is own. private 286 ke
2: Actallyvirtual memory and muliprogramming
am is Wa

e mol rn-tetefore the CPU can be given ashe proces

ifn information in the address space and the memory space are cach
il ino, groups of fixed size, the table implementation of the address
ec is simplified. The physical memory is broken down into groups of
“ze called blocks, which may range from 64 to 4096 words each, The
“mp refers to groups of address space of the same size. As an exampl
fa age or block has 1 K words, then address space is divided into 1024
juesand main memory is divided into 32 blocks. Although both page anda
sare divided into groups of 1 K words. a page refer tothe organization
Ars space, while a block refers
ie organization of memory spac
Je programs are also considered to
* slit into pages. Portions of
‘gums ate moved from auxiliary
Sony to main memory in records

Pages

¡alió the size of a page. Tapes Block
Let us consider a co
“als us consider a computer with sn ma
Aedes space of 8 K and a memory z ns
m4 K If we divide each into pee
Sabie! K words, eight pages and Page? mar
Sn a obuined, o pic ee Nom
a 2! At any given time, upto une ein Max 2
gs adress Rn

à pace may reside and Memory
i memory y, e oli four Fig. 421 Address Space 4
do, 07 in any one of the four ES en Groupe of Mar

MG Compter Arcitectare
1 opine rin aiéren space 10 emo space is facilite
es casera to be presented by 180 number
greed an ane within the page. In a computer having 29 worg,

à ify a line address and the remai ly
“ie employed to specify ining hij
ie aia adress specify the page number. In he example gp” x
A address us 19 bits. Because dach page consists of 210 q, of en the
‚abe Bight oder thre bits of virtual address will specify one of the gin, "Gf ge CP pat the 60!
A ad baton ater 10 Bits give the line address within the page 1, ap yen main memory. Then: cal to the operating
price nan hat the line address in address space and memory" #f# "ae page from auxiliary memory and keep i
Sie sans the Gaby mapping needed is from a page number to a blo „= ration
o leen eee " what are paging and segmentation ?

Teapot 01010011 |Wirwataddren E ‘paging — Paging is 2 memory management scheme that permits he

2 ee] Ar ess space oF & proces to be noncontigus. Paging ave the
rome pst problem of fitting hevarying-sized memory chunks ont the bac

5 abe problem ring chunks onto the hacking

* per ich most ofthe previous memory management schemes suflered

“e fo WA

fe bitin ite eck
Ne,
43)

ent of the word referenced bythe vial ald ya
stems produced lo
into main meray

mL Matte | eegmentation — Segmentation is a memory management scheme that
at Bade] | fhe algress space of a single process ino blocks that muy be placed
I ner] | Se ontiguous areas of memory to reduce the average size of request
Boar] pe i R
5 FT Tot 054, Givea short note on virtual memory organization. What paging?
an Memory (R.GPY, June 2014)

Adres Reger
Or

is paging ? Explain how paging can be implemented in CPU to
es virtual memory. (R.GRY, June 2009, 2012, 2013)
Ans, Refer to Q.47 and Q.53,

$5 Write comparison between paging and segmentation.
a 5 (R.GPY, June 2017)

Ans, The comparison between poging and segmentation is
Table 43 Comparison between Paging and Segment
T Segmentat

Ces
Fig. 422 Memory Table in @
; able in a Paged System
Organization ofthe rhemary ma Seat ‘ial Point
yes o/mapping table in a paged system is dei a |
o memory Page able has cightwords, one for each page. nf) [Awareness of programmer
Fires the bree ass denotes the page number and the content of Mew] | ts technique
ese lek number wie it page is stared vemory. The | |Stucture of memory
D and ra ql are now available in main memory in bos} | _ [viewed as
‘page has bess ar ack location, a presence bit indicates west 1) |Support vital memory
à from ausiliary memory into main memory. W| |) |Koepseparate procedures
and data
© [Support table whose

to SO ow os

ik

Unity

i 7 .
" pro forpagingisshown in ie 4.23, by vo
ak Tae ine 100 parts — a page number 3 2 6 | Pete rome
did nn nn!
ET used as an index into a page unı Pan se Mm
er wed as an index ino à page taa Ct] 1
nase adress of each page in physical memory hy H
mache oe alto def yeah The
ig tie memory ani :
“guts sen @ the me det :
Pat
TT
Ta
rame Number ze]
° JB
mm * Lapel Memory >
A co a à
Fig. 423 Paging Hardware Bo CIE
‘The paging model of memory is shown in fig. 4.24, The page sie Fl PS] men | A
bythe hava The sie of page is cal a power a 2 ser all
SE yes and 16 MD pr ag, pending onthe computer achte | Le 5 E
selection of power afZ as a pogo size makes the translation ofa logicaladds| =? s
into page suber and page oe parculaly easy. the Sie of lopcal ais 7
space 12%, ada page size is addressing units, hen the high orderm- nt Physics! Memory Pr Menor
Dflopial adie indicates the page number, and then low-orderbits shoe : 25 Paging Example for a
page off Tus; the logical address is as follows - Fe. 424 Paging Model of Logical ear per
a 4 32 byte Memory with 4 byte Pages
we, N— and Physical Memory ee
057. Explain demand paging and swapping. (R.GRV Le
ns that each page
” ns Demand Paging - Demand paging simply means tht cach pa
pm din pas ns be ipicement win Be Ares is brought in only when itis needed, tat is on demand. Wih
ce mie consider the memory in fig. 425, Using a pages] fe demana Paging, it is not necessary to load an entire process in
nnd sical memory of 32 bt (ke. pages). we show hon | nan te
ases view of memory od inst pi Logical 48 sible for a proces to
De on [rita Jo pial memory. Logkalet te fact has remarkable consequence. It legos ible = ee
tune hs tls Ope nd | fm mem. Wa demand a net]
Lal adres 3 (page 0. ae mapa ea address 20 (= (5799 Fay avaro af how much memory is available moet et
Laie ess 4 page) So phyical addres 23 (= ambar must devise ways to structure the progam ine DEAE Tt

Bel. according to page table, page | MP] Abe Lu 7 ft For the operating
roger a alse ap ph lc (OO | scr oe aims. Tha obs rie sing Se RS

Vel ads 13 map ph ag PE A, Beau proces exces nin man memo

‘Main Memor

buksense Operatic]

longterm queue of
Sytem

pecas tenis pie stored
‚hnidiak:. These arc brought in. one
Latine as-space becomes
Sisiluble: As processes. are | T
“cmléted, they move out of
ist memory: Now situation
“as that none of the process in
ly are in ea sae. Rar
¿q 9*thay remaining idle. the processor
3 svp one uf the process back out
y obte disk imo a intermediate
FE guiblit: This is a queue of cxisting
process thar bare been kicked abs
‘oui of the memory. The operating | Lang:
‘system then brings in another
ress rom iniermedite que,
or it honours a new process
request from the Jong term
queue Execation hen continues
“it be newly arved process.
cen SE Discs about the hardware support for paging Stems wy
Ans, Each operaig sy
Mos allete a page ble Tre
stored withthe other
petrol lock
The hand

Longer
Que

Il

a (a) Simple Joh Scheduling
I Storage
Main Memory

‘Operating
System

totrmetate
Queue

atte

6) Swapping
4.26 Use of Swapping

stow methods far storing pgs
be foreach proces. À pointer i ihe ps u.
nier values its he atu cou) he ps

bi

the page number fri. This task ei

locaton
eva PTR antoni, We mus fs index ini the pas?
2 lt provides the frame number, which is combined with

to produce the actual address. We an the

0 1 FS two memory accesses a dotes
a mem able entry and one fr the be Ne U
(oa factor of 2 te. Hence, mem
od by?

Logica

Ares
212]
Page Frame
E un wi
4 Paste
El con
Pips
TUE Menor
e { =
TUR Mis =
r
Page Table

Fig. 4.27 Paging Hardware Support with TLB

‘The standard solution to this problem isto use special, small, fast-lookup
fardnare cache, called translation look-aside buffer (TLB). The TLB is
fsocsive. high-speed memory. Each entry in the TLB consists of two parts
fey ot ug) and a value, The TLB is used with page tables in the following
nay The TLB contains only a few of the page table entries. When a logial
adress is generated by the CPU. its page number is presented tothe TL, Ihe
pas number is found (known as TLB hit, its frame number is immediately
ile and is used to access memory. If the page number 1.n0t in TLB
(inown as a TLB miss), a memory reference to the pago table mast be made.

0.59. Write the description about the hardware requirement for
segmentation implementation.

Ans. Segments are formed at program translation tie by grouping
‘ther logically related items. For example, typical process may have separat
da, and stack segments. Data or ende are si her proces
ay be placed in their own dedicated segments. Being a result of eich
‘cents may be placed in separate, noncontiguous ares of physic] met

pla sr be placed in contiguos areas of
ns belonging to u single segment must be plied in comers of bots
management.

cal memory. Thus, segmentation posses

‘tiguous and noncont Tor memory

and noncontiguous schemes ce AT

A logical-address space is a collection of segments Each RAR

am and a length, The addresses specify both the PE grec by 10
Set within the segment. The user therefore specifies <A

Fries a segment name and an offset

dés alimplementuion segments arenumboreg
js sement NEN her dun BY a segment name“
Sitists-of'e two tuple
7 «gegantat furberoffSet>
Sin pal mem in seemented systems general au,
Ass e address translation mechanism is nes
‘ay orgutaatton, some add needed
NO dimarsorl vinualsegrent address into its unidimensioa
“lali; This, we must define an implementation to map tm
«ies ina addresses ino one-dimensional physical addresses Tai
© affected by a segment table, Each entry of the segment table ha
base a segment limi. The segment base contains the st

FEN and a

© cg,

Adress where tho segment resides in memory whereas the «
spécifiés te length ofthe segment

A

Seqmeot Tbe

esp: Adi Error

Fi 428 Sepmenaion Hardware
#428 shows he use oa segment table A Toga den ds

two parts ~ a segment number, s, and an offset into that segment, E ke

semen! member suse a an index ino Ihe segmen aa Mar ke

lala ads mus be br D and te nam E O

gl rem one O

Physical memory of the desired byte, © + lists

Physical Met

mit Pp nase

1400
2400]

1000
400
o
1100
1000

1100
6300
5300
3200
‘00

3200 [Segment
Semen]

4700]

a ET

soo
ro

(Samen
Berl

ig. 4.
Fig 4.29 shows the sit
4. Te segment table has a

29 Example of Segmentation ve
ation with ive segments numbered from 0%,
Separate entry for each segment giving the bag

Gt 463

he length of
Bi at location 439

‚ggment in physical memory (or base) and i
rie Scene 264 aes Tong and bey
eto byte 53 of segment 2is mapped omo cata

Cartes ce to byte 1222 of segment 0 wi ren diay

a or because this segment is only 1,000 byes longs the
pen

“ teme!
ne im
De ed

what is page fault ? What technique
gi

ation of paging differs from paging

re and segments are not. és

al way

S are used to handle page
#17, when the execution oa program stars, one or more pages
des ino main memoryaid the page ble is set to indicate erp
Am is executed rom main memory unlit atempts to reer,
Fl happens. the execution of the present program is suspended uu)
led page is brought into main memory. Because loading a page fens
isymemory lo main memory is basically an VO operation, the operating
Pin alacates thisitask 10 the VO processor. In the meantime, contro is
ed to the next program in memory that is waiting o be processed in
"ECT, Late, when the memory block has been allocated and the transfer

A seg, the original program can resume its operation.

al memory system, ¡fa page fault happens then it signifies that
Axis referenced by the CPU is not in main memory: In case the main
ami fll, it would be essential to remove a page from a memory block
«ke room for the new page. The replacement algorihm is used o select
‘Sch pages to be removed. The task of a replacement policy is 10 uy 10
anti page least likely to be referenced inthe immediate future
age Fault Handling Techniques - The firstin, first-out (FIFO) and
ieee recently used (LRU) are the two of the most common replacement
‘esis, The FIFO algorithm chooses for replacement the page which has
‘ssin memory the longest time. Each time a page is loaded into memory its
cation number is pushed into a FIFO stack. FIFO will be fll whenever
‘sar has no more empty blocks, IF a new page must be loaded then the
EE test recently brought in is removed. The page tobe removed i esl
Sel since its identification number is atthe top of the FIFO stack. The
‘advantage of the FIFO replacement policy is tha its impler etn à
Safe disadvantage of this policy is that under certain ireumstances POS
must end loaded from memory too frequen 1
Sage other hand, the implementation ofthe LRU policy more
eh Palo has ben mare hin con the assumpuior hat he ka
a Ff’ Petter candidate for removal than the least recen PAR
Moo! The LRU algorithm can be implemented by SoCs pen js
Page which is in main memory. If pages 106

a vi

4

énor Arenteëturs
pc Te ou socie Vi
hot incremented by 1 at xed interval of time,
ne vaine tien emt. The os
Being ero: féranse tier Count indicates 1h
ir abspbinled pages bate been reference.
f Wile e short mote om page fault.
am Relat to 0.60.
62. What do pou mean by effective access time ?
sacd We te probably of page fault (0 p
L'expert po be civic to zero, ic, there will be only a few page
fete ces time is
EAT= (1 =p) x m, + p * Page fault time
ice nos me is directs proportional fo he paga fat rate. T y
‘dhe tee aces tine, we mus low how much time ls ecded oo
E juga fl. For example average page ul service time is 20 misent
Emo ascss üme 2 nanosevonds, then the effective acees time in meg
5 EAT = (1 =p)» 75 + px 20 x 106
75 + 20,000,000 p
+ 19999925p
Af qué acces out f 1000 causes a page Fault, Ihe effective access iy
EAT = 75 + 19999925 x 1
20,000,000 = 20 microseconds

2.43, Explain any page replacement algorithm withthe help of example
(R.GRY, June 2017
Ans: The various page replacement algorithms are explained as below
&) Firsein-First-Out (FIFO) = The simplest ace
ie st page replacem
alyonthm is a FIFO algorithm. A FIFO replacement algorithm associates vi
ach page the time when that page was brought into memory. When 3 PF
Mare replaced, he oldest page is chosen. AFIFO queue is maintain toi
all pages in memory. The pages are replaced a the head of the queue. Wise!
pags in m 1 head of the qi
Pape is brought into memory, it insets at the til of the queue.

Aa ee

erie
F8. 4.30 FIFO Page Replacement Algorithm

Rary

ED Weg
faults, They
Then gp

ry

1
7
7
3

Phe teen

sant uses
y in ihm also Süfers Fo

Y ¿se emp)

es brought in first. Since O ts the next Ed

o fault for ti ind su
d, since it was the fist ofthe re passe ig

be brought in. Nowgthe next reference to 0 will ue

cad by page O. This process continues as shown in fig,

¿E faults altogether

or ge replacementitlgorithm is easy o understand and program
page Trance is not alwys good. The page replaced may be an
is fat was Used Tongtimeagoand sno longer ned. On
Ena q contain a bes used variable hat as niza y

Le FIFO Pal

Im Belady's anomaly. We wil study it
hephysical memory size and the number of page frames avale
Amber of page faults should decrease, Duct this the perfomance
anced. But this isnot essentially the case if FIFO is used asthe page
t policy Generally, this is referred o as Belady's anomaly, Let us, for
“ehe a reference string 2, 3, 4, 5.2, 3, 6,2, 3, 45,6.
431 depiets that with 3 page frames, FIFO gives 9 page fault
WE Ihe number of page faults increases when we increase the number
ame from 3 to 4 and becomes 10! This is clearly anomolous and
anse tin fig. 431
13 +
ajaja
aja
La
4.31 Page Faults
ee these figures, we can m
cause inthe case depicted by fig. 4.32 the page i eferenced as
[Tus ts evicted inthis specific string, This typeof anomolou bebo
fsb: ray found for specific types of page reference sting I doe
“bs appen fr all reference strings,
L 13
aja
3

ec

3

a 7

7

5
5
3
7

LI

with 3 Page Frames
that

Fig.

Ewe thoroughly s the page faults

¡El

Fig. 4.32 10 Page Faults with 4 Page Frames

E né pies 1 replees page.

ii rel ‘ Ci fer à
A ge 2 is about o be Used. Wien i then fu q
ay) Oprima! Page Replacement Algoritlim — The. ory, fg Fs page 3 since, of the three pages
ei ta pgs for which timo tothe ne py, gr se. This proces contin,
SP ign has the Lowest page-Tau rate ofa igen [E pe ES other
Sos ft Bcd «anomaly is also called OPT or me Eye 12 al
y dealers consider the following fung, ER HP er
O ,0:3.2.1,2,0,1,7,0,1 ting
à As ari seul yield nine page ful, as shown in ig
dae refentes tase (alts at fill the three empty frames, e 8
cise 7 wil not be used until reference 1,
lucy a ond pu {a 14. The reference to page 3 rep "x
£4 wilt he lant oF the three pages in memory to be references”

asshownin ig 43a |

RER

El

‘
o
pre a Page Replacement
Na ie paje als, optimal replacement is much better re Get
gora ion (5 Tas In fact: no replacement algorithm can LRU is theoretically realizable, it is not cheap. To fully employ
this here seg in three frames with less than nine faults, ve A ecesary 10 maintain a linked list of ll pages in memory with he
iy used page al the front and the least recently used page at the

cr!

Rs
Ha

rei 0
SR 9 x 25 0 5 2 ayi thatthe list must be updated on every memory erence
eM pagein thelist, deleting it, and then moving it 10 the front isa very

ear EL
i E 5 apa
H BE Ting operation. Eier (expensive) special hardware ses r
Page Frames 7 NUMERICAL PROBLEMS
Fig. 433 Optimal Page Replacement Algorithm

Clery this or sible 0 implement, because old is i
a IAE | pk An address space x specified by 16 is andthe corespondine
oes gene sa standard aginst which to judge other algorithms, pumrapece YS ite ghore in he address space?

à Least Recently Used (LRU) - The LRU poli is on eu |: — I) pan many words are ere in Ihe memor space?
à page-replacement algorithm and is considered to be good. When a page fui id (RGP, June 2015)
‘occurs, throw out the page that Has beensunused for the longest time. The
approach is the least-recently-used (LRU) algorithm. In general, the LRU
Alora pero tet ban FIFO. The comia hat LRU taki
Abe pattems af program behaviour by assuming thatthe page used in A
isin’ pot is Ist key tobe référé in the near futore, LRU replace yl! The logical address space in a computer
dssociales with each page the time of that page's last use. When a Pag gene. Each segment can have up 10 32 pases of A
be replaced, LRU chooses that page that has not been used for the In | Akal memory consists of 4K blocks of 4K words in each. Form
etd fe. Thiers heopial page eplacemenalgoriha lo UA physical address formats. (GR, Dec. 200,
ji in hos rather than forward, pf 90 Logical address: “T-bits S-bits J2-bits
¡o ¿oe result of applying LRU replacement to a reference string is shO*” 24
Si 434. The LRU algorithm produces 12 fault, The first five falls °° Segment [Page [Word] = 24e
same as the uptimal replacement. When the reference to page 4 005% 4
ore LRU replacement sees that, of the three frames in m mo Pe
We ed leit recently. The most recently used page is page 0, and just Hs: ic | Ward]
hat page 3 was usa, Thus. the LRU gor replaces page 2 "1 —

Ans.
Ans

16 bis 2 DE GK Warde
= 8 bits = 2% = 256 words
system const of
AK words in each.
late the
2013)

Physical address: “12-biis 12-bils

Un 193

ee is specified by 32-bis and co, or.
prado An less eek mg, jai memory ste has abres spa of 8K par
pig spice M here in the address space » Avian words and page and block sizes of 1 Korg, ma, Memory
E He ma ER ere in the memory Space pee fe ges occ during ave time inet pz oli
A) Ho PAR of 4 K words, how many pages. ere same page I referenced agin iis none ange
dan Ma page cons! RES ang y | re 420126140102357 ed
‘drove ja the system? RGR, Jy N ‚mine the 4 pages that are resident in main memory af
TE aq = ie ean] Der change the replacement alert mei 7 Sch
cee Ans number of words, ia dhe-adress space per FIFO (i) LRU. (RGRS:, June 2010)

= 2
24 bits Au
‚ber. of words in memory space

3) Memory apre

soe ia
La 2282 16M words à
N
A pur
(ay SD son K panes a
: 16M
= MA boca iz

Pook 13 An aires spi specified by 24 bis and the correspon
memory space by I ite
i). How.many words are there in the address space ?
dl). How many words are there in the memory space ?
(ii) If page consist of 2K words, how many pages and bi
ase here in the sytem?
or
An address space à specified hy 24 bits and the corresponding mens
‘space by 16 bis. How many words are there in address space and how mes
Ds are there in memory space ? (RGP, Dec. 28

Sol.) Address space = 24 bits 22% = 161M words as
(ib Memagy space = 16 bits 221 64 K words An
5 16M
tip Se “EKpages Ai
EN
Fe 732 blocks u

Prob.14. A virtual memory system has an address space of BK work“
Mémer space of 4K words and page and block size of IK words. The foll™
Page reference changes occur. during a given time interval —

MU 4201261401023 87

Ine the Jour pages that are resident in main memory 00%

Pate reference change ifthe replacement algorithm used as- y

(D. LRU. (i) LFU (ii) FIFO, (RGP, June À

Sol.

@ © m]
Pagein| Contents| Page in Contents| Page

; in| Conte
Main | of | Main | of | My | on
Memor| LRU | Memory! Lev | Memory] riko

0124| 4200 | 0124 | 401 | ons | anor
0124 Wf. 4012 | 0128 | 4012 | ora | 5201
0126 | W126 | 0146 | 4016 | 0126 | 2016

do | 0126 | 0261 | 0146 | 4061 | 0126 | 2016

4 | 1246 | 2614 | 0186 | 0614 | 0146 | 0168

07 00146 | 6140 | o146 | 6140 | o146 | 0164

} | 0146 | 6401 | ots6 | sani | 0146 | 0168

mel 0146 | 6410 | 0146 | 6410 | 0146 | 0164

2 | 0124 | 4102 | 1246 | 6412 | 1246 | 1642

3 1023 | 1346 | 6413 | 2346 | 605 |

5 0235 | 1456 | eus | 2345 | 42
Cr 2357 | 1367 | 6417 | 2357 | 2357 |
Prob.15.A virtual memory system has 6 K words of adress space and

3K words of memory space. Page references are made by CPU in the

Alowing sequence —

3, 2, 0, 3, 4, 1, 2,20

Find out the pages that are available at the end if the replacement
‘hori used is (i) LRU (ii) FiFO.
Asume the page and block sizeof K words. (RGR, Des 2010)
al
Page O er oO
Reference| Pagein [Contents| Pagein | Content
“* | Main Memory | of LRU | Main Memory | of FIFO
inital 03 320 03 320
3 023 203 023 320
4 034 034 04 204
1 134 341 14 oi
> 124 412 14 a
1 2
à o | i | 1%

SÍ Caidos me following page reference sri
Pk Com G3 21.

RAILS GRR 2 L236

O bund occ forte following page replace,
Remember the frames real emp

2 sali FIFO-
st ii
NCGEDRWEE
Ep

LEL PROCESSING, PIPELINING GENERAL

CONSIDERATION, ARITHMETIC PIPELINE, AND
INSTRUCTION PIPELINE 4
al

Qt Esplain the parallel processing in short. (R.GBX., Dec. 2005)
Or

iin cplanator noe an parallel procesa. (RGR, Jane 200)
pilar parallel processing ? Explain the significance of parallel
sin. CRGPY, Dec. 2015) |

lie Parallel processing is an efficient form of information processing
sist emphasizes the exploitation of concurrent events in the computing
pres. Concurrency implies parallelism, simul
ers may take place atthe sam tant; and pipelined events may take
‘teem overlapped time spans. In a computer system, these concurrent evens
Reatuinable at various processing levels. Parallel processi
‘uen execution of several programs in the computer. I is in contrast
ocessing. It is a cost-effective means. 10 improve system
omance through concurrent activities in the computer
Pele processing can be seen from various levels of complex: Ai
as É ‘es level, it is distinguished between parallel and serial operations by
een "fers ud. SN reis pre ra et et
Sisters with parallel load operate with all the bis of he word
Seth OUsly. Ata higher level of complexity, parallel processing can Be
and Baving a multiplicity of functional uns which perform ¡denia
sins operations simultaneously. By distributing the data among DO
nit functional units, parallel processing is established. Asan example
u oki and shift operations can be separated int three nis a

ae fa contro! unit:
verted to each unit under the supervision of 8 & 3

sin the rosters Al

Pole method of pain
Perating in Parallel is shown in

À es prhtectire TE
di tee fre units dep 7 pico
hon apesified > us
pared with
econ perormed
A UE denoved jn cuch cu
be Wigan: The anthmetic

ream is produced by

ve from the sub

ps

(a) SISD' Computer

ena wih mieger numbers are B
ie alder and intoger là ri RS
e taco pin opertonare aon | a Y
limo ye cal operating i ly
SAL Loge, dif, and increment E GE ue MÈRE

alias. can ‘be performed E :
basent different data. All units : wi
‚ar independent ofeach other, therefore
‘be uit gan be shifted while another
uberis bing incremented. Generally,
"y mulifunctional. organization is
‘ssocind wih a complex control uni
socoordiaae llth activities among the Fig. 3.1 Processor with Mule
various components, Functional Unite

Q.2, Mitte donen the Flynn's classification of computers, P
RGP Vy June20n

Data Siam

Fa Or
522 War ls Flynn's taxonomy ?

(R.GPV, Dec, 2015, June 2019
{2 As: Computer organizations are characterized by the mbltipliity oft
re provided to service the instruction and data streams, Listed bei
ate Flynn's four machine organizations

() Single instruction stream-single data stream (SISD) (©) MISD Computer

Gi) Single instrutionsteam-multiple data streäm (SIMD)

(i) Muhiple instruction stream-single data stream (MISD)
a 6 Multiple instruction Stream Multiple data stream (MIMD).
esc: organizational classes are shown by ck diagrams it

y wn by the block diagram
fe. ‘ En So aofzaion depends onthe uliplicity of simultancous es”
system components. Conceptually, only three types of #5!
Para re tee inthe stration, Both instructions and das 2%
fetched from tho memory modules. Instructions are decoded by te cone

‘uni, which
eco] “el the decoded instruction stream to the processor uns

Data streams flow between the
uliple memory modules can be e

1s, 15; psy
cu Po] cry

E ns,
A | fa

y E su
Sy 1 955 bad

Bee]

> (@ MIMD Computer
+52 Flynn's Classification of Various Computer Organizations

Processor andthe memory bidet
"ployed inthe shared memory SUP"

fms parallel processin

i

oe

ter Organization ~ Fig. 5.2 (a) sho,
suse in most serial computers avalan
but may be overlapped in their exar,
As SID processor systems are pipeline, atin
pane mar ove funcional uni ii. One cog ISD
‘aif tb functional units. . pi!
(i) SIMD Computer Organization — This class is ilus
À tea corresponds fo array processors. As shown in fi

trate iy
$2

ea ro by the same contol nih

"ea receive Ihe same instruction broadcast from th
paraa on different data sets from distinct data streams. The sje
best may have aile modules. Further the SIMD macho
del into word-slce versus itlice modes.

= mir MISD Computer Organization - This organization 4

Sepi cb fig, 82 (0). There aren processor units, each receiving
ane instructions operating over the same data stream and its derivatvet

“Ph reals (oui) of ane processor become the input (operands) of the ney

prosesror in the mscropipe. This structure has received much less attention

“od has beso challenged as impractical by some computer architects, No y,

“ebodiment of this class exists.

iy) MIMD Computer Organization - This organization is shows
in fig. 52 (0), Most multiprocessor systems and multiple computer systems
can be classified in this category; An intrinsic MIMD computer implrs
interactions among the 1 processors since all memory streams are derived

‘fom the same data space shared by all procossors. If the n data streams were
Served from disjointed subspaces of the shared memoriéS, we would hase

The’so-called multiple SISD (MSISD) operation, that is nothing but ast oft

independent SISD uniprocessor systems. the degree of interactions amor

Processors is high, the intrinsic MIMD computers tightly couple

* Üihenwise we consider them loosely coupled. Most commercial MIMD
mate ate loosely coupled.

ES What de you mean by parallel processing ? Write the Flys’
plein of prac processing. a (RGB, June 2004
ee Or

D ica all

? Explain the significance of Pa

Leche Fm’ cion comparen RGP. Dec 200)
Para Processing — Refer to Q.1

aM "Classification of Parallel Processing ~ Refer 10

£04 What do yon understand by pipelining ? Explain the Pire"

recelo oth th help of an name Conk ? Expleë

ces ih ample
tas: Pipelining du technique of decomposing a sequential

PAR eis each sbprocess being: execated in a special

dedicated

Ut 100 |
„ich operates concumenty with ll other sens. À piptine car
e Mieson of processing Scuments trous
188 Hows Esch segment does partial processing
minoned. The result achieved fom the computer À

10 tre next segment inthe pipeline. The final moult ater
sm have pssed trough al segments hr ram png
st sw of information is analogous to an industrial ash Io A
po aies aay compa oe a A
splits ments atthe same time, By associating regir wih ch cones
er gl ic ee ee
ait Pt tion between each segment so tha each can operate on detect
simultancossIy

The most simple Way of SEGA the pipeline structure so imagine that
ca ment hasan input register followed by a combinational circa Roger
ems data nd the combinational circuit performs the suboperation ine
ar segment. Ina given segment the output ofthe combinational iu
eo he input register ofthe next segment A clock isgiven wall esters
BE lps elapsed o perfor all segment
A efommation flows through the pipeline one 4
Site time. We demonstrate the pipeline |
atom by means of simple example, as

pateo:
ame that we want to perform the
«vesoed multiply and add operations with a
sra of numbers
ABC ori 1.2.3,

Each suboperation isto be implemented in
‘segment within a pipeline. Each segment
«ins one or two registers anda combinational
Gut as depicted in fig. 53. Ry through Rs

registers which receive new data with every

ck pulse. Multiplier and adder are
Snbinational circuit, In each segment of the
line following suboperations are performed
RICA; RIB, Input A and B,
RICRERZRACC, Mlipiyandipuc,
Re R34 Add C; to produc

fé ofeach clock. Fist clock pulse transfers Aj and B; into RI and
{Sein clock pul et of RI and R2 ito R3 and into RA
¡Dn loc pulse transfers the produto it Sodi Rd

lock pulse transfers Ay and B into RI and R2, Third lock pu
all tree segme à ‘and By into RI and R2, transfers
{ellie segments simullaneouslyItkeeps A; and B into Ri and Be ee
| Pole of Ra 2 3, eses Ca ino

a
jon
pisos
fe

ed by the way

ie

apie

mo

RE

Fig. 5.3 Example of
Pipeline Processing

oe ee

cra
to Gil up the pipe and retrieve the Gi,

dilo one rcp down the pipeline, This o,
ring te sysien. Cho more input data are avai
nil the last output emerges out of the pipe]

UTS as fgg
tn
in

SER nur agri pra pps precesor secure
alas ans oise drone cc

“Plain the
within a segmen,

(R.GPY, June %
0

Eiplain the basic structure of pipeline processor. (R.GP.V., Dec, 01)
+A: pipeline processor consists of a sequence of m datasprocesing
¡eli called sages or segments, which collectively perform a single opera
“Gi rem of data operands passing through them, Some processing tals
fer an operand set has
passe thigh the entre pipeline. As shown in fig. 5.4 stage S, continsà
ultimo input register or Jatch R, and a datapath circuit ©, that is usualy
Sombinstieial The Rs hold partially processed resultsias they move troop
¿pe Pipeline tie also serve as buffers tha prevent neighbouring stages fr
Ämerfering ige athe. A common clock ‘signal causes the Rj's lo
state SnchronoMÉ Eh R.receives'a new sel of input data D,

UV 20

ge S; y except For Ry whose data is supplied & N

ng singe S - 1 except for ‘ from at external

ty repent he rvs computed by C, dam he ne

Aer! Once D). has been loaded into RC! proceed a ae D 3
ek

es LD, Th in each lock a eee

ea
Sous
QA Explain throughput in elation pipelining, (RGP, Jane 3010)
dn. The objective of parallel processing isto speed up the compares
sing capability and inctease its throughpmy, tht ia the anne oe
Sivareinereases with parallel prosessingand with the coset he see
ases, But, technological developments have decreased human ou
Soin where parallel processing techniques are economically least.
0. Explain he term speed in relation to pipeining

(RGP, June 2010)

transfers

Or
Derive an expression for speedup ratio of a pipeline processing.
(R.GPY, June 2014)
ns. Consider a nonpipetine unit that takes a time equal tot, to completo
aut sk The total time required for n tasks is ty. The speed of a pipeline
"essing over an equivalent nonpipeline processing is defined by the ratio
4 m,
u deny
Ase number of tasks increases, n becomes much larger than k-1 and.
K+n- I approaches the value oFn. Under this condition, the speedup becomes
sn
| %
If we assume that the time it takes to process a task is the same in the
eine and nonpipeline circuits, we will have 4, = ki
Including this assumption, the speedup reduces to

7
©
‘This shows that the theoretical speedup that a pipeline can provide is k,
Mere k is the number of segments in the pipeline.

28. Prove that a k-stage linear pipeline can be at most k-times faster

"that of non-pipelined serial processor. (R.GPV, Dec. 2006, 2017)
‚Ans. Consider the execution of m tasks using a k-stage pipeline. In this
ee task willbe completed after k-lock (because there are sagen) and
x alning m — 1 tasks aro shipped out atthe rate of one task per pipeline
Therefore, k + (m1) clock periods are required to complete m tasks

Sic
| "ES age pipeline Ill tasks are executed without any overlap, má

Br "3

e bic eh tsk as 10 pass through ay
an Etage pipeline can be shown as follows. **

Sst fects ir y

Stage

te IS NO Overlap

raf clocks required when tasks are verlpped in

D thes & when m approaches infinity. This implies that
Flag are caried ou! using on k-stage pipeline, a K-fo j
an be expected

GE Diese al factors which affect the perfo

When
creas

mance of pipelinin
RGP, pis pd
ns. À pie performance can be measured by is throughput item
ot suilioas Of Instructions executed per second or MIPS. Another popular
E incas of perfuemance Bs the number of clock cycles per instruction or CP,
“These qGatiitis are related by the equation
3 ot
ns en
‚hie f ls the pipeline's clock frequency in MHz and the values of CPI asf
"MIPS ere average figures that can be determined experimentally by processing
É suites of representative programs. The maximum value of CPI forva singe
‘pipeline Bone, making tbe pipctinc’s maximum possible throughput equalto .
‘Spoce:sime diagram isa useful way to visualize pipeline behaviour, which
som ts lization of each pipeline stage asa function of time. In general,
space ti diagram for an m-stage pipeline has the form of an mn grid
sere is the namber of clock cycles to, complete the processing of some
¿sequence OFN inswuctions of interest.
'Anoiher general nicasure of pipeline performance is the speedup Sim)

m,
x Ta)
[were Tm) the excention time for some target’ workload on an met
pee and HH) is the execution time for the sume workload on a simile
Bspipeised processor Li reasonable to assume that T(1) 5 MT)
pr

GI. Dis he space tiggram fr four segment pipeline show
en ra four segment pipe
Le A Sales to process eight tasks. (GRY, June 2003, 2

DE

Une Y

chaviourofa pipeline can be illustrated with space-time fg.
jagram shows the segment utilization as a function of time The
¿ram of four segment pipeline is shown in Dig. 55 (5),

‚ans THE
ponte di
ime in clock eycles and the

sad acs ment number. The diagram shows eight states Ti
etic Ta executed in four Segments. Initially, he task Ty is handled by
sooth Ter the fist clock, AE segment 2 is busy with tas Ty ang

(a) Four-segment Pipeline
Clock Cycles —

Set |
e:

Ra]

E E E E |
HE Ts [Ts | Ts Ta
- ft

(6) Space-time Diagram for Pipeline
Fig. 5.5

‘This process is continuing in this manner, the first task Tı is completed
¿let Fourth clock cycle. After fourth clock cycle now, pipe completes one
every clock cycle. Thus, no matter how many sement are there inthe
sm, once the pipeline is full it takes only one clock period o obtain a
capa,

Considera K-segment pipeline with a clock eye
tas The task, requires time equal to Ko complete operation, The
"maining n-1 tasks emerge from the pipe at the rate of one task per clock
‘le and they wll be completed after a time equal to (n= 1). Therefore, for
Completion of n tasks using a K-segment pipeline requires K + (n — 1) clock
ales. Thus, the time required to complete all the operations of space time

le time tpused to execute

} “agram shown in fig. 5.5 (b) is 4 + (8 ~ 1) » 11 clock cyeles.

‚ment pipeline showing

2.11. Draw a spacestim of a sic se
we ie pat (RGPY, June 2019

time i takes to process eight tasks.

An The spacetime diagram of six segment pain is soya nf

3

trie
STR
TELE
ital
Se
de Te

= ¡UTE
a
a e Trad

Fig. 56

7 Draw a space time diagram for a
takes to process eight tasks, Ñ
(R.GPV, Dec. 291

“Ais: Rise 0 QT and QM

556438, what d yo understand by arithmetic pipeline ?
in 6 RGP, June 2015
2

Dive à short note on arithmette pipeline.(R.GP.V, June 2005, 2013,
Or

Explalo arithmetic pipelining: GP, June 201

Ans. Aarituoci pipeline divides an arithmetic operation into suboperatos
“for exocation in the pipeline segments. In very high speed computers, the pipet,
arithmetic units re sed 10 implement floating-point operations, multiplication
of fixed-point numbers, and similar calculations encountered in scientific probe
À pipeline muliplieris necessarily an array maltiplier with special adders design
te reduce the carry propagation ime through the partial products, Floating-post
“operations are easily decomposed into suboperations.
3: Q14: Draw and explain the pipeline for floating-point addition and
“iuberaction. (RGLV, June 2010
5%, de To normalized floating-point binary numbers are used as inpuisto
À Ve Mating point adder: poles,
2 x=a #2
Y=Bx2b
ÉSbere A and B are two frictions which represent the mantissas
atelbeesponeats As depicted in fig 5.7, floating-point addition and Sub
sit be done in four segments. The registers represented by R are PR
Feten the segments to store intermediate results. The suboperations *
shared in he following four segments -

and, aandb

An te mamissas.
PQ AU or subit o mantissa.

Lio) Nertlize the result

|

1

Une: 208

re exponents are compared by subtacn them to elle thee
a Te age exponent electo! the espn th rn The
nee erence determines how many times the mans ssosites e

po er exponent must be shifted 10 the right. This generates an ai
pe quo mantissas
is worthnoticed that the shift must be designed as à cumbimtional
lla minimize the shift time, lo segment 3, the two mañtissas are added
e cid. The result is nommalized in segment 4 un overflow takes
oc e mantissa ofthe sumor difference is shifted right andthe expooe
nened by one. When an underflow takes place, the numberof leading
Fe m ne mantissa determines the numberof let shifts in the mansa nd
E amber which must be subtracted from the exponent

sent

Expenents BR
won a8

nef Lt

®

Compare
Exponen
by Subiración

Difference

Segment:

R

T

‘Choose Exponent

—
fae |__| “year
; coo

Exponent
T T

Fig. 5.7 Pipeline for Floating-point Addition and Subtraction
‘The suboperations performed in each segment are explained by the following
"merca example. For simplicity, we use decimal numbers, although fs. >

"fer to binary numbers. Assume the two normalized floating point numbers =
x = 0.9504 x 10?
Y = 0.8200 «10?

Segment

Segment à

afc exponents are subtracted 10 üchjeye
yg elected a the exponent of the result. ty,
ms of Y lo he right 19 achieve —
0.9804 » 10
y 20.020 x 10°
tr ae dr same AOL In cary
‘cio ote vo matias generate the sum
O
ma ral De sm sage 3 at as Fraction wig
gouer "e accomplished by shifting the mantissa once ig,
ght and. ate úesponent by one to achieve the normalized un
Ze 0.10328 x 10%
Ya Aoating-pain pipeline, he comparator, shifer. adder-subtractoy
cientes ud decrementer are implemented with combinational cire
‘Alcan thatthe ie delays ofthe four segments are ty = 60 ns, ty 70 9
2 200 as, ig 9 ns and the internos rgistes have a delay oft, = 10 ns. The
operario bet, rt; +1, Ons. An equivalent nonpipelin floating.
pt dae tracto wil ve a sly time, Y + + +g +t, = 320 ns. The
pleitos adder had a speedup of 320°110 = 2.9 over the nonpipelined adder
GIS: What i pipelining ? What is the need of pipelining ? Explain de
erganisation of an urithmerc pipeline. (R.GPV, Dec. 2011)
Ans Hele 10 QA and Qu,

3
eg

es

QA How the pipeline processing is done in an insítuction pipeline ?
Esplaia wi ming diagram for four segment instruction pipeline,
(R.GPV,, June 2005)

Or
Hei short note on instruction pipeline. (R.GBV, Dees 2005, 2013)
‚dus. An instruction pipeline operates on Wstream of instructions bY

is fetch, deoode and execute phases ofthe instruction cycle. An

In bon pipeline reads consecutive instructions from memory while previous
a ana es being exceed in other segments. This makes the instruction
serie Phaces to overiap and perform simultaneous operations
Fo digression associated with such a scheme is that an insructio

o-segmeit pipeline. By means 0
is; the-istruction fetch segment can be implemented
bi a Queue rather than a stack. Wienevet

Unit 0 26)

sn wit sot sing MEMOS he conto inrement the pra counter
esto res val 10 read consecuve Insucion few monas
tea ed into the FIFO ber o be execu oma ti, Fat
cons a instruction Sream can Be kept ina queue. wang lor decoding
Hg by the execution segment. The instruction steam au
Ponge econ mega Takei een ais
ifr edi instructions. Whenever there pace in he FIFO Bulle,
nm uni tacts the next instruction fetch phase. The ble works like a
co which contro exratsche änutions forthe execution un

int

è

In addition to fetch and execute phases, computers with complex
cseaction need oth phases 10 process an instruction completly. In the
sat general ense, the COMPULET Tequites to process each instruction with the
Aloving sequence, of steps —

(6) Fetch the instruction from memory.

(i) Decode the instruction.

(ii) Caleulate the effective address.

(iv) Fetch the operands from memory.

(9) Execute the instruction.

(vi) Store the result in the appropriate place.
¿me instruction pipeline does not opersie at its maximum rate due to
‘Gindifficulties, Different segments may take different times to operate on.
‘teazoming information. For certain operations, some segments are skipped.
Asanexample, a register mode instruction does not require an effective address
‘atulaion. Two or more segments may need memory access at the same
Ine, causing one segment to wait until another is finished with the memory.
By using two memory buses for accessing instructions and data in separate
module, memory access conflicts are sometimes resolved. In this manner,

m word and a data word can be read simultaneously from two

Aeent modules

plie its function depends on the instruction and the manner itis executed.
an, OUr Segment Instruction Pipeline — Suppose thatthe decoding of thé
mación can be combined with the calculation of he effective address into
jos Segment. Further, it is assumed that most of the instructions place the
Jul into a processor so that the instruction execution and storing of the
Ia Lean be combined into one segment. This reduces th instruction pipefine
0 four segments:
i gg sing ofthe instruction cycle in the CPU with a fourssement pipeline
wn in fig, 5.8. At the time of executing an instruction in seginent 4, the

sai ticos. aoscage i busy’ Fetching an operand from m
Sei pereepante sient circu, the effective address can be

A Be Wird visados, and whenever the memory i available, he fo
e de enorm insinictions cas be fetched and kept in an instr tion Fe
0.

lane po er tapar nthe instruction cycle can overlap ang
‘our fret instructions ean he in progress of being processed at the ot
cola iets he Same

né
eich struction
from Memory

Memory 5
cole

the sequence may be a program control
normal sequence, In such a case, the
rgments are completed and all information
leted. Then, the pipeline restarts from the
counter. Likewise, when acknowiedged,
Pipeline to empty and start again from 2

|

4

1

| sep instruction 1 is being ex

{he other instructions

[ua be used. Then, the pipeline continues until a new branch instruction is |
pip

}® sore the result of the operation in the data men

actor

E

(ernst, Fo

vo

=
of

4H

Fig. 5.9 Timing of Instruction Pipeline
‚The operation of the instruction pipeline is shown in fig: 5.9, In te |
nial axis, the time is divided into steps of equal duration. Four segments
ted in the diagram with an abbreviated symbol.

() Segment Fl fetches an instruction
(i) Segment DA decodes the instruction and calculates the effective

io
re denot

ss
dinéSegment FO fetches the operand.
(iv) Segment EX executes the instruction.

[Lilisconsider that the processor has separate instruction and data memories
sb operation in FI and FO can proceed at the same time. Ifa branch
"im is absent, each segment operates on different instructions. Hence, in
uted in segment EX; the operand for instruction
‘Ysbeing fetched in segment FO; instruction 3 is being decoded in segment DA;
‘od instuction 4 is being fetched from memory in segment FI.

Now, consider that instruction 3 is a branch instruction. As soon as this
stuction is decoded in segment DA in step 4, the transfer from FI to DA
‘halted until the branch instruction is executed in
8p 6, tn case the branch is taken, a new instruction is fetched in step 7.
Menthe branch is not taken, the instruction fetched previously in step 4

SSountered, q
nthe pipeline, another delay may take place, if the EX segment requires
ory while the FO segment

"quites to fetch an operand. In such a case, segment FO must wait until

ment EX has finished its operation.
217, Draw a four segment instruction pipelin
ram, 2

je. Also draw the timing:
(RGB, June 2010)

Sine 2014),

Draw a four segment pipeline. RGP.

Ans. Refer ta Q.16.

© GK Formule a si segment instruction pipeline for a computer
‘the óperailos to de performed in each segment. RGP, m
"Ane. The pipeting must have more Stages to gain speedup. Fig
six ing iustructior pipeline for camputer The decom,

' provessing inte six segment s-us follows

ec
me 2073,
5.10 sho,

[Cin Operands

Update PO
Empty Pipe

Fig. 5.10 Six Segment Instruction Pipeline
8): Fetch Instruction - Read the next expected instruction ino +

(li) Decode Instruction =Determint: the opcode and the operand
specifiers,
» (iti) Calculete Operands - Calcülate the effective address of ech
Saurce operand. This may involve displacement, register indirect, dis
+r other forms of address calculation.

13. 60) Fetch Operand Fetch
in registers.need not be fetched. *
6) Execute Instruction - Perfor the indicated operation and *
the result. iF yi the specified destination operand location.
09 Write Operand ~ Store the result in mieinory.

és
cach operand from memory. Ope

or

Um are
a, Diferentiate instruction and arithmetic pipeting e

4
= RG

= K Jame 2014)
piferentiate between arithmetic and instruction peine,

(RGPF, June 2016)
arithmetic pipe

ns. The differences between instruction and abhi
BE instruction pipeline used to process alt instructions,
¿smetic pipeline is used 10 process arithmetic a
sion, subtraction, multiplication et.
m AM high performance computer are now equipped with
snocion pipeline. The number arithmetic pipelines varies fo processors
¿lo processorss

(üi) In instruction pipeline, the execution ofa stream of instructions
ante pipelined by overlapping the execution of the current instructions. An
imei pipeline divides an arithmetic operation, such as a multiply, into
elige arithmetic steps each of which is executed one-by-one in different
‘gs in the ALU.

020. Whatis the difference between instruction pipeline and arithmetic
pine ? What ure the advantages of pipelining ? (RGR, Dec. 2006)
1 Any Refer to Q.19.

Alvantages of Pipelining —

@) Pipelining offe
alim in digital compute
| (i) Pipeline processing has led to the tremendous improvement of

m throughput in the modern digital computer.

i whereas

© instructions such as

an economical way to reálize temporal

0.21. What are different conflicts that will ris in pipeline ? How de
| puremove the conflicts ? (GRS, Dec. 2012)

À Ans. The difficulties that cause the instruction pipeline 1 deviate fri
‘mal operation are called instruction pipeline conflicts. There are three, à
"ajo instruction pipeline conflicts, which are explained as below ~

5 re caused by avcess 18
(8 Resource Conflicts - These conflits ar access
‚mory by two segments at the same time. Most of these eonfiets cam be

“solved by using separate instruction and data memo

‚nic arise when am
i) Data Dependency Conflicts - Such cont u. ré iid
mitetion depends on the result of a previous instruction,
}yetavaitable

3d

ill dec a
N à degradation of performance in an in
preteen Pet instructions di nat complete certain op
rn Pe a, dependency takes place when a
he Bras place A tri
i ee u yetwvaable. Asan example, an instruction in
eau det et and which is being produced at “Eo
Segment may require Teich on ape hen
nn imsrcton in segment EX. So. the second ins
eo dat become avilable by the first Inst
RSS dependency may take place when an operand address canna y
cala since fermion required by the addressing mode isnot avait
Seg cumple an instan with register nd
fe eye a revs inicios i ding the
‘epee So the operand access o memory mus be delayed until the nego
de available, Such conflicts between data dependencies are handled y
‘pibetined computers in variety of methods,

Tic sinless sechnique is o inset hardware interlocks. A Creu y
dele nations whose source operands are destinations of instruction
Arber op in e pipelie, is called an interlock. Detection of this situate
ss the section whose source isnot available o be delayed by enough
‘hock gles to resolve the conflict. By using hardware to insert the nea
aly, ds eppreach matins the program sequence,

Opera forwarding is another approach that uses special hardware
ét con un then avoid by routing the data through special pas
between ppehbe sepmenn. As an example, instead of transfetring an ALL
result no 2 desunation register the hardware checks the destination open
ad if seguid as a soure o the next instruction, it passes tHe 1

truc

ir te

‘leccly int the ALU input, by passing the register file: This technique needs |

étions hardware patas through muliplxers as Well asthe cireuit which
ett comic
pean compte he responsibilty fooling dant probs
ss givento the compiler which transtaics the high-level programming languss®
into 2 machine lngioge program oo
Compiles far Such computers 1 des fit
y mers 15 désigned lo detect a data con
inate ‘the instructions as necessary to delay the loading of the conflicting A
‘inserting no-opertion instuctions. This technique is known as delayed 19
tip Branch Dißfieukies — These difficulties arise from branch #
‘ter nacos that han he vali ok PC
While operating un instruction age
ti pipeine, one of the major difficulies
caen of branch instructions: bach instruction may be condo"!
incoditional, By loading the program counter with the target address

struction
ttn 4
ion, À

Uta v 218

sonal branch always changes the sequential program flow. ln à
branch, the control selects the target instruction if the condition in
ep ne next sequential instruction ifthe condition isnot satisfied The
rciraction breaks the normal sequence of the instruction steam, causing,
k operation of the instruction pipeline. In pipelined computers,
ea hardware techniques are used to reduce the performance degradation
A ae approach of handling a conditional branch is to prefetch the target
ion in addition to the instruction following the branch. Both are saved
ihe branch is executed. In case the branch condition is successful, the
tine continues from the branch target instruction, An extension of this
dure isto continue fetching instructions from both places until the branch
ion is taken. At that time, control selects the instruction sream of the
core program NOW; 3

“Another approach he use of a branch target buffer or BTR. The BTB
m assoeitive memory included in the fetch segment ofthe pipeline. In the
SD, each entry has the address of a previously executed branch instruction
sn the target instruction for that branch. In addition, it also stores the next
fer insinietions after the branch target instruction. Ifthe pipeline decodes a
{exc instruction, then it searches the associative memory BTB forthe address
Ale instruction. In case it is in the BTB, the instruction is available directly
| stretch continues from the new path. When the instruction is notin the
578, the pipeline shifts to a new instruction stream and stores the target
| sitet in the BTB. This scheme has the advantage that branch instructions
À Mic have occurred previously are readily available in the pipeline without
| itemuption
___Theloop buffer, a variation of the BTB, isa small very high speed register
fie maintained by the instruction fetch segment of the pipeline. If program
‘op is detected in the program, then it is stored in the loop buffer in its
«sc including all branches. The program loop can be executed directly
hou having to access memory until the loop mode is removed by the final
| ching out

In some computers, branch prediction procedure is used. A pipeline with
"ach prediction employs some additional logic to guess the outcome of a
4 P"diional branch instruction before itis executed. Then, the pipeline starts
{etching the instruction stream from the predicted path. A correct prediction
| Siminates the wasted time caused by branch penalties.
| mal Most RISC processors, the delayed branch procedure is used. In this
Radu the compiler detects the branch instructions and rearanges the
À chine language code sequence by inserting useful instructions that keep the
{ "line operating without interruptions.

edit

|

‘mean by pieline ? Explain Pipeline cop
AS
"209,

(Qh Exp how branch instructions are handled in pipetinig ,
5 RGRE, June 4,

Ans. Referto Q2 10,
2 8.24. Explain the herdware interlocks in relation to pipelining,
(RGP, June 297

2

© Ams: Reles to Q21.
925: Eiplain the operand forwarding in relation 10 pipelining,

(R-GPY, June 201
Ans. Refer © Q.21 2
9.26. Explain the term data dependency. (R.GRY., June 2008, 207
‘As: Refer to 021 4

(027. Explain the term pipeline conflicts.(R.GRY:, June 2008, 2013)

5 Or ‘

Write short note on pipeline conflicts
Or

Wiat do yon meun by instruction pipeline conflicts ? Explain inshor.

(RGP Vs June 2005

(R.GPY, June 2013)

‘Ans, Reñèr Lo QI.

man Na does pipeline improve performance ? Ma ae he arios
bris Aerie ‘affect the performance of pipeline processors ?
ah ir impact on throughput. (RGP, June 2009
„ars Performance Improvement by Pipeliñing — Pipelining offers an
cena torcalize temporal parallelism in Fo omaten. The conce
bles poss in ¿computers similar to asembl nes in an ind
Po egy pelin, one must subdivide input task ino seque
: parias E which can be executed by a specialized hardware sg”
en "ürreutly with other stages if the pipeline. Successive tasks
canes tnt be pips and get executed in an overlapped fashion atthe
task level. The súbdíision uf labor in assembly lines has contributed 1°
se token pipelinine

|
i
i

feed that can be achieved 2

1 EN
Sol Welbave, aa be
sere) "Rn 6, t= 100 ns, n = 200, tp = 20 ns
200% 100
er Ca
6200-1) x20 ~ “78 as
00
Sax = = 10 =
¡3 max 70
Prob.3. The timie delay of the four segments in the pipeline processor

À Pipeline 2

| tine calculated in part (i) ?

Unt-v 25

NUMERICAL PROBLEMS

ron. Determine he number of lack cycles tha takes 1 proc

6-segment pipeline (Ro Dec. 2002)

yo ras in a

Sol. Given. 6 segments

200 tasks
Number of clock cycle

k

tht n- 1)
6 +200 - 1 = 205 cycles Ans.
prob.2. A nonzpipelined system takes 100 ns to process a task. The same
"in be processediin a six-segment pipeline with a clock cycle of 20 ns.
ine the speedup ratio ofthe pipeline for 200 tasks. Whatis the maximum
(R.GRK, June 2009, Dec. 2010)

sreasfollows —
Ty = $0 ns, t= 35 ns, ty = 95 ns and ty = 45 ns. The interface

register delay time 1, = 5 ns. i
() How long would it take to add 100 pairs of numbers in the

) How can we reduce the total time 10 about one-half of the

Sol (i) Clock cycle = 95 +5
For n= 100,
k=4,

1, 100 ns
Time to add 100 numbers = (k + n — 1)

SS 10d 10-7 = 103 ps Ans.

(ii) Divide segment 3 into two segments of 50 +5 =55 and 45 +5

0 ns,

Ap 35 ns, k=
Time to add 100 numbers = (ktn- Ute
5 +99) 55 * 107

= 572 «10 © 5.72 ps

joint pipeline adder to
RGP,

ge Sting oía number be Xy, XX Cone,

ps

ad sg
Dec. igs
x

Fig. S.H Pipeline for Caleulating an Inner Product

1 robe, Im certain scientific computations it Is necessary to perform the
arithmetic operation (4, + 8) (C;* DA with a stream of numbers. Specifyq
peine configuration 1 carryout this task, Lis the contents ofall register

cd dle pipeline for i= 1 through 6. (R:GPV, Dec. 2062)

an intro rary +0)
Fach ones eran tobe implemented in a segment within a pipeline
Foi ae e me osea acombinatinal cuit store
ok pls. Th Y are repsiers that receive new data with ev
Sins Drm meer paco
ReAR OB,

R3+-C,R4 LD, Di

y E is Ay, By, Ci and Di
RSC RED, Ree RIRE Inputs Ay Be Ga
RTE RS «RE Mutiply

|
|
|
|

Unt-v 297
at of each clock is shown in fig. 5.13

m [samen Smet
me Le) “y
= 1 = =
y. [esop | ro
ied een ¡co +09
fat sol crop
pe |la.*na| cn)
me [seal oros Pie
Pisce 0) +00 nennen)
Fig. 5.13

nn
VECTOR OPERATIONS, MATRIX MULTIPLICATION, AND.
|) MEMORY INTERLEAVING, MULTIPROCESSORS,
¡CHARACTERISTICS OF MULTIPROCESSORS

(029. Write short note on vector processing.
Or

(RGP, Dec. 2012)

iy
“Ge definition of vector processing. And enlist its application.

j (RGR, June 2014, 2016)

Am There is a class of computational problems that are beyond the
‘ails of a conventional computer. These problems are characterized by
de ct that they require a vast number of computations that will take a
«menional computer days or even weeks to complete. In many science and
“gineeing applications, the problems can be formulated in tems of vectors
‘4 matices that end themselves to vector processing.

Computer with vector processing capabilities ae in demand in specialized
‘ications, The following are representative application areas where vector
essing is of the utmost importance

(© Long-range weather forecasting

i) Petroleum explorations

(i) Seismic data analysis

(iv). Medical diagnosis

(©) Acrodynamics and space flight simulations
i)_ Artificial intelligence and expert systems
(il) Mapping the human genome

(Vii) Image processing,

seen pm. IBGE Dex yy |
7

ünr:v 219

¿rec dress instruction with three fields specifying the base address

de shortmot on si
se ıype of SIMD machine, Which ha, po | merands. An additional fel dat provides the length o dat noms the
is NE machines designed by Say Din 149" Pris considers thatthe vector operands reside m mem! I
® omnerill A fine © r our Cet Rs. TH à ;
dede Croy-! in 1976 and continuing es on the processor with a lange number of regte
ee nye oy D and cng Se de isn Wis os anh estan st a
ES 19 have dominated seen decades 08 ges por wth iin operation. Fr uch case. the bse
€ ication is full of statements like Led ah in the vector instruction specify a group of CPU reise
re bet crunching application ike sand Fag man
A pie cay afi = lil + eli en ort note on mati multiplication.

Forti ore 0st
wher ch u ae setos. ln
i ies the compa

ble SIMD architecture wel suited
{6 this ype of vector processing is illustrated
Tala 54, This machine takes two n-element
Viens ss input and operates on the
orrespondiag elenens in parallel employing
3 Vector ALL which can operate on all n
ments simikaneously. I generates a vector
Rail. The inpot and. output vectors can be
A special vector register or in memory
‘Veeiot Computers also need to do scalar
=ppériont and med vectorscalar operations.

Qi. What does pipeline, vector and array processors mean in para
nee. (RGPY, June 200)

‘Ans. Pipeline - Refer to Qu,

Vector Processors ~ Refer to Q30.

Array Processors - An amy processors ia processor which performs
‘amputations on large arays of data. An attached array processor is anauslio
Processor attached to a general purpose computer, In specific numeric

‘ompuistion operation, itis intended to improve the performance of the host
computer,

is, arrays of numbers, usually in flo,
to add the ith elements of b and topo”

FB

=

|

Fig. 5.14 A Vector ALU

An SIMD array processor is processor which Has a single instruction

maple = data organization. 1 manipulates vector instruction by mull:

unctional units responding to a common instruction. Therefore both !YPe° of
array protessors manipulate vectors but differ in their internal organization:
u = ‘the general instruction format of the vector processo”

: (RGPV, Dec. 2014

Ans. Fig. 5.18 Stages a possible instruction format for a vector processo!

PRET 5: ]

Fig. 5.15 Insrächen Forma for Vector Processor

|

{int in the product matrix.

ge:

33. Write à sh
(R.GPE. June 2017)
©
Explain any one vecor processing method with suitable Wastration,
(R.GRY, Dec. 2010)

de e ¿lo Mig vi vector puc The
konn matrices consists n° inner products orn* multipty - add operations.
o genios n none amd cure un oy be cn
e ion of wo 33 rain À and D

¡lipication

«example,
Pula as] fou be bis E m4

a onblbn be OS

le | E br bal len en

TE product matrix Cs a 3x3 matrix whose elements are related to the

AE A and bythe ines prod
eye À au by

For example, the number in the first row and first column of matrix € is
‘skulsted by letting i= 1,j = 1, to get

ern = ayibyy + aber + aba

aus requires three multiplications and (afer initializing ey, to 0) three
ition. The total number of multiplications or additions required to compute
matrix product js 9 x 3 = 27. If we consider the linked multiply ~ add
tion © + a x b as a cumulative operation, the product of two nn
ticos requires n° multiply-add operations. The computation consists 0£

inner products, with each inner product requiring n multiply ~ add

tions, assuming that € is initialized to zero before computing each

[eect ie inne product coms ofthe sum of prod rs of

$form

CAB] + Ang AB ADA

al apálcaion & y he cal to 100 or even 1000, The
tion na ire voor processor is shown ini. je
E ge oe ier in memonyar in processor register. The Nay
ee paie and de Haig poi der pps ar agua
dudo Al sementregies int mulipier and agas
lat 0. There hour the adder is 0 forthe frst gh y
ost bb pipes are Al A and B, pis are brought in and multiplicd ara an
Halo pair per cycle; Afr the fiat our cycles, the products begin 1 ye
sad othe Quipüt ofthe adder. During the next four cycles 0 is added to y%
produc süleig the alder pipeline. Al the end ofthe eighth cycle, the yng
pa: Nets AB trough A,B, ar in th (dur adder seaments, and he pa
Tous prodicts, Agi through Ags, are in the multiplier segments, Acne
Begin of the ninth cycle, the output of the addet is A1B and the output of
(Ge mul ie ABs, Thus, the ninth celo stars the addition A By + Asp.
ihc aide pipeline. The tenth cycle stars the addition AzB3 + AgB and soon,
= Tala pattern breaks down the summation into four sections as follows —
CAB + AyBs + AgBy + AuBıs +--+ A2B2 + A6B6 + AjgDy
+ AjaBia ++ A3By + AyBy + Ay Byy + AysBis ++ AB,
+ AgBs + AnBız* ArgBo +.

Wii there are no more product terms to be added, the system insert
oar zeos ino the’ multiplier pipeline. The adder pipeline will then have one
‘paral product in each of its four segments, corresponding to the four suns
Used in the four rows im the above equation. The four partial sums are thea
added to form the final sum,

dy

‘Moher
Pipeine

Taser
Pipeline

Fig. 3.16 Pipeline for Calculating an Inner Product
2:34. Write short note on memory interleaving. (R.GRV., Dec. 2011)
- Ae, Pipeline and vector processors need simultancous access 10 memo
Aroma ar more sources. An instruction pipeline may need the fetching of
instrestig and an operand ut the same time from two different se!

; PART
i à data register (DR). The address register
(AR) and dala regis ess registers receive information

en address bus and the da ave

got a data bus. To dif
sional data

{ont pits of the address are used, The modular system
| amemor ses while oer modules are inte prec

nN word and each module can honor a memory request
‘of the other modules.

Re

1 sates Bo T T

1 a a [Res em
i Reniser | [Roger] | Reser
|

}

ce

|
RE Ei |
| Fig. 5.17 Multiple Module Memory Organi
1 Mebenefit from a modular memory is that itallows the use of a technique
ay as interleaving. In an interleaved memory, various sets of addresses
adlecated to various memory modules. A modular memory is useful in
‘seth pipeline and vector processing. A vector processor which utiles
{afstayinterleaved memory can fetch n operands from diferent modules,
Tie effective memory cycle time can be reduced by a factor close to the
samber of modules. À CPU with instruction pipeline ean take benefit of multiple
{eemory modules so that each segment in the pipeline can access memory
[Férendent of memory access from other segments

tion

|, 035. Define the terms Pipeline, speed up ratio and memory interleaving.
| (R.GRN, May 2018)
| Ans. Pipeline ~ Refer to Q.4.

À. Speedup Ratio - Refer to Q.7.

| Memory interleaving — Refer to Q.34

1,929. What do you understand by multiprocessor ? Write its

ice ast pipeline needs two or more operands tothe ee Ue ‘Mevacteristics, ROP, June 2017)
Forsimltancous access, the memory can be patio" | a
sand do | Whats multiprocessors ? (RGRK., Dec. 2015)
j Or ith
InaßeRne multiprocessor. Explain clearly the characteristics of

rocessors, (RGP, Dec. 2013. June 2016)

> Esplaña the characteristics of muliprog,
Hig AA
teens an interconnection of two or more che
eat ip up ‘The term “processor” in multpro LS
eel hii tala os
fa We EPL or an VO processor: Notmally, a computer system with ar en
5 ho pbs à sted moliprocessor, However. a computer with one CPU a!
ras oF cbite PO pensions i called armultiprocessot system when the capabjji,
are lost to that of the CPU. Two main characteristics
“sen ae sharing nid interaction
Phe hardware structure of a multiprocessor is configured so all cpu,
‘Share the’ main’ memory and so the CPU and main memory share all Lo
‘Although this type of sharing is restricted in multiprocessor sysiem
vale memories, it can be assumed that sharing is a valid con
* ment fk be interaction between processing elements of a multiprocessor
tw complete » funktion, Here; the important point to be considered is the unit
intbraction The basic unit of interaction may be a data element, a record, or
à fe ef records: A multiprocessor is well designed only if it allows different
As af intescóon, A true multiprocessor system must provide intracion
| bebwee complete programs as well as interaction between instructions ol
Paria program
1 Wis possible 16 determine the hardware and software requirements of
‘ulligeacessor only ifthe sharing and interaction levels are precisely defined
_ Accor to PH. Enslow, the salient features of a true multiprocessor system
are sutmrized as follows —
© The system must have two or more processing elements, and
ths capabilities ofall processing:clements must be approximately same.
ti} All processing elements share one common memory unit
di) All VO devices and VO channels are shared by all processing

-cleenis

ñ (iv) The operation of the whble system is controlled by one operatin£

systert; which provides necessary interactions between processors and the

Programs in different levels:

0.37. Write Haven différer characteristics of multiprocessor.
x (RGB Ye, June 2

"Ans. Retorto 0.36.
BIE: Classify mutiprocenors.

clistltction ot mulipmocessórs is done by their
Rule system with common shared men

memo

14 ed system. Each processor element in this system contains its own private

J: Be

unta

eon ly coupled:

À ted à Is coupled moltinemcessor This
| al idly coupled muluprocessors provide à cache men as
amó, Moreover, there is a global common m ses o
Y on CPU Memory that all CPU's caw
| the CPUs by placin
|

à as a shared mer

À Therefore, information can be shared amos
tal common memory.

$e
1° another microprocessor model is the distributed memory or hiosely

fealmemory.The processorsare tied together by a switching scheme designed
À Braue information from one processor to another through a message-passing

“eee. The processors Send program and data to other processors in packets
A picket is made of an address, the data content, and some error detection
ende, The packets are addressed to a specific processor or taken by the first
Saisie processor, relying n the communication system used. Loosely coupled
“sem are efficient when the interaction between tasks is minimal, in contrast
déni coupled’ systems can tolerate a higher degree of interaction between
cs

039. What are the similarities and differences between multiprocessor
and multicomputer systems ?

‘Ans. Similarities - Multiprocessor and multicomputer systems have both
| Sigport concurrent operations. However, there is an important distinction
ctucen a system with multiple computers and a system with multiple
roteS6ors. Computers are interconnected with each other by means of
communication lines to form a computer network.

| Differences - The network includes several autonomous computers that
| may or may not communicate with each other. A multiprocessor system is
À corolled by one operating system that provides interaction between processors

‘oA all the components of the system cooperate in the solution of a problem.

R.GPK, Jane 20/0)

| 0.40. Write a short note on supercomputers.

Ans. A supercomputer is a commercial computer with vector instructions

and pipelined floating-point arithmetic operations. They are very powerful,

Vb-erformance machines used mostly for scientific compuraions. To speed
mize the

%P he operation, the components are packed tightly tos gether to.

dance that the electronic signals have to travel. Supercomputers

| neil techniques for comoving the heat rom cet 1 prova
“om burning up because of their close proximity.

The instruction set of supercomputers contains the standard data wansfer,

manipulation and program control instructions: of conventional coment

Nt is augmented by instructions that process vectors and combinations of

|
ja
{Bhi

1
las

gipeicomputet is > computer system best kgs
e gy
DR ls equipped wih multiple funciona nee
Tn pipet contiguo. Albough the supercomp at
Spurge applications found in all other computo y
E mirad lr e type of mmetcatealeulations involving ye
Tf orling-point numbers. "
20, Seperenmpiden are ot suitable for normal everyday processing op,
pal Copan salados. They are Ried in their use 10 a number q
e te anglicanos, sac e america whether forecasting, sesimie wur.
‘aalystsand space reséarch. They havelinifed use and limited market because |
their high ec.
"Tie fret supercomputer developed in 1976s the Cray-1 supercompuig,
"Al ised vector processing with 12 distinct functional units in parallel, Cra,
Sesh entendet in supmeompaer o snliprocessor configuration cal |
¿Cray XeMP and Cray Y-MP. The new Cray-2 supercomputer is 12 times more
“powerful than the Cray-1 in vector processing mode. Another early moda
" pupercomputr isthe Es VP-200. thas a scalar processor and a vector
“proceso that can pets concurrents

I

>

CSECAT-401 N)
B.E. (Fourth Semester) EXAMINATION, June, 2011
(Common for CS, EC & IT En;

28. Branc
OMPUTEIÏ LA

‘STEM ORGANIZATION

‘Attempt any one question from each Unit. All questions carry equal
marks
Unite.
da) Draw the Von-Neufiann Model Of a digital computer. Explain its
various subsystems, (See Unit. Page 9, 0.6) 10
(0) Explain with the help of examples, the addressing modes of a basic
computer, (See Unit, Page 105, 0.26) 10
or
Dra and explain the architecture of 8085 microprocessor. ** 10
‚Acompüter uses a memory unit with 265 K words of 32 bits each. A
binary instruction code is stored in one word of memory. The instruction
as four parts : an indirect address, an operation code, the register
¡code part to specify one of 64 registers and an address part: — 10
(How many bits are there in the operation code, the register
code part and the address part ?
(i) Draw the instruction word format and indicate the number of
bits in each part
(ii) How many bits are there in the data and address inputs of the
memory ?
(See Unit- If, Page 100, Prob.)
Unit-Il
Explain the following terms
(0 Microinstruction
(i) Microprogram
Gi) Control address register
(») Sequencer (See Unit, Page 80, Q.47)
© Control memory. (See Unit-H, Page 77. Q.40)
Explain the concept of address sequencing. Also explain mapping of
an instruction. * 10

(See Unlt-l, Page 79, Q45)
Unit-Ul, Page 77, Q<

or

) Write down the algorithm for addition and subtraction with signed-

magnitude data, Also draw the flowchart (See Unit, Paged5,Q.14) 10

“according to new revised syllabus ofR.GP.Y it isnot Included in syabus
0)

tipi

Tp etn os 2:80 m
a ae ae (See Ui

2 Unit-tll
Yay, Differenüane between the following:
A Asotated and memory-mapped VO
di) Synchronous and Asynchronous serial data transfer 2
(8) Explain potting and Daisy chaining relied fo establishing prog

res ar RER 043)
ie) Explain the following modes of data transfer

(© Program controlled (i) Interrupt driven,
LE Gi) Direct memory access.

1

292 Whatis an 10P ? Expla
DT TRS

(See Unit, Page 13
Unie
Aa) Dr ad explain the memory hierarchy in a digital computer What
are he advantages of cache memory over main memory 9

a

| > (See Unit-1V, Page 172,049
(o), Whats Associative Memory ? Explain the concept of address space
and memory space in virtual memory. (See Unit-IV;Page 1
or
8... Write short notes on any mo ofthe Following :
4a) Mapping techniques of cache memory (See Unit.
©: Cacheimtializaion and wring nto cache (See U
(©). Types of RAM and ROM
(8) Memory management aa

10 cach
Page 164, 0.32)
Page 166.0.38)

(See Unit-IV,Page I

9. (a) Weite dem the Fist classification of Computer. i

|
|

(See Unit-V, Page 196.22)

vector and array processors mean in parallel

+ Ab). What does pipeline,
x LV, Page 218, Q31)10

Processing ?

addition a
Page 204.0

i 0

BE (Fourth Semester) EXAMINATION, pe 291
(Common for CS, EC & IT Engg, Roues?
COMPUTER SYSTEM ORG une

Attempt one question fromeach Unit, Total

we: Questions tobe atte

Nome re five. All questions carry equal marks as
Unit-1

1. (2) Discuss the orgaiization of 8085 microprocessor. What ae the

different flags of 8085 flag register ?
(0) Explain the following

(i) Microopérations

di Maérooperations

(ii), Program counter eur di

(iv) Instruction cycle a

y (See Unit-M1, Page97,Q.15)

“10
each
Page 29,031)

(Ste Uni

Input output instructions
or
Draw a common bus system with four registers withthe help of
multiplexers (See Unit. Page 24, Q.30 10
(0) A digital computer has a common bus system for 16 register of 32
bits each. The bus is constructed with multiplexers 10

® How many selection inputs are there in each multiplexer?
(i) What size of multiplexeris needed ?
(ii) How many multiplexers are there inthe bus ?
(See Unit, Page 17:Prob.3),

niet
Explain how the mapping from an instruction code toa microinstruction
address can be done by means of a read only memory. E o
©) With the help of block diagram, describe the organization of a
miroroganmed contol unis CU Page 1,023) 10
Or 2
Explain the following in detail PA
i) Address sequencing

©) Draw and explain the organization of a CPU showing the connections
betwen te eto Lap. 01510

10

common bus. (See

“Now according tonew revised syllabus of. GP. itis ot included in splabus
® a

eg Unkel

da): Differentiate between the following

a ki) > Synefronois end asynchronous modes of serial data {rang 10
© Gay term inkitised VO and direct memory access,

(See Unit, Page 131,
Fb) Explain ln bref the instruction set of 8085 microprocessor
on types of insrctons).

(Give

or 10

What ae de diferent types of DMA techniques ? Explain the base

principle of DMA. (See Unit-IH, Page 134, 0.56) 15

Explain priority interrupt and polling in contexto interrupt init

vo. (Gee Unit-II Page 122, Q.39) ja
nit.

1a) What is meant by memory hierarchy in a computer system ? Also
wry?

explain what is meant by associative memory and virtual mem,
(See Uni
(6) Explain the following in relation to cache memory
(i) “Locality of reference (See Ui
Gi). Bitratio E
EN Mapping
(iv) Writing into cache
(9) Cache initialization.

Or
Explain memory protection and memory seg

: Management hardware, =
The access time of a cache memory is 100 ns,and that of main
memory is 1000 ns. It is estimated that 80 percent ofthe memory
‘equests are for read and the remaining 20 percent for write. The hit
‘tio for read access is 0.9, A write through procedure is used — 10
6) + What is the average access time of the

Seb memory ead eels?

„What isthe average access tine of the system for both read

in Sie ees?

(U Wet is the hit ratio taking into consideration the write cycles ?

(See Unit-1V; Page 174, Prob)

system considering

Unit-v
What is pipeliting? What is in e
tion OF aaah tit need of pipelining ? Explain the pipeline
ration times pito. "See Uat Page 206. 0.1929
fom according to em Fevbed labs of GP, itis not included in US
ow),

write short notes on any two of the following

Computer Architecture
Or

10 each
1 (4) Vector processors and (See Unit: Page 218, 030)
array processors ve)

(1) Interconnection structure =
(e) Interprocess communication 2
(6) Memory interleaving. ei

CSAT-402 (GS)

papel BE. (Fourth Semester) EXAMINATION, June, 2012
R (Grading System)

2 (Common for CS & IT Engg. Branch)

Note =

(a)

©)

2 (a)

o

0)

COMPUTER SYSTEM ORGANIZATION

Attempt all questions. All questions carry equal marks.
"Describe the Von-Neumann model and explain the functioning of ts
components. (See Unitel,Page9,0.6)
Explain and draw a diagram of a bus system that use multiplex k,
register of n bits each to produce an #-line common bus.

(See Unit

Page 23,0.29)
Or

What is instruction cycle ? Explain different phases of instruction cyel
and show flow chart for instruction cycle. >
Explain various addressing modes with the help of example.

(See Unit, Page 105,Q.26)
Discuss in brief microprogram control unit and hardwired control
unit (See Unit-1I, Page 72, 0.34)
Draw and explain flowchart for addition and subtraction of floating
Point number. (See Unit-1, Page 65, Q.27)

Or
Represent the number (+ 46.5)19 as a floating point binary number
with 24-bits, The normalized fraction mantissa has 16 bits and the
exponent has 8 bits. (See Unit-U, Page 68, Prob.12)

Define the following:

(i) Micro-operation (Set
(i) Microcode (See Unit, Page 80, 0.46)
(ii) Microinstruction (See Unit-, Page 77,043)

(iv) Microprogram. (See Unit-I1, Page 79, 0.45)

y Nom, according to new revised syllabus of R.GP.V, itis not included in sylsbes

pa

eee
in Wh soläble csample the working principle of DMA contra.
Fa ee it,

What de you mean by intemapt? Explain

techniques ? a
0

Vit do you mean by sinchronous and asynchronous data transfr ,

Explain handshaking method of asynchronous data transfer,

Esplai the use of the following instructions

(i: DAA GRIM €

‘What is cache coherency ? Why is it necessa

‘approaches for cache coherency. e Un

Explain associative memory with ts hardware or

the procedure for reading and writing data i
(eu

ociative memory
AVP
o
Explain in shoe the following
) Memory Hierarchy (See Unit-IV, Page 1.
() Memory Management Hardware
‘Whats pay ? Explain how paging ean be implemented in CPU wo
acces vial memory (See Un
Formulate six segment instruction pipeline fora computer. Spec
te operation tothe performed in each segment

E (See Unit-V, Page 210.9
Draw and explain the typical functional structure of a SIMD array
processor

oy

ta)

o

Explain te followingremne= 7
di): Data dependency
tib. Pipeline conflicts
(ui) Interpröcessor communication
(Us) interconnection structure

(See UnitW Pay
(See Unit-V, Page

.Q20)
214,027)

BE Pr Some EXAMINATION, Dec. 2012

OMPCTERSISTEM ORGANIZATION
(Gsirtaary

LINES)

() Auternpi any one questi a
y Oe question rom

nol included in syllabus

@

»

10)

N)

“

w

according To new revised syllabus of R.GP.V, is not included in syllbos

Computer Architecture

Unit

the different types of registers used i

explain
Expat how these registers are connected to à

in a basic computer.
Explain a

Common Bu
(See Unie. ag
age 22, 0.26)

din and eiplä thé functional block diepran cre!
Dra Also draw its flag structure, dr

Or 7
‘A digital computer has a common bus system for 16 registers of 32
fis each. The bus is eonsiucted with imliplerene ee 0722
(0. How many selection inputs are there in each multiplexer?
Gi) Whatsize of multiplexer is needed ?
(ii) How many multiplexers are there in the bus ?

(See Unit Page 17, Prob)
how the hardware that implements the following statement include
the logic gates for the control function and a block diagram for the
digas bguntcr with a count enable input 7

xyTy# Ty +y Ta: AR € AR +1

(Gee Une.

proces

1026, Prob)

nit
Draw and explain functional microprogram control unit block diagram
(See Unit-I, Page 71, 0-32) 7
Write short notes on the following : (Any Two) 7
(Control memory (See Unit-, Page 77, 0.40)
(i) Nano programmed control unit Se
(ii) Hardwired control Unit
Or A
Explain phases of instruction cycle. Also draw and explain instruction
cycle flowchart. E
Draw the block diagram of a BCD adder. Explain how decimal
subtraction can be performed. iL
BIN
Differentiate between isolated VO and memory mapped VO and give
advantage and disadvantage of each. if
‘What are different modes of data transfer? Explain the DMA controller

With block diagram, What is meant by block transfer ?
‘See Unit-T, Pa

(See Unit-11, Page 69,091)

or
What do you mean by intemupt ? When a device interrupt occurs,

how does the processor determine which device issued the interrupt ?
oes the Processor determine PR a, Page 122,0.38)7

m

Computer Archtactine

Neumann model and explain the

‘iy als the dat transfer insruction of 8085 microprocessor. y

functio

aa angune program lo add 1x0 Sit number 46H ang 3 rire
“nd store the result at 4008 a r
Auen | Draw and explain the bus tre for the data transfer betwen
10 Wai cache memory? Expandir! mapping techniques 13 0 pages an the common bus te do
ache memory system, (See Unit, ae | ne og om
(oy Ase mise este consis of 64 nes. oF los divigeg | FT ter (See Unit Page
09 Akne seu, Main memory contains 4K blocks of 128 words qu 00: Thee sie bate Orts
Show’ te formar of main memory addresses and tag bitin get | (D Con i st a
Los (See LIN, Page 176, Propays | di) Micro operations Riel FE
be | Unien

(a) What do you mean by associative memory ? Explain match logic of

Associative memory withblock diagram. (See Unit Page 180,019)
(b) A digital computer has a memory unitof64 Kx16 and a cache memory,
+2 Of 1K words. The cache uses direct mapping with a block size «y

| 4. (m Drawand explain the microprogrammed control unit withnext address
pu gemein, (See Uni. Page, QG)
(o) Explaindhehardwäre for signed magnitude addition subtraction with

¡dq ize of | block diagrams el (See Unit-H, P 14

@ How many bits are there in the tag, index, block and word | 5
fields of the address format ? 4. (a) Compare horizontal and vertical organization. Give their advantages
(6) How many blocks can the cache accomodate ? and disadvantages. (See Unit, Page 83,052)
(i) How many bits are there in each word of | (0) ¿Describe in detail Booth’s multiplication algorithm and its hardware
Y age 174, Prob.6) implementation (See Unit-I, Page $0,018)

A u Unit-m
(a). What are different confit that will rise in pipeline ? How do yöll

remove the conflicts, (See Unit-V, Page 211, Q.21)7
(b) What is pipeline speedup ? Draw a space time diagram for a Sike

segment pipeline showing the time it takes to process eight tasks
(See Unit-V, Page 204,Q.12)7

(6) Whatisa DMA transfer? Explain in detail how this is accomplished.
See Unit, Page 129,047)

® Explain the classification of the instruction set of S085

e microprocessor with suitable example.

. Waite noes on following y or

(a) -Interprocessor communication *

ee process (See Unit-Y,Page217.Q.9)

(a) Why is priority handling desired in interrupt controllers ? How do the
| different priority schemes work ? — (See Unit-I11, Page 128, Q.44)
= (0) Write an 8085 code to obtain 2's complement on the 16 number
a E stored at locations x and x + 1. Store the result in y amd y + 1
ET P= (Fourth Semester) EXAMINATION, June, 2013 | locations.

LT. ¡COMPUTERSYSTEM ORGANIZATION
a” (OS/TT-A02)

€) “Altempt one question from each Unit.

Unite
(3) Explain associative memory with its hardware organization. Explain
how the data is read and write in the associative memory.
(See Unit-V, Page 150,049)
(©) Whatis paging? Explain how paging con be implemented in CPU 10
| © Mate Een ou pre re a US
" (a) Write short notes on —
(6) Cache memory

7 according to new revised syllabus of RG, is not included in syllabus
0

bte :

Gi) All questions carry equal marks,

157, 0.23)

(See Unit-IV,

ae Management Hardware.
ie gites paco computer sySiem consists OF 128 yy,
RS: Frs cs oe into 32 pages of 4 K words in euch, eu
ter consists bf 4K blocks of 4K. words in each, Forms ®t
Bical and physical address formal... (See Unit-IV, Page 191, Ir, Ue
> Unit-V 5
Abr do you mean by paralle) processing ? Write the Flynn.
élastificurron of parallel processing. See Unit-V, Page 198, 9.30
OÖ Eeplai and draw the model of crossbar switch organization po
cesabishing an incercoanection network in multiprocessor system, 19
: x or
D! Write short motes ~ |
18). Arithmetic pipeline
A} Intesprocessor communication
{Hi} Pipeline conflicts
{8} Hypercube interconnection.

)

(See Unit-V, Page 204, 9.13)

(Seel

XAMINATION, Dec. 2013
‘COMPUTER SYSTEM ORGANIZATION
x: (CSAT-402)
az
sie! RM). Atiempt one question from each Unit
LA AML questions cary equal marks.

R Units
(8). Wali the Fech and execute cycle for the following instructions:
00 AND ** (ii) LDA **

10) Draw Vón-Ncumano architecture, What à cum:
Deve me. What Wan: tage nenne

a À or
(a) Whar istinstniction cycle ? Ex;
ion cycle ? Explain different phases of instruction
cycle and show flowchart for instruction Ent dl
(0) Write the fiction of the following in computer sy
(D Accumilltor

stem

D (See Unit
Gi) . Instruction régisier (See Unit-1, Page 1:
ii. Memory Address Register (See Unit-L Page 15,017)

(iv). Program counter, 14,010

(See Unit=1, Pa

419),

Computer Architecture
Unitar
What are the major design considerations in
sequencing? (Seel
Draw Nowehart to explain how addition and subte
1 im numbers can be done, Also draw
for the same,

micro instruction
1, Page 80, 0.49}
tion of two fixed

À cna ting fll es
(See U P se

Or
4) Hardwired control unit is faster than micropre
pe i stity this statements
| (m) Explain Booth’ algorithm with i theoretical
(See Unit, Pages0.Q18
| J 150, Q.18)
|; ( What isan inputoutput Interface ? Explain the isolated versus memo
mapped VO, ps
{b) White instruction (8085) to: Load 00H in the accumulator, dceremeat
| the accumulator: Display the result,
or
| à (o) Whatlare the different modes of data transfer? Explain each mode in
I desa (See Unit Page 11.027)

(0) “Write an assembly program to obtain an multiplication table of 12
using repeated addition,

u
j paged segmentation, the reference time inereasesand fragmentation
decreases", Justify your answer.
(b) Write about the hardware for memory management ae
Or
8. (a) Explain multiport memory organization with neat sketch, ++
| (0) Explain how associative memory page table is used for effective

(See Unit-IV, Page 155,Q.22)

storage utilization,
Unit-V R
fine multiprocessor. Explain clearly the characteristics o
pean tga ares i {See Unit-V,Page 221, 0.36)
(b) What are Interconnection structures ? Explain the scheme ‘crossbar
switch in detail.
| or it f tel
(8) What is parallel processing ? Faplin she sgnfianes of perl
racessing. Li Yran’s classification of computer
Progeasiag List the Fly el (See Unit-V, Page 198. Q.3) 4

Write short notes er
(Array Processor a

: lo Pipelias! (See Unit-V, Page 206, Q.16)
| 0 Instruction Pipeline, not included in sylabus à

“according to new revised syllabus of RGP:
an

Sp hear Seve) EXAMINATION, June,
RE Wow ERSYSTEM ORGANIZATION
ieee (CS1F-402)

(0. Answer five questions. In each question part A, B, ¢ à
12 parry wt D par as intra choice. s
iad Al pars ofcsch question are tobe attempted at one place,
A Al quecdcns carry equal mars, out of Which part A and y

(Max. 50 words) carey 2 marks, part C (Max, 100 words,
“La 3 mart, part D (Max. 400 words) carry 7 marke
Except numerical, Derivation, Design and Drawing eto.

25 Units

di) “How many operations this code can perform ?
(D: How many memory locations can be addressed ? 2
SH (See Unit-I, Page 99, Prob.1)
e) “Convert hexadecimal number (F3)yg into decimal number. / 3

À © (See UnitIKPaged3,Prob.1)

| (4) Briefly éxplain all the addressing modes of computer instruction. 7
: (See Unit-IMgPage 105. 0.26)

Or

> Draw und explain Von Neumann model of computer and explain its
subsystems, (SeeUnitlyPage 9, 0.0 7

E ¿(See Unit-, Pa

Br. ‚Write a Brief note on mictöprogram >

oe {See Unit-I, Page

‘the following tio statement two register

1) den ORI. R2) else if (Q = 1) then (RI R3)

RIEF (See Unit-1, Page 26, Prova
63 A

3

Computer

iferentiate hardwired and microprogrammed contro!
Ds and demerits of each of them. (See Univ il. Page ri. n

Or
‚Take an example and explain the design of arithmetic and logic unit
(See Unit-M, Page 34, Q.3)

@
‘ Page 74,0.36)7

j Unit
Classify instruction set of 8085 “2
Differentiate simplex, halfduplex and full duplex data transfer ++ 2
Briefly explain Daisy-chaining priority method of intemupt. 3

(See Unit, Page 126, 0.42)
Write three modes of data transfer and explain any one of them. 7

(See Unit IM, Page 1.9.27)

w
| ©

| or
What is assembly language programming ? Write any one program
| in assembly language and explain it. 7
| Unit-1V
cone example for primary and one for secondary memory. 2
(See Unit-IV Page 142.07)
Ye jarssplain hit ratio in cache organization.(See Unit-IV. Page 169, 0.40)2
Give one-one example for semiconductor, magnetic and optical
memory. (See Unit-IV, Page 142,0 3
(a) With the help of a diagram explain how cache is used in cache
“organization. Explain mapping techniques. (See Unl-IN Page 164,Q34)7
or

Give a short note on virtual memory organization. What is Paging ?7
181, 0:54)

4. (a) ¿6h

©

(a) Draw a four segment pipeline. (See Unit-V, Page 209. 0.17)2

sion. 2
0) ive definition of vector processing Ad ali appli.
: E (See Unit-V, Page 217, Q.29)

Derive an expression for speedup ratio ofa pipeline processing. 3

(See Unit, Page 201,07)
segment pipeline showing the
See Unit-V, Page 203, O11) 7

i (d) Draw a space time diagram of a six
time it takes lo process eight tasks

or ;

i fferentat instruction and arthmeti pipeline .

H eee (See Unit-V. Page 211, 0.19)
|" Nonjaccording to new revised syllabus of LGV, Itismotincinded insyllabos
aa)

AMINATION, Dec 55

FE OMPOTER SYSTED ZATION
RGPV § x ges SCSI)

Answer five questions. In each question part À, y €
compulsory and D part has intemal choice. i
A pars of each question are to be attempted at one place

All questions carry equal marks. out of which part A ang y
(Man. $0 words) carey 2 marks, part C (Max. 100 wong.
scary 3 marks, part D (Max. 400 words) carry 7 marks or

iv). Except numericals, Derivation, Design and Drawing ere
E Ue
(Ge) Explain tbe data ransfer between register and memory
(8): Draw and explain the implementation of 1-bit register.
A (See Unit, Page 19,02,
49 Draw the fimetionat block diagram of microprocessor 8085 any
explain in bret. .
(8) What is the difference between a direct and indirect address
2 How many references to memory are needed for cach
‘ype of instruction to bring an operand into a processor register?
Give attest three examples of each type, (See Unit-Itl, Page 94, Q.13)
or
‘What is instruction cele” Explain different phases @Piinstiétion
5 Uniti
18), Whatis meant by Hardwired control 2 (See Unit: Page 68, 0.30)
$0). What is microprogramming and microprogrimmed control unit ?
(Gee Unit-tT, Page 75.0.
19 Compare horizontal and verse Organization, Give their advanta
‚and disadvantage (See Unit-11. Page 83, Q.
(a) With neat block diagram, explain the working principle
MÉEPPrOYram sequencer, (See Unit-Il, Page 80.0.

E or
Esplain-Rooth’s algorithm f :
nut ul sonithm for multiplication of two fixed poin

ee Mastratethe:same with a sumple multiplication of IVO

numbers of your choice (Gee Unit, Page 50.048)

' accardingto! ‘Rev revised syllabus of GP. is not Included in syllabus
414)

Computer Arias”

Unit-THt :

what do you mean by programmed 10 (See Unt, Page 12 Q28)
Explain the drawbacks in programmed LO and tnterrupt driven 110
16,031

Draw and explain typical block

I, Page 131,083)
ay Write an assembly program 6 obtain the multiplication table of re
O using repeated addition.

or

How is imerrupuV/O better than programmed LO ? Discuss
completely how the vatious signals are exch:

(See Uni

I, Page 116.032)
Unit-rv
What ¡8 cacho memory ? Why is

it implemented Y

(See Unit-1V. Page 159, 0.26)

(b) What is cache coherency ? Why is it necessary ? Explain different

approaches for cache coherency. ait, Page 173,046)

Draw and explain the virtual memory organization,

(See Unit-IV, Page 176,Q.47)

Explain associative memory with its hardware organization. Explain
how the data is read and write in the associative memory

(See Unit-IV, Page 150, Q.19)

Or
What are the various mapping methods used with cache memory
organization ? Explain any one in detail. See Unit-1V, Page 164, 032)
Unit-V

Explain the basic structure of pipeline processor.

(See Unit-v, Page 200, 0.5)
plain the general instruction format ofthe vector processor.

(See Unit-V, Page 218, 0.32)
Write a short note on hypercube interconnection. “
What is the purpose of system bus controller ? Explain how the
system can be designed to distinguish between reference to local
memory and reference to common shared memory

Or

Draw and explain the: model of erossbar switch organization for
establishing an interconnection network in multiprocessor system J
How many switch points are there in a crossbar switch network that
connects p processors to m memory modales

ee BE
"Som, according to new revised yllabusoFR.GP.V, itis not included in syBabus

45

(1) Answer five questions. In each question part A,
compulsory and D part has internal choice.

(i) Ait pans of each question are to be attempted at one place

i) AN questions camry egal marks, out of Which part À ang y
Max. 50 words) camry 2 marks, part C (Max. 100 won
carry 3 nurks, part D (Max. 400 words) carry 7 marke el

Gis) Except numericals, Derivation, Design and Drawing ete

Unit

Beis

(2), {tube content of address bus is 0101 and the content of data is 1199
snd read write signals (se), then what do you understand by th
information ? -

(01. Conver the following numbers with the indicated bases to decimal
22 Gi) (4310),

(See Unitll,Page<43, Prob)

(6) Explain, what do you understand by instruction cycle, Explain with
the bel of flowehan. »

{Ar Explain corinon bus system architecture with the help of diüfäm.

(See Unite, Page22, 0.28)
or
Write down different types of registers used by CPU, so e:
ed by CPU, aso explain
the general register organization with the help of diagram. a
(See UnitchPäge 180410
vain
48) Design the half adder with the help of its truth table. a
(9. Itwe are working wit 8-bit compute
y, then whatwill be the size of
een opt
te} - What is, microinsuru

i formal? Explain different field of
io Sn (See Unit-I, Page 78.0.4)
you understand by microprogrammed control ? Explain the

Block diagram of micro programmed control organization.

(See Unit-11, Page 72,039

+ Or
According to NeW revised abus [RGP
ts)

ts not included in syllabus

À (a) Woe down diferent modes ofatatanster. (See Un

Computer Archi
he memory unit of a computer has 256 K words of 32 bit each,
Te puters an suction format wil tas a see, The
STE lo pei one olsen mao ee
field 1 specify one of 60 processor registers und a memory ade
rei mn mr at mero o is.
Son mn me word (an nie
Uni
y Why does DMA have priority over the CPU when für . :
memory transfer ? (See Unit. Page 130, 0.50)
Ne rasen pasion ar crane
Ge te GAS)
(0 Wi da gen lan prog int Due a
for interrupticycle 2 (See Units, Page 125.Q.40)

(0

Or
What 18 difference between isolated Input and Outpu and memory
Mapped Input and Output ? Write different advantages an
übadvanınges ofeach, nd
Unit-1V
À, (a) DraW the memory hierarchy. (Sec UniIV Page141,04)
19) Point out the difference between direct mapping technique and
Associated mapping technique, wit he help ol example
(See Univ Page 164,030)
(©) Anaddress space is specified by 16 bits andthe corespondin memory
space by 8 bits
{0 How many words are there inthe address space ?
(i How many words are there inthe memory space ?
(See Ne Page 191. Prah 10)
(@) Explain the concept of vital memory with he help of example
(See Unie Pate 176047)
or
A digital computer has a memory unit of 64 K * 16 and a cache
memory of 1 Ko words. The cache uss dise mapping with a Bock
size of four words =
© How many bits are herein the a,
address format
(ii) How many bits are there in each ne and how are the)
divided into funcion ? Include a valid bit
i) How many blocks can th cache accommodate?
rd (See Unit-TV, Page 174, Probiti

Is not included in spltabus

index, block and word field 6!

iow, according to new revised ayllabos of RGP.
en

ipeline:? (See

ua) Wan yon wma armee pi

LU ove un ds fre between sion
Stay Wine doi different Characteristics of multiprocessor.

See Unft Page 222 q 4,
ic ys toherence and why is il important in shared me

a tem? How can is problem be resolved with sage"?
cha controller ? {See UN Page 173,9,

= or
Wii d 1 und by inter processor communication? Exp
it the beip pf example ain
| RE. (Porth Semester) EXAMINATION, Dec. 2015
¿COMPUTER SYSTEM ORGANIZATION
{CSTF402)

Answer five questions. In each question part A, B, C
compulsory and D part has internal choice.

il). Al! pars ofeach questions are to be attempted at one place.

{iii} AU questions carry equal marks. out of which part A a
AUS 90 words Gary 2 marks, part C (Mas, 100 word]
teary 3 marks. pat D (Max. 400 words) carry 7 marks

(iv) Except numerical, Derivation, Design and Drawing etc.

Unit

(a) What is registers 7 (See Unit-1, Pi
see Unit-I, Page 12.Q.11)
(DI Write down the basic function of computer. (See Unit-I, Page 3, 0.1)
fe). Define implicit and register addressing mode with example.
à See Unitslll, Page 104, 0.24)
(@) Explain Von-Neumann model for computation.
(See Unit-l, Page 10.0.0)

or
Draw the block diagram of 8085 mieroprocessor.
Unit

(a) What is the parity bit and why iS 2

and why we seit 2(See Unir, Page 63, 024)

(2), How te selection of address À done In contol memory.”
Draw and explin cal hardwired control unit

i (See Unite. Page 69,031)

(4) Wat are the major design considerations in micro instruction

sequencing ? (See Unit-H, Page 80. 0-49

Va itis not included in sya

Computer Architecture:
Or
explain flonting point representation with example
(See Uniti, Page 62, Q.

1 Unitat
| ay Define the term LO interface a
[% (m) Define the term simplex, half duplex and full duplex $
1 {a Liat the features of (OP. (See Unit Page 126,9)
À {a Explain the different modes of ster beten
j computer and VO device. (See Unit1IL Page 111,027)
Explain handshaking method ofasynchronous data transfer with diagram. **
Unit-IV x
4 to) What isthe usée viral memory in computer system?
; (See Unit-IV; Page 176,Q.47)
(6) Explain the Operation of cache memory(See Unit. Page 1570.29)

(See Unk-IV; Page 150,019)
‘computer system

(0) ¿Draw block diagram of memory hierarchy i
AN, Page 140,03)

| fandexplaininbrief,

Write short notes on ‘Memory Management Hardware’
Unit-V

| 8 (a) What is Flynn’s Taxonomy ?
(b) What is Multiprocessors ?
(©) What is parallel processing

processing.

Give a summary of arithmet

for the vector architecture,

| Or

What are the different forms available to establish an inter-connection

network ? Give the summary of those.

(See Unit-V, Page 196, 0.2)
(See Unit-V, Page 221, Q.36)

? Explain the significance of parallel
(See Unit-V, Page 195. 0.0)

€ and logical operation that are defined

@

CSmrr-402
IE. (Fourth Semester) EXAMINATION, June 2016
COMPUTER SYSTEM ORGANIZATION
In each question part A.B, C is
/as internal choice.
‘re to be attempted at one place.

its notinctuded in splisbis

Note: (i)

Answer five questions,
‘compulsory and D part hi
(id) All parts of each question

Nom according to wow revised slabs PR GR
fc)

a gots RS arpa C Mar Top and
O e part D (Max. 400 words) carry 7 mark, 76)
era, Derivation, Design and Draw

4), Exeept umeie te
ont
cde and data bus are maltiploxed ?
{00 Why Cet Page 22,2
A, Whats aviary memory ? (See Unit: Page 146 9.19

odel
(See Unita, Py

4) Explain the features of Von-Neumann

A 801.05,
(A) Wat is instruction format ? Explain various instruction format,
(See Unit Page 94,1

or

Explain disen icroopertion wth example. (See Uni, Page 33, q 39,
UNIT-H

fa) Define Micro-program (See Unit-HI, Page 79, Q.45)
(0) Wharis nano programmed control unit ? .
(e), Difereniate betscen hardware control unit and micro programmed

sonmrol unit (See Unit-IT, Page 74, Q.36)
Hardware control und is faster than micro program control unit
Sustfy this sutement, (See Unit-Il, Page 74, 0.36)

“

or

How is multiplication of floating point number achie

ed ? Expl
‘sing flow chat (See Unit $29)

| Page'68, 0.29)

ENT.
y
te)

Wat is DMA? (See Unit-I, Pa
ee Unit-I11, Page 129, Q.46)
What is he role of a priority interrupt ? (See Unit MI, Page 123,037)

‘What do you mean by serial ransmissi
Span 3°" mean dy seal wansmision and parallel transmission

14) Compare and contrast DMA and 1

0 processors.
(See Unita Page 138,0.61)

E Or

Expl daisy, ‘chaitiing priority fordata ‘tratisfer.

(See Uni

IN, Page 126, 0.42)
{ CE "
| (a) What is mésnory hierarchy »

(©), What are the'tharacteratics of.

(See Unit-ty, Page 140.0)
che memory ?

Computer Archiloeting

Explain how associative memory page tabl

lo is used for effective
storage utilization.

E (See Unit, Page 188.022)
Or
swith the help of diagram explain how cache is y,
organization. Explain mapping techniques (See Unit-1V.
UNIT-¥
(a) What is Flynn’s Taxonomy, ? eich
{b) What is inter-connection network ? D
(0 Define multiprocessor\Explain clearly the characteristics of
multiprocessors. (See Page 221.Q.36)
(a) Differentiate between arithmetic and instruction pipeline

(See Unit-V, Page 211.0.19)

ca
age 1640.34)

(See Unity

Or
Give definition of vector processing. And enlist its application
(See Unit-V, Page217,Q.29)

17-228
BLE. (Fourth Semester) EXAMINATION, June 2017
‘Choice Based Credit System (CBCS)
COMPUTER ARCHITECTURE

Notes

() Attempt any five questions.
All questions carry equal marks.
1. (a) Describe Von Neumann model with the help of diagram,
(See Unit-L Page 20,Q.6)
(©) Using 8 bits 2°s complement integer, show how to perform the
subtraction operation 18-16, (See Unit, Page 61, Prob.11)
2. (a) Whats the decimal value of tbc following unsigned binary integers
©) Explain hardwiced micro-programmed control unt
(See Unitll, Page 72,034

3.. (a) What are different addressing modes ? Explain each of them.
(See Unit- Hl, Page 105,26)
(b) Write comparison between RISC and CISC. (See Unit-IIl, Page 104,021)
+ (0) Explain DMA with he he ofblock diagam (Se Uni, Page 131,053)
(0) Explain how a stacks implemented inthe memory system ofa computer.
4 (See Unkel, Page 87, 04)

(@) Explain about auxiliary and associative memory.
(See Unit-1Y, Page 153, 0.20) |
the concept of virtual memory. (See Únit-1V, Page 176, O47 |

‘New according ny revised labs of RGRN, til ya |
en |

segementation,
(See URN. Page 181, os
cement algorithm with the help of exam.
¿Ses Unit: Page 188, G

essor? Write its charetris,
(Seo Uni-V Page 221, Q 39
(See Unit. Page 204 0,13)

Sa) ifn Sitoparison Herr paging and

DA Explain any page rep!

2h} Mit don cadera Ey multiproc

(9) Brlaverilimef pipelining
re dhafı nes on
2:18), Mair maltpistion

ADN Priory Aterrapt

Fe) Ihstracnon format,

(See Unit. Page219,Q,34,
(See Unit, Page 122, Q 34)
(See Unit HT, Page 91, 0.8)

X. Atwanpt aay five questions, each question carries equal marks.
(iD Assume suitable dew if missing.
6) Whats Von-Neumana model of computer ? Explain its various
subsystems, (See Unit, Page 10.0.6)
10). Discus in brief about Logic and Shi Miero-operätions 2
(See Unit, Page 339.36)
Whit are the different ways of respresenting a signed number a
hatte bests On ? Why 2) ne
(Ser Unit Page 42, 0.8)
(©) Detemine whether the following Ys complement notations stand

ir positive or negative numbers. Give hei, values in decimal

m 81110000
fii) moon
orten
(901010101,

ta)

(See Uni
1a) Compere RISC and CISC characteristics

(eet
1) Discuss the flowing with examplés —

6) Zero-adäfess instructions
e

1, Page 43, Prob3)

iI, Page 104.0.

1

Compnter Archetmetun

i One-address instructions
id Two-address instructions
(See Unit Page dk. G17

Explain in detail various fields of microinstruction format wih
disgran. (See Unit, Page 78, Q.44)
Write in detail about the design of hard wired control unit

w 5
(See Unite, Page 69,Q.31)

Write about various types oF ROM €

15)

(See Unite Page 144,0.
What do you mean by/issoGiative memory ? Explein i with block
diagram. (See Unit-1V, Page 150,Q.19)
What is Memory Hicrarchy ? And explain the need for it

(See Uait-IV. Page 140,03)
What is a DMA scheme of data transfer ? Discuss its operating
principle ? (See Unit Page 132,054)
‘What do you mean by pipeline ? Explain pipeline conflicts.

(See Unit-V, Page 214, 0222)
Prove that a K-stage linear pipeline can be at most K-times faster
than that of No pipelined serial processor (See Unit-V Page 201, Q.)
5.) Write short notes on =
a) Addressing Modes
() Virtual Memory
(0 Input Output Processor.

0)

AO]

0)

«a

(0)

(See Unit-IM, Page 104,Q.23)
(See Unit-V, Page 176,047)
(See Unit: Page 136, 0.60)

17-4005 (CBGS)

(Fourth Semester) EXAMINATION, May 2018

Choice Based Grading System (CBGS),
COMPUTER ARCHITECTURE,

Note: (D Total number of questions are ich.
Gi) Atempt any five questions
(li) AN questions carry equal mars
1. (1) Draw Von Neumann model of computer and explain all the
e. subsystems of computer. (See Unit-1, Page 10,0.6)
e on ? Explain any four of
(0) What do you mean by logie micro opera
O operations. Die one ige ofloie unit wilh ts union
=: “be (See UnictsPage3S,039)

es

Computer Architecture

2. (a), Explain sign-magnitude, 's and 2's complement numbers wi

Hage

range for eight bit registers (See
(0) Explain the process of multiplication using BOOTH method

Solve = $ x 2 using Booth method. (See Uni Page 61 Prop y

(5) What do you mean by zero, one, two and three address instru;
2 Give suitable examples. (See Unit-N, Pages, ¢
{by Explain PUSH and POP instructions, Differentiate infix and pou,
rotation with an example. (See Uni, Pageto. gg

4. (a) Explain the three ways of data transfer to and from peripherals
(See Unit-Uh Page 112,Q.7,

do) Whats Cache ? Explain the principle of “Locality Of references
Enlist and explain replacement algorithms.

(See De. Page 172,Q.45

À (a) Explainhiteaio. Generate expression for hifi. Drive an express

for effective access time (t)” ¡Py and are access time of cache

anid main memory respectively hy isthe hit ratio of cache,

(See Unit-IV Page 170,040)

(0) Whatis mapping ? Name all thetypes of cache mapping and explain!

any one in deal (See Unit-IV, Page 164,033)

8. (a) What is mulfiprocessor ? Explain the characteristics of

mulliptocessrs. (See Unit-V, Page 222, 0.36)

(0), Delfin the term Pipeline, speed up ratio and memory interleaving

(See Unit-V, Page 221,035)
7. (a) Draw block diagram of memory hierarchy of computer system.
Explain why 3 level hierarchy is necessary.
(See Unit-1V, Page 142,03)
{h) Write a short note on virtual memory. (See Unit-IV, Page 176, Q47)
3. (a) Page fault (See Unit-IV, Page 188, Q.60 |
(b} Daisy chaining (See Unit-H1, Page 126, Q.42)
(e) Control memory {See Unit-11, Page77,Q40 |
(4) Shifl micro-operation (Gee Unit, Page 32,039 |
|
y +

q on

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