Computer Organization

Student will be able to know that fundamental concepts behind computer organization. this PPT includes the following topics: Introduction
Functional Units of Computer
Number Representation and Arithmetic Operations
Memory Location and Addresses
Addressing Modes
Pipelining
Memory Hierarchy
I/O Organization
Control Signals Generation

1. Computer Organization By Mr.S.Selvaraj Asst. Professor (SRG) / CSE Kongu Engineering College Perundurai , Erode, Tamilnadu , India Thanks to and Resource from : V. Carl Hamacher , Zvonko G. Vranesic , Safwat G. Zaky “Computer organization”, 5 th Edition, McGraw Hill, 2012

2. Preamble Introduction Functional Units of Computer Number Representation and Arithmetic Operations Memory Location and Addresses Addressing Modes Pipelining Memory Hierarchy I/O Organization Control Signals Generation 8/13/2021 2 Computer Organization

3. Introduction to CA Computer Architecture is a blueprint for design and implementation of a computer system. It provides the functional details and behaviour of a computer system and comes before computer organization. Computer architecture deals with 'What to do?' 8/13/2021 Computer Organization 3

4. Introduction to CO Computer Organization is how operational parts of a computer system are linked together. It provides structural relationship between parts of a computer system. It implements the provided computer architecture. Computer organization deals with 'How to do?' 8/13/2021 Computer Organization 4

5. Computer Architecture Vs Computer Organization 8/13/2021 Computer Organization 5

6. Types of Computer 8/13/2021 Computer Organization 6 Type Specifications PC (Personal Computer) It is a single user computer system having moderately powerful microprocessor. Workstation It is also a single user computer system, similar to personal computer however has a more powerful microprocessor Mini Computer It is a multi-user computer system, capable of supporting hundreds of users simultaneously. Main Frame It is a multi-user computer system, capable of supporting hundreds of users simultaneously . Software technology is different from minicomputer. Supercomputer It is an extremely fast computer , which can execute hundreds of millions of instructions per second . For example, weather forecasting, scientific simulations, (animated) graphics, fluid dynamic calculations, nuclear energy research, electronic design, and analysis of geological data (e.g. in petrochemical prospecting).

7. Generation of Computer 8/13/2021 Computer Organization 7 Generation Description First Generation The period of first generation: 1946-1959. Vacuum tube based. Second Generation The period of second generation: 1959-1965. Transistor based. Third Generation The period of third generation: 1965-1971. Integrated Circuit based. Fourth Generation The period of fourth generation: 1971-1980. VLSI microprocessor based. Fifth Generation The period of fifth generation: 1980-onwards. ULSI microprocessor based.

8. Quiz 1 Which type of computers are used for whether forecasting? 8/13/2021 Computer Organization 8

9. Preamble Introduction Functional Units of Computer Number Representation and Arithmetic Operations Memory Location and Addresses Addressing Modes Pipelining Memory Hierarchy I/O Organization Control Signals Generation 8/13/2021 9 Computer Organization

10. Functional Units of Computer 8/13/2021 Computer Organization 10

11. Functional Units of Computer 8/13/2021 Computer Organization 11 Operation Description Take Input The process of entering data and instructions into the computer system Store Data Saving data and instructions so that they are available for processing as and when required. Processing Data Performing arithmetic, and logical operations on data in order to convert them into useful information. Output Information The process of producing useful information or results for the user, such as a printed report or visual display. Control the workflow Directs the manner and sequence in which all of the above operations are performed.

12. Connection between Memory and Processor 8/13/2021 Computer Organization 12

13. Components of Processor 8/13/2021 Computer Organization 13 Components Description IR It holds the instruction that is currently being executed . Its output is available to the Control Circuits , which generate the timing signals. PC It keeps track of execution of a program . It contains the memory address of the next instruction to be fetched and executed. MAR It holds the address of the location to be accessed. MDR It contains the data to be written into or read out of the addressed location. GPR General Purpose Registers are used to store the operand values temporarily . R0,R1,R2,R3,.... Rn-1

14. Quiz 2 Which holds the address of the memory location? IR PC MAR MDR GPR 8/13/2021 Computer Organization 14

15. Hardware Components of Computer Computer Organization 8/13/2021 15

16. Motherboard Structure 8/13/2021 Computer Organization 16

17. RAM 8/13/2021 Computer Organization 17

18. ROM 8/13/2021 Computer Organization 18

19. Hard Disk 8/13/2021 Computer Organization 19

20. Quiz 3 RAM is a non-volatile memory? TRUE FALSE 8/13/2021 Computer Organization 20

21. Preamble Introduction Functional Units of Computer Number Representation and Arithmetic Operations Memory Location and Addresses Addressing Modes Pipelining Memory Hierarchy I/O Organization Control Signals Generation 8/13/2021 21 Computer Organization

22. Numbering and Character Set BCD 4 bit ASCII 7 bit EBCDIC 8 bit UNICODE 16 bit 32 bit 8/13/2021 Computer Organization 22

23. BCD 8/13/2021 Computer Organization 23

24. ASCII Table 8/13/2021 Computer Organization 24

25. EBCDIC Table 8/13/2021 Computer Organization 25

26. 8/13/2021 Computer Organization 26

27. UTF - 16 8/13/2021 Computer Organization 27

28. Power of 10 8/13/2021 Computer Organization 28

29. 8/13/2021 Computer Organization 29

30. 8/13/2021 Computer Organization 30

31. Quiz 4 2 36 = ____? 8/13/2021 Computer Organization 31

32. Number Representation 8/13/2021 Computer Organization 32

33. Quiz 5 Represent in 20-bit 2’s Complement Number: (-20) 10 a. 1111 1111 1111 1110 1100 b. 1111 1111 1111 1110 1011 c. 1111 1111 1111 1111 0100 d. 0000 0000 0000 0001 0100 8/13/2021 Computer Organization 33

34. Addition and Subtraction 8/13/2021 Computer Organization 34

35. Quiz 6 Convert the following pairs of decimal numbers to 5-bit 2’s-complement numbers, then perform addition and subtraction on each pair. Indicate whether or not overflow occurs for each case. (a) 7 and 13 (b) −12 and 9 8/13/2021 Computer Organization 35

36. Multiplication of Unsigned Numbers using Array Method (Normal) 8/13/2021 Computer Organization 36

37. Multiplication of Unsigned Numbers using Sequential Circuit Method - Algorithm 8/13/2021 Computer Organization 37

38. Multiplication of Unsigned Numbers using Sequential Circuit Method 8/13/2021 Computer Organization 38

39. Multiplication of Signed Numbers Using Sign Extension 8/13/2021 Computer Organization 39

40. Booth Algorithm for Signed Numbers Multiplication 8/13/2021 Computer Organization 40

41. Quiz 7 Using Booth's Algorithm for multiplication, the multiplier -46 will be recoded as___ 8/13/2021 Computer Organization 41

42. Multiplication of Signed Numbers Using Booth Algorithm 8/13/2021 Computer Organization 42

43. Quiz 8 Multiply (+13) * (-6) using booth algorithm. 8/13/2021 Computer Organization 43

44. Quiz 8 - Solution 8/13/2021 Computer Organization 44

45. Bit-pair Recoding Algorithm for Fast Multiplication 8/13/2021 Computer Organization 45

46. Example – Bit-pair Recoding 8/13/2021 Computer Organization 46

47. Preamble Introduction Functional Units of Computer Number Representation and Arithmetic Operations Memory Location and Addresses Addressing Modes Pipelining Memory Hierarchy I/O Organization Control Signals Generation 8/13/2021 47 Computer Organization

48. Memory Location and Address The memory consists of many millions of storage cells , each of which can store a bit of information having the value 0 or 1. Each group of n bits is referred to as a word of information, and n is called the word length . The memory of a computer can be schematically represented as a collection of words, as shown in Figure. Modern computers have word lengths that typically range from 16 to 64 bits . If the word length of a computer is 32 bits, a single word can store a 32-bit signed number or four ASCII-encoded characters, each occupying 8 bits, as shown in Figure. A unit of 8 bits is called a byte. 8/13/2021 Computer Organization 48

49. Memory Location and Address Machine instructions may require one or more words for their representation. The memory can have up to 2 k addressable locations . The 2 k addresses constitute the address space of the computer. For example, a 24-bit address generates an address space of 2 24 (16,777,216) locations . This number is written as 16M (16 mega), where 1M is the number 2 20 (1,048,576). 8/13/2021 Computer Organization 49

50. Quiz 9 a 32-bit address generates how many address locations? 8/13/2021 Computer Organization 50

51. Big Endian and Little Endian Assignments The name big-endian is used when lower byte addresses are used for the more significant bytes (the leftmost bytes ) of the word. The name little-endian is used for the opposite ordering, where the lower byte addresses are used for the less significant bytes (the rightmost bytes ) of the word. ( Reverse ) 8/13/2021 Computer Organization 51

52. Big Endian and Little Endian Assignments 8/13/2021 Computer Organization 52

53. Quiz 10 Consider a computer that has a byte-addressable memory organized in 32-bit words according to the big-endian scheme. A program reads ASCII characters entered at a keyboard and stores them in successive byte locations, starting at location 1000. Show the contents of the two memory words at locations 1000 and 1004 after the word “Johnson” has been entered. Repeat Problem for the little-endian scheme. 8/13/2021 Computer Organization 53

54. Quiz 10 - Solution In Big Endian Scheme: Byte contents in hex, starting at location 1000, will be 4A, 6F, 68, 6E, 73, 6F, 6E. The two words at 1000 and 1004 will be 4A6F686E and 736F6EXX. Byte 1007 (shown as XX) is unchanged. In Little Endian Scheme : Byte contents in hex, starting at location 1000, will be 4A, 6F, 68, 6E, 73, 6F, 6E. The two words at 1000 and 1004 will be 6E686F4A and XX6E6F73. Byte 1007 (shown as XX) is unchanged. 8/13/2021 Computer Organization 54

55. Preamble Introduction Functional Units of Computer Number Representation and Arithmetic Operations Memory Location and Addresses Addressing Modes Pipelining Memory Hierarchy I/O Organization Control Signals Generation 8/13/2021 55 Computer Organization

56. Addressing Modes The different ways for specifying the locations of instruction operands are known as addressing modes . 8/13/2021 Computer Organization 56

57. Types of Addressing Modes 8/13/2021 Computer Organization 57

58. Quiz 11 Registers R4 and R5 contain the decimal numbers 2000 and 3000 before each of the following addressing modes is used to access a memory operand. What is the effective address (EA) in each case? (a) 12(R4) (b) (R4,R5) (c) 28(R4,R5) (d) (R4)+ (e) −(R4) 8/13/2021 Computer Organization 58

59. Types of Instructions The instructions are classified into 4 basic types based on the number of operands used in the instructions. Three-address Two-address One–address and Zero-address instruction. 8/13/2021 Computer Organization 59

60. Preamble Introduction Functional Units of Computer Number Representation and Arithmetic Operations Memory Location and Addresses Addressing Modes Pipelining Memory Hierarchy I/O Organization Control Signals Generation 8/13/2021 60 Computer Organization

61. Pipeline Intro To improve the performance of a CPU we have two options: 1) Improve the hardware by introducing faster circuits. 2) Arrange the hardware such that more than one operation can be performed at the same time. Since, there is a limit on the speed of hardware and the cost of faster circuits is quite high, we have to adopt the 2nd option. Pipelining is a process of arrangement of hardware elements of the CPU such that its overall performance is increased. Simultaneous execution of more than one instruction takes place in a pipelined processor 8/13/2021 Computer Organization 61

62. Case Study Consider a water bottle packaging plant. Let there be 3 stages that a bottle should pass through, Inserting the bottle( I ), Filling water in the bottle( F ), and Sealing the bottle( S ). Let us consider these stages as stage 1, stage 2 and stage 3 respectively. Let each stage take 1 minute to complete its operation. Now, in a non pipelined operation, a bottle is first inserted in the plant, after 1 minute it is moved to stage 2 where water is filled. Now, in stage 1 nothing is happening. Similarly, when the bottle moves to stage 3, both stage 1 and stage 2 are idle. But in pipelined operation, when the bottle is in stage 2, another bottle can be loaded at stage 1. Similarly, when the bottle is in stage 3, there can be one bottle each in stage 1 and stage 2. So, after each minute, we get a new bottle at the end of stage 3. Hence, What is the average time taken to manufacture 1 bottle by using with pipeline and without pipeline?. 8/13/2021 Computer Organization 62

63. Case Study Solution Without pipelining  = 9/3 minutes = 3m. With pipelining  = 5/3 minutes = 1.67m . 8/13/2021 Computer Organization 63

64. Pipelining Executing the machine instructions concurrently is called as pipelining . a pipelined processor may process each instruction in four steps , as follows: Fetch (F): read the instruction from the memory. Decode (D): decode the instruction and fetch the source operand(s). Execute (E): perform the operation specified by the instruction. Write (W) : store the result in the destination location. 8/13/2021 Computer Organization 64

65. 4-stage pipeline 8/13/2021 Computer Organization 65

66. Execution in a Pipelined Processor Execution sequence of instructions in a pipelined processor can be visualized using a space-time diagram. For example, consider a processor having 4 stages and let there be 2 instructions to be executed. We can visualize the execution sequence through the following space-time diagrams: 8/13/2021 Computer Organization 66

67. Performance of a pipelined processor Consider a ‘k’ segment pipeline with clock cycle time as ‘ Tp ’. Let there be ‘n’ tasks to be completed in the pipelined processor. Now, the first instruction is going to take ‘k’ cycles to come out of the pipeline but the other ‘n – 1’ instructions will take only ‘1’ cycle each, i.e , a total of ‘n – 1’ cycles. So, time taken to execute ‘n’ instructions in a pipelined processor: In the same case, for a non-pipelined processor , execution time of ‘n’ instructions will be: 8/13/2021 Computer Organization 67

68. Quiz Consider a ‘5’ segment pipeline with clock cycle time as ‘1 minute’. Let there be ‘20’ instructions to be completed. What is the estimated time to execute all the instructions in the pipelined processor? What is the estimated time to execute all the instructions in the non-pipelined processor? 8/13/2021 Computer Organization 68

69. Speedup, Efficiency and Throughput 8/13/2021 Computer Organization 69

70. Quiz Consider a ‘5’ segment pipeline with clock cycle time as ‘1 minute’. Let there be ‘20’ instructions to be completed. What is the estimated time to execute all the instructions in the pipelined processor? What is the estimated time to execute all the instructions in the non-pipelined processor? What is the speedup? What is the efficiency? What is the throughput? 8/13/2021 Computer Organization 70

71. Hazard and its Types Any condition that causes the pipeline to stall is called a hazard . The other names for stalls is idle periods and bubbles . There are three types of hazards occurs in pipelined operation. These are Data Hazard Instruction Hazard Structure Hazard 8/13/2021 Computer Organization 71

72. Stall - Example 8/13/2021 Computer Organization 72

73. Data Hazard Any condition in which wither the source or the destination operands of an instruction are not available at the time expected in the pipeline is called data hazard . 8/13/2021 Computer Organization 73

74. Instruction Hazard The pipeline may also be stalled because of a delay in the availability of an instruction . For example, this may be a result of a miss in the cache, requiring the instruction to be fetched from the main memory. Such hazards are often called control hazards or instruction hazards . 8/13/2021 Computer Organization 74

75. Structural Hazard The situation, when two instructions requires the use of a given hardware resources at the same time is called structural hazard . Most common case in which this hazard may arise is in access to memory . For Example, One instruction may need to access memory as part of the Execute or Write stage while another instruction is being fetched. 8/13/2021 Computer Organization 75

76. Quiz 12 Consider a pipelined processor with the following five stages: F: Instruction Fetch D: Instruction Decode and Operand Fetch C: Execute M: Memory W: Write Back The F, D, W and M stages take one clock cycle each to complete the operation. The number of clock cycles for the EX stage depends on the instruction. The ADD and SUB instructions need 1 clock cycle and the MUL instruction needs 3 clock cycles in the C stage. Operand forwarding is used in the pipelined processor. What is the number of clock cycles taken to complete the following sequence of instructions? ADD R2, R1, R0 R2 <- R0 + R1 MUL R4, R3, R2 R4 <- R3 * R2 SUB R6, R5, R4 R6 <- R5 - R4 8/13/2021 Computer Organization 76

77. Quiz 12 - Solution 8/13/2021 Computer Organization 77

78. Preamble Introduction Functional Units of Computer Number Representation and Arithmetic Operations Memory Location and Addresses Addressing Modes Pipelining Memory Hierarchy I/O Organization Control Signals Generation 8/13/2021 78 Computer Organization

79. Memory Hierarchy, Cost, Size, Speed Comparison 8/13/2021 Computer Organization 79

80. RAM Memory Organization 8/13/2021 Computer Organization 80

81. Example How many 64 x 8 RAM chips are needed to provide a memory capacity of 2048 bytes? Assuming that 64 x 8 RAM chips means 64 x 8 bit RAM chips, Since 8 bits = 1 byte, Each RAM chip has 64 x 1 byte = 64 bytes. Thus the number of chips to address a memory capacity of 2048 bytes will be, 2048/64 = 32 chips. 8/13/2021 Computer Organization 81

82. Quiz 13 How many 128x16 RAM chips are needed to provide a memory capacity of 8KB? How many 512Wx4B RAM chips are needed to provide a memory capacity of 1GB? 8/13/2021 Computer Organization 82

83. Static RAM Continuous power is needed for the cell to retain its state. If power is interrupted, the cell’s contents are lost . Hence, SRAMs are said to be volatile memories because their contents are lost when power is interrupted. Static RAMs can be accessed very quickly . Access times on the order of a few nanoseconds . SRAMs are used in applications where speed is of critical concern. 8/13/2021 Computer Organization 83

84. Dynamic RAMs Static RAMs are fast, but their cells require several transistors, so highly expensive and lower density RAMs can be implemented with complex cells . We need less expensive and higher density RAMs can be implemented with simpler cells. But, these simpler cells do not retain their state for a long period , unless they are accessed frequently for Read or Write operations. Memories that use such cells are called dynamic RAMs (DRAMs ). Information is stored in a dynamic memory cell in the form of a charge on a capacitor , but this charge can be maintained for only tens of milliseconds . Since the cell is required to store information for a much longer time, its contents must be periodically refreshed by restoring the capacitor charge to its full value. 8/13/2021 Computer Organization 84

85. RAM Types Different types of volatile memories have been developed like SRAM DRAM ADRAM SDRAM SDR SDRAM DDR SDRAM DDR2 SDRAM DDR3 SDRAM DDR4 SDRAM DDR5 SDRAM RDRAM (RAMBUS) 8/13/2021 Computer Organization 85

86. ROM Both static and dynamic RAM chips are volatile , which means that they retain information only while power is turned on. There are many applications requiring memory devices that retain the stored information when power is turned off . For example, we need to store a small program in such a memory, to be used to start the bootstrap process of loading the operating system from a hard disk into the main memory. But, a special writing process is needed to place the information into a non-volatile memory. Since its normal operation involves only reading the stored data , a memory of this type is called a read-only memory (ROM ). 8/13/2021 Computer Organization 86

87. ROM Types Different types of non-volatile memories have been developed like ROM, PROM, EPROM, EEPROM , Flash Memory ( Digital Cameras, MP3 Players ) Flash Cards ( Memory Cards ) Flash Drives ( Pen Drives, SSD Hard Disks ) , etc. 8/13/2021 Computer Organization 87

88. Quiz 14 Which type of ROM is uses UV light to erase the content? 8/13/2021 Computer Organization 88

89. Secondary Memory Different types of secondary memories have been developed like Magnetic Hard Disks CD-ROM DVD 8/13/2021 Computer Organization 89

90. Magnetic Hard Disk 8/13/2021 Computer Organization 90

91. Magnetic Hard Disk Seek time , is the time required to move the read/write head to the proper track . This time depends on the initial position of the head relative to the track specified in the address. Average values are in the 5- to 8-ms range . The second component is the rotational delay , also called latency time , which is the time taken to reach the addressed sector after the read/write head is positioned over the correct track . On average, this is the time for half a rotation of the disk. The sum of these two delays is called the disk access time. 8/13/2021 Computer Organization 91

92. Quiz 15 There are 16 data-recording surfaces with 65,536 tracks per surface. There is an average of 512 sectors per track, and each sector contains 256 bytes of data. Find out the capacity of the Hard Disk. 8/13/2021 Computer Organization 92

93. Cache Memory The cache is a small and very fast memory , interposed between the processor and the main memory . The effectiveness of this approach is based on a property of computer programs called locality of reference. This behavior manifests itself in two ways: temporal and spatial . The first means that a recently executed instruction is likely to be executed again very soon . The spatial aspect means that instructions close to a recently executed instruction are also likely to be executed soon. 8/13/2021 Computer Organization 93

94. Hit rate and Miss rate Let h be the hit rate, M the miss penalty, and C the time to access information in the cache . Thus, the average access time experienced by the processor is t avg = hC + (1 − h)M the average access time experienced by the processor in such a system is: t avg = h1C1 + (1 − h1)h2C2 + (1 – h1)(1- h2)M where h1 is the hit rate in the L1 caches. h2 is the hit rate in the L2 cache. C1 is the time to access information in the L1 caches. C2 is the miss penalty to transfer information from the L2 cache to an L1 cache. M is the miss penalty to transfer information from the main memory to the L2 cache. 8/13/2021 Computer Organization 94

95. Quiz 16 Cache access time (C)= 100 ns, Memory access time (M) = 500 ns, If the hit rate is 90 % then what is the effective access time? 8/13/2021 Computer Organization 95

96. Cache Memory Mapping Techniques There are several possible methods for determining where memory blocks are placed in the cache. 4 Techniques: Direct Mapping Associative Mapping Set Associative Mapping K-way Set Associative Mapping 8/13/2021 Computer Organization 96

97. Example - Cache Memory Mapping Techniques Consider a cache consisting of 128 blocks of 16 words each, for a total of 2048 (2K) words, and assume that the main memory is addressable by a 16-bit address. The main memory has 64K words, which we will view as 4K blocks of 16 words each. For simplicity, we have assumed that consecutive addresses refer to consecutive words. 8/13/2021 Computer Organization 97

98. Direct Mapping The simplest way to determine cache locations in which to store memory blocks is the direct-mapping technique. In this technique, block j of the main memory maps onto block j modulo 128 of the cache, as depicted in Figure. Thus, whenever one of the main memory blocks 0, 128, 256, . . . is loaded into the cache, it is stored in cache block 0. Blocks 1, 129, 257, . . . are stored in cache block 1, and so on. Since more than one memory block is mapped onto a given cache block position, contention may arise for that position even when the cache is not full. The direct-mapping technique is easy to implement, but it is not very flexible. 8/13/2021 Computer Organization 98

99. Direct Mapping 8/13/2021 Computer Organization 99

100. Direct Mapping Examples 8/13/2021 Computer Organization 100

101. 8/13/2021 Computer Organization 101

102. 8/13/2021 Computer Organization 102

103. Associative Mapping In this method, a main memory block can be placed into any cache block position. The tag bits of an address received from the processor are compared to the tag bits of each block of the cache to see if the desired block is present. This is called the associative-mapping technique. It gives complete freedom in choosing the cache location in which to place the memory block, resulting in a more efficient use of the space in the cache. When a new block is brought into the cache, it replaces (ejects) an existing block only if the cache is full. In this case, we need an algorithm to select the block to be replaced. Many replacement algorithms are possible. The complexity of an associative cache is higher than that of a direct-mapped cache, because of the need to search all 128 tag patterns to determine whether a given block is in the cache. To avoid a long delay, the tags must be searched in parallel. A search of this kind is called an associative search. 8/13/2021 Computer Organization 103

104. Associative Mapping 8/13/2021 Computer Organization 104

105. Associative Mapping 8/13/2021 Computer Organization 105

106. Set Associative Mapping Another approach is to use a combination of the direct and associative-mapping techniques. The blocks of the cache are grouped into sets , and the mapping allows a block of the main memory to reside in any block of a specific set. Hence, the contention problem of the direct method is eased by having a few choices for block placement. At the same time, the hardware cost is reduced by decreasing the size of the associative search. 8/13/2021 Computer Organization 106

107. Set Associative Mapping 8/13/2021 Computer Organization 107

108. Set Associative 8/13/2021 Computer Organization 108

109. Quiz Assume a computer main memory contains 8192 blocks, and each blocks contains 256 words (1 word = 1 Byte). And also a block-set-associative (BSA) cache memory consists of a total of 32 blocks which is divided into 4 –block sets. Find out the number of bits for physical memory, TAG,SET and WORD fields ? A) 21 , 10, 3, 8 B) 21, 11, 2, 8 C) 19, 8 , 4, 7 D) 19, 9 , 3 , 7 8/13/2021 Computer Organization 109

110. Need of Virtual Memory In most modern computer systems, the physical main memory is not as large as the address space of the processor. For example, a processor that issues 32-bit addresses has an addressable space of 4G bytes . The size of the main memory in a typical computer with a 32-bit processor may range from 1G to 4G bytes . If a program does not completely fit into the main memory, the parts of it not currently being executed are stored on a secondary storage device , typically a magnetic disk . 8/13/2021 Computer Organization 110

111. Virtual Memory 8/13/2021 Computer Organization 111

112. Preamble Introduction Functional Units of Computer Number Representation and Arithmetic Operations Memory Location and Addresses Addressing Modes Pipelining Memory Hierarchy I/O Organization Control Signals Generation 8/13/2021 112 Computer Organization

113. I/O Device Accessing 8/13/2021 Computer Organization 113

114. Connection for Processor and I/O devices 8/13/2021 Computer Organization 114

115. I/O Device Accessing Methods Memory Mapped I/O Program-Controlled I/O 8/13/2021 Computer Organization 115

116. Memory Mapped I/O The I/O devices and the memory share the same address space ; this arrangement is called memory-mapped I/O . It is used in most computers. With memory-mapped I/O, any machine instruction that can access memory can be used to transfer data to or from an I/O device. For example, if DATAIN is the address of a register in an input device, the instruction reads the data from the DATAIN register and loads them into processor register R2. Load R2, DATAIN Similarly, the instruction sends the contents of register R2 to location DATAOUT, which is a register in an output device. Store R2, DATAOUT 8/13/2021 Computer Organization 116

117. Program-Controlled I/O Consider a task that reads characters typed on a keyboard, stores these data in the memory, and displays the same characters on a display screen. A simple way of implementing this task is to write a program that performs all functions needed to realize the desired action. This method is known as program-controlled I/O. 8/13/2021 Computer Organization 117

118. Implementing I/O operations There are two other commonly used mechanisms for implementing I/O operations : Interrupts Direct Memory Access (DMA ) The following techniques are used to handle multiple devices interrupt requests : Vectored Interrupts Nested Interrupts Multiple Priority Scheme Polling Daisy Chain Scheme 8/13/2021 Computer Organization 118

119. Interconnection Standards SCSI Bus SATA SAS FIREWIRE PCI Bus PCI Express Universal Serial Bus (USB) 8/13/2021 Computer Organization 119

120. Preamble Introduction Functional Units of Computer Number Representation and Arithmetic Operations Memory Location and Addresses Addressing Modes Pipelining Memory Hierarchy I/O Organization Control Signals Generation 8/13/2021 120 Computer Organization

121. Control Signals Generation We now examine how the processor generates the control signals that cause these actions to take place in the correct sequence and at the right time. There are two basic approaches : Hardwired control and Micro-programmed control 8/13/2021 Computer Organization 121

122. Thank you and any ??? 8/13/2021 Computer Organization 122