CSN221_Lec_15.pdf MIPS ISA and Datapath design

CSN221_Lec_15 MIPS ISA and Datapath design

1. Course Website: http://faculty.iitr.ac.in/~sudiproy.fcs/csn221_2015.html
Piazza Site: https://piazza.com/iitr.ac.in/fall2015/csn221  
Dr. SudipRoy
CSN‐221: COMPUTER ARCHITECTURE 
AND MICROPROCESSORS
MIPS ISA & DatapathDesign
(Lecture -15)

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Use of MUX:

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Control Unit:

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Recap: Computer Performance: Execution Time:

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= (100 x 10
9
) (1) (925 x 10
‐12
) seconds

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The datapathand the clock of the CPU:
In an instruction like add $t1, $t1, $t2, how do we know $t1 
is not updated until after its original value is read?
Read
address
Write
address
Write
data
Data
memory
Read
data
MemWrite MemRead
Read
register 1
Read
register 2
Write
register
Write
data
Read
data 2
Read
data 1
Registers
RegWrite
PC
1. STEP 1: A new instruction is loaded from memory. The 
control unit sets the datapath signals appropriately so that
registers are read,
ALU output is generated,
data memory is read and
branch target addresses are computed
2. STEP 2:
The register file is updated for arithmetic or lw
instructions.
Data memory is written for
 a sw instruction.
The PC is updated to point to the next instruction
In a single‐cycle datapatheverything in Step 1 must complete 
within one clock cycle.

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Slowest instruction determines the clock cycle time:
If all instructions must complete within one clock cycle, then the cycle time has to 
be large enough to accommodate the slowestinstruction.
For example, lw $t0, –4($sp) needs 8ns, assuming the delays shown here
reading the instruction memory 2ns
reading the base register $sp 1ns
computing memory address $sp-4 2ns
reading the data memory 2ns
storing data back to $t0 1ns
8ns
If we make the cycle time 8ns then every instruction will take 8ns, even if they 
don’t need that much time.
For example, the instruction add $s4, $t1, $t2really needs just 6ns.
6ns
reading the instruction memory 2ns
reading registers $t1 and $t2 1ns
computing $t1 + $t2 2ns
storing the result into $s0 1ns