Da3_on_FPGA_education_program_by_DIAT.pptx

Education program

1. DAY 3- Operators and Data Flow Modeling (VHDL)

2. Quote of the Day Have a D efinite Goal

3. What you will Learn Today Half Adder Half Subtractor Full Adder 1 Bit Comparator 4 Bit Comparator 4 to 1 Multiplexer

4. About p antechsolutions Manufacturers of Lab equipment's(ECE &EEE) and Sensor Interface Manufacturer of Brainsense EEG Headset Reconfigurable Algorithms on AI Manufacture of AI development Boards Vision: To help 10 millions students to learn technology in a easy way

5. About me https://www.linkedin.com/in/jeevarajan/ My Primary Expertise Microcontroller Architecture: 8051,PIC,AVR,ARM,MSP430,PSOC3 DSP Architecture: Blackfin,C2000,C6000,21065L Sharc FPGA: Spartan,Virtex,Cyclone Image Processing Algorithms: Image/Scene Recognition, Machine Learning, Computer Vision, Deep Learning, Pattern Recognition, Object Classification ,Image Retrieval, Image enhancement and denoising . Neural Networks : SVM,RBF,BPN Cryptography :RSA,DES,3DES,Ellipti curve,Blowfish,Diffe Hellman Compilers: Keil,Visual DSP++,CCS, Xilinx Platform studio,ISE , Matlab, Open CV www.pantechsolutions.net

6. Announcement Attendance Link at 8.30 pm Minimum attendance required for an E-Certificate is 18 Days. Attendance link will be valid for 2 hrs. after the event. For Internship Candidates no attendance required ,it will be accessed from the LMS Portal. (learn.pantechsolutions.net) Recorded Video Streaming for some classes to improve Learning Experience Only Xilinx FPGA and tools will be covered.

7. Half Adder

8. VHDL C ode for HALF ADDER library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity Half_adder is PORT (A: IN STD_LOGIC; B: IN STD_LOGIC; SUM : OUT STD_LOGIC; COUT : OUT STD_LOGIC); end Half_adder ; architecture Behavioral of Half_adder is begin SUM <= A XOR B; COUT <= A AND B; end Behavioral ;

9. Half Subtractor

10. VHDL Code for HALF SUBTRACTOR library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity Half_adder is PORT (A: IN STD_LOGIC; B: IN STD_LOGIC; SUM : OUT STD_LOGIC; COUT : OUT STD_LOGIC); end Half_adder ; architecture Behavioral of Half_adder is begin SUM <= A XOR B; COUT <= (not)A AND B; end Behavioral ;

11. Full adder

12. VHDL Code for full Adder library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity Full_adder is Port (A, B, CIN : IN STD_LOGIC; Sum, Cout : OUT STD_LOGIC); end Full_adder ; architecture Behavioral of Full_adder is begin Sum <= A XOR B XOR CIN; Cout <= (A AND B ) OR (A AND CIN ) OR ( CIN AND B ); end Behavioral ;

13. Single BIT COMPARATOR

14. VHDL Code for Single Bit Comparator library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity Comparator_4bit is port ( a,b : in std_logic ; aeqb , agtb , altb : out std_logic ); end comparator_4bit; architecture Behavioral of comparator_4bit is begin aeqb <= ‘1’ when (a=b) else ‘0’; agtb <= ‘1’ when (a>b) else ‘0’; altb <= ‘1’ when (a<b) else ‘0’; end Behavioral ;

15. 4 Bit Comparator

16. VHDL Code for 4 BIT Comparator library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity Comparator_4bit is port ( a,b : in std_logic_vector (0 to 3); aeqb , agtb , altb : out std_logic ); end comparator_4bit; architecture Behavioral of comparator_4bit is begin aeqb <= ‘1’ when (a=b) else ‘0’; agtb <= ‘1’ when (a>b) else ‘0’; altb <= ‘1’ when (a<b) else ‘0’; end Behavioral ;

17. 4 to 1 Mux (Multiplexer) Multiplexer (MUX) select one input from the multiple inputs and forwarded to output line through selection line.

18. VHDL code using 4:1 multiplexers using when select construct LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY MUX4_1 IS PORT(A, B, C, D :IN STD_LOGIC; SEL :IN STD_LOGIC_VECTOR (1 DOWNTO 0); Y :OUT STD_LOGIC); END MUX; ARCHITECTURE DF OF MUX_1 IS BEGIN Y <= D WHEN SEL = “11” ELSE C WHEN SEL = “10” ELSE B WHEN SEL = “01” ELSE A WHEN SEL = “00” ELSE ‘X’ ; END DF

19. VHDL code using 4:1 multiplexers using With-Select construct Library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity MUX_SELECT_SIGNAL_ASSIGNMENT is Port ( A,C : in STD_LOGIC; B,D : in STD_LOGIC; SEL : in STD_LOGIC_VECTOR (1 DOWNTO 0); Y : out STD_LOGIC); end MUX_SELECT_SIGNAL_ASSIGNMENT; architecture Behavioral of MUX_SELECT_SIGNAL_ASSIGNMENT is begin WITH SEL SELECT Y <= D WHEN “11”, C WHEN “10”, B WHEN “01”, A WHEN “00”, ‘X’ WHEN OTHERS; end Behavioral ;

20. Printed Certificate &Online Support System @ Rs 999 Rs 500+18% GST(offer price ) Where you have the recorded video ,Watch at any time Videos will be enable after live in online support system, take free preview by signing up learn.pantechsolutions.net Practice on your own time. (Join the 30 Days Challenge ) www.pantechsolutions.net

21. Thank You www.pantechsolutions.net For learning hub visit learn.pantechsolutions.net