Design and Implementation of Synchronous FIFO Interfaced with RAM.pptx

Design and Implementation of Synchronous FIFO Interfaced with RAM

1. “Design and Implementation of Synchronous FIFO Interfaced with RAM” Final Year Project Presentation On National Institute of Technology Manipur PRESENTED BY : Rahul Phulwariya (14UEC024) Ritesh Kumar Singh (14UEC017) Sachin Kumar (14UEC018) UNDER THE GUIDANCE OF : Mr. Manoj Kumar Assistant Professor ECE Department

2. Introduction Synchronous FIFO Functional Description of Synchronous FIFO Cascading FIFOs to Increase Width FIFO Interfaced with RAM Comparison of Single RAM with Application C onclusion And Future Work References C ONTENTS National Institute of Technology Manipur

3. We have designed Synchronous FIFO of 16×4 bit size . We have cascaded two FIFOs each 4 bit to make it 8 bit that is how we have increased the data width. Then we have cascaded FIFO with RAM . We have used FIFO as buffer to write the data in a sequential way. INTRODUCTION

4. The Synchronous FIFO is a First-In-First-Out memory queue with control logic that manages the read and write pointers, generates status flags, and provides output signals. Synchronous FIFOs are the ideal choice for high-performance systems due to high operating speed Supports data width up to 8 bits. Synchronous FIFOs also offer many other advantages that improve system performance and reduce complexity. These include status flags: synchronous flags, half-full, programmable almost-empty and almost-full flags Supports memory depths of up to 256 locations. Invalid read or write requests are rejected without affecting the FIFO state. SYNCHRONOUS FIFO

5. The Synchronous FIFO has a single clock port for both data-read and data-write operations. Data can be written via DataIn port . The memory full status flag Full(high) indicates that no more empty locations remain in the module's internal memory. Data can be read out of the FIFO via the DataOut port. The memory status flag Empty(high) indicates that no more data resides in the module's internal memory. Functional Description of Synchronous FIFO Fig. 1: RTL diagram of synchronous FIFO

6. Signal Direction Description DataEn Input Data Input : Synchronous to CLK WriteEn Input Write Enable (Request) ReadEn Input Read Enable (Request) CLK Input Clock for Write and Read operations (Rising Edge) RST Input Synchronous initialization of all FIFO functions, flags, and pointers Full Output No additional writes can be performed Empty Output No additional reads can be performed DataOut Output Data Output: Synchronous to CLK SYNCHRONOUS FIFO Table 1: Pinout Description of Synchronous FIFO

7. Memory Array Write pointer Compare logic Read pointer SYNCHRONOUS FIFO Write Interface Read Interface Write data Write Enable Full (Flag) Read data Read Enable Empty (flag) Fig. 2: Block Diagram of Synchronous FIFO

8. D3 D2 D1 D0 Clock Empty flag Full flag Design of Sync. FIFO starts with creating a data element of desired ‘Data Width’. For every High clock pulse Data can be write or Read or can idle. Writing process : First compare logic check the condition of Full flag , if set writing process can’t be done. Reading process : First compare logic check the condition of Empty flag , if set then Reading process can’t be done. This is done by comparing position of Head Tail and status of Looped flag. Looped flag : False Head pt. Tail pt. Write En . Read En . L1 L2 L3 L4 . . . . . . . . . . . . . . . . . . . . Lx-1 Lx

9. D3 D2 D1 D0 Clock Empty flag Full flag To Write or Read data form memory we need memory pointer , so we have taken Tail and Head Pointer. Initially the Head and Tail Pointer is at same position and Looped flag is also False and the FIFO memory is Empty. After writing some data Head will move to L4 and Tail is still is at L1. The Empty flag is now changed to Low. For High Read Enable the data pointed by Tail pointer is read out and pointer is incremented by 1 position i.e Tail pointer is at L2 and Head pointer is still at L4. Now after continuous Writing the Head pointer will reach to last memory element and then after it will get looped and again it will be at the initial memory and if further writing happen then it will reach to Tail pointer. This mean the memory is FULL and we can’t do further writing. Looped flag : False Head pt. Tail pt. Write En . Read En . L1 L2 L3 L4 . . . . . . . . . . . . . . . . . . . . Lx-1 Lx

10. SYNCHRONOUS FIFO Fig. 3: Simulation waveform of 16×4 Synchronous FIFO The obtained output is

11. SYNTHESIS REPORT OF SYNCHRONOUS FIFO Table 2: Parameters of designed Synchronous FIFO

12. The larger size FIFO can be created by cascading smaller FIFOs . The user needs to choose the FIFOs with his configuration and then the number of FIFOs can be cascaded in the different format depending upon application. There are two types of cascading possible with FIFO to increase depth and width. Cascading two or more FIFOs to form a deeper FIFO. Building a wider FIFO by connecting two or more FIFOs in parallel. CASCADING FIFOS TO INCREASE DATA WIDTH

13. CASCADING FIFOS TO INCREASE DATA WIDTH Fig. 4: Block Diagram of Cascaded FIFO

14. We have used structural modelling style for our design in which we have declared two 16×4 synchronous as a component and then mapped it to our desired port. The output of FIFO1 is mapped to the input of FIFO2 and then finally 4 bit output of both FIFO, FIFO1 and FIFO2 is augmented to form a 8 bit data. data_8_bit<= d1(3)&d1(2)&d1(1)&d1(0)&d2(3)&d2(2)&d2(1)&d2(0); CASCADING FIFOS TO INCREASE DATA WIDTH

15. CASCADING FIFOS TO INCREASE DATA WIDTH Fig. 5(A): RTL Diagram of Cascaded FIFO Fig. 5(a): Internal Architecture of cascaded FIFO

16. We made CLK of both FIFO same so that both FIFO can be synchronized. But have taken different Read enable and WRITE enable for FIFO 1 and FIFO 2, but final Empty and Full flag is common i.e a single Empty and Full flag is used to represent the emptiness or fullness of whole system. So here we start giving data from data Data_In and after some time we enable READ_1 and also enables WRITE_2 of FIFO 2. Once the FIFO 2 get full, we stop writing in FIFO 2 and keeps on writing in FIFO 1 until it get full. Once both FIFO get Full a common Full flag will indicate that both FIFO is full, then we start taking out data parallel form and augment it to get 8 bit data. CASCADING FIFOS TO INCREASE DATA WIDTH

17. CASCADING FIFOS TO INCREASE DATA WIDTH Fig. 6: Simulation Waveform of cascaded FIFO

18. ‘dat1’ and ‘dat2’ represent 4 bit data of FIFO 1 and FIFO 2 respectively. ‘data_8_bit’ represent 8 bit data after augmenting. At 1540 ns read enable made High and we can 8 bit get out from data_8_bit. At approx. 1840 ns when all data get read out, the empty flag whole system ‘ emp ’ get High. CASCADING FIFOS TO INCREASE DATA WIDTH

19. CASCADING FIFOS TO INCREASE DATA WIDTH Fig.7 : Utilization , Timing and Memory Report of Cascaded FIFO SYNTHESIS REPORT

20. Parameters No. of Slice register used 15 out of 54576 available No. of Slice LUTs used 54 out of 27288 available Total Gate Delay 5.259 ns Total Memory uesed 348232 Kb CASCADING FIFOS TO INCREASE DATA WIDTH Table 3: Different parameters of Cascaded FIFO after simulation

21. What is RAM? Random-access memory(RAM) is a form of computer data storage. This device allows data items to read and write in roughly. RAM is volatile memory. FIFO INTERFACED WITH RAM

22. RAM is the array of Register and it’s size denotes width of RAM. RAM has a clock which is denoted by ‘cl’ which is used to synchronize every process of the system. ‘ read_en ’ and ‘ write_en ’ are Read enable and Write enable, thus reading and writing process can only be done when these are high. Fig. 8 represents Register-transfer level ( RTL ) diagram of RAM. FIFO INTERFACED WITH RAM Implementation of 256×4 RAM Fig. 8 : RTL Diagram of RAM

23. FIFO INTERFACED WITH RAM Signal Direction Description data_in Input Data Input : Synchronous to CLK ram_add Input Ram Address Line cl Input Clock for Write and Read operations (Rising Edge) read_en Input Read Enable (Request) write_en Input Write Enable (Request) data_out Output Data Output: Synchronous to CLK Table 4: Pinout description of RAM

24. Fig. 9: r epresents Block diagram of FIFO interfaced with RAM. In FIFO with RAM, FIFO act as a buffer which passes data in first in and first out manner while in RAM address pointer is incremented and data get stored in sequence. FIFO INTERFACED WITH RAM Fig. 9: Block Diagram of FIFO Interfaced with RAM INTERFACING OF FIFO WITH RAM

25. FIFO INTERFACED WITH RAM Fig. 10: Simulation Waveform of the FIFO Interfaced with RAM

26. Comparison of Single RAM with RAM interfaced with FIFO Fig. 11: Utilization summary of RAM Fig.12: Utilization summary of RAM interfaced with FIFO

27. Comparison of Single RAM with RAM interfaced with FIFO Parameters RAM RAM Interfaced with FIFO No. of Slice 1 out of 27288 94 out of 8672 No. of Bonded IOBs 19 out of 296 23 out of 304 Total Gate Delay 6.492 ns 6.492 ns Total Memory 359520 kb 359560 kb Table 5: Synthesis Result Comparison of ‘Single RAM’ and ‘RAM Interfaced with FIFO’

28. Expanding Word Width: FIFOs are very easy to cascade in their word width. Extending Memory Depth: The memory depth of synchronous FIFOs is easily extended FIFO with RAM is independent of its length. Therefore, it is possible to create fast FIFOs with a length of several thousand words. NOC and USART architectures can be designed using synchronous FIFO. APPLICATIONS

29. Conclusion A detailed study of Synchronous FIFO, it’s cascading with another FIFO to increase the width of data and finally it’s interfacing with RAM is carried out in this project. The emphasis was given to design a synchronous FIFO to eliminate problem associated with asynchronous FIFO. We also used this FIFO for various application such as cascading to FIFO to increase the width of data. We also interfaced FIFO with RAM and compare its functionality with a single RAM. It was observed that memory used by RAM Interfaced with FIFO was less than a single RAM. Also, the total Gate delay for single RAM and a RAM with FIFO were same. The design is tested and verified by VHDL coding with simulation in Xilinx ISE 14.7 environment to observe the output waveform obtaining the performance parameters. Future Scope In future we can cascade FIFOs to increase the depth of FIFO, we can also design NOC and UART architectures using synchronous FIFO. CONCULSION AND FUTURE SCOPE

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