Designing a synchronous binary irregular counter with counting sequence

Designing a synchronous binary irregular counter with counting sequence

1. Designing A Synchronous Binary Irregular Counter With Counting Sequence

2. Prepared By Name: Rokon, Md. Shafaat Jamil ID: 17-33084-1

3. Topics To Be Covered Introduction State Diagram Next-State Table K-Map Counter Implementation

4. Introduction Counter A counter is a device which can count any particular event on the basis of how many times the particular event(s ) is occurred . Synchronous Counter Synchronous Counters are so called because the clock input of all the individual flip-flops within the counter are all clocked together at the same time by the same clock signal

5. State Diagram

6. Flip Flop Transition Table .

7. Next-State Table Q3 Q2 Q1 Q0 Q3 Q2 Q1 Q0 J0 K0 J1 K1 J2 K2 J3 K3 1 1 1 1 X 1 X 1 1 X 1 X 1 1 X X 1 X 1 1 X X 1 X 1 X 1 1 X X 1 X X 1 Present State Next State 1 1 1 1 X 1 X X 1 X

8. K-Map X X X 1 X X X X X X X X X 00 01 11 10 00 01 11 10 Q3Q2 Q1Q0 X X 1 X X X X X X X X X X X X X 00 01 11 10 00 01 11 10 Q3Q2 Q1Q0 J0 Map K 0 Map

9. K-Map Cont... . X X X 1 X X X X X X X X X 00 01 11 10 00 01 11 10 Q1Q0 X X 1 X X X X X X X X X X X X X 00 01 11 10 00 01 11 10 Q3Q2 Q1Q0 J1 Map K 1 Map

10. K-Map Cont... . X 1 X X X X X X X X X 1 X X X 00 01 11 10 00 01 11 10 Q1Q0 X X 1 X X X X X X X X X X X X X 00 01 11 10 00 01 11 10 Q3Q2 Q1Q0 J2 Map K 2 Map Q3Q2

11. K-Map Cont... . 1 X 1 X X X X X X X X 1 X X X 00 01 11 10 00 01 11 10 Q1Q0 X X X X X X X X 1 X X X 1 X X X 00 01 11 10 00 01 11 10 Q3Q2 Q1Q0 Q3Q2 J3 Map K3 Map

12. Logic Expressions J0 = Q2Q3’ K0 = 1 J1 = Q2Q3’ K1 = 1 J2 = Q0+Q3 K2 = 1 J3 = Q2’ K0 = 1

13. Counter Implementation (Drawing) .