Digital Design Flow.pdf

In semicustom digital ASIC design, a circuit is constructed by using a set of predefined logic components, known as standard cells. These cells are predesigned and their layouts are validated and tested by the foundry (or an specialized company). Standard-cell ASIC technology allows us to work at the gate level rather than at the transistor level and thus greatly simplifies the design process. The device manufactures usually provides a library of standard cells as the basic building blocks. The library normally consists of basic logic gates, simple combinational components (and-or inverters, multiplexers, full adders, etc.) and basic memory elements (D-type latch and flip-flop). Some libraries may also contain more sophisticated function blocks, such as an adder, barrel shifter, random access memory (RAM), etc.

1. Developed by Ahmed Abdelazeem © 2024 All rights reserved..Developed by Ahmed Abdelazeem © 2024 All rights reserved..
Digital IC Design Flow
Ahmed Abdelazeem

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Target Audience
Interested in learning Digital IC Design

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There are no prerequisites
Prerequisites

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Index
1.Motivation
2.Electronic Circuits and
Integrated Circuit Overview
3.VLSI Digital Design flow
4.IC Industry Overview
5.Digital Front-End Design flow
6.Digital Back-End Design Flow
7.Verification Prospective
8.EDA Overview
3

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Motivation
4
First Integrated
circuit, 1964 The Intel 4004, 1971
2,300 Transistors
The Intel 486 DX2,
1992
1.2M Transistors
Itanium 2
“Montecito”, 2006
1.7B Transistors

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Motivation -2
5
Apple M3
Introduced 2023
Technology TSMC 3nm
memory 2MB L1
20MB L2$
8MB L3$
Cores 16
Threads 16
Frequency 2.8-4.06 GHz
Die Size 141.7 mm2
#Transistors 92 B
Apple M3
max

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Motivation -3
6
•How on earth do we design such a Monster???
SoC -OMAP3 3430

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Motivation -4
7
•Hummmm!, we have a problem…
“Moore’s Law of Engineers”
Logic transistors per chip “in Millions”
Productivity Trans./ Stuff
-
Mo

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Motivation-5
8
•The Solution…
Design
Abstraction
Design
Automation
“EDA”
Design Re-use
“IP”

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Design Abstraction Levels
9
Applications
•Generic Software
Operating System
•Controlling Software
Architecture
•HW/SW Interface
System
•High-level organization
Digital Logic
•Building-block Modules
Logic
•Building-block Gates
Circuit
•Transistors, Capacitors, etc.
Devices & Interconnects
•Structures, interconnects
Physics
•Electrons, Ions, etc.
Software
Hardware
HW/SW

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10
Are you interested in
Digital IC Design?

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Implementation of Semiconductor Chips
•Semiconductor chips are used everywhere:
-Computers
-Cellular phones
-Tablets
-Smart Phones
-Gaming systems
-DVD players, TVs
-Watches
-Cars
-Medical devices
-Pacemakers and coffee pots
-Space stations
-Greeting cards
-. . .
11
Everywhere

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Types of IC Elements
12
ResistancesBipolar Transistors
H
W
L
R=
L
HW
Drai
n Gat
e
Sourc
e
n-well
co ntact
Substrate
co ntact
P+ P+ P+ n+
n-
well
Capacitances
V
i
n
VSS
VD
D
V
out
C
dg12
C
db2
C
db1
Inductances
Ii I
j
V
i
V
j



=
aj
jiji
ij
loopaloop
jiji
dadadIdI
rIIaa
jii
111
4
L
ij
Oxide
Bulk
Gate
==
=
= =DBC GBC GSC SBC GDC
Useful
Parasitic

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IC Definition
13
•Integrated circuits (IC) is a complex set of electronic components and their interconnections etched on a
chip.

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Discrete vs. Integrated Electronics
14
Circuits using discrete
components
Integrated Circuits

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Analog vs Digital Signals
15
❑Analog: continuous in time and amplitude
❑Digital: discrete in time and amplitude
[Razavi, 2014]

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Why Digital IC Design?
❑Digital Circuits are:
▪Less sensitive to noise (robust)
▪Easier to store (digital memories)
▪Easier to process (digital signal processing: DSP)
▪Amenable to automated design
▪Amenable to automated testing
▪Easier to port from one technology to another
▪Direct beneficiary of Moore’s law (down-scaling)
16

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Exact Prediction of IC Evolution -Moore’s
Law
17
1965. The number of
transistors in ICs will
double every 18
months
Source: https://www.intel.com/content/www/us/en/homepage.html

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IC Scaling
18
20um
Bipolar
2um 14nm 2nm
MOS
FinFET
GAA
… … …
•Reduction of transistor size ∼10 mlntimes
•Change of transistor type 4 times
Less power comsuming
Less leakage current
Less leakage current
So urc e : Ga rt n er

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Increase of IC Component Number
19
3 transistors 54 billion transistors27 million
transistors
First IC
Intel Pentium 3
Google TPUv4
… …

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Increase of IC Absolute Power
Consumption
20
2 W 2 kW150 W
=2x
First IC
Intel Pentium 3
Huawei Kirin 9000e
… …
Electricalpanel

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Increase of IC Specific Power Consumption
21
∼1W/cm
2
∼300W/cm
2
∼8W/cm
2
∼
First IC
Intel Pentium 3
Google TPUv4
……
Nuclear reactor

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Increase of IC Performance
22
10 kHz 8x8x5,2 GHz2,3 GHz
∼
First IC
Intel Pentium 3
Qualcomm snapdragon 865
……

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Increase of Complexity
23
Computation
1970’s -…
Networking
1990’s -…
Mobility
2000’s -…
Cloud
2010’s -…
ClassicMoore

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Changes in Markets
24
Enterprise
Software
HPC, Data Center
(AI accelerators)
Networking Mobile/5G AR / VR
Industrial
Automation
HealthcareAutomotive
Financial
Services
PC/Gaming
Government &
Aerospace
Memory
Era of Smart Everything Era of distributed intelligenceEra of Innovations
Most important: automotiveand IoT

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Era of Smart Everything
25
From the everyday-helpful to the sublime
Voice Assistants
Setting up calendar…
Critical support
for the elderly
Advanced Robotics
Home cleaning
robots…
Remote robotic
surgery
Mapping/Navigation
Package
delivery…
Humanitarian
mapping
Digital Imagery
Smartphone photos…
Diabetic retinopathy
screening

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Eraof Distributed Intelligence
26
World to generate
175
Zettabytes
of data by 2025
100B
Intelligent
Connected
Devices
Compute
1980 1990 2000 2010 2020
10
18
10
9
10
4
10
15
10
2
2030
Distributed
Intelligence
Network
Everything
Cloud
Everything
Mobile
Everything
Digitize
Everything

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Eraof Innovations
27
Comput
ing
power
2010 2020 2023
WSE-2
850,000
AI-optimized cores
Cloud TPU v4 Pod
> 1 ExaFLOPS
GTX 580
1.6 TeraFLOPS/ 512
CUDA cores

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Inconsistency between Moore’s Law and
the New Era
28
Compute performance reaching reticle size limit
CPU/GPU complexity grew over the last 15 years
Reticle Size Limit
2007 2023
GPUs
Server CPUs
Die size
~860mm
²
Cost of fabricating silicon accelerating
Silicon cost per yielded mm² for a 250mm² die
1x
2x
3x
4x
5x
6
x
45nm32nm28nm20nm14/16nm7nm5nm3nm
Normalized Cost Per yielded mm²

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Alignment with the New Era
29
Time
System Compexity
Moore’s
Law
(Silicon)
SysMoore
Era
(System)
System-On-Chip
a
Moore’s Law is slowing down…
Automotive
Consumer
Networking
HPC/Data Center
Mobile
IoT / Edge
Multi-Die System
Complexity gap

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Alignment with the New Era (2)
30
New
Era
Further
scaling -
Angstroms
(10
-10
),
Trillion
(10
12
)
Transition
to multi-
die
systems
Intensive
use of AI

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Alignment with the New Era: Further
Scaling
31
Planar FinFET
Horizontal nanowire Vertical nanowire
2010 2015 2020 2022 >2025
32nm 14nm 3nm 2nm 2-3 Angstroms (10
-10
)
…

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Alignment with the New Era: Further
Scaling (2)
32

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Alignment with the New Era: Further
Scaling (3)
33
3 transistors 90 billion transistors27 million
transistors
First IC
Intel Pentium 3
AMD EPYC
… …
Trillion transistors
10
12

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Alignment with the New Era: Transition
from Monolithic to Multi-Die Systems
34
Multi-Die
Systems
2.5D:
Interposer-
mounted
chiplets
Recursive
compositio
n
formulation
… stacks of
stacks
Heterogene
ous stacks
mounted on
interposers
/ bridges
3D stack(s)
-regular
structures
(memory,
FPGA, …)

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Alignment with the New Era: Intensive Use
of AI
35
1956 1975 1980 1990 2010 2023
AI birth
Early neural networks Natural language
Robotics
Expert systems Deep learning
Big data
1
st
rise
2
nd
rise
3
rd
rise

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History and Evolution of The IC Industry
36
⚫Semiconductor Industry Association (SIA) Roadmap
Date 1999 2005 2010 2018 2023
Technology (nm) 180 65 28 5 1
Minimum mask count 24 25 27 30 50
Wafer diameter (mm) 200 400 400 450 500
Memory samples (bits) 1G 8G 32G 10T 100T
Transistors/cm
2
6.2M 180M 330M 1.5G 20 G
Maximum number of metal layers 6-7 9 9 12 25
Clock frequency (MHz) 1250 3200 5200 20000 35000
IC sizes (mm
2
) 400 596 699 750 1200
Power supply (V) 1.5-1.60.8-1.2 1.2-10.37-0.42
0.28-
0.33
Maximum power (W) 90 150 171 183 2200
Number of pins 700 1957 2734 3350 4200

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Technology Roadmap
37
Smaller, cheaper
Increasing Design Cost
Faster
Less Power
Parasitics CD
Variability
Leakage Power
Density
.7µm
•1991
.5µm
•1992
.35µm
•1993
.25µm
•1994
.18µ
•1996
.13µm
•2002
.09µm
•2004
65nm
•2006
45nm
•2008
32nm
•2010
22nm
•2012
14nm
•2014
7nm
•2018
5nm
•2020
3nm
•1990

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VLSI Digital Design Style
❑Due to time and cost constraints, very few teams and/or companies develop
products from device level through to system level.
❑Various Design Styles are available to shorten the time-to-market and
development cost.
❑Trade-offs are take n into consideration, as abstractions are usually designed
generically and therefore come with some overhead.
❑In the following slides, we will briefly discuss:
▪Full custom design
▪Standard Cell based ASIC design
▪Field-Programmable Gate Array (FPGA) design
▪Microprocessor (Software)
38

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VLSI Design Styles –Full Custom
❑Full Custom Design
▪The original design style.
▪Everything is done at transistor level
▪Rarely used in digital design
▪High cost
▪But gives significant gain in performance.
▪Analog designs mostly
39

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VLSI Design Styles –Semi Custom
•Design is compiled using ready blocks:
-Technology-dependent fixed size physical designs
Digital standard cells
Small cells performing simple logic used to build larger designs
(Boolean primitives: and, or, xor; flip-flops; adders, etc.)
Hard macros (Hard IP)
Ready physical design (analogcells, I/O cells, etc.)
-Technology-independent behavioural descriptions, synthezible
to physical design using standard cells and if necessary hard-IPs
Soft macros (Soft IP),
Synthezibleregister transfer level descriptions of complex functions (processor cores, arithmetic units, etc.).
System-level macros (SLMs)
High level behavioural descriptions (DSP logic, digital filters, etc.)
40
Logic created
from standard
cells
Hard macros
I/O
Soft
macro

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VLSI Design Styles -FPGA
❑FPGA –Field Programmable Gate Array
▪Array of configurable logic blocks, and programmable
interconnect structures
▪Fast prototyping, cost effective for
low volume production
▪HDL (hardware description language) –
is used
41

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Design/Manufacturing Options
•Full-Custom
-All design and manufacturing process cycles are circuit specific
•Semicustom
-Some design and manufacturing cycles is predefined
•Programmable
-Functionality achieved by configuring (programming) already
fabricated general purpose IC
42
Full-
Custom
Semi-
Custom
Prog.
Cost
(design/manufacturing)
High Small Low
Quality
(performance/area/power)
Best Low Low
Time-to-Market
(time-to-market)
Long Short Short
Production Volume
(use cases)
LargeMedium Small
Full-Custom and Semicustom fabrication is used for Application Specific ICs
(ASIC), i.e. manufactured for specific purpose

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IC Industry overview
43
❑Semiconductor sales
revenue worldwide (2022)
▪~ 600 billion USD

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VLSI Design Ecosystem
44

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IC Industry in Egypt
45

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IC Fabrication process
❑Sand to Silicon process:
GLOBALFOUNDRIES Sand to Silicon
46

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The Life of CMOS Inverter
47
Specification
“Device that outputs the
inverse of its input with
minimum size and
power”
RTL
module invx1(
input wire a,
output wire z );
assign z=!a;
endmodule
Gates
a Z
invx1
Transistor and Layout

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Digital Design Flow
48
Cell description coding (RTL)
Description simulation
Logic Synthesis
yes
yes
no
no
Synthesis tool
STA tool
STA tool
Physical synthesis tool
Verification
tool
Verification
tool
Logic Simulation
Finished design
Post-layout STA
Timing OK?
Formal Verification (RTL
VsGate level circuit)
Formal Verification
(Layout vs.Synthesized
Netlist)
Specification
Floorplanning,
Placement & Routing
Pre-layout STA Timing
OK?
Specification
9 bit resolut ion 10 bit
200 MHz conversion
rate 400 MHz
200 MHz clock
freq uency 400 MHz
Integral nonlinearity 1
LSB
. . . . . . . .
IC design

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Digital IC Designer
❑How to be a Digital IC Designer?
▪knowledge of Logic Design basics and concepts
▪knowledge of Computer Organization and Architecture
▪Very good understanding of Hardware Description language HDLs
▪Very good understanding of Digital IC Design flow
▪Hands-on experience using Digital design Synopsys/Cadencetools
▪Scripting languages (Python-TCL-Perl…..)
▪Basic knowledge of IC industry with all division, companies and customers.
▪Logical thinking and creativity for problem solving
49

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Digital ASIC Design Flow Responsibilities:
Frontend VS Backend
50
Digital Frontend team
•Choosing microarchitecture, suitable algorithms to use, number of pipeline
stages…etcaccording to the system specifications.
•Developing synthesizable RTL and constraints.
•Developing suitable DC scripts for synthesis and DFT.
•Specifying power domains and generating UPF maps.
•Performing verification for the RTL.
•Performing gatelevelsimulations to check backend deliverables.
Digital Backend team
•Meeting timing requirements of setup and hold according to SC library
specifications.
•Meeting special timing requirements asked by the digital team (ex. Skew
balancing).
•Matching digital team intended design: gatelevelnetlist matching RTL.
•Meeting physical design rules specified by the foundry (DRC, LVS,
Antenna, DFM)
•Minimizing IR drop over the design so that it is below a defined
threshold (~2%)
•Minimizing power consumption so that it’s comparable to a similar node or
similar design.

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Self-evaluation
7 point * 10 = 70 total percentage ex. 50/70…etc
Strength points:
•.
•.
•.
Week Points:
•.
•.
•.
51

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Resources
•ASIC Design Roadmap
•Digital Logic and Computer Design by M. Morris Mano
•"Computer Organization and Design: The Hardware/Software Interface" by David A. Patterson and John L.
Hennessy
•"Computer Architecture: A Quantitative Approach" by John L. Hennessy and David A. Patterson
•Verilog HDL: A Guide to Digital Design and Synthesis by Samir Palnitkar
•FPGA Prototyping by Verilog Examples: Xilinx Spartan-3 Version by Pong Chu
•ASIC Physical Design Notes
•ASIC Design Training
52

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“Three Letter Words”
•PDK –Process Design Kit
•HDL –Hardware Description Language
•RTL –Register Transfer Level
•EDA –Electronic Design Automation
•ASIC –Application Specific Integrated Circuit
•FPGA –Field Programmable Gate Array
•IP –Intellectual Property
•DRC –Design Rule Check
•LVS –Layout Vs. Schematics
•RCX –Resistance/Capacitance Extraction
•DFM –Design for Manufacturing
•DFT –Design for Testability
•UPF -Unified Power Format
•PnR–Placement and Routing
53

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Thank You ☺