digital electronics made easy hand written notes Gate ECE
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May 28, 2018
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About This Presentation
MADE EASY Electronics and communication handwritten notes
Slide Content
Ei HAND WRITTEN NOTES
FELECTRONICS & COMMUNICATION
ENGINEERING
= SUBJECKi=
DIGITAL ELECTRONICS
A)
2 |
> 18
Vueuveveeus
FELECTRONICS & COMMUNICATION
ENGINEERING
= SUBJECKi=
DIGITAL ELECTRONICS
A)
2 |
> 18
Vueuveveeus
BooLean ALGE ara
Boolean Algebra :
© when no of variable are less. (123) E
oo 1 À
© Eis prafered when output
K-map =
SHES are 2,3,1,5 LUPO 5 Variable)
© output is 0.107, à
© when no. of va
Tabolation method
this used when no. of variables are more
Boolean Algebra *
A complement — À or. A :
Boolean Algebra :
© when no of variable are less. (123) E
oo 1 À
© Eis prafered when output
K-map =
SHES are 2,3,1,5 LUPO 5 Variable)
© output is 0.107, à
© when no. of va
Tabolation method
this used when no. of variables are more
Boolean Algebra *
A complement — À or. A :
oblem;
AGr Adce
ception. a)
RPP
E nn
3 No. of logic gate y E
> speed T awe = :
> Power dissipation Y
> compleaity of cirwit less TE
fan in + (no. of input y) = i
5 cont +
Robien:
Simplity
AB + ABs + AGCD
sa)
ABE AS (+60)
= nec + AS
Ale +6) ar et = 846)
ï
A(B+E)
= A6 Ac
CCS
) (a:
Aar AC TAB + BCE
AG+8+) + BC
= A + BC i
1
|
E n+ ACB) + BC
ATanspas|tion Theorem
(Ar 8) (Are) A+8c [
pace CL
chesmete
AGr Adce
ception. a)
RPP
E nn
3 No. of logic gate y E
> speed T awe = :
> Power dissipation Y
> compleaity of cirwit less TE
fan in + (no. of input y) = i
5 cont +
Robien:
Simplity
AB + ABs + AGCD
sa)
ABE AS (+60)
= nec + AS
Ale +6) ar et = 846)
ï
A(B+E)
= A6 Ac
CCS
) (a:
Aar AC TAB + BCE
AG+8+) + BC
= A + BC i
1
|
E n+ ACB) + BC
ATanspas|tion Theorem
(Ar 8) (Are) A+8c [
pace CL
chesmete
[ana = T+ve
@| (arerc) Car8+e) carere)
CA4 Gac) are} E 1
| A+ BC
Mm] (At8) (ATG) (Ara) AB) | = re
‘soll (Are) Car 8) CTI)
| >
Lo] en teem
= (Are) Are
@| (arerc) Car8+e) carere)
CA4 Gac) are} E 1
| A+ BC
Mm] (At8) (ATG) (Ara) AB) | = re
‘soll (Are) Car 8) CTI)
| >
Lo] en teem
= (Are) Are
= Grae
(Bra) (848)
“AB + Ac + BC (ATA)
AB + À; +6cA + ABC
AB (14) + Accıra)
BC is Known as redondan! term se notused
Jor not compulsory term.
pa ee
AG + AC +80 = AG+ AC
| or redundancy — theowm
(©) Three variable
each variable comes twice
©) One voriable is complemented
| | The term which is complemented
ie token
(Bra) (848)
“AB + Ac + BC (ATA)
AB + À; +6cA + ABC
AB (14) + Accıra)
BC is Known as redondan! term se notused
Jor not compulsory term.
pa ee
AG + AC +80 = AG+ AC
| or redundancy — theowm
(©) Three variable
each variable comes twice
©) One voriable is complemented
| | The term which is complemented
ie token
¡GAL
are complemented only one an
n which is UnComplemeri
conanieat
minima
Complement Expression
Truth table
Ven Diagram
‘Switching circuit
‘Statement
are complemented only one an
n which is UnComplemeri
conanieat
minima
Complement Expression
Truth table
Ven Diagram
‘Switching circuit
‘Statement
|
A| Minimization :-
ol + Y
sai
Fara) > men the
FU GE»
xy +2
+ RENTE 1 — =
A| Minimization :-
ol + Y
sai
Fara) > men the
FU GE»
xy +2
+ RENTE 1 — =
«| soP (Sum of Produot Form)
Anc_+ Kec + AGE
| In sor form, ‚ach product term_is ‚known as Minter or
Implicant |
Sop Form is used when ©/P of togical
(means 1> A and 0>A)
is 4
En Ss > 101 “ABC
9 > 1001 — A66D
|
@ves:| For the given truth table . minimize SOP expres
Tem r ==
a A ==
| o E
| A E E
| Salsa
ea Si
| AG + AB 5 A
FEN su
| 3 ES
y can written as
[va
YCA.@ - =m(023)
“logical pression in sop dorm:
Y» AB + AG + AB
& (Ara) + A8
B + AB ye
(8+A)18+2)
_ar6 |
= Are
Anc_+ Kec + AGE
| In sor form, ‚ach product term_is ‚known as Minter or
Implicant |
Sop Form is used when ©/P of togical
(means 1> A and 0>A)
is 4
En Ss > 101 “ABC
9 > 1001 — A66D
|
@ves:| For the given truth table . minimize SOP expres
Tem r ==
a A ==
| o E
| A E E
| Salsa
ea Si
| AG + AB 5 A
FEN su
| 3 ES
y can written as
[va
YCA.@ - =m(023)
“logical pression in sop dorm:
Y» AB + AG + AB
& (Ara) + A8
B + AB ye
(8+A)18+2)
_ar6 |
= Are
fom
(ft is a minimal form)
each term must have all variable.
ee 46 AG
Tus each, minctern" will contain all variable
= Ac + ABE + ABc + ABC + ABC + ABC
| sc + ABE + ABC + ABS 1 ABC
ie. Sterms.
(ft is a minimal form)
each term must have all variable.
ee 46 AG
Tus each, minctern" will contain all variable
= Ac + ABE + ABc + ABC + ABC + ABC
| sc + ABE + ABC + ABS 1 ABC
ie. Sterms.
Form (Product of Sum) 3
(At 81€) (Av Bre) (At816)
| fs form are vendo oe Toye
0 À
ER
S10) — AëC
J > wor > Asch
CET: CE
take only tat valve at which op is "0
Ara) (At 8)
B+ AA
a
3 | Y can be written in ros form as,
704.8) ma (63)
‘and for sop «
7 (48 = =m 2)
(At 81€) (Av Bre) (At816)
| fs form are vendo oe Toye
0 À
ER
S10) — AëC
J > wor > Asch
CET: CE
take only tat valve at which op is "0
Ara) (At 8)
B+ AA
a
3 | Y can be written in ros form as,
704.8) ma (63)
‘and for sop «
7 (48 = =m 2)
maximum _ pos
=!
EM)
min or max terms
Total no_ of are
3 ie. (ABC)
Sta) no: of min or man terms are
16 logical expre
(AD total
AB
AG
46 Ate
mö AB
Awe Ate
Note] with maximum possible logical expression
pi
are
e
logical expression
for n-4 what is the total no. of
logical expression =
=!
EM)
min or max terms
Total no_ of are
3 ie. (ABC)
Sta) no: of min or man terms are
16 logical expre
(AD total
AB
AG
46 Ate
mö AB
Awe Ate
Note] with maximum possible logical expression
pi
are
e
logical expression
for n-4 what is the total no. of
logical expression =
Dual Form =
tive logic ive logic
> -ive logic mans high
= tive logie means higher
voltage . cartes pond:
logic ‘0
togie
2oqfc
voltage _ corresponds to
aus} toc ©
ge >
a] wighor aus a} voltage (Was logia 1: then «be logie
tie 0 — iv
gic ı > -08V
089 is tai valve than -ı.7v then it is +ive logic
logic AND —ive loge AND
e Y
aso!
or gate
a that + ive logic
logie OR gate and -ive logic
wie OR gate
tive logic ive logic
> -ive logic mans high
= tive logie means higher
voltage . cartes pond:
logic ‘0
togie
2oqfc
voltage _ corresponds to
aus} toc ©
ge >
a] wighor aus a} voltage (Was logia 1: then «be logie
tie 0 — iv
gic ı > -08V
089 is tai valve than -ı.7v then it is +ive logic
logic AND —ive loge AND
e Y
aso!
or gate
a that + ive logic
logie OR gate and -ive logic
wie OR gate
>| Deal expression is used to convert «ive logic. into rive
Logic or, ive logic ‘to +ive logic
a ar8
Dual is nothing but —ive logic
(Az BE) (A128 +8 (At 8710)
mi again dual then.
Ae + Asc + ABC
Y any logical expression , # two times
Bann +
E=
| resulting same expression
TEE
AB= 8c +Ac
Dual: -__
48) (8:10 (Arc)
Gz AD (ALO
BA+ BC+r AC +AC
nur Ses AC again same are
In some of the logical expression not all its dual gives
[the same expression. =
dhesmate race TA
Logic or, ive logic ‘to +ive logic
a ar8
Dual is nothing but —ive logic
(Az BE) (A128 +8 (At 8710)
mi again dual then.
Ae + Asc + ABC
Y any logical expression , # two times
Bann +
E=
| resulting same expression
TEE
AB= 8c +Ac
Dual: -__
48) (8:10 (Arc)
Gz AD (ALO
BA+ BC+r AC +AC
nur Ses AC again same are
In some of the logical expression not all its dual gives
[the same expression. =
dhesmate race TA
Sie 2s
In self Dual expression , if one time dual
expression.
© are n variables then
Ten :2 dual expression. _
is used
total no. of se dual expr-
A Set duos =]
A=A
Ws Foon»2 > 2 4
hen» dual expression
SS
AA A
O
wo for n-3 = 2
Then 16 dual expression
JADE, Bo) 6 wABaeceee
€) | Complement =
ÿ asc + Aes + AGC
complement is,
8 +6) (Ar8+C) (A+8+6)
YEAR
--
O AND — oR
AA complement
O
complement oj each variable .
o
hase
juas]
In self Dual expression , if one time dual
expression.
© are n variables then
Ten :2 dual expression. _
is used
total no. of se dual expr-
A Set duos =]
A=A
Ws Foon»2 > 2 4
hen» dual expression
SS
AA A
O
wo for n-3 = 2
Then 16 dual expression
JADE, Bo) 6 wABaeceee
€) | Complement =
ÿ asc + Aes + AGC
complement is,
8 +6) (Ar8+C) (A+8+6)
YEAR
--
O AND — oR
AA complement
O
complement oj each variable .
o
hase
juas]
e] ven Diagram =
for two variable (4,8). ie AS
m 7
WER
@ given venn diagram. minimize _sop_enpression
aded regen
AB+AB+AG
ACHETE
A+AB
GA) (AB)
Ate
(0.0) Go eosjorm) _
Sop expression
for two variable (4,8). ie AS
m 7
WER
@ given venn diagram. minimize _sop_enpression
aded regen
AB+AB+AG
ACHETE
A+AB
GA) (AB)
Ate
(0.0) Go eosjorm) _
Sop expression
AB + AB + A6 +AG
B(AtA) + B(AtA)
618
1
= ABE
For_3- variable :- = £ Sr
=
sop orm jor shaded portion asc
cine)
ABC+ ABcr acc + ABC + AB
=o:
BC (A1A) + AB(E*C) + Actaıd) a
ABr BC+ CA
B(AtA) + B(AtA)
618
1
= ABE
For_3- variable :- = £ Sr
=
sop orm jor shaded portion asc
cine)
ABC+ ABcr acc + ABC + AB
=o:
BC (A1A) + AB(E*C) + Actaıd) a
ABr BC+ CA
«| Switching Circuit
|For Series :
Truth table =
A Y
1 1
|
| For Parailet
Th place of bulb
the some but so!
@ For A=ı. transistor
shgrt circuit
|For Series :
Truth table =
A Y
1 1
|
| For Parailet
Th place of bulb
the some but so!
@ For A=ı. transistor
shgrt circuit
=TA6+ AC) 6
= ABB + ACO
= ABB + ACO
circuit have 3 input
is 1 for the follaving
8 and €
A_and
A ,Band-c are tue
wo A ,Bandc are false _
the Op jor.
then minimize
“Op yet
A togic 3 input
majority no of 3/es are logie 1
to minimizing expression E
Ses an =
Rec ABC NAB SNOB
TT IAE
BCCATA) + Ac( 818) + AB (Etc)
Aes BcıcA
dhssmte
eno CLI
is 1 for the follaving
8 and €
A_and
A ,Band-c are tue
wo A ,Bandc are false _
the Op jor.
then minimize
“Op yet
A togic 3 input
majority no of 3/es are logie 1
to minimizing expression E
Ses an =
Rec ABC NAB SNOB
TT IAE
BCCATA) + Ac( 818) + AB (Etc)
Aes BcıcA
dhssmte
eno CLI
LOGIG_ GATE.
Basic Building Block.
f= x a
me — universal gate
= Arithmetic cut
a
generator J checker
(ainory to gray, Gray to Binary)
EXNOR
the ng are
oer
ja ASE
ame
es eve gene
it af Were 5 m feedback te
we apply O then gato _
er
pre A
ie the OP.
| eujer means whatever ‘the MP
Bot there is a feedbock and ihe Ye is stable if we give |
1 ond if gives o Wen ofp iso wei
El
as ve,oJe is also
quo stable stale.* *
3 Hence it. is @ Bistable mullivibraior.
mei
elassmate
Basic Building Block.
f= x a
me — universal gate
= Arithmetic cut
a
generator J checker
(ainory to gray, Gray to Binary)
EXNOR
the ng are
oer
ja ASE
ame
es eve gene
it af Were 5 m feedback te
we apply O then gato _
er
pre A
ie the OP.
| eujer means whatever ‘the MP
Bot there is a feedbock and ihe Ye is stable if we give |
1 ond if gives o Wen ofp iso wei
El
as ve,oJe is also
quo stable stale.* *
3 Hence it. is @ Bistable mullivibraior.
mei
elassmate
Eta
Sind
cie Define 1 land smetime ©
also called fable multivibrator
period (T) = 6 Ted
20 tra
of wer ters in feedback
in fg. the porpten delay oj each NOT
gensralor square wave ©
Sun
wor sec Ten jrequencg of
=
¡000 pes
109 nz
Sind
cie Define 1 land smetime ©
also called fable multivibrator
period (T) = 6 Ted
20 tra
of wer ters in feedback
in fg. the porpten delay oj each NOT
gensralor square wave ©
Sun
wor sec Ten jrequencg of
=
¡000 pes
109 nz
OY
me Ki shown in the fig the prorogation delay o) each nor gat
period of wave I
is __gnsec. Then time generated equare
Astable MuHivibrator_, | square wave „generalor
T= 2Nipg
243k 2n80c 12 psec
Fagor nar gore
| Thus time period at x end y is some
AND GATE 37
(ote oe
tow Le logie "O".
iative tw
classmate
me Ki shown in the fig the prorogation delay o) each nor gat
period of wave I
is __gnsec. Then time generated equare
Astable MuHivibrator_, | square wave „generalor
T= 2Nipg
243k 2n80c 12 psec
Fagor nar gore
| Thus time period at x end y is some
AND GATE 37
(ote oe
tow Le logie "O".
iative tw
classmate
Y ABC (AB). € A (80) A
| =D
3 AD gote is in working
janging. in Enabled |
— ge emily any eS ren.
~ | then it will act as
|
>| In eo logic family
Hosting input will aut as logic D
A 4 Y =
4
_topenor floating 46) — se ee
= Question occurs mostly from ect and TTL. in Exam
Unosed H/PS 3 +
Ti =e
1
=] In mottipin (HP) “AND qote umusel (Pp can be
connected to logia 1. ar" puil Cat
>| unused Ye can be connected to logic “o” or
= pull Down”.
map I
| =D
3 AD gote is in working
janging. in Enabled |
— ge emily any eS ren.
~ | then it will act as
|
>| In eo logic family
Hosting input will aut as logic D
A 4 Y =
4
_topenor floating 46) — se ee
= Question occurs mostly from ect and TTL. in Exam
Unosed H/PS 3 +
Ti =e
1
=] In mottipin (HP) “AND qote umusel (Pp can be
connected to logia 1. ar" puil Cat
>| unused Ye can be connected to logic “o” or
= pull Down”.
map I
fs
used Tr.
IO
then unused 2/p can be open
Sears ar, de due
be down
Best way to cobnecting uwsed ein Wve) in AND gate is
connecting
to E, join
to logic'1"
elasemate
na CET
used Tr.
IO
then unused 2/p can be open
Sears ar, de due
be down
Best way to cobnecting uwsed ein Wve) in AND gate is
connecting
to E, join
to logic'1"
elasemate
na CET
[os Gate :— (inclusive oR)
RD
>
L
+
|
|
Te
aR ga = follows bath comme
and Associative law.
© a mmotative law :-
+8 = BrA
do fssociative law
BC = (AtB)4C
==>
Enable and Disable :—
1 1
o —
Op is changing as UP
a SE E?
is changing or we soy
trol
the gate is enabled.
°
ma ELI
RD
>
L
+
|
|
Te
aR ga = follows bath comme
and Associative law.
© a mmotative law :-
+8 = BrA
do fssociative law
BC = (AtB)4C
==>
Enable and Disable :—
1 1
o —
Op is changing as UP
a SE E?
is changing or we soy
trol
the gate is enabled.
°
ma ELI
> pis fixed or not changed
it is cold to be disoble
used Ups :-
is connected 1" logic. O7
| in ok gate, umused 5/P à
down.” =
nnact to one of the used 1/P
is ecı then unused ip canbe open ar jloated
the unused yp 5 d 4
In OR gate, Best way of connecting
the given 1/P op is
SD
SS
— Sen
A a E
floated) 1 E
a
za 0
Cm
©) AB
<) AB
In TIL, au yes ae
float then it is loo L
it is cold to be disoble
used Ups :-
is connected 1" logic. O7
| in ok gate, umused 5/P à
down.” =
nnact to one of the used 1/P
is ecı then unused ip canbe open ar jloated
the unused yp 5 d 4
In OR gate, Best way of connecting
the given 1/P op is
SD
SS
— Sen
A a E
floated) 1 E
a
za 0
Cm
©) AB
<) AB
In TIL, au yes ae
float then it is loo L
froblem| For _Ecı „OR, SNVERTER
If all yp are Hoating Im ECL
and Op y= AB Ans
If all yp are Hoating Im ECL
and Op y= AB Ans
NAND GATE :~ (Gubbied oR)
7
> When both Ip high the op i ow
LE.
=D
Y enable
1— 0
© disabe ( noichonging if one
UP 5010)
NANO gate follow commutolive law butnot jollow associative
ET ee
5 >
only fo qote mot follow ossociafive law ie universal
NAND or NOR gate
unused 1/p in NAND gate can be connected similar
=D"
(Bubtied AND)
OR gate followed ty Not gate.
mere.
rent
chssmite ra [EJ
7
> When both Ip high the op i ow
LE.
=D
Y enable
1— 0
© disabe ( noichonging if one
UP 5010)
NANO gate follow commutolive law butnot jollow associative
ET ee
5 >
only fo qote mot follow ossociafive law ie universal
NAND or NOR gate
unused 1/p in NAND gate can be connected similar
=D"
(Bubtied AND)
OR gate followed ty Not gate.
mere.
rent
chssmite ra [EJ
5 unen both vp is tow te Ye!
y disable.
both are some as OR qote
A A a
te connected similar to
unused up in NOR
y disable.
both are some as OR qote
A A a
te connected similar to
unused up in NOR
Poner 1 inverter
It is also called controlled invert
Note
Then we say se
odd na.oj same Typ gives some o/p
AQ AQA0A - O [and even no same 9%/p gives aze
om so on Jos op.
>| B0s0e0-...n - 8. Hn 5 odd à
0 > if 9 is even
ET ni
HX & the We Men Ye is
=
E oo 2 =
(om Da Dre
do x fi Fe: a
CE
ai] ap of even exog gate have same op.
GS
It is also called controlled invert
Note
Then we say se
odd na.oj same Typ gives some o/p
AQ AQA0A - O [and even no same 9%/p gives aze
om so on Jos op.
>| B0s0e0-...n - 8. Hn 5 odd à
0 > if 9 is even
ET ni
HX & the We Men Ye is
=
E oo 2 =
(om Da Dre
do x fi Fe: a
CE
ai] ap of even exog gate have same op.
GS
Internat diagram of EXOR gate :- een
commutative
no,
ExoR gate follow both
ExOR gate
57 E
A er 2
1
si = N een
o E 2 i
\
7 =
o = =
\
The Or of ExOR gale is 1. when no. oj ls ot the
1e is odd mo. A cs
logical expression :- E
Y = Age + AGS + ABE + ABC E
= 001 + 010 + 100. + 111 => odd po of t's.
7 = Se Cee)
The reduced form of this eapression ie,
Ae e@c
dhcsmate PT ET
commutative
no,
ExoR gate follow both
ExOR gate
57 E
A er 2
1
si = N een
o E 2 i
\
7 =
o = =
\
The Or of ExOR gale is 1. when no. oj ls ot the
1e is odd mo. A cs
logical expression :- E
Y = Age + AGS + ABE + ABC E
= 001 + 010 + 100. + 111 => odd po of t's.
7 = Se Cee)
The reduced form of this eapression ie,
Ae e@c
dhcsmate PT ET
EXNOR or ANOR +
en ere
expression - _(A+6) (A+ 6)
whan ARB, then’0/P ter Hite >
erejore coincedence logic CKt and also called as equiv
detector
AFB ‚Te Pis aw
when
conto) (inverter)
CES
en ere
expression - _(A+6) (A+ 6)
whan ARB, then’0/P ter Hite >
erejore coincedence logic CKt and also called as equiv
detector
AFB ‚Te Pis aw
when
conto) (inverter)
CES
e660 6---- > =
I mr =A
farce. aca =
AQADA=_A
ADADADA= 1
and = on
ExoR and emor S|
wert cry” when
EE EA
ie
Find expression of AO 806. _
A0 80 €
Géragec
= (erA8)C + (G6+48)c
= (AB -AB)E + (ÂAB+AB)C
= (e +A6) = (408) =
AGG
AB+A8
(ABrABIO + (AB ADC
SABE ARGH TE AGc + ABC
I mr =A
farce. aca =
AQADA=_A
ADADADA= 1
and = on
ExoR and emor S|
wert cry” when
EE EA
ie
Find expression of AO 806. _
A0 80 €
Géragec
= (erA8)C + (G6+48)c
= (AB -AB)E + (ÂAB+AB)C
= (e +A6) = (408) =
AGG
AB+A8
(ABrABIO + (AB ADC
SABE ARGH TE AGc + ABC
Minimize
w A080c
is) 40806
Ze) AO 8 oe
©) ABrEC+ AC
for GOR > opis 1 when où vo of 15 at ue
Inthis case.,
Y= Aosec
2060 AA nee =
always complemented > Et 15
EXOR and EXNOR are „new
occurs
‘complement only when even variable ZE ES
ERA
EXNOR gate is even no. ot
> | ewor gate is odd no. rs
w A080c
is) 40806
Ze) AO 8 oe
©) ABrEC+ AC
for GOR > opis 1 when où vo of 15 at ue
Inthis case.,
Y= Aosec
2060 AA nee =
always complemented > Et 15
EXOR and EXNOR are „new
occurs
‘complement only when even variable ZE ES
ERA
EXNOR gate is even no. ot
> | ewor gate is odd no. rs
AL AC 6 @ A6
si | (ad sas) @ as
(AB AB) + (MST AG) A8
AB (A+8) +46 Sa BED
ag + Ae + [(Ar@(ard)] 8
n «AG +[AGr+AETAS
ad +A + AG
+76 =
(AAT TA r6)
se A+AG
ATB APS,
en]
SYMBOLS :—
es =— > J AE
NOR =
E CTA
AO
C=.
si | (ad sas) @ as
(AB AB) + (MST AG) A8
AB (A+8) +46 Sa BED
ag + Ae + [(Ar@(ard)] 8
n «AG +[AGr+AETAS
ad +A + AG
+76 =
(AAT TA r6)
se A+AG
ATB APS,
en]
SYMBOLS :—
es =— > J AE
NOR =
E CTA
AO
C=.
Universal
3
Seh
IDD =
AND as
A
Ar
Sp;
EA
Y (AA 8:48)
+ 86:48)
(A(At8) + a
ae
Sa
ees
B
gatee tesla
2 gate
3 agate
AG
=
8 ee
OB
3
Seh
IDD =
AND as
A
Ar
Sp;
EA
Y (AA 8:48)
+ 86:48)
(A(At8) + a
ae
Sa
ees
B
gatee tesla
2 gate
3 agate
AG
=
8 ee
OB
Alare)+ GA
Ass
3 Terme)
el ES
=_ abre = AOS
Ass
3 Terme)
el ES
=_ abre = AOS
> implement X
quired
a cancetted 4,
Fo tve ani -0R => Tao level: NAD =NAND
Tano-or_= HAND -nAND |
quired
a cancetted 4,
Fo tve ani -0R => Tao level: NAD =NAND
Tano-or_= HAND -nAND |
To implement op form, — only, NAND_ gate alone.
2
It implement fos form, only ınor gate alone mae
ES
a
|
[ip Et) then min mo. aj Gote
|
Dee:
Twolevel OR- AND
Twolevel_NOR - NOR
2
It implement fos form, only ınor gate alone mae
ES
a
|
[ip Et) then min mo. aj Gote
|
Dee:
Twolevel OR- AND
Twolevel_NOR - NOR
Digital circuit
J
E
combination cut Sequential cı
tp is only depend = presento] Pasent
asent Typ. E Previous
No feedback = feedback.
No memory a Memory.
ee. Hay Adder (Ha)
FA
mur
4 e9- FlipFlop (FF)
DEMUX
J
E
combination cut Sequential cı
tp is only depend = presento] Pasent
asent Typ. E Previous
No feedback = feedback.
No memory a Memory.
ee. Hay Adder (Ha)
FA
mur
4 e9- FlipFlop (FF)
DEMUX
Construct truth table
write togical expression in 80P 0! FOS form
ible
) Minimize logical expression if Pos
) Implement logie circuits
HALF ADDER CHA) =
2)
A08
implement
mio m.o} NANO
© min mo 4 war
write togical expression in 80P 0! FOS form
ible
) Minimize logical expression if Pos
) Implement logie circuits
HALF ADDER CHA) =
2)
A08
implement
mio m.o} NANO
© min mo 4 war
NOR
MA USING NANO
gate
Gate
(6) HALF SUBTRACTOR :-
W Ti table =
D
D—
Dr
= AB
CET En if
AMG. à sum
CARRY
GARRY
ADO - aum
SNo. of nok gate |
2+3 25
a8 | of Barrow
o of a o AN
-- 3 — =
— 1 = = == E
ü o EE
io _logical_expression +=
4 “pigrerence AB + A6
ARO Ke a
Implement :-
MA USING NANO
gate
Gate
(6) HALF SUBTRACTOR :-
W Ti table =
D
D—
Dr
= AB
CET En if
AMG. à sum
CARRY
GARRY
ADO - aum
SNo. of nok gate |
2+3 25
a8 | of Barrow
o of a o AN
-- 3 — =
— 1 = = == E
ü o EE
io _logical_expression +=
4 “pigrerence AB + A6
ARO Ke a
Implement :-
TE mun)
a on bate
taxa ogeoder
a on bate
taxa ogeoder
o
10
o
1 o
(Cm EC 1
fon ü T
ei ere
x Bc + AGC +A > A®80€
= mot
CARRY = ABC t ABC +
AB+ BC HAC
me tam toble of carry shows the mazority of ''S Junction.
= zm 85607) =
= =
y = tea
SS ae ERE
= 7 - Aes@c
EJ
— ARALAR
> Mea —
3 In full adder each logic gate hove propogotion delay Of ta
to provid sum or carry OP. it requires 10 2tpq delay
7 SS >= ==="
10
o
1 o
(Cm EC 1
fon ü T
ei ere
x Bc + AGC +A > A®80€
= mot
CARRY = ABC t ABC +
AB+ BC HAC
me tam toble of carry shows the mazority of ''S Junction.
= zm 85607) =
= =
y = tea
SS ae ERE
= 7 - Aes@c
EJ
— ARALAR
> Mea —
3 In full adder each logic gate hove propogotion delay Of ta
to provid sum or carry OP. it requires 10 2tpq delay
7 SS >= ==="
T non, Wie Fee + AC «Ae, SAGE FE BE
Mana) E BA) 57
1 Bea ee CD
OA 7
5
logizal expression Jor Sum= AC BOC CARRY= AGH8CIAC
Î aie. of mA and: or gate = .zun, 1-98
@ mir. roof NAND 28
Ge a) 06 NOR =
mx. of Mur = :
NS. op DEGODER «= tii, (ax8) Decoder and 2-0R gate
Mana) E BA) 57
1 Bea ee CD
OA 7
5
logizal expression Jor Sum= AC BOC CARRY= AGH8CIAC
Î aie. of mA and: or gate = .zun, 1-98
@ mir. roof NAND 28
Ge a) 06 NOR =
mx. of Mur = :
NS. op DEGODER «= tii, (ax8) Decoder and 2-0R gate
«Implementation of Full odder
since AO BOC = A080c.
NIAND iS replaced by WOR
— 2208s
ABsgcee
CARRY
are) (c+ 408)
AC + ARE HARO OC + GAS HBAS
AC + ABr 86 +A8
© (AB) + AB
‘AB+ 8c + CA
since AO BOC = A080c.
NIAND iS replaced by WOR
— 2208s
ABsgcee
CARRY
are) (c+ 408)
AC + ARE HARO OC + GAS HBAS
AC + ABr 86 +A8
© (AB) + AB
‘AB+ 8c + CA
PARAWLEL ADDER
There are three type of oder
fo) oder (we write with sequential okt)
Porolle] _odder
tok. ahead carry oder (4)
In serial adder only one Fuilodder (FA) is used to add gra.
of bits
Tt is stowest adder
TRES ER
AMID Ay Ay
ere aes Tito
:- ara and 1 HA required N
or LEA is required
forallet_ adder is used to add grodp of bits
7 odd two m bit no it requires (ui) Full adder and !
Wal} adder. or.
N Full adder or
(ZN) Half adder and n-» OR gotes required. _
| Diagrom_of Raraliel_adder ı-
as 05
There are three type of oder
fo) oder (we write with sequential okt)
Porolle] _odder
tok. ahead carry oder (4)
In serial adder only one Fuilodder (FA) is used to add gra.
of bits
Tt is stowest adder
TRES ER
AMID Ay Ay
ere aes Tito
:- ara and 1 HA required N
or LEA is required
forallet_ adder is used to add grodp of bits
7 odd two m bit no it requires (ui) Full adder and !
Wal} adder. or.
N Full adder or
(ZN) Half adder and n-» OR gotes required. _
| Diagrom_of Raraliel_adder ı-
as 05
Farollel adder & ao called Rippe carry adder.
Propogation deby from Wp array 10 Ye array. Hence
His also KNOWN as Ripple carry adder
Pek TEES E —
_ each FA will prov
= le 2 topic
adder provide: total delay of
Disadvantage of parallel adder is carry propogation delay present
AS 00oj bit increases- speed of operation reduced
m amd this Wok ahead carry adler ıs used
== RENE
> carry CCin)
F: = Fropoqation E
© = Generation term = er
= Ac ® Br Se
Gi = COB - Ae
Si Rec pets zu =
Cia PiCir Gi i= a
Propogation deby from Wp array 10 Ye array. Hence
His also KNOWN as Ripple carry adder
Pek TEES E —
_ each FA will prov
= le 2 topic
adder provide: total delay of
Disadvantage of parallel adder is carry propogation delay present
AS 00oj bit increases- speed of operation reduced
m amd this Wok ahead carry adler ıs used
== RENE
> carry CCin)
F: = Fropoqation E
© = Generation term = er
= Ac ® Br Se
Gi = COB - Ae
Si Rec pets zu =
Cia PiCir Gi i= a
Pisco + Pilg + Gy
6 (PCat Ge) + Gr
PP + PaPiGo
PAPA GOA Ara PG + G
P, Cet
Sula of AND ene nsile AS
mo of ANO Gate = menti = à
7
ne op OR “Gate = n
| ator propogation delay = tra
a] This is gastar than _ parallel adder
5 exct |
6 (PCat Ge) + Gr
PP + PaPiGo
PAPA GOA Ara PG + G
P, Cet
Sula of AND ene nsile AS
mo of ANO Gate = menti = à
7
ne op OR “Gate = n
| ator propogation delay = tra
a] This is gastar than _ parallel adder
5 exct |
Diff (A-B-<) GARRO
E
ü
o
o
_
ae eme E
E Sm (02,40
RGc + AGE + AGc +ABL
Bc + À (6c185) |
ec + À (800)
add AGC two more:-
ABLE +c) +(ArA)Bct cA(618)
Ag+ Act 8c
= 2m 03m
qu Implementation =
a Sp sers
:
E
ü
o
o
_
ae eme E
E Sm (02,40
RGc + AGE + AGc +ABL
Bc + À (6c185) |
ec + À (800)
add AGC two more:-
ABLE +c) +(ArA)Bct cA(618)
Ag+ Act 8c
= 2m 03m
qu Implementation =
a Sp sers
:
+ AGC + ABC + ABC
LAB: AB)
Banaw eapr
y Rac
ABCC+E) +
Ae + c (AB)
ze
poes
LE
>
a,
se Helen) = one.
e
Ful Subhactor will be implemented with 2-WS ard ı OR Gate
Important Aues:-
70. ef NAND qoie
ro. of NOR
ogcal_enmessen
3
sj
A080c
> ABrACı ee © Aero
gote
jor Onterence
\oqical expr Barros
no Oj MUA: 2
1 (ans) Decoder and zar gate
no. of Decoder
LAB: AB)
Banaw eapr
y Rac
ABCC+E) +
Ae + c (AB)
ze
poes
LE
>
a,
se Helen) = one.
e
Ful Subhactor will be implemented with 2-WS ard ı OR Gate
Important Aues:-
70. ef NAND qoie
ro. of NOR
ogcal_enmessen
3
sj
A080c
> ABrACı ee © Aero
gote
jor Onterence
\oqical expr Barros
no Oj MUA: 2
1 (ans) Decoder and zar gate
no. of Decoder
OM PARATOR 3
Truth Hable :-
sp =
>
¿AA ESA SÓ
2
Notezior equoliy condition AO08. condition
Hoïds
H _AAAA ae eu to 6, 6,8, Eo
Mer the eqyuatty condition $
(Fg 6s) (A, 6 Gs) (A) (Ao 28)
Truth Hable :-
sp =
>
¿AA ESA SÓ
2
Notezior equoliy condition AO08. condition
Hoïds
H _AAAA ae eu to 6, 6,8, Eo
Mer the eqyuatty condition $
(Fg 6s) (A, 6 Gs) (A) (Ao 28)
K- Mar
Te is used when e is 0,1, and x (dont care)
vepresentotion is used
In K-MAP gray code
K-map iS qrophiool _ representation
ne = Bor
> coch auccesswe term is changed ey only one
cit oe
vo variabler À
For Three variable
usa AYES 00
—
Te is used when e is 0,1, and x (dont care)
vepresentotion is used
In K-MAP gray code
K-map iS qrophiool _ representation
ne = Bor
> coch auccesswe term is changed ey only one
cit oe
vo variabler À
For Three variable
usa AYES 00
—
ES
Fae) = APS
airs 70025
4a. = m
El
|] a
the function ls A.
{ro need of any gote)
Fae) = APS
airs 70025
4a. = m
El
|] a
the function ls A.
{ro need of any gote)
(A = M (0,3) + 242)
ANS o 4
je
1058) - A+8
(A.B)
= = (3) +
fae)
In S0P form y all are Us means. op
Au are don't care
means = dont core
| nree variobie +
F(A, 6,0)
= m (3.67)
Zi we toke 6c then itis
tedundont term amd it
must be tened:
we
ana = ACT AB
classmate:
pact
ANS o 4
je
1058) - A+8
(A.B)
= = (3) +
fae)
In S0P form y all are Us means. op
Au are don't care
means = dont core
| nree variobie +
F(A, 6,0)
= m (3.67)
Zi we toke 6c then itis
tedundont term amd it
must be tened:
we
ana = ACT AB
classmate:
pact
AS Gee AB | po sol
“Re + Aw + AC
Kos provide minimise expression bot nes sn
iz mo Sol” olso
| unique
FARO > msm 2d (36)
Be Ge ec 83
SERRAT
me]
|e. 5
Z mloi,61) +2 Al 35)
“Re + Aw + AC
Kos provide minimise expression bot nes sn
iz mo Sol” olso
| unique
FARO > msm 2d (36)
Be Ge ec 83
SERRAT
me]
|e. 5
Z mloi,61) +2 Al 35)
f(A 6.6)
Foor Variable
f(A, 6,0.0)
ae Nod
28
Foor Variable
f(A, 6,0.0)
ae Nod
28
pave DoT =) ale Ete ie
@:] for the K-map minimize FOS empre
ANS ere me Ge bre
> oy
à fra:
Be) = (601675) =
> 4unchon are fume if the position of
me in K-map. and if tt
VS place
> 0 are placed -a
| at o's place 15 are placed then the function is compleme,
[to each other = E
[a Proem — 26 - page -13
@:] for the K-map minimize FOS empre
ANS ere me Ge bre
> oy
à fra:
Be) = (601675) =
> 4unchon are fume if the position of
me in K-map. and if tt
VS place
> 0 are placed -a
| at o's place 15 are placed then the function is compleme,
[to each other = E
[a Proem — 26 - page -13
(me method for_umiting
the expression from
Truth_toble)
=
+647
ABRO + ABTS
the expression from
Truth_toble)
=
+647
ABRO + ABTS
MULTIPLEXER sE OOOO
Tt is combinational circuit
up one ot the 1/e is honstere
Depending on cantipl ar select
to the Op Line
Ti ig select tp then olso colle as Data selector, Or
Many 70,008 CRE or, UANL logo Eek Sex , parallel to
serial sckt
Lo,
no of dota 1/F
ro. of select yp. _Ceontvat ep)
Tt is combinational circuit
up one ot the 1/e is honstere
Depending on cantipl ar select
to the Op Line
Ti ig select tp then olso colle as Data selector, Or
Many 70,008 CRE or, UANL logo Eek Sex , parallel to
serial sckt
Lo,
no of dota 1/F
ro. of select yp. _Ceontvat ep)
(és tagical expression
x
0
ell aja
[a
@ logicol expression :-
TA EE
x
0
ell aja
[a
@ logicol expression :-
TA EE
Taler
|__Impementation 0
y mux
with tower
=>
Implement 8:1 MU»
order t-
ELE TER
|__Impementation 0
y mux
with tower
=>
Implement 8:1 MU»
order t-
ELE TER
muxas
nor
y
CRIE
CH
no
mux ía required for nor Gote
o - RTE
—
1
[P 0-1
MX (271) is required 40r
ARO TAG
A8
+
AND Gate
nor
y
CRIE
CH
no
mux ía required for nor Gote
o - RTE
—
1
[P 0-1
MX (271) is required 40r
ARO TAG
A8
+
AND Gate
A6 +Axo
Ave
[5 amore: required
exo
gate required zrı Mur.
Ave
[5 amore: required
exo
gate required zrı Mur.
3 mx required (2:0
3 mur required (2:1)
for HA
for WS
or Sfr
=] Any two variable
with sI MUX
EXNOR =
3 mur required (2:1)
for HA
for WS
or Sfr
=] Any two variable
with sI MUX
EXNOR =
mentation oy given 109}
— JE
a el 1480 =
=m(0,1.4.6,7)
EN
— JE
a el 1480 =
=m(0,1.4.6,7)
EN
1-4: ur and
required
Implement logical expression
jueo = Cl
w AB as select tine
AC
8c
© BE =
required
Implement logical expression
jueo = Cl
w AB as select tine
AC
8c
© BE =
© 0} three variable implement
[ane x1 Mor and ane NOT E All 0 = pement
AL Thre
mu:
x q— alt Thee
LI some jour.
Al Three are tour implement
30-20
Gus
+ = mu
DUT)
first comert
it ınlo minterm expression f= =m (2.3.5.6)
[ane x1 Mor and ane NOT E All 0 = pement
AL Thre
mu:
x q— alt Thee
LI some jour.
Al Three are tour implement
30-20
Gus
+ = mu
DUT)
first comert
it ınlo minterm expression f= =m (2.3.5.6)
Hazard
arard ts cars due to ropogation delay of the logic cut
give cut
H here is propagoton delay of
| delay in Ano gate.
arard ts cars due to ropogation delay of the logic cut
give cut
H here is propagoton delay of
| delay in Ano gate.
AE by adi
atico Fedundont Fe
and oyname Hazard
in œmbinotional oxt
Hazard :- These Mazads can
essential
redundant
be
ter
avoided
atico Fedundont Fe
and oyname Hazard
in œmbinotional oxt
Hazard :- These Mazads can
essential
redundant
be
ter
avoided
Memories
y
y
Kort samt ar
‘ite | stead orky 7 Are
> Random access | > Rardomaan rs
> Vottaile y Non votataite pr BY
3 Temporary | Permanent 3
tata sata
6105/ System program
| Ferrite core —- DRO > Discrichive
Rama (Random access memory)
3| Each memory beation it m bits are
capacity (2°x m)
3| with obit address - mon no. of ™
is a”
>| ux 8 memory
FDA
=] 12 address line
8 — dota lines
static
3. Stored Like FF
(71)
dom
do
read
stored
cordon
= y
+
> magnetic tape
3 Magnetic bubb
> Ferrite core
; ccd
(chorqed couple
device
only out
then memary,
fention repair
y
y
Kort samt ar
‘ite | stead orky 7 Are
> Random access | > Rardomaan rs
> Vottaile y Non votataite pr BY
3 Temporary | Permanent 3
tata sata
6105/ System program
| Ferrite core —- DRO > Discrichive
Rama (Random access memory)
3| Each memory beation it m bits are
capacity (2°x m)
3| with obit address - mon no. of ™
is a”
>| ux 8 memory
FDA
=] 12 address line
8 — dota lines
static
3. Stored Like FF
(71)
dom
do
read
stored
cordon
= y
+
> magnetic tape
3 Magnetic bubb
> Ferrite core
; ccd
(chorqed couple
device
only out
then memary,
fention repair
ont
> Random access
3 Voltaile
errite core
Memorie
q
+ Read onty
> Random aanss
; Non volataile
Permanent
data
6105/ System pr
— DRO >
AN
Secondary
=
anda Serial access
nn memory
disk 2 moqnetic tape
co > Magnetic Eubb
DVD 3 Ferrite
gram
Discrichive
RAM (Random acess memory)
tm
= man
bits ave
no. of
Ho 3 eco
(charged cup
devi,
read only out
stored then mem
memory ta
> Random access
3 Voltaile
errite core
Memorie
q
+ Read onty
> Random aanss
; Non volataile
Permanent
data
6105/ System pr
— DRO >
AN
Secondary
=
anda Serial access
nn memory
disk 2 moqnetic tape
co > Magnetic Eubb
DVD 3 Ferrite
gram
Discrichive
RAM (Random acess memory)
tm
= man
bits ave
no. of
Ho 3 eco
(charged cup
devi,
read only out
stored then mem
memory ta
DEMUX (DEMULTIPLEAER) 5
ine WP and Mam op.
Denn iG combrational eut wbich have one Ip and may o/e
mienne
an select Up, weis
Also Known as 1to many ckt 0% dato disiituior
[ruth table :
ine WP and Mam op.
Denn iG combrational eut wbich have one Ip and may o/e
mienne
an select Up, weis
Also Known as 1to many ckt 0% dato disiituior
[ruth table :
DAT
|
4
|
|
1
|
= TT SOM m i
Go 1x8 Demo = 1x2 DEMUX de =
PS re PEN (XG DEMUX Z
Two vemu SEM =
Ixeu Demon = TA® peux
HSE emo Rs DEMO = .
: = rc
PAGE
|
4
|
|
1
|
= TT SOM m i
Go 1x8 Demo = 1x2 DEMUX de =
PS re PEN (XG DEMUX Z
Two vemu SEM =
Ixeu Demon = TA® peux
HSE emo Rs DEMO = .
: = rc
PAGE
DECODER
| 2 toy decoder
2x4 Decoder :
a lan
son
to seven
minimum
ger
si bie
deonder
©
>| Bessder isa combinational cut which have many ir and me
de
1 is used to convert binary data to ather code (binaky to
Binary to octal (3x2)
eco to Decimal 3
AGE
SE ABE 3 D =
Y» - ABE
E ÿ = Ys,
Decoder and DEMUX internal ckt remoins sam
| 2 toy decoder
2x4 Decoder :
a lan
son
to seven
minimum
ger
si bie
deonder
©
>| Bessder isa combinational cut which have many ir and me
de
1 is used to convert binary data to ather code (binaky to
Binary to octal (3x2)
eco to Decimal 3
AGE
SE ABE 3 D =
Y» - ABE
E ÿ = Ys,
Decoder and DEMUX internal ckt remoins sam
oder rane 4
DOE)
AGC + Ans
235.67)
DOE)
AGC + Ans
235.67)
ENCODER +
the combinational eut «
used to convert other
octal to Binary
Decimal to eco
Hexadecimal to 6
to Binary Encoder
E { Encode
in normal encoder one Y igh and corvespom
Binary available at the op
> fa prionty enader no. of Iyp iS Bigh only highest priority
ho corresponding Binary is available at the
Truth _ tobe
Tor £6 Is Tu
ERTEILT:
o_o
o_o
EE
o
i
|
|
|
|
|
o
o
o
the combinational eut «
used to convert other
octal to Binary
Decimal to eco
Hexadecimal to 6
to Binary Encoder
E { Encode
in normal encoder one Y igh and corvespom
Binary available at the op
> fa prionty enader no. of Iyp iS Bigh only highest priority
ho corresponding Binary is available at the
Truth _ tobe
Tor £6 Is Tu
ERTEILT:
o_o
o_o
EE
o
i
|
|
|
|
|
o
o
o
“contains AND
pemox contains AND
contains oR
_|= decode:
ENCODER
pemox contains AND
contains oR
_|= decode:
ENCODER
Fuip- FLOP _
multi vibrator
CONT ENT
>| this basic memory element.
| at can store» bits
SI FF rave two Je which have complemented
S| xt have two stoble state hence itis known c
to each ı
as eistable
1 SR FF 3 oKts
2 Jk FF > Truth toble Be
3 D FF > Co table A
Ware = equation
5 Excitation toble OTAN
> conversion from one to another.
3 simple cxt ER
mure
| a using mot gate the problem, ft
= Tp then w WAND or nor gafe instead of
mor gate E
[rra ref only ved for song et Ga if alo vsed der
divider
pepe diveder. ——
= area:
EA
multi vibrator
CONT ENT
>| this basic memory element.
| at can store» bits
SI FF rave two Je which have complemented
S| xt have two stoble state hence itis known c
to each ı
as eistable
1 SR FF 3 oKts
2 Jk FF > Truth toble Be
3 D FF > Co table A
Ware = equation
5 Excitation toble OTAN
> conversion from one to another.
3 simple cxt ER
mure
| a using mot gate the problem, ft
= Tp then w WAND or nor gafe instead of
mor gate E
[rra ref only ved for song et Ga if alo vsed der
divider
pepe diveder. ——
= area:
EA
NAND,
enable — 1
oisble- ©
fevious state (no chonge)
A Ea
re er See A
previous state
invailid state
a ee e
|
= o 7 @AND enable is 1 a
zz 130
disable
then we change a a!
a position
Ae ¡y
Previous State 3 os [a
o oi |o
o
vo
1
mati (2-6-9) TT
SR wtch 15 used to eliminate switch bouncing
eomcirq means vibmtion aj Suite when an or Of
enable — 1
oisble- ©
fevious state (no chonge)
A Ea
re er See A
previous state
invailid state
a ee e
|
= o 7 @AND enable is 1 a
zz 130
disable
then we change a a!
a position
Ae ¡y
Previous State 3 os [a
o oi |o
o
vo
1
mati (2-6-9) TT
SR wtch 15 used to eliminate switch bouncing
eomcirq means vibmtion aj Suite when an or Of
SR Flip Flog
x Hold state,
x Hold state,
Craractenstic table
Roses,
o
o
Oe iS wild
satisfy the above condition
Excitation table :—
Gnas
Disadvantage of SR FF is imailid. state
Present when
ET ande@-s
To avoid this IR FF is used
Roses,
o
o
Oe iS wild
satisfy the above condition
Excitation table :—
Gnas
Disadvantage of SR FF is imailid. state
Present when
ET ande@-s
To avoid this IR FF is used
| AO a
SA
= Le
2 act [TT
SA
= Le
2 act [TT
characterishe table —
Anı!
20
1
o
o
1
Tops erection =
minimizahon -
|
As
1
| Gon = 34, + Kn
| ih
‘Exitation table :—
EN ee
whioh ts
eliminated
Anı!
20
1
o
o
1
Tops erection =
minimizahon -
|
As
1
| Gon = 34, + Kn
| ih
‘Exitation table :—
EN ee
whioh ts
eliminated
D-Flip Flop +
Tuth table
cx»
o x
ï o
i 0
Characteristic table =
I
| excitation table :—
An An
Tuth table
cx»
o x
ï o
i 0
Characteristic table =
I
| excitation table :—
An An
T Flip-Flop
E
| &cwhon table :-
| Qs Goes SE
ORTO: kes
o eı a = a
TE = a
E
E
| &cwhon table :-
| Qs Goes SE
ORTO: kes
o eı a = a
TE = a
E
inside 3% FF
1 due Hop.
ip Flop = one bit storing element
Set Reset =
[rose mode of an =
De
7 dag is
1 due Hop.
ip Flop = one bit storing element
Set Reset =
[rose mode of an =
De
7 dag is
trigger he Trigger
A)
pay
a may chomes many |
change only ones
A)
pay
a may chomes many |
change only ones
Race Arround condition +
„| occurs in zu flip-flop (Draw back)
= Da El
co 1
SE
if tpw = 1onsec i
er - ınse. Then
Glock
mas, [Pas u je
y ITT a
hen. To remove race Orromd condition;
ne L hiper trace [eae lex < < tpder
7 K= 1 then wand tait
E nd therefore the Oe
[is charges several time in single otock puse
In Jk FF. RAG occurs when
is “fore than that of tdctocx
| Condition to remove face arround condition =
W trdetocn << trar =
w Use of Masterslaw jlipflop- _ x
ÿ To increase the propagation delay of He Hla
„| occurs in zu flip-flop (Draw back)
= Da El
co 1
SE
if tpw = 1onsec i
er - ınse. Then
Glock
mas, [Pas u je
y ITT a
hen. To remove race Orromd condition;
ne L hiper trace [eae lex < < tpder
7 K= 1 then wand tait
E nd therefore the Oe
[is charges several time in single otock puse
In Jk FF. RAG occurs when
is “fore than that of tdctocx
| Condition to remove face arround condition =
W trdetocn << trar =
w Use of Masterslaw jlipflop- _ x
ÿ To increase the propagation delay of He Hla
of Stove never go to (1) therefore
Race arround condition iS removed
iS 3-@ and n-Q@ therefore
only when the
iS change only when slave 0/p is char
1 is tevel trigered and edge ig slave
Race arround condition iS removed
iS 3-@ and n-Q@ therefore
only when the
iS change only when slave 0/p is char
1 is tevel trigered and edge ig slave
Conversion of one ff to Other FF %
ocedur a>
) Required FF characteristic table
silable FF excitation table
JK-Flip Flop to D-Füp- Flop
D án Gn
CSC
) write the logical expression for 3 and «
ocedur a>
) Required FF characteristic table
silable FF excitation table
JK-Flip Flop to D-Füp- Flop
D án Gn
CSC
) write the logical expression for 3 and «
implementation
va,
Implementation:
ges u un un un o
va,
Implementation:
ges u un un un o
Implementation —
TT.
TT.
Implementation
==
arta
= rie
==
arta
= rie
ul DILL
as
pa + DA
as
pa + DA
latch
aa tiered
Asynchronous okt
1
Setup lime
The_min. time required
Ur al prapér level vofore
chock
Hold time:
The
min vequired
applying clock
Flip Flop.
3 Edge higeed
y Synchronoug ont
to Keep
aly apply
Note: Any ff we give Dota first th
Hoe we apply chic
same level
to Keep
tip is after
aa tiered
Asynchronous okt
1
Setup lime
The_min. time required
Ur al prapér level vofore
chock
Hold time:
The
min vequired
applying clock
Flip Flop.
3 Edge higeed
y Synchronoug ont
to Keep
aly apply
Note: Any ff we give Dota first th
Hoe we apply chic
same level
to Keep
tip is after
tore >)
group or bis. 4
y {of
n bit nerr are cascaded in register
cio SI PO
& PISO
tw PIPO,
EE AAA
Shift register
Storage register
ER
a
7
3
%
n
GE dala Storage
> For serial in register the
requires n clan pulse
3 so register to store n bit data E rewire m cle
= 7
5150 register used to provide n Glock pulse delay to
Tp dota.
elininrte eee = aa me) |
3
group or bis. 4
y {of
n bit nerr are cascaded in register
cio SI PO
& PISO
tw PIPO,
EE AAA
Shift register
Storage register
ER
a
7
3
%
n
GE dala Storage
> For serial in register the
requires n clan pulse
3 so register to store n bit data E rewire m cle
= 7
5150 register used to provide n Glock pulse delay to
Tp dota.
elininrte eee = aa me) |
3
nbit data
oe BEIGE
&-n clack
serially out it requires
C67)
In
o cu
It is
sTPO
code
register to
1 clock pul
pulse
used to
s used to
serial
provide nbit d
and provide
required
to parallel converter
comert Temponal code
Slow
fo tobt
convert
serial
Parallel
= Spacial
The
cut
nine
qf «OÙ Si register which |
ia
Ste three chk pulses
applied
then
the dasa
if the system
is. ==
AA
@ 101
warn
90930.
oe BEIGE
&-n clack
serially out it requires
C67)
In
o cu
It is
sTPO
code
register to
1 clock pul
pulse
used to
s used to
serial
provide nbit d
and provide
required
to parallel converter
comert Temponal code
Slow
fo tobt
convert
serial
Parallel
= Spacial
The
cut
nine
qf «OÙ Si register which |
ia
Ste three chk pulses
applied
then
the dasa
if the system
is. ==
AA
@ 101
warn
90930.
Bee es
wor MW
on
Ds
fribially loaded rip ox pulse applied continuously
after how moy a pose again the data become
1010 =
de of variable x-oR is
&
o
Cfarollel in serial out) :—
Salad in
en
=
E
[comtrol¡-0 - Parallel an
¡en
3 in piso register fo Provide parallel in it requive veloc |
puse ard to | provide fo serial om (iy lex
pulse
wor MW
on
Ds
fribially loaded rip ox pulse applied continuously
after how moy a pose again the data become
1010 =
de of variable x-oR is
&
o
Cfarollel in serial out) :—
Salad in
en
=
E
[comtrol¡-0 - Parallel an
¡en
3 in piso register fo Provide parallel in it requive veloc |
puse ard to | provide fo serial om (iy lex
pulse
eiso is also used to conver spacial code to 'temporial
En
D
PIPO __(Farallel in parallel out)
© used as storage register
Parallel in it requires 1 alock puis
parallel out it requires 0 clock pul
|
E
Important
zu,
q
I
Ty JE left operation,
plied by 2”
Each shift right operation performed them dota is divide
by 2 ES = — + -
ba JP n shift right operation performed then dela is
divided by 2° i
rot [LT]
En
D
PIPO __(Farallel in parallel out)
© used as storage register
Parallel in it requires 1 alock puis
parallel out it requires 0 clock pul
|
E
Important
zu,
q
I
Ty JE left operation,
plied by 2”
Each shift right operation performed them dota is divide
by 2 ES = — + -
ba JP n shift right operation performed then dela is
divided by 2° i
rot [LT]
St] COUNTERS :
ter STR count
applied. it
frequency divider „
no of
z be sed
s time measure ment, frequency
vrement ; @& measyrement,, pulse width
t
canta rer
nase: J
16x Puse widlth = Total wrdtth
Aso used for waveform _generalor
with nf
mas. possible stage in the winter ©
mein
were N. no. of stage
no. of FF
Depending on clock Pulse applied
1 Asynchronous
counters of two type
Synchronous
‘Asynchronous Sypobronovs
Different FF are applied | are aprlied same
with different clack + Rs
It © stower
ee Se
UP ar down
mo
ter STR count
applied. it
frequency divider „
no of
z be sed
s time measure ment, frequency
vrement ; @& measyrement,, pulse width
t
canta rer
nase: J
16x Puse widlth = Total wrdtth
Aso used for waveform _generalor
with nf
mas. possible stage in the winter ©
mein
were N. no. of stage
no. of FF
Depending on clock Pulse applied
1 Asynchronous
counters of two type
Synchronous
‘Asynchronous Sypobronovs
Different FF are applied | are aprlied same
with different clack + Rs
It © stower
ee Se
UP ar down
mo
> NO. of stage use in counter
mean modolus of counte
ie y “op 5 counter 5 stage
Mob n counter nage US
ide counter i applied with
Jequency of 10mm.
jrequency *
tout
> lel Modm and moon are cascaded then iF to will act an
MOD mm counter
Se
content
Basic *
Kipple_ counter
Non binary ripple counter
Ring counter
Johnson counter
Synchronous series carry
‘Synchronous
parallel carry
Se ee i
Ripple _counfer
Tt is a Asynchrovovs counter.
Different FF used different clock pulse.
Toggle mode. =
Only one FE is opphèd with external clk and other
is are cin is from | previous ff op. (whether A u &).
3 Te fF applied with | extemal otk
bit
will acts as LS
mean modolus of counte
ie y “op 5 counter 5 stage
Mob n counter nage US
ide counter i applied with
Jequency of 10mm.
jrequency *
tout
> lel Modm and moon are cascaded then iF to will act an
MOD mm counter
Se
content
Basic *
Kipple_ counter
Non binary ripple counter
Ring counter
Johnson counter
Synchronous series carry
‘Synchronous
parallel carry
Se ee i
Ripple _counfer
Tt is a Asynchrovovs counter.
Different FF used different clock pulse.
Toggle mode. =
Only one FE is opphèd with external clk and other
is are cin is from | previous ff op. (whether A u &).
3 Te fF applied with | extemal otk
bit
will acts as LS
cxt Shaun
change wi
a
[> mis
fig. @ toggle for every clk pote
An, change from 1-0. ie. @, changes |
aaa as men
Mop 8 ripple
[Timing Diagram +—
dar sie:
3
1
1
i
1
3
4
4
|
pr
change wi
a
[> mis
fig. @ toggle for every clk pote
An, change from 1-0. ie. @, changes |
aaa as men
Mop 8 ripple
[Timing Diagram +—
dar sie:
3
1
1
i
1
3
4
4
|
pr
In bit ripple counter propesalion delay
tray then time period of Chk \
1
=.
un ely
ieee 1
trap
teat
tran
edge trmger — > counter
E inter
Bit Ripple counter (Down counter) >
Al
d| Erdorahon
a The ckt shown in IM @ topges for every clock pulse
> a, toggles when Ra changes from o to
3 a. toggles unen A, changes from a to A
table
tray then time period of Chk \
1
=.
un ely
ieee 1
trap
teat
tran
edge trmger — > counter
E inter
Bit Ripple counter (Down counter) >
Al
d| Erdorahon
a The ckt shown in IM @ topges for every clock pulse
> a, toggles when Ra changes from o to
3 a. toggles unen A, changes from a to A
table
This is
the co
_ avid decoding
the input clock
this is just Like
\
called ripple counter. because
of
called
ae previous __FF_ output
then Ripple counter
¡US
TS and clock is applied then tray 15 deb
000
foo:
(000)
unwanted or decading error. |
also called trangent state
errors transient state preseni in ripple
due to propogation delay
error strobe signal is used
re
Stabe
Strobe signal is zero for ni and offer trot f
is one for
neat clock. then atl the pis zero der
the
transient
time therefore due to strobe signal
we can
remove decoding error
[ax = neu + Ts
[= In ripple
counter with nff man. possible state
is 2”
Frequency after
n_3SFF inthe Ripple counter 18
Tan
=. (ie. jor FF op fra)
1
1
1
a
3
3
1
a
4
nae
the co
_ avid decoding
the input clock
this is just Like
\
called ripple counter. because
of
called
ae previous __FF_ output
then Ripple counter
¡US
TS and clock is applied then tray 15 deb
000
foo:
(000)
unwanted or decading error. |
also called trangent state
errors transient state preseni in ripple
due to propogation delay
error strobe signal is used
re
Stabe
Strobe signal is zero for ni and offer trot f
is one for
neat clock. then atl the pis zero der
the
transient
time therefore due to strobe signal
we can
remove decoding error
[ax = neu + Ts
[= In ripple
counter with nff man. possible state
is 2”
Frequency after
n_3SFF inthe Ripple counter 18
Tan
=. (ie. jor FF op fra)
1
1
1
a
3
3
1
a
4
nae
Clear and preset dee known as Asynchronau
S$.8.3,% 0,7
Ciear
rH one
Fraset ase lo se or
er
Non Binary Ripple _ counter
co counter :— (pecarie counter)
4 Hip hop used
S$.8.3,% 0,7
Ciear
rH one
Fraset ase lo se or
er
Non Binary Ripple _ counter
co counter :— (pecarie counter)
4 Hip hop used
nn
Au 66D counter is Deamde counter but reverse
rot true
eco counter rs Asymmelne op time Diagram
Oye pequercy of aco conter is 4/10
law for 8 clock and high for 2clock in ay,
duty cycle is 20%
Asynchrongus counter follow steps:
Trigger p> tive
don
counter
Au 66D counter is Deamde counter but reverse
rot true
eco counter rs Asymmelne op time Diagram
Oye pequercy of aco conter is 4/10
law for 8 clock and high for 2clock in ay,
duty cycle is 20%
Asynchrongus counter follow steps:
Trigger p> tive
don
counter
| Ring Gounter :- (e counter)
P me last ff 5 tad to Jin
? Only one FF op is high and remaining FF are low
|
|
In_4bit ring counter ustates are there. (ie. tor ner ther
n states) A =
ü Tu table
=> Im synchronous counter the
ip remains same
Wd Time Diagram :=
fox zu
P me last ff 5 tad to Jin
? Only one FF op is high and remaining FF are low
|
|
In_4bit ring counter ustates are there. (ie. tor ner ther
n states) A =
ü Tu table
=> Im synchronous counter the
ip remains same
Wd Time Diagram :=
fox zu
Pase shift bm generated waveform
360 ]
9.
Apriobtian.
> used in Stepper motor control
i
3 in Analog to Digital comertor
2 No. of unused state in ring counter is
4
| ning counter using 3-k
last o/p can not be connected
stat ring counter:
360 ]
9.
Apriobtian.
> used in Stepper motor control
i
3 in Analog to Digital comertor
2 No. of unused state in ring counter is
4
| ning counter using 3-k
last o/p can not be connected
stat ring counter:
(©) Johnson Counter:
Cop)
> Symmeh Op wovefarn
3. &-Slages are there jor 4 bit counter
3 Phase shift 360 - 90
3 Tt is qui like so
=>
E a] ofato}
Truth Table
eu a a
o
estate
©
no. of used state
{unused state
on unter , ET
Walking counter ar
Cop)
> Symmeh Op wovefarn
3. &-Slages are there jor 4 bit counter
3 Phase shift 360 - 90
3 Tt is qui like so
=>
E a] ofato}
Truth Table
eu a a
o
estate
©
no. of used state
{unused state
on unter , ET
Walking counter ar
ao
og
Johnson
AND
| Disadvantage
lock cot r oc
state)
ay.
Synchronous
nter
trar
counte!
NOR
a8
a
a0
Ss»
state One two
gate
decode
used
propagation delay o} each
unter
then
Tu =
trace
(when counter enter into unusej |
og
Johnson
AND
| Disadvantage
lock cot r oc
state)
ay.
Synchronous
nter
trar
counte!
NOR
a8
a
a0
Ss»
state One two
gate
decode
used
propagation delay o} each
unter
then
Tu =
trace
(when counter enter into unusej |
A| Syn
F
öl ee
la
|
la
E
ra
| m
Fre
planation :
Ckt_shown in fig. is Synchorous series camy up counter
To this counter @o toggles dor every clock pulse
A, toygles uen @=1 and Glock is applied
@ toges u >
S will toggles when &-6,-a, -ı and cor applied
This Okt may be down counter when @ is connected
1
A A Te
th table
Clock AA
2 o 10 3
3 o rt .
4 o oo >
5 o o
= E ai
pact
F
öl ee
la
|
la
E
ra
| m
Fre
planation :
Ckt_shown in fig. is Synchorous series camy up counter
To this counter @o toggles dor every clock pulse
A, toygles uen @=1 and Glock is applied
@ toges u >
S will toggles when &-6,-a, -ı and cor applied
This Okt may be down counter when @ is connected
1
A A Te
th table
Clock AA
2 o 10 3
3 o rt .
4 o oo >
5 o o
= E ai
pact
pin of AND Gate
Tox
fou. trdre + thane.
Ripple counter < Synchronous serial carry 2 Synchronow fil
faratlek carry counter for faster logie
Tox
fou. trdre + thane.
Ripple counter < Synchronous serial carry 2 Synchronow fil
faratlek carry counter for faster logie
| Egpchromus Series carry counter ;
i es
2 _Ckt shown in fig. is Synchorou carry | up counter
Explanation :
2 In this counter a töggles der every clock pulse
As toggles when @=1 and block ia applied
2. toggle 1 A= Got and clock applied
Ay will toggles when a,-48,>a9 =1 and close japptidd
This OK may be dawn counter when & is connected 1p
T
ü Truth table
| clock
Cn
no
Hee)
17
ro
TE
i es
2 _Ckt shown in fig. is Synchorou carry | up counter
Explanation :
2 In this counter a töggles der every clock pulse
As toggles when @=1 and block ia applied
2. toggle 1 A= Got and clock applied
Ay will toggles when a,-48,>a9 =1 and close japptidd
This OK may be dawn counter when & is connected 1p
T
ü Truth table
| clock
Cn
no
Hee)
17
ro
TE
dann
nt,
126)
4
parallel carry counter 7
Synchronos
> Kipple counter 2 Sÿnchronous serial corry
parait carry counter for faster logie
FEI — =
nt,
126)
4
parallel carry counter 7
Synchronos
> Kipple counter 2 Sÿnchronous serial corry
parait carry counter for faster logie
FEI — =
CA |
Sypchronous counler design for The given _saquence
| fatter Desgn a Bynchomcounter jor the count sequence
gar o FE
69 -
boos >
* 2
x Ve edge
STATE DIAGRAM
Sa] procedure
Identify ro of FF and Wp and %p
W®_Constwet slate _tabk
dy logical expression fr ur
Minimize
©) Empleme
the cur
w site table :-
Nertstale
Sypchronous counler design for The given _saquence
| fatter Desgn a Bynchomcounter jor the count sequence
gar o FE
69 -
boos >
* 2
x Ve edge
STATE DIAGRAM
Sa] procedure
Identify ro of FF and Wp and %p
W®_Constwet slate _tabk
dy logical expression fr ur
Minimize
©) Empleme
the cur
w site table :-
Nertstale
state table
a, Se
TEN
To = ado +
Tm plemen tation +
a, Se
TEN
To = ado +
Tm plemen tation +
Content
> Various mo syslem
) Aúlbmetic operation | > complement
7 Add, 50%,
> Dota representation, > unsigned
a
vas aetna aes
|
T ae
weighted Ynwerghiegt
> Rısitional weighted > No weighted
ee Binary , ook =
3. gay code . exces
| Decimal , Hexdecimal
| Boo code
1
2 Anumber system with base or radia r contains
es Gor),
| different digt ang they are from (0— ru)
|
|
Y = Base or radix
Different Dgit
> Various mo syslem
) Aúlbmetic operation | > complement
7 Add, 50%,
> Dota representation, > unsigned
a
vas aetna aes
|
T ae
weighted Ynwerghiegt
> Rısitional weighted > No weighted
ee Binary , ook =
3. gay code . exces
| Decimal , Hexdecimal
| Boo code
1
2 Anumber system with base or radia r contains
es Gor),
| different digt ang they are from (0— ru)
|
|
Y = Base or radix
Different Dgit
Conversión (Various number system):
o othas: =)
S dee!
Y divite
other base
vert deci into any
er _ Port _mottiply froohonal port: with r
I
0.625x2
COTES
OS *x2
ESA
062558
[2 when we percer Gus bas
increased
comer? Can,
convert (25). —
"16 125%
EI er
CFE
o othas: =)
S dee!
Y divite
other base
vert deci into any
er _ Port _mottiply froohonal port: with r
I
0.625x2
COTES
OS *x2
ESA
062558
[2 when we percer Gus bas
increased
comer? Can,
convert (25). —
"16 125%
EI er
CFE
Convert (27-4) O
2] LE | 7
72)
DEL = 1% 1 =
(123. 12 ),
| Others 40 Decimal ©
CRATRARY a
[5 To comer! any other base r to decimal mullply each
digit_with positional weighted then add
then,
= Kıyr + Kay ekg al + WT aes
| convert (10101 1),
12294 0x2 + 1x2°+ O x2
CEA
Coe eat
convert (67-48 = Cd
EXT
convert (GAD),
NIG? EL 10 x16 +
11 + 160-493
2816 4160413
2] LE | 7
72)
DEL = 1% 1 =
(123. 12 ),
| Others 40 Decimal ©
CRATRARY a
[5 To comer! any other base r to decimal mullply each
digit_with positional weighted then add
then,
= Kıyr + Kay ekg al + WT aes
| convert (10101 1),
12294 0x2 + 1x2°+ O x2
CEA
Coe eat
convert (67-48 = Cd
EXT
convert (GAD),
NIG? EL 10 x16 +
11 + 160-493
2816 4160413
3 | Octal to Binary Er Binary to
(SAT Gy
represent
oy its bit binary formate.
convert (37-25) OX
(our: 00101),
ary fo octal --
Ss] convert (10110. 11),
= (or no . 110).
CEA
Hexadecirol to Binary and Binary to Hexadecimal:
3] Each digit is represent by
4 bit binary
eo
(Go100101 1001 100),
al to octal or octal to He
octadeoman
O
[= tee 1810 vo1 ),,
(SAT Gy
represent
oy its bit binary formate.
convert (37-25) OX
(our: 00101),
ary fo octal --
Ss] convert (10110. 11),
= (or no . 110).
CEA
Hexadecirol to Binary and Binary to Hexadecimal:
3] Each digit is represent by
4 bit binary
eo
(Go100101 1001 100),
al to octal or octal to He
octadeoman
O
[= tee 1810 vo1 ),,
>
a
a
ARITHMETIC
Sub :-
OPERATION 3,
muttiplication +
110110
„101101
E 1010
a3)
a
a
ARITHMETIC
Sub :-
OPERATION 3,
muttiplication +
110110
„101101
E 1010
a3)
(fay).
ST =
a ATA = Up = UN
9A wee, e E
oo see» w ADD =
HS 74 BAD
DE TEA O
Sobiract =
o E
ST =
a ATA = Up = UN
9A wee, e E
oo see» w ADD =
HS 74 BAD
DE TEA O
Sobiract =
o E
Binary y
Decimal
19°
[cis complement — RE
> Subtroct From no. 40 the given
Comp of ( 1010) _
Tire
| mon no. possible
CEA
15 complement of ro 1101
= Thigh
=e =
Determine 95 compliment aj Decimal 267
E 99 99
= cm
73%6
Det. F's comp. of Hem 2689
ERE
RE]
= EE
Decimal
19°
[cis complement — RE
> Subtroct From no. 40 the given
Comp of ( 1010) _
Tire
| mon no. possible
CEA
15 complement of ro 1101
= Thigh
=e =
Determine 95 compliment aj Decimal 267
E 99 99
= cm
73%6
Det. F's comp. of Hem 2689
ERE
RE]
= EE
Sl [nn or
TS complement
TD determine vs
complement
st white Gays
(at right most)
complement
then acd 1 at (se
ad Det 7e comment oj 9:00 =
RO)
= loro 73%
varo =
Hoi Lz l= ee
Determine
28 complement of 10110 v1 >
on
= 01001.00
compli
ere 10 prier Hera decimal 5385
ü ECETIA FF FE
TSI ES
ABIT
—— 3
accrue
TS complement
TD determine vs
complement
st white Gays
(at right most)
complement
then acd 1 at (se
ad Det 7e comment oj 9:00 =
RO)
= loro 73%
varo =
Hoi Lz l= ee
Determine
28 complement of 10110 v1 >
on
= 01001.00
compli
ere 10 prier Hera decimal 5385
ü ECETIA FF FE
TSI ES
ABIT
—— 3
accrue
Binary coded decimol
Weighted code
8co
0000
TOO invalid 80D code or don"t care
1110
00
3
During Arithemetic_eperation y imald- Bon present the
add omo to get correct result
A combinational Kr © applied cp «ui
which E represenkel æ 05D, O10, , Ole is Yo, wat
then Tie eco is divisible oy 3. then logie exPrssi
de y is
Weighted code
8co
0000
TOO invalid 80D code or don"t care
1110
00
3
During Arithemetic_eperation y imald- Bon present the
add omo to get correct result
A combinational Kr © applied cp «ui
which E represenkel æ 05D, O10, , Ole is Yo, wat
then Tie eco is divisible oy 3. then logie exPrssi
de y is
write 8cD code each
[ee Se
Excess -3 ole -
| unweighted code
It is self complement cade
Only unweighted code which is self complement is. em
3-00de
The
code which addition 4 9 is self complemenl code
es augı
3331. 7 weighted ¢ Self complemented —
a — |
[ee Se
Excess -3 ole -
| unweighted code
It is self complement cade
Only unweighted code which is self complement is. em
3-00de
The
code which addition 4 9 is self complemenl code
es augı
3331. 7 weighted ¢ Self complemented —
a — |
2421
write 2421 weighled code
so 811
e100 7 H me
eta? = =
= TO —
Binary to Gray code:
“fe Binary to Gray
Unweighted code 5 »
5 ccessive no. is differ by 1 bit =
3| aise called unit distance code,
= Reflective code. amd Minimum
65 8, 8, 8 =a
Gs Gi Gi Ge
write 2421 weighled code
so 811
e100 7 H me
eta? = =
= TO —
Binary to Gray code:
“fe Binary to Gray
Unweighted code 5 »
5 ccessive no. is differ by 1 bit =
3| aise called unit distance code,
= Reflective code. amd Minimum
65 8, 8, 8 =a
Gs Gi Gi Ge
sentation :
Data representation
1
TE
ea
logic=0 — +ive
sentahon “ive no. ore represented in simiby
represent -ive ro in sign magnitude
change. In 15 complement represent al
first write positive m. and: then 1s
to 4
And in 25 complement first write jie ro. and
la represent m 25 complement or toit
malent decimal we.
101) - (010) _
Data representation
1
TE
ea
logic=0 — +ive
sentahon “ive no. ore represented in simiby
represent -ive ro in sign magnitude
change. In 15 complement represent al
first write positive m. and: then 1s
to 4
And in 25 complement first write jie ro. and
la represent m 25 complement or toit
malent decimal we.
101) - (010) _
To find 5-4 ?
Se C4)
0101
1100
1100
# 0001
complement addition any ac
discarded
of bit copy mae
to extend no
complement
bit
Page - 6)
> an)
> bone)
(000 111)
1001
Hoot
11001 =>
Binary Sign mag
0000 +0
oo to
Sor
5100
GTaoi
chsenate
Se C4)
0101
1100
1100
# 0001
complement addition any ac
discarded
of bit copy mae
to extend no
complement
bit
Page - 6)
> an)
> bone)
(000 111)
1001
Hoot
11001 =>
Binary Sign mag
0000 +0
oo to
Sor
5100
GTaoi
chsenate
bit
range of Signed mag
» » US complem +7
2 Complement —& => +7
(ra)
signed mag. and 1% complement
not — Te
3 | For 25 complement +
ET) &
Using 2% complement
oon
o100
EN x :
overflow may occur when same (wo
sign vo. are added in signed
we can only represent.
A ARTE
conditon for overflow is
onde y _overfiow.
range of Signed mag
» » US complem +7
2 Complement —& => +7
(ra)
signed mag. and 1% complement
not — Te
3 | For 25 complement +
ET) &
Using 2% complement
oon
o100
EN x :
overflow may occur when same (wo
sign vo. are added in signed
we can only represent.
A ARTE
conditon for overflow is
onde y _overfiow.
L Cin - carry into ®
{into mag
corny from msg
{into mag
corny from msg
&:] Design a _synchvonas counter using OFF fo. he
| 02255536 7>0
le
ree 146 is unused
{wed tack où condition
| ei
E Bt 6—0 1
Toth table: = =
BEREZ ns =>
Qa, @ | 42,8. 80 a
000 Win Tie) =
TTS Bo 3
roel CEA y
os
Eels ta = 2
(emi o 00 a
[ono So Fr =
(BEE an
___ [2 % avoid ck out change unused
| cotes in state roble
|
1 |
| 02255536 7>0
le
ree 146 is unused
{wed tack où condition
| ei
E Bt 6—0 1
Toth table: = =
BEREZ ns =>
Qa, @ | 42,8. 80 a
000 Win Tie) =
TTS Bo 3
roel CEA y
os
Eels ta = 2
(emi o 00 a
[ono So Fr =
(BEE an
___ [2 % avoid ck out change unused
| cotes in state roble
|
1 |
[moore _§ Mealy 3
e = y
Mare Mealy
3.9% depend or
complex
s no: of stat
e = y
Mare Mealy
3.9% depend or
complex
s no: of stat
=
ner type a 2 ti Wekhted resi
palace RAR tadde
‘Gralle) _ comparator type
(9) dut slope Integrating type.
ley Digital to Anolog converter (ac) :-
Resolution / Step size
® Arotog ap voltage
9 Ms Resolution @ Error Accurac
Resolution /Step si
It change in analog voltage corresponding
increment in Ahe T/p
E salohion PER
reference voltage corresponding to logic y
no. of eits
Resolution X Decimal equivalent
b reference Voltage sv
is applied then analog voltage is
— Resolution
ner type a 2 ti Wekhted resi
palace RAR tadde
‘Gralle) _ comparator type
(9) dut slope Integrating type.
ley Digital to Anolog converter (ac) :-
Resolution / Step size
® Arotog ap voltage
9 Ms Resolution @ Error Accurac
Resolution /Step si
It change in analog voltage corresponding
increment in Ahe T/p
E salohion PER
reference voltage corresponding to logic y
no. of eits
Resolution X Decimal equivalent
b reference Voltage sv
is applied then analog voltage is
— Resolution
do Vs 3-
Full sale voltage is the mar. gp witage of ‘DAG
Resalution
Mes —
error acceptable in ADC'sor acs
tesxution or step size
Analog to 7 Digital converter :-
har@eterish
(6n+176) d8
Full sale voltage is the mar. gp witage of ‘DAG
Resalution
Mes —
error acceptable in ADC'sor acs
tesxution or step size
Analog to 7 Digital converter :-
har@eterish
(6n+176) d8
Resclution of R-2Rlodder typa DAG"
lola ==
foge 41
omy
error „sm
colibarate at 25° ic. error at asc iszero
5 +25: à Smv
DAME = 2001 "e
lola ==
foge 41
omy
error „sm
colibarate at 25° ic. error at asc iszero
5 +25: à Smv
DAME = 2001 "e
Digital to Analog en
A) Weighted Re
{ss resistance - ar) me reine |
> In_wexhted resistor DAC the accuracy ts less due
to use of different resistance.
> To evercome this we use RAR ladder use)
A) Weighted Re
{ss resistance - ar) me reine |
> In_wexhted resistor DAC the accuracy ts less due
to use of different resistance.
> To evercome this we use RAR ladder use)
todder
Inverted tadder
Nan _ inverting
* Inverting
| set _R-2R ladder
De
Wal equivalent af Binary data
265
NN
3 Bit RAR ladder (inverting)
ees
=
Inverted tadder
Nan _ inverting
* Inverting
| set _R-2R ladder
De
Wal equivalent af Binary data
265
NN
3 Bit RAR ladder (inverting)
ees
=
x decimal
hare Ground then (logicak
virtual ground and ground) the switch is ok
some potential then chorging and discharging
of switth emblen removed in previous cut.
T= Vp
hare Ground then (logicak
virtual ground and ground) the switch is ok
some potential then chorging and discharging
of switth emblen removed in previous cut.
T= Vp
ler type ADC à comparator is used in 1/pstoge
comparer p< wattage with reference vol
| provided 6 by “DAC c feedback. _
A counter isused to went no of olack pulses app
when Onolog voltage (Va) 18 greater thah pac valtog]
then -Yp is 1 ten counter count and if analog
voltage) en Yp is o and counter stops count
and itgive the comparative dyital Yp
voltage (Va) is less than reference voltage (Dac
Man. no. of clock pulses required dor“
conversion 8 27-1
Mon conversion time = Q™1) Tax
Conversion time depends on 4/p analog votlage
Also called famp type Abc =
comparer p< wattage with reference vol
| provided 6 by “DAC c feedback. _
A counter isused to went no of olack pulses app
when Onolog voltage (Va) 18 greater thah pac valtog]
then -Yp is 1 ten counter count and if analog
voltage) en Yp is o and counter stops count
and itgive the comparative dyital Yp
voltage (Va) is less than reference voltage (Dac
Man. no. of clock pulses required dor“
conversion 8 27-1
Mon conversion time = Q™1) Tax
Conversion time depends on 4/p analog votlage
Also called famp type Abc =
uralte} comparator type:
For noit comparator required
at resistor required
2°x n priodty encoder
auedl Flash abc (fastest ADO)
7 ina
brote
ie pulse is required:
Therefore dis fastect. ADC among ait
Man no of clock pulse required jor n bit_conversion
is which is Inside PIPO.
For noit comparator required
at resistor required
2°x n priodty encoder
auedl Flash abc (fastest ADO)
7 ina
brote
ie pulse is required:
Therefore dis fastect. ADC among ait
Man no of clock pulse required jor n bit_conversion
is which is Inside PIPO.
SAS, 1000
realen iS
= 0040
2001
ana
ne Re
conversion
Ring counter ls used’ to set the base
Control ext
is used to reset
Wac voy
E MO present to
‘control ext ie er
Maeve. e
En SAR Type ADS, Mal pe
A
+ Previousl
Jerversion time
sion Ame uniform for any analog
is Independent of ma] |]
realen iS
= 0040
2001
ana
ne Re
conversion
Ring counter ls used’ to set the base
Control ext
is used to reset
Wac voy
E MO present to
‘control ext ie er
Maeve. e
En SAR Type ADS, Mal pe
A
+ Previousl
Jerversion time
sion Ame uniform for any analog
is Independent of ma] |]
is mostly used in orgital ekt 10 provide inferfe
ith
microproge so"
Dbal_ slope
SS one
|
= 7
zii
> olwoys greater than va slope.
ae
F Nu ae
In Oval slope -a unter is used to count lock pulse
| convenion fly munter is. Yeset to zero
and switch s is connected fo Wy (analog voltage) ah
inteqrater ie integrating analog voltage Op of _integrade
will becom -ive witüge . due to this comparator Ypi
| 4. and counter continues es clock pulses after
ok pisas again counter valve became zem
2 =
at this ime h control cki ont sai ste
| Ve. integration upto Tz time op of
dis to this munter again amin
clock puises Toe of near eme +i
ard comparalor become 0 due to this comte
ith
microproge so"
Dbal_ slope
SS one
|
= 7
zii
> olwoys greater than va slope.
ae
F Nu ae
In Oval slope -a unter is used to count lock pulse
| convenion fly munter is. Yeset to zero
and switch s is connected fo Wy (analog voltage) ah
inteqrater ie integrating analog voltage Op of _integrade
will becom -ive witüge . due to this comparator Ypi
| 4. and counter continues es clock pulses after
ok pisas again counter valve became zem
2 =
at this ime h control cki ont sai ste
| Ve. integration upto Tz time op of
dis to this munter again amin
clock puises Toe of near eme +i
ard comparalor become 0 due to this comte
count when counter stops
me
Sims & the most acwrake noc among
3 AL ripple and noise is seperated or c
by capacitor. (therefore this have more |
Aue to integraler)
mar. no. of clock pulse
3 ie dowest among ol.
Application +
E moi; used In: digital “voltmeter.
Cioo« pulse :—
=}; counter type am
Ceres
me
Sims & the most acwrake noc among
3 AL ripple and noise is seperated or c
by capacitor. (therefore this have more |
Aue to integraler)
mar. no. of clock pulse
3 ie dowest among ol.
Application +
E moi; used In: digital “voltmeter.
Cioo« pulse :—
=}; counter type am
Ceres
(Diade AND Gate)
C@iod OF Gate)
use transistor .
C@iod OF Gate)
use transistor .
=
E
[were gate Weis 1. Um ern) eines
current source. E =
3 | when logic gate pis o Cm it will act
coment Sink
‘orfyons
MES
and saturalisn region wansistor will act as
Je Te
E 86
HER
28
E
[were gate Weis 1. Um ern) eines
current source. E =
3 | when logic gate pis o Cm it will act
coment Sink
‘orfyons
MES
and saturalisn region wansistor will act as
Je Te
E 86
HER
28
Graracteris tr family
| Poryation delay = (py)
His measured in nsec
Tor + brune
ha tr
tere tein
ocr -0N On OFF
> forogation delay is always measured from 507. \loe
the diag.
to OFF time is more compare to orr
time doe to saturation or storatge time
Rawer_dissipation :— »
pation by each
| Poryation delay = (py)
His measured in nsec
Tor + brune
ha tr
tere tein
ocr -0N On OFF
> forogation delay is always measured from 507. \loe
the diag.
to OFF time is more compare to orr
time doe to saturation or storatge time
Rawer_dissipation :— »
pation by each
Fan avt
It f
blo
oqi
man, no of
gate
logic gate
fanout,,
fanout ,
Maa. {an cot
RIRE ROO LA TE
fanout, 10
(COS
man. fan out
TTL have maa. fonour
Noise Margin
It is the
the logic family
mon. noise voltage
which will
that ¢
Lima, Lot
nd dan out
that can be
nat_affect
It f
blo
oqi
man, no of
gate
logic gate
fanout,,
fanout ,
Maa. {an cot
RIRE ROO LA TE
fanout, 10
(COS
man. fan out
TTL have maa. fonour
Noise Margin
It is the
the logic family
mon. noise voltage
which will
that ¢
Lima, Lot
nd dan out
that can be
nat_affect
Basic gate - nor gate
ted sons
as 10 mw
NM = 02V
Fanout = 3
à
=
>
> Fom = so0PJ
2
2
2
wired AND used
Disadvantage :-
1 lower speed of operation
2. low Noise margin
3. fowest Jan out ~
ted sons
as 10 mw
NM = 02V
Fanout = 3
à
=
>
> Fom = so0PJ
2
2
2
wired AND used
Disadvantage :-
1 lower speed of operation
2. low Noise margin
3. fowest Jan out ~
|
een open Se
e tog 4ONsec
el
Ce
In ven logic . A tr switch
the Tr having lower Vpesar then fist
alow other Tr to on. this pheromeron
Hogging
Integrofed Injection logie (ru) ==
resultar
|
|
Ha ingeching the current into Base
covers less space _
FL hove high density.
to Nor gate
een open Se
e tog 4ONsec
el
Ce
In ven logic . A tr switch
the Tr having lower Vpesar then fist
alow other Tr to on. this pheromeron
Hogging
Integrofed Injection logie (ru) ==
resultar
|
|
Ha ingeching the current into Base
covers less space _
FL hove high density.
to Nor gate
"no problem of
"PI OT PS
al logic omily.
ssi 1-12
mst = 699 | pp op gates
isi 100-000 | in this integration
| vist > 1000 .
pNP and NPM
Tm Ti topic, due to integration of
tess area hence density are mare
It is mostly used in MS] and tsi
tr. it Occupies
in PEL bgic
Logic family
Also called MTL (Merged logic - fomily) due to
integration of transistor
"PI OT PS
al logic omily.
ssi 1-12
mst = 699 | pp op gates
isi 100-000 | in this integration
| vist > 1000 .
pNP and NPM
Tm Ti topic, due to integration of
tess area hence density are mare
It is mostly used in MS] and tsi
tr. it Occupies
in PEL bgic
Logic family
Also called MTL (Merged logic - fomily) due to
integration of transistor
DTL (Dade Transistor logic) family :
AND Gate followed by wor gate
e
0k vesister used only for digchargi
“ce. The capacitance which is discharge. is Transition cap
The cut to called Basie ore gate
In this any one of the Ar
HP are low
is bw. o
D, ane 01 Dg will become forward bias
where æ Dand ©, will become reverse bias due to +
Tr Ti isorr and Yp is 1 ul = =
‘Da and Dg become
D, Will became forward bias —
when all the "p's are high then
is nano gate
240 PT
SY
Fanout = 3
TE prowdes wired AND operahon.
| To increase for out =
we intraduce Tr in
| place of Diode.
SKA resistor used z
to tower the 1, sx]
current:
ec
classmate, called srancano fit IGE)
AND Gate followed by wor gate
e
0k vesister used only for digchargi
“ce. The capacitance which is discharge. is Transition cap
The cut to called Basie ore gate
In this any one of the Ar
HP are low
is bw. o
D, ane 01 Dg will become forward bias
where æ Dand ©, will become reverse bias due to +
Tr Ti isorr and Yp is 1 ul = =
‘Da and Dg become
D, Will became forward bias —
when all the "p's are high then
is nano gate
240 PT
SY
Fanout = 3
TE prowdes wired AND operahon.
| To increase for out =
we intraduce Tr in
| place of Diode.
SKA resistor used z
to tower the 1, sx]
current:
ec
classmate, called srancano fit IGE)
CHTL) family:
ye EN
th Threshold Lo
in place of | DIT
is used
Diode
(Highest noise margin)
la since
in DTL
all diode and Transistor
is —ive
‘ere coejficient CS - e- 25 VV C
EN
Higher voltage Swing —
oe
3 td =
Bigg = SS mw
Fom= 4950 PJ x 5000 PT _
Fanout = 8
Basic gate - NAND gate
Noise margin = 4v-SY
ye EN
th Threshold Lo
in place of | DIT
is used
Diode
(Highest noise margin)
la since
in DTL
all diode and Transistor
is —ive
‘ere coejficient CS - e- 25 VV C
EN
Higher voltage Swing —
oe
3 td =
Bigg = SS mw
Fom= 4950 PJ x 5000 PT _
Fanout = 8
Basic gate - NAND gate
Noise margin = 4v-SY
Tru
The cxt Shown
[basically have
Phase
(Transistor
“Multiemitter
Multiemitter
stor logic) jomil.
Fransistor
T
A
E
in 49
three stage
ze stage
‘splitter
“active pollup. ofp stage -_
aj Tr Te
Tr (Ti) connek 40 Vee.
| Operation «-
> Any
one of HP
low. or al pS are low- than E8
is
re. eE). Om collector tase (Je 8!
junchon
is_R6
Te
is in achve mode. due to this Tr. Ta
and 5
are
Orc. Cin œraf region) where as Ty
in is SAT
Hence op ys 1.
when au
the es are high then we (ee sect)
FES
ce A CEA
mode ot.
— operation
a Reverse active. —
aserto
«TD
The cxt Shown
[basically have
Phase
(Transistor
“Multiemitter
Multiemitter
stor logic) jomil.
Fransistor
T
A
E
in 49
three stage
ze stage
‘splitter
“active pollup. ofp stage -_
aj Tr Te
Tr (Ti) connek 40 Vee.
| Operation «-
> Any
one of HP
low. or al pS are low- than E8
is
re. eE). Om collector tase (Je 8!
junchon
is_R6
Te
is in achve mode. due to this Tr. Ta
and 5
are
Orc. Cin œraf region) where as Ty
in is SAT
Hence op ys 1.
when au
the es are high then we (ee sect)
FES
ce A CEA
mode ot.
— operation
a Reverse active. —
aserto
«TD
and 13 are Te
Hence an
voltage af whiok Tr- takes logie
aus iii dei
adi
ted ons
Bes = tOmo
FOM = 100 PI
Fanout = _10
nen ouv
ibs asia
Diode Dis used to cutoff Ty Tu when Ta
on
Advantage of Totem pole =
lower power: dissipation
dof operation
bisaduontage of Totem pole <=
is not used in wired logie
ET ogi al
Hence an
voltage af whiok Tr- takes logie
aus iii dei
adi
ted ons
Bes = tOmo
FOM = 100 PI
Fanout = _10
nen ouv
ibs asia
Diode Dis used to cutoff Ty Tu when Ta
on
Advantage of Totem pole =
lower power: dissipation
dof operation
bisaduontage of Totem pole <=
is not used in wired logie
ET ogi al
ERE
| 10 vesiator used in collector in O/P state
or noise generation, $0 in p> high troy
operation
In TTL if any yp is open ‘it behaves ab logic
Clamping diodes ‘are connected in tp stage
tansialor doing high frequency ‘of operation
y
fa
Clamping D.removes ringing Of high rquency Operation
There are different type
©, standard Tr
&) Nigh speed
©) low power
(A) sohotthy TTL
| 10 vesiator used in collector in O/P state
or noise generation, $0 in p> high troy
operation
In TTL if any yp is open ‘it behaves ab logic
Clamping diodes ‘are connected in tp stage
tansialor doing high frequency ‘of operation
y
fa
Clamping D.removes ringing Of high rquency Operation
There are different type
©, standard Tr
&) Nigh speed
©) low power
(A) sohotthy TTL
1
|
|
1
High speed TTL: ä
In standard TTL logic
valve reduce then tat reduces and
High speeol “logic jomily
oe speed pie TL: E E
_In TTL log family if Resistor volve increased
then power dissipation “reduced and resuitant is
mene a2 OP power rt
Schottky diode B u
If sehottky diode is used
Bose region then it will remove Storage
satoration delay. the fomily “Known as Schottky diode
are
|
|
1
High speed TTL: ä
In standard TTL logic
valve reduce then tat reduces and
High speeol “logic jomily
oe speed pie TL: E E
_In TTL log family if Resistor volve increased
then power dissipation “reduced and resuitant is
mene a2 OP power rt
Schottky diode B u
If sehottky diode is used
Bose region then it will remove Storage
satoration delay. the fomily “Known as Schottky diode
are
(Emitter coupled logic family);
It is never go in saturation region
Work only in cutofí and Active region
It ie jostest logic family due to work ins Active and
cher region, (Beesuse it ig man satmaled) t
conan contains tuo stage
Differential ame” wp stage
Emitter follower 0/6519) a
med oa
Ect logic fomily LA 2) gate 0
Due to use of cc Stage in the op fanout is high
Negative spkes donot Offect the transistors dueto -ie
pote Spe
uses —ive power supply. cue to. this any spike
negativa wttage nor offect operation
It is never go in saturation region
Work only in cutofí and Active region
It ie jostest logic family due to work ins Active and
cher region, (Beesuse it ig man satmaled) t
conan contains tuo stage
Differential ame” wp stage
Emitter follower 0/6519) a
med oa
Ect logic fomily LA 2) gate 0
Due to use of cc Stage in the op fanout is high
Negative spkes donot Offect the transistors dueto -ie
pote Spe
uses —ive power supply. cue to. this any spike
negativa wttage nor offect operation
ont COIL
togic.0 N { Fis égic 1—modte—onty
tage 1 assy
vottage—suppty is negative.
provide. wired - AND: logiG
togic.0 N { Fis égic 1—modte—onty
tage 1 assy
vottage—suppty is negative.
provide. wired - AND: logiG
channel Mos
logie ©"
Logic L
Variable Yasietor hence In mas
we use _ MOSFET
Since rer is voltage
civeuit in place aj reg» vesistor
NMos NOT Gate:
NMOS NANO Gate
y Yoo
logie ©"
Logic L
Variable Yasietor hence In mas
we use _ MOSFET
Since rer is voltage
civeuit in place aj reg» vesistor
NMos NOT Gate:
NMOS NANO Gate
y Yoo
she >
power "dissipation
= 70 nsec
rom - O7 97
Fonout = SO
During loc © oF
Dyromie PD a
During tonsitian from _
Pros
power "dissipation
= 70 nsec
rom - O7 97
Fonout = SO
During loc © oF
Dyromie PD a
During tonsitian from _
Pros
contol AY
o * High “impedence High tmpad]
= gh impad.
ü
1
o A
Symbol of Transmission qate =
o * High “impedence High tmpad]
= gh impad.
ü
1
o A
Symbol of Transmission qate =
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