Digital Fundamentals (202040303) MODULE 1 Introduction
Module 1 Binary Systems and Logic Circuits, The Advantage of Binary, Number Systems, The Use of Binary in Digital Systems, Logic Gates, Logic Families: Transistor-Transistor Logic(TTL), Emitter-Coupled Logic(ECL), MOSFET Logic, TTL Gates. PROF. SUNAYANA DOMADIA DIGITAL FUNDAMENTALS (202040303) ‹#›
Introduction PROF. SUNAYANA DOMADIA DIGITAL FUNDAMENTALS (3130704) ‹#› Digital Electronics is that branch of electronics which deals with the digital signals to perform various tasks and meet various requirements Digital Electronics is very important in today's life because if digital circuits compared to analog circuits are that signals represented digitally can be transmitted without degradation due to noise. It is based upon the digital design methodologies and consists of digital circuits, IC’s and logic gates It uses only binary digits.
PROF. SUNAYANA DOMADIA DIGITAL FUNDAMENTALS (3130704) ‹#› Need for Digital Electronics Most analog systems were less accurate and were slow in computation and performance Digital system have the ability to work faster than analog equivalents It was much economical than analog methodologies as the performance was faster.
Applications PROF. SUNAYANA DOMADIA DIGITAL FUNDAMENTALS (3130704) ‹#› Almost all devices we use on a daily basis make use of digital electronics in some capacity. Digital electronics simply refers to any kind of circuit that uses digital signals rather than analogue. It is constructed using circuits calls logic gates, each of which performs a different function. The circuit will make use of different components that are all standard, but that are put together in different combinations to achieve the desired result. It circuit will also include resistors and diodes, which are used to control current and voltage.
Applications PROF. SUNAYANA DOMADIA DIGITAL FUNDAMENTALS (3130704) ‹#› Many of our household items make use of digital electronics. This could include laptops, televisions, remote controls and other entertainment systems, to kitchen appliances like dishwashers and washing machines. Computers are one of the most complex examples and will make use of numerous, complex circuits. There may be millions of pathways within the circuit, depending on how complex the computer and its functions need to be. Use in Machine learning and AI for mathematical calculations
Block diagram of Computer PROF. SUNAYANA DOMADIA DIGITAL FUNDAMENTALS (3130704) ‹#›
PROF. SUNAYANA DOMADIA DIGITAL FUNDAMENTALS (3130704) ‹#› Logic Gates Most basic logical unit of the digital system is gate circuit Types of gate circuits are as follows AND Gate OR Gate NOT Gate (Inverter) NOR Gate NAND Gate XOR Gate XNOR Gate
PROF. SUNAYANA DOMADIA DIGITAL FUNDAMENTALS (3130704) ‹#› AND Gate AND Gate has an output which is normally at logic level “0” and only goes “HIGH” to a logic level “1” when ALL of its inputs are at logic level “1” A B C Logic Notation A B C 1 1 1 1 1 Truth Table 2-input AND Gate
PROF. SUNAYANA DOMADIA DIGITAL FUNDAMENTALS (3130704) ‹#› OR Gate OR Gate or Inclusive-OR gate has an output which is normally at logic level “0” and only goes “HIGH” to a logic level “1” when one or more of its inputs are at logic level “1”. A B C Logic Notation A B C 1 1 1 1 1 1 1 Truth Table 2-input OR Gate
PROF. SUNAYANA DOMADIA DIGITAL FUNDAMENTALS (3130704) ‹#› NOT (Inverter) Gate NOT gate has an output which is always opposite to input level. A C Logic Notation A C 1 1 Truth Table Inverter Gate
PROF. SUNAYANA DOMADIA DIGITAL FUNDAMENTALS (3130704) ‹#› NOR Gate NOR Gate is an OR gate followed by an inverter. A B C Logic Notation A B C 1 1 1 1 1 Truth Table 2-input NOR Gate
PROF. SUNAYANA DOMADIA DIGITAL FUNDAMENTALS (3130704) ‹#› NAND Gate NAND Gate is an AND gate followed by an inverter. A B C Logic Notation A B C 1 1 1 1 1 1 1 Truth Table 2-input NAND Gate
PROF. SUNAYANA DOMADIA DIGITAL FUNDAMENTALS (3130704) ‹#› Exclusive-OR (X-OR) Gate X-OR gate that has 1 state when one and only one of its two inputs assumes a logic 1 state and has 0 state when all of its input are same. Also known as anti-coincidence gate or inequality detector. A B C Logic Notation A B C 1 1 1 1 1 1 Truth Table 2-input XOR Gate
PROF. SUNAYANA DOMADIA DIGITAL FUNDAMENTALS (3130704) ‹#› Exclusive-NOR (X-NOR) Gate X-NOR gate that has 1 state when all of its input are same and has 0 state when one of its input has 0 state and other input is 1 state. Also known as equality detector. A B C Logic Notation A B C 1 1 1 1 1 1 Truth Table 2-input XNOR Gate
PROF. SUNAYANA DOMADIA DIGITAL FUNDAMENTALS (3130704) ‹#› NAND as Universal Gate NOT using NAND A A’ A B (AB)’ ((AB)’)’ = AB AND using NAND A B A’ (A’B’)’ = (A+B) OR using NAND B’
PROF. SUNAYANA DOMADIA DIGITAL FUNDAMENTALS (3130704) ‹#› NOR as Universal Gate NOT using NOR A A’ A B (A+B)’ ((A+B)’)’ = A+B OR using NOR A B A’ (A’+B’)’ = AB AND using NOR B’
PROF. SUNAYANA DOMADIA DIGITAL FUNDAMENTALS (3130704) ‹#› Number Systems
PROF. SUNAYANA DOMADIA DIGITAL FUNDAMENTALS (3130704) ‹#› Conversion among Bases Possibilities Example Hexadecimal Decimal Octal Binary 25 10 = 11001 2 = 31 8 = 19 16 Base
PROF. SUNAYANA DOMADIA DIGITAL FUNDAMENTALS (3130704) ‹#› Decimal to Binary Technique Divide by two, keep track of the remainder First remainder is bit 0 (LSB, least-significant bit) Second remainder is bit 1 and so on Decimal Binary
Binary to Decimal Technique Multiply each bit by 2 n , where n is the “weight” of the bit The weight is the position of the bit, starting from 0 on the right Add the results Binary Decimal
PROF. SUNAYANA DOMADIA DIGITAL FUNDAMENTALS (3130704) ‹#› Example (Binary to Decimal) 1 0 1 0 1 1 1 x 2 1 x 2 1 0 x 2 2 1 x 2 3 0 x 2 4 1 x 2 5 + + + + + 1 2 101011 2 = 32 + + + + + 43 10 43 10 8
PROF. SUNAYANA DOMADIA DIGITAL FUNDAMENTALS (3130704) ‹#› Example (Binary to Decimal) 1 1 . 1 1 1 x 2 1 x 2 1 + 1 2 11.11 2 = + 3.75 10 3.75 10 1 x 2 -2 1 x 2 -1 + 0.25 0.5 + + +
PROF. SUNAYANA DOMADIA DIGITAL FUNDAMENTALS (3130704) ‹#› Octal to Decimal Technique Multiply each bit by 8 n , where n is the “weight” of the bit The weight is the position of the bit, starting from 0 on the right Add the results Octal Decimal
PROF. SUNAYANA DOMADIA DIGITAL FUNDAMENTALS (3130704) ‹#› Example (Octal to Decimal) 7 2 4 4 x 8 2 x 8 1 7 x 8 2 + + 724 8 = 468 10 468 10 4 16 448 + +
PROF. SUNAYANA DOMADIA DIGITAL FUNDAMENTALS (3130704) ‹#› Example (Octal to Decimal) 4 3 . 2 5 3 x 8 4 x 8 1 + 3 32 43.25 8 = + 35.3281 10 35.3281 10 5 x 8 -2 2 x 8 -1 + 0.0781 0.25 + + +
PROF. SUNAYANA DOMADIA DIGITAL FUNDAMENTALS (3130704) ‹#› Decimal to Hexa-Decimal Technique Divide by 16 Keep track of the remainder Decimal Hexa-Decimal
PROF. SUNAYANA DOMADIA DIGITAL FUNDAMENTALS (3130704) ‹#› Example (Decimal to HexaDecimal) 1234 10 = ? 16 16 1234 2 1234 10 = 4D2 16 16 77 13=D 16 4 4
PROF. SUNAYANA DOMADIA DIGITAL FUNDAMENTALS (3130704) ‹#› Example (Decimal to HexaDecimal) 1234 10 = ? 16 16 1234 2 1234 10 = 4D2 16 16 77 13=D 16 4 4
PROF. SUNAYANA DOMADIA DIGITAL FUNDAMENTALS (3130704) ‹#› Hexa-Decimal to Decimal Technique Multiply each bit by 16 n , where n is the “weight” of the bit The weight is the position of the bit, starting from 0 on the right Add the results Hexa-Decimal Decimal
PROF. SUNAYANA DOMADIA DIGITAL FUNDAMENTALS (3130704) ‹#› Example (HexaDecimal to Decimal) A B C C x16 B x16 1 A x16 2 + + ABC 16 = 2748 10 2748 10 12 x16 11 x16 1 10 x 16 2 + + 12 176 2560 + +
PROF. SUNAYANA DOMADIA DIGITAL FUNDAMENTALS (3130704) ‹#› Octal to Binary Technique Convert each octal digit to a 3-bit equivalent binary representation Octal Binary
PROF. SUNAYANA DOMADIA DIGITAL FUNDAMENTALS (3130704) ‹#› Hexa-Decimal to Binary Technique Convert each hexadecimal digit to a 4-bit equivalent binary representation Hexa-Decimal Binary
PROF. SUNAYANA DOMADIA DIGITAL FUNDAMENTALS (3130704) ‹#› Example (Octal to Binary) 705 8 = ? 2 7 0 5 101 000 111 705 8 = 111000101 2
PROF. SUNAYANA DOMADIA DIGITAL FUNDAMENTALS (3130704) ‹#› Binary to Octal Technique Group bits in threes, starting on right Convert to octal digits Binary Octal
PROF. SUNAYANA DOMADIA DIGITAL FUNDAMENTALS (3130704) ‹#› Example (Binary to Octal) 1011010111 2 = ? 8 1 011 001 1011010111 2 = 1327 8 111 010 3 2 7
PROF. SUNAYANA DOMADIA DIGITAL FUNDAMENTALS (3130704) ‹#› Hexa-Decimal to Binary Hexa-Decimal Binary Hexa-Decimal Binary 0000 8 1000 1 0001 9 1001 2 0010 A 1010 3 0011 B 1011 4 0100 C 1100 5 0101 D 1101 6 0110 E 1110 7 0111 F 1111
PROF. SUNAYANA DOMADIA DIGITAL FUNDAMENTALS (3130704) ‹#› Example (Hexa-Decimal to Binary) 10AF 16 = ? 2 1 0 A F 1111 1010 0000 10AF 16 = 1000010101111 2 0001
PROF. SUNAYANA DOMADIA DIGITAL FUNDAMENTALS (3130704) ‹#› Binary to Hexa-Decimal Technique Group bits in fours, starting on right Convert to hexadecimal digits Binary Hexa-Decimal
PROF. SUNAYANA DOMADIA DIGITAL FUNDAMENTALS (3130704) ‹#› Example (Binary to Hexa-Decimal) 1011010111 2 = ? 16 0010 1011010111 2 = 2D7 16 0111 1101 2 D 7
PROF. SUNAYANA DOMADIA DIGITAL FUNDAMENTALS (3130704) ‹#› Octal to Hexa-Decimal Technique Convert Octal to Binary Regroup bits in fours from right Convert Binary to Hexa-Decimal Octal Hexa-Decimal
PROF. SUNAYANA DOMADIA DIGITAL FUNDAMENTALS (3130704) ‹#› Example (Octal to Hexa-Decimal) 1076 8 = ? 16 1 0 7 6 110 111 000 1076 8 = 23E 16 001 1110 0011 0010 E 3 2
PROF. SUNAYANA DOMADIA DIGITAL FUNDAMENTALS (3130704) ‹#› Hexa-Decimal to Octal Technique Convert Hexa-Decimal to Binary Regroup bits in three from right Convert Binary to Octal Hexa-Decimal Octal
PROF. SUNAYANA DOMADIA DIGITAL FUNDAMENTALS (3130704) ‹#› Example (Hexa-Decimal to Octal) 1F0C 16 = ? 8 1 F 0 C 1100 0000 1111 1F0C 16 = 17414 8 0001 100 001 100 4 1 4 111 7 001 1 000
PROF. SUNAYANA DOMADIA DIGITAL FUNDAMENTALS (3130704) ‹#› Signed Binary Numbers Two ways of representing signed numbers: 1) Sign-magnitude form, 2) Complement form. Most of computers use complement form for negative number notation. 1’s complement and 2’s complement are two different methods in this type.
PROF. SUNAYANA DOMADIA DIGITAL FUNDAMENTALS (3130704) ‹#› 1’s Complement 1 1 1 1 1 1 1 1 - (1’s complement of 1101) 1 1 1 . 1 1 . 1 . - (1’s complement of 101.01) 1 1 1 1 1’s complement of a binary number is obtained by subtracting each digit of that binary number from 1. Example
PROF. SUNAYANA DOMADIA DIGITAL FUNDAMENTALS (3130704) ‹#› 2’s Complement 2’s complement of a binary number is obtained by adding 1 to its 1’s complement. 1 1 1 1 1 1 1 1 - (2’s complement of 1100) 1 . - (2’s complement of 101.01) 1 1 1 . 1 1 1 1 . 1 1 1 1 1 + + 1 1 1 . Example
PROF. SUNAYANA DOMADIA DIGITAL FUNDAMENTALS (3130704) ‹#› Representation of negative number in 2’s complement form Express -65.5 in 12 bit 2’s complement form. 2 65 1 2 32 2 16 2 8 2 4 2 2 2 1 1 0.5 x 2 = 1.0 65.5 10 = 01000001.1000 2 So, result in 12-bit binary is as follows: For negative number, we have to convert this into 2’s complement form -65.5 10 = 10111110.1000 2
PROF. SUNAYANA DOMADIA DIGITAL FUNDAMENTALS (3130704) ‹#› Exercise Express -45 in 8-bit 2’s complement form. Express -73.75 in 12 bit 2’s complement form.
PROF. SUNAYANA DOMADIA DIGITAL FUNDAMENTALS (3130704) ‹#› 9’s Complement 9’s complement of a decimal number is obtained by subtracting each digit of that decimal number from 9. 9 9 9 9 3 4 6 5 6 5 3 4 - (9’s complement of 3465) 9 9 9 . 7 8 2 . 2 1 7 . - (9’s complement of 782.54) 9 9 5 4 4 5 Example
PROF. SUNAYANA DOMADIA DIGITAL FUNDAMENTALS (3130704) ‹#› 10’s Complement 10’s complement of a decimal number is obtained by adding 1 to its 9’s complement. 9 9 9 9 3 4 6 5 6 5 3 4 - (10’s complement of 3465) 2 1 7 . - (10’s complement of 782.54) 9 9 9 . 9 9 7 8 2 . 5 4 4 5 1 6 5 3 5 1 + + 2 1 7 4 6 . Example
PROF. SUNAYANA DOMADIA DIGITAL FUNDAMENTALS (3130704) ‹#› Subtraction using 9’s complement Obtain 9’s complement of subtrahend Add the result to minuend and call it intermediate result If carry is generated then answer is positive and add the carry to Least Significant Digit (LSD) If there is no carry then answer is negative and take 9’s complement of intermediate result and place negative sign to the result.
Example 7 4 5 . 4 3 6 . - 8 1 6 2 2) 436.62 - 745.81 2 5 4 . + 1 8 6 9 . 8 3 9 . 1 9 3 9 . 1 9 - 4 3 6 . 6 2 - 9’s complement 9’s complement As carry is not generated, so take 9’s complement of the intermediate result and add ‘ – ‘ sign to the result
PROF. SUNAYANA DOMADIA DIGITAL FUNDAMENTALS (3130704) ‹#› PROF. SUNAYANA DOMADIA DIGITAL FUNDAMENTALS (3130704) ‹#› Subtraction using 10’s complement Obtain 10’s complement of subtrahend Add the result to minuend If carry is generated then ignore it and result itself is answer If there is no carry then answer is negative and take 10’s complement of result and place negative sign to the result.
PROF. SUNAYANA DOMADIA DIGITAL FUNDAMENTALS (3130704) ‹#› Example 7 4 5 . 4 3 6 . - 8 1 6 2 2) 436.62 - 745.81 2 5 4 . + 1 9 6 9 . 8 1 3 9 . 1 9 3 9 . 1 9 - 4 3 6 . 6 2 - 10’s complement 10’s complement As carry is not generated, so take 10’s complement of the intermediate result and add ‘ – ‘ sign to the result
PROF. SUNAYANA DOMADIA DIGITAL FUNDAMENTALS (3130704) ‹#› Subtraction using 1’s Complement Obtain 1’s complement of subtrahend Add the result to minuend and call it intermediate result If carry is generated then answer is positive and add the carry to Least Significant Digit (LSD) If there is no carry then answer is negative and take 1’s complement of intermediate result and place negative sign to the result.
PROF. SUNAYANA DOMADIA DIGITAL FUNDAMENTALS (3130704) ‹#›
PROF. SUNAYANA DOMADIA DIGITAL FUNDAMENTALS (3130704) ‹#› Subtraction using 2’s Complement Obtain 2’s complement of subtrahend Add the result to minuend If carry is generated then ignore it and result itself is answer If there is no carry then answer is negative and take 2’s complement of result and place negative sign to the result.
PROF. SUNAYANA DOMADIA DIGITAL FUNDAMENTALS (3130704) ‹#›
PROF. SUNAYANA DOMADIA DIGITAL FUNDAMENTALS (3130704) ‹#› Binary Codes
PROF. SUNAYANA DOMADIA DIGITAL FUNDAMENTALS (3130704) ‹#› Any discrete element of information that is distinct among a group of quantities can be represented with a binary code ( i . e . , a pattern of O ' s and l ' s ) .
PROF. SUNAYANA DOMADIA DIGITAL FUNDAMENTALS (3130704) ‹#› 8421 BCD Code (Natural BCD Code) Each decimal digit, 0 through 9, is coded by 4-bit binary number 8, 4, 2 and 1 weights are attached to each bit BCD code is weighted code 1010, 1011, 1100, 1101, 1110 and 1111 are illegal codes Less efficient than pure binary Arithmetic operations are more complex than in pure binary
PROF. SUNAYANA DOMADIA DIGITAL FUNDAMENTALS (3130704) ‹#› Excess Three (XS-3) Code Excess Three Code = 8421 BCD + 0011(3) XS-3 code is non-weighted BCD code Also known as self complementing code 0000, 0001, 0010, 1101, 1110 and 1111 are illegal codes
PROF. SUNAYANA DOMADIA DIGITAL FUNDAMENTALS (3130704) ‹#› Gray Code Only one bit changes between each pair of successive code words (Unit distance code). Gray code is a reflected code. The reflected binary code (RBC), also known just as reflected binary (RB) or Gray code after Frank gray is an ordering of the binary numeral system such that two successive values differ in only one bit (binary digit).
PROF. SUNAYANA DOMADIA DIGITAL FUNDAMENTALS (3130704) ‹#› Binary to Gray Conversion Conversion of n-bit Binary number (B) to Gray Code (G) is as follows: Example: Convert (1001) 2 to Gray Code. 1 Binary Gray 1 1 1 1
PROF. SUNAYANA DOMADIA DIGITAL FUNDAMENTALS (3130704) ‹#› Gray to Binary Conversion Conversion of n-bit Gray Code (G) to Binary Number (B) is as follows: Example: Convert Gray code 1101 to Binary. 1 Gray Binary 1 1 1 1
PROF. SUNAYANA DOMADIA DIGITAL FUNDAMENTALS (3130704) ‹#› Error-Detecting Codes Noise can alter or distort the data in transmission. The 1s may get changed to 0s and 0s to 1s. Because digital systems must be accurate to the digit, errors can pose a serious problem. Single bit error should be detect & correct by different schemes. Parity, Check Sums and Block Parity are the examples of error detecting code.
PROF. SUNAYANA DOMADIA DIGITAL FUNDAMENTALS (3130704) ‹#› Parity Parity bit is the simplest technique. There are two types of parity – Odd parity and Even parity. For odd parity, the parity is set to a 0 or a 1 at the transmitter such that the total number of 1 bits in the word including the parity bit is an odd number. For even parity, the parity is set to a 0 or a 1 at the transmitter such that the total number of 1 bits in the word including the parity bit is an even number. For example, 0110 binary number has “1” as Odd parity and “0” as even parity.
PROF. SUNAYANA DOMADIA DIGITAL FUNDAMENTALS (3130704) ‹#›
Lecture 1 Logic families 1
INTRODUCTION 2 Logic Family: It is a group of compatible ICs with the same logic levels and the supply voltages for performing various logic functions circuit They have been fabricated using a specific configuration. They are the building block of logic circuits. 2
INTRODUCTION 3 ICs are integrated using following integration techniques SSI (upto 12) MSI (12 to 99) LSI (100 to 9999) VLSI (10,000 to 99999) ULSI (> 100,000) 3
Types of logic families 4 Logic Families Bipolar Logic Family RTL Saturated DCTL IIL DTL HTL TTL Non- Saturated Schottkey TTL ECL Unipolar Logic Family MOSFET 4
UNIPOLAR LOGIC FAMILIES 6 MOS devices are unipolar devices and only MOSFETs are employed in MOS logic circuits. These families are: PMOS (p-channel MOSFETs) NMOS (n-channel MOSFETs) CMOS (Both p- and n- channel MOSFETs are fabricated on same silicon chip) 6
1) DC supply voltage 8 CMOS and TTL are available in different supply voltage categories In each IC, Vcc pin is connected to positive supply and GND pin is connected to ground of supply. 8
Basic Characteristics of ICs 7 DC supply Voltage Logic levels 7
2) LOGIC LEVELS 9 Four different kind of Logic level specifications are defined: V IL , V IH , V OL ,V OH V IL , V IH : These are the input logic levels (Low & High) V OL , V OH : These are the output logic levels (Low & High) 9
3) Noise Immunity 10 Noise is unwanted voltage that is induced in electrical circuits and can cause threat to proper operation of circuit. Noise immunity is the ability to tolerate a certain amount of unwanted voltage fluctuations on its inputs without changing outputs 10
3) Noise Immunity 11 For example, If noise voltage causes the input of 5V CMOS gate to drop below 3.5V in HIGH state, then input lies in unallowed band and the operation becomes unpredictable 11
4) Noise Margin 12 A measure of circuits’ noise immunity is called Noise margin. It is expressed in volts. Two Noise margins are specified for logic circuits, High level Noise margin (V NH ) and Low level Noise margin (V NL ), expressed as: 12 It is the maximum noise voltage added to an input signal of a digital circuit that does not cause an undesirable change in the circuit output. It is expressed in volts.
13 13
5) Power Dissipation 14 This is the amount of power dissipated in an IC. It is Determined by the current Icc, that it draws from the Vcc supply, and is given by , Pd =Vcc X Icc. 14 Power dissipation is measure of power consumed by the gate when fully driven by all its inputs.
6) Propagation Delay 15 15 Propagation delay is the average transition delay time for the signal to propagate from input to output when the signals change in value. It is expressed in ns.
7) Fan out 16 The maximum number of inputs of the same series of an IC that can be connected to a gates’ output and still maintains the specified output voltage level. 16
Fan in Fan in is the number of inputs connected to the gate without any degradation in the voltage level. for example a two i/p gate will have fan in equal to 2. 17 17
Operating temperature Operating temperature range- Industrial application is 0 o C to 70 o C Military application is -55 o C to 125 o C 18 18 All the gates or semiconductor devices are temperature sensitive in nature. The temperature in which the performance of the IC is effective is called as operating temperature. Operating temperature of the IC vary from 00 C to 700 c.
Figure of Merit 19 19
PROF. SUNAYANA DOMADIA DIGITAL FUNDAMENTALS (3130704) ‹#› Transistor Transistor Logic (TTL) Dependence on transistors alone to perform basic logic operations. Most popular logic family. Most widely useful bipolar digital IC family. The TTL uses transistors operating in saturated mode. It is the fastest of the saturated logic families. Good speed, low manufacturing cost, wide range of circuits, and the availability in SSI and MSI are its merits.