Digital Integrated Circuited Applications

SSI Latches and flip flops
Ring Counter
Johnson Counter
Design of Modulus N Synchronous Counters
Shift Registers
Universal Shift Registers
Design considerations of the above sequential logic circuits with relevant Digital ICs, modeling of above ICs using VHDL

1. Digital IC Applications Mr. Y.Srinivas Assistant Professor Department of Electronics and Communication Engineering VISHNU INSTITUTE OF TECHNOLOGY (A) Vishnupur, Bhimavaram

2. UNIT-5 Sequential Logic Design SSI Latches and flip flops Ring Counter Johnson Counter Design of Modulus N Synchronous Counters Shift Registers Universal Shift Registers Design considerations of the above sequential logic circuits with relevant Digital ICs, modeling of above ICs using VHDL

3. SSI Latches and flip flops Several different types of discrete latches and flip-flops are available as SSI parts. These devices are sometimes used in the design of state machines. SSI latches and flip-flops have been eliminated to a large extent in modern designs as their functions are embedded in PLDs and FPGAs. Nevertheless, a handful of these discrete building blocks still appear in many digital systems, so it’s important to be familiar with them. Figure shows the pinouts for several SSI sequential devices. The only latch in the figure is the 74x375, which contains four D latches, similar in function to the “generic” D latches. Because of pin limitations, the latches are arranged in pairs with a common C control line for each pair.

4. Contd … Among the devices in Figure , the most important is the 74x74, which contains two independent positive-edge-triggered D flip-flops with preset and clear inputs. Besides the 74x74’s use in “random” sequential circuits, fast versions of the part, such as the 74F74 and 74ACT74, find application in synchronizers for asynchronous input signals. The 74x109 is a positive-edge-triggered J-K flip-flop with an active-low K input (named K or K_L). Another J-K flip-flop is the 74x112, which has an active-low Clock input.

5. Introduction to Counters In General Flipflop it will store one bit of information at a time. But more than one bit storing we are not supposed to prefer Flipflops . Then go for REGISTER. Register is used for storing more no. of bits and also shifting data which is in the form of 1s / 0s. A counter is a Register, capable of counting the number of clock pulses arriving at its clock input. And a specified sequence of states appears as the counter output.

6. Ring Counter A looping process or cyclic process of counting clock pulses in the manner of Synchronous is known as Ring Counter. looping process apply by using Feedback system. n-Bit ring counter counts n-clock pluses with n- no.of flipflop’s .

7. Rotation moment of counting Clock pulses

8. 4-Bit 4-State Ring counter using IC 74X194 The simplest shift-register counter uses an n-bit shift register to obtain a counter with n states, and is called a ring counter. Figure 8-59 is the logic diagram for a 4-bit ring counter

9. Contd … The 74x194 universal shift register is wired so that it normally performs a left shift. However, when RESET is asserted, it loads 0001 (refer to the ’194’s function table ). Once RESET is negated, the ’194 shifts left on each clock tick. The LIN serial input is connected to the “leftmost” output, so the next states are 0010, 0100, 1000, 0001, 0010, ……. Thus, the counter visits four unique states before repeating. A timing diagram is shownin Figure

10. Contd …

11. Contd … In general, an n-bit ring counter visits n states in a cycle. The ring counter in Figure 8-59 has one major problem—it is not robust. If its single 1 output is lost due to a temporary hardware problem (e.g., noise), the counter goes to state 0000 and stays there forever. Likewise, if an extra 1 output is set (i.e., state 0101 is created), the counter will go through an incorrect cycle of states and stay in that cycle forever. These problems are quite evident if we draw the complete state diagram for the counter circuit, which has 16 states. As shown in Figure 8-61, there are 12 states that are not part of the normal counting cycle.

12. Contd … A self-correcting counter is designed so that all abnormal states have transitions leading to normal states. A self-correcting ring counter circuit using IC 74X194 is shown in below Figure . The circuit uses a NOR gate to shift a 1 into LIN only when the three least significant bits are 0.

13. Contd … The below figure shows how all abnormal states lead back into the normal cycle.

14. VHDL Code for Ring Counter library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity  Ring_counter  is     Port ( CLOCK : in  STD_LOGIC;            RESET : in  STD_LOGIC;            Q : out  STD_LOGIC_VECTOR (3  downto  0)); end  Ring_counter ;  

15. Contd … architecture Behavioral of  Ring_counter  is signal  q_tmp :  std_logic_vector (3  downto  0):= "0000"; begin process(CLOCK,RESET) begin if RESET = '1' then      q_tmp <= "0001"; elsif   Rising_edge (CLOCK) then      q_tmp (1) <= q_tmp (0);      q_tmp (2) <= q_tmp (1);      q_tmp (3) <= q_tmp (2);      q_tmp (0) <= q_tmp (3); end if; end process; Q <= q_tmp ; end Behavioral;

16. Johnson Counter/ Twisted Ring Counter An n-bit shift register with the complement of the serial output fed back into the serial input is a counter with 2n states and is called a twisted-ring, Moebius , or Johnson counter. Below Figure shows is the basic circuit for a Johnson counter .

17. Contd … The timing diagram of Johnson counter

18. Contd … The normal states of Johnson counter are listed in below table. If both the true and complemented outputs of each flip-flop are available, each normal state of the counter can be decoded with a 2-input AND or NAND gate, as shown in the table. The decoded outputs are glitch free.

19. Contd … An n -bit Johnson counter has 2 n - 2n abnormal states, and is therefore subject to the same robustness problems as a ring counter. A 4-bit self-correcting Johnson counter can be designed as shown in below Figure. This circuit loads 0001 as the next state whenever the current state is 0xx0. A similar circuit using a single 2-input NOR gate can perform correction for a Johnson counter with any number of bits. The correction circuit must load 00……01 as the next state whenever the current state is 0x……x0.

20. Contd …

21. VHDL Code for Johnson Counter library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity  Johnson_counter  is Port ( clk : in STD_LOGIC; rst : in STD_LOGIC; Q : out STD_LOGIC_VECTOR (3  downto  0)); end  Johnson_counter ;

22. Contd … architecture Behavioral of  Johnson_counter  is signal temp:  std_logic_vector (3  downto  0):= "0000"; begin process( clk,rst ) begin if  rst = '1' then temp <= "0000"; elsif   Rising_edge ( clk ) then temp(1) <= temp(0); temp(2) <= temp(1); temp(3) <= temp(2); temp(0) <= not temp(3); end if; end process; Q <= temp; end Behavioral;

23. Synchronous Counters When counter is clocked such that each flipflop in the counter is triggered at the same time, the counter is called as synchronous counter. 2-Bit Synchronous Counter

24. Contd …

25. 3-Bit Synchronous Counter

26. Contd …

27. 4-Bit Synchronous Counter

28. Design of Modulus N Synchronous Counters The counter with n flip flops has maximum mod number 2 n . For example, 3-bit binary counter is mod-8 counter. This basic counter can be modified to produce MOD numbers less than 2 n by allowing the counter to skip states those are normally part of counting sequence. Example 1: Design a MOD-5 synchronous counter using JK flipflops and implement it. Also construct a timing diagram. Solution: Step 1: Determine the number of flip flop needed . Flip flop required are 2 n ≥ N Here N = 5 n =3 i.e. three flip flops are required Step 2: Type of flip flop to be used: JK flip flop

29. Contd … Step 3: 1) Excitation table for JK flip flop

30. Contd … Now, we can derive excitation table for counter using above table as follows:

31. Contd … Step 4 K-map simplification

32. Contd …

33. Contd …

34. Contd …

35. Decade Counter A 4-bit decade synchronous counter can also be built using synchronous binary counters to produce a count sequence from 0 to 9. A standard binary counter can be converted to a decade (decimal 10) counter with the aid of some additional logic to implement the desired state sequence. After reaching the count of “1001”, the counter recycles back to “0000”. We now have a decade or Modulo-10 counter.

36. Contd …

37.   The Binary State Sequence for BCD Decade Counter

38. VHDL Code for Decade Counter library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity DECADECOUNTER is Port ( CLK,RESET : in STD_LOGIC; Q : out STD_LOGIC_VECTOR (3 downto 0)); end DECADECOUNTER;

39. Contd … architecture Behavioral of DECADECOUNTER is SIGNAL COUNT:STD_LOGIC_VECTOR(3 DOWNTO 0); begin PROCESS(CLK,RESET) BEGIN IF(RESET=’1’) THEN COUNT<=”0000”; ELSE IF(CLK’EVENT AND CLK=’1’) THEN IF (COUNT<”1001”) THEN COUNT<=COUNT+1; ELSE COUNT<=”0000”; END IF; END IF; END IF; END PROCESS; Q<=COUNT; END Behavioral;

40. UP/DOWN SYNCHRONOUS COUNTER  

41. Contd …

42. Contd …

43. VHDL code for synchronous up-down counter library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity updown_count is      Port ( clk , rst,updown : in  STD_LOGIC;           count : out  STD_LOGIC_VECTOR (3 downto 0)); end updown_count ;

44. Contd … architecture Behavioral of updown_count is signal temp:std_logic_vector (3 downto 0):="0000"; begin process( clk,rst ) begin if( rst ='1')then temp<="0000"; elsif ( rising_edge ( clk ))then if( updown ='0')then temp<=temp+1; else temp<=temp-1; end if; end if; end process; count<=temp; end Behavioral;

45. Design of Synchronous Counter using IC74191

46. Contd …

47. Shift Registers Binary Information in a register can be moved from stage to stage within the register or Out of the register upon application of clock pulses. This type of Bit movement or shifting is essential for certain arithmetic and logical operations used in Microprocessors.

48. Modes of operation of Shift register we have 4 types of modes of operations in shift registers. ( i ) Serial in serial out Shift Register (ii) Serial in parallel Out Shift Register (iii) Parallel in serial out Shift Register (iv) Parallel in parallel out shift register

49. ( i ) Serial in serial out Shift Register (SISO): The input to this register is given in serial fashion i.e. one bit after the other through a single data line and the output is also collected serially.

50. (ii) Serial in parallel Out Shift Register

51. (iii) Parallel in serial out Shift Register

52. Contd …

53. (iv) Parallel in parallel out shift register In this register, the input is given in parallel and the output also collected in parallel. The clear (CLR) signal and clock signals are connected to all the 4 flip flops.

54. VHDL Code for Shift Register LEFT SHIFT: library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity leftshift is Port ( clk,reset,din : in STD_LOGIC; d : out STD_LOGIC_VECTOR (7 downto 0); q : out STD_LOGIC); end leftshift ;

55. Contd … architecture Behavioral of leftshift is signal reg:STD_LOGIC_VECTOR (7 downto 0); begin process ( clk,reset,din ) begin if(reset='1')then reg <="00000000"; else if ( clk'event and clk ='1') then reg <= reg (6 downto 0)& din; q<= reg (7); end if; end if; end process; d<= reg ; end Behavioral;

56. RIGHTSHIFT: library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity rightshift is Port ( clk,reset,din : in STD_LOGIC; d : out STD_LOGIC_VECTOR (7 downto 0); q : out STD_LOGIC); end rightshift ;

57. Contd … architecture Behavioral of rightshift is signal reg:STD_LOGIC_VECTOR (7 downto 0); Begin process ( clk,reset,din ) begin if(reset='1')then reg <="00000000"; else if ( clk'event and clk ='1')then reg <=din & reg (7 downto 0); q<= reg (0); end if; end if; end process; d<= reg ; end Behavioral;

58. VHDL code for Parallel In Parallel Out Shift Register library  ieee ; use ieee.std_logic_1164.all;  entity  pipo  is  port( clk : in  std_logic ;   D: in  std_logic_vector (3  downto  0);   Q: out  std_logic_vector (3  downto  0)); end  pipo ; architecture arch of  pipo  is begin  process ( clk )  begin  if ( CLK'event and CLK='1') then  Q <= D;  end if;  end process; end arch;

59. VHDL Code for Serial In Parallel Out Shift Register library  ieee ; use ieee.std_logic_1164.all; entity  sipo  is  port(   clk , clear : in  std_logic ;   Input_Data : in  std_logic ;   Q: out  std_logic_vector (3  downto  0) ); end  sipo ;  architecture arch of  sipo  is begin  process ( clk )  begin  if clear = '1' then  Q <= "0000";   elsif  ( CLK'event and CLK='1') then   Q(3  downto  1) <= Q(2  downto  0);   Q(0) <= Input_Data ; end if; end process; end arch;

60. Universal Shift Register A register is capable of shifting in one direction only. i.e either right shift or left shift. Hence it is named as unidirectional shift register. A register is capable of shifting in both the direction. i.e. right shift and left shift. Hence it is named as bi-directional shift register or Universal Shift Register. This register can perform three types of operations, stated below. Parallel loading Shifting left Shifting right.

61. Contd …

62. Contd …

63. 4-Bit Bi-Directional Universal Shift Register IC 74LS194

64. VHDL Code for Universal Shift Register IC74x194 library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity universalshiftregister is Port ( clk , reset, din,l_r : in STD_LOGIC; d : out STD_LOGIC_VECTOR (7 downto 0); q : out STD_LOGIC); end universalshiftregister; architecture Behavioral of universalshiftregister is signal reg:STD_LOGIC_VECTOR (7 downto 0); begin process( clk , reset, din, l_r ) begin if(reset='1') then reg <="00000000";

65. Contd … else if( clk ' event and clk ='1') then if( l_r ='1') then reg <= reg (6 downto 0) & din; q<= reg (7); else reg <=din & reg (7 downto 1); q<= reg (0); end if; end if; end if; end process; d<= reg ; end Behavioral;