DIGITAL SIGNAL PROCESSORS INTRODUCTION 2

DIGITAL SIGNAL PROCESSORS INTRODUCTION 2

1. CEC337-DSP ARCHITECTURE AND PROGRAMMING Dr.N.Ameena Bibi Associate Professor ECE,GCE,Dharmapuri

2. CONTENTS 01 02 Basic Architectural Features DSP Computational Building Blocks 03 Bus Architecture and Memory 04 05 Data Addressing Capabilities 06 Programmability and Program Execution 07 Speed Issues & Features for External Interfacing UNIT I-ARCHITECTURES FOR PROGRAMMABLE DSP PROCESSORS Address Generation Unit

3. 1.3 BUS ARCHITECTURE AND MEMORY In conventional microprocessors, the von Neumann architecture is used, wherein the program and the data reside in the same memory and a single bus (Address + Data) is used to access both. This slows down the program execution. To speed up the program execution, it is desirable to have the program and data reside in two separate memories and have two buses for the processor to access the two memories . This modification, which is called the Harvard architecture

4. Even with separate memories, the program and data, it is not possible to fetch the two operands required for multiplication along with the program instruction, and the processor has to wait for the second operand. It would therefore be required to provide dual data memories in addition to' program memory and provide each with a separate bus for the processor to access them simultaneously. This will require a lot of hardware and interconnections to implement, thereby increasing the cost 1.3 cntd….

5. ON CHIP MEMORY Multiple memories with individual buses , some of the memories along with their buses on chip. On-chip memories help in running DSP algorithms faster than when the memories are located off-chip . On-chip memories can have dedicated address and data buses unlike off-chip memories , whose buses are often multiplexed to reduce the pin count on the DSP. There are several issues related to the design of on-chip memories. Speed: The on-chip memories should match the speeds, of the ALU operations in order to maintain the single-cycle instruction execution requirement of the DSP. Size: Size is a major constraint for on-chip memories. More area occupied by the on-chip memory the less will be the area available for other functions. 1.3 cntd….

6. ORGANIZATION OF THE ON CHIP MEMORY T he entire memory required to. implement a DSP algorithm should reside on-chip . On-chip memory should be partitioned into program and data spaces. If necessary, the data memory should be further divided into separate areas for storing data samples, coefficients , and results. This way, an instruction with two operands can be fetched and executed and the result saved all in a single cycle. Writing the program and data into the on-chip memories is done before the program execution. results are read off the on-chip memory after the program execution is completed. There are several other ways in which the on-chip memory can be organized efficiently and in cost-effective manner. 1.3 cntd….

7. 1 . Many DSP algorithms require repeated executions of a single instruction such as the multiply and accumulate or a loop consisting of a few instructions. The result is normally saved only after the repetitions are completed. It is, therefore, sufficient to provide only two blocks of on chip memories to hold the operands required for the execution of the instructions. 2. On-chip memories can be designed such that they can be accessed more than once in an instruction cycle. This means that their access times should be sufficiently small to match the timing requirements of single-cycle instruction execution. 3. On-chip memories can be configured for different uses at different times depending on the requirements. 1.3 cntd….

8. 1.4 DATA ADDRESSING CAPABILITIES The data processed by a digital signal-processing scheme typically consist of signal samples and filter coefficients. An efficient way of accessing data while performing computations can go a long way in the overall performance of an implementation. The data addressing capability -of a programmable DSP device is provided by means of its addressing modes.

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11. Example :What are the memory addresses of the operands in each of the following cases of indirect addressing modes? In each case, what will be the content of the addrreg after the memory access? Assume that the initial contents of theaddrreg and the·0ffsetreg are 0200h and OOlOh, respectively a. ADD *addrreg-. b. ADD+ * addrreg c. ADD offsetreg +, * addrreg d. ADD * addrreg , offsetreg 1.4 cntd ….

12. Special Addressing Modes Circular Addressing Mode In acircular buffer, successive data samples are stored in sequential buffer locations until the end of the buffer is reached. After reaching the end we start all over from the beginning, of the buffer . To access a data sample from a circular buffer, a circular addressing mode is used. The implementation of such an addressing mode in hardware requires three registers: a pointer register (PNTR) to keep track of current address, a start, address register (SAR) to hold the start address of the buffer, and an end address register (EAR) to hold the end address of the buffer . Cases : 1. SAR < EAR, and updated PNTR > EAR 2. SAR < EAR, and updated PNTR < SAR 3. SAR > EAR, and updated PNTR > SAR 4. SAR > EAR, and updated PNTR < EAR The buffer size in the first two cases = (EAR - SAR + 1) and in the last two case is = (SAR - EAR + 1) 1.4 cntd ….

13. Pointer Updating Algorithm for the Circular Addressing Mode Updated PNTR ← PNTR ± increment If SAR < EAR and .if Updated PNTR >.EAR, then New PNTR ← Updated PNTR - Buffer size and if Updated PNTR < SAR, then New PNTR ← UpdatedPNTR,+ Buffer size If SAR > EAR and if Updated PNTR'> SAR. then NewPNTR ← UpdatedPNTR -Buffer size and if ,Updated PNTR < EAR, then , New PNTR ← UpdatedPNTR + Buffer si ze Else New PNTR ← Updated PNTR 1.4 cntd ….

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15. Bit Reversed Addressing Modes In decimation in time (DIT) FFT, in the case of an 8-point FFT. the input data x{O). x(I).x(2),x(3). x(4). x(S), x(6). and x(7) need to be accessed in the order x(O), x(4),x(2), x(6). x(l), x(5) x(3), and x(7). Current ,index = previous index + B(l/2(FFT size) The reverse-carry-add operation can be provided in: the architecture to implement this special addressing mode. The architecture will require a register to keep track of the index at any time in addition to the capability to propagate the carry in the reverse direction during the add operation in order to generate the next index to be used to access data. To provide this capability in parallel with the instruction execution, a special address generation unit is employed. 1.4 cntd ….

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17. 1.5 Address Generation Unit The function of the address generation unit is to provide the addresses of the operands required to carry out the DSP operations . Since many instructions, such as the mUltiply instruction, require more than one operand for their execution, the address generation unit should work fast enough to provide the addresses within the time constraints imposed by the instruction execution requirements. In order to carry out the computations required for the specialized addressing modes the address generation unit in a DSP implementation is provided with a separate arithmetic unit of its own . This way, address computation overhead is removed from the main ALU, thereby allowing ino perform more efficiently.

18. Address generation typically involves one of the following operations: l. Getting a new value from an immediate operand, a register, or a memory location. 2. Incrementing or decrementing the current address. 3. Adding or subtracting an offset to the current address. 4. Adding or subtracting ail offset to the current address, comparing the new address with the limits defined for a circular addressing mode, and generating a new address as per the circular addressing mode algorithm. 5. Generating a new address from the current address by applying the bit reversed addressing mode algorithm. 1.5 cntd …

19. The hardware necessary to carry out the various operations may consist of the following an ALU registers to store the current value, the offset, and the new value; registers to store the limits of the circular buffer ; logic to implement the circular addressing mode ; and the logic to implement the bit-reversed addressing mode. 1.5 cntd …