Digital System Design-Synchronous Sequential Circuits
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Jul 26, 2022
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About This Presentation
Behavioral modeling of sequential logic modules: Latches, Flip Flops, counters and shift registers applications
Synchronous Sequential Circuits: Analysis and synthesis of synchronous sequential circuits: Mealy and Moore FSM models for completely and incompletely specified circuits, State Minimizatio...
Slide Content
MATRUSRI ENGINEERING COLLEGE
DEPARTMENT OF ELECTRONICS AND COMMUNICATION
ENGINEERING
SUBJECT NAME: DIGITAL SYSTEM DESIGN WITH VERILOG
FACULTY NAME: Mrs. B. Indira Priyadarshini
MATRUSRI
ENGINEERING COLLEGE
DEPARTMENT OF ELECTRONICS AND COMMUNICATION
ENGINEERING
SUBJECT NAME: DIGITAL SYSTEM DESIGN WITH VERILOG
FACULTY NAME: Mrs. B. Indira Priyadarshini
MATRUSRI
ENGINEERING COLLEGE
INTRODUCTION:
Givesadetailedpresentationofsynchronoussequentialcircuits(finitestate
machines).Itexplainsthebehaviorofthesecircuitsanddevelopspractical
designtechniquesforbothmanualandautomateddesign.Dealswithageneral
classofcircuitsinwhichtheoutputsdependonthepastbehaviorofthecircuit,
aswellasonthepresentvaluesofinputs.Theyarecalledsequentialcircuits.In
mostcasesaclocksignalisusedtocontroltheoperationofasequentialcircuit;
suchacircuitiscalledasynchronoussequentialcircuit.
UNIT-III
OUTCOMES:
AftersuccessfulcompletionofthisUnitstudentsshouldbeableto
Analyze,designandimplementsequentiallogiccircuitsintermsofstate
machines.
ImplementsequentialcircuitsusingVerilogcode
MATRUSRI
ENGINEERING COLLEGE
Givesadetailedpresentationofsynchronoussequentialcircuits(finitestate
machines).Itexplainsthebehaviorofthesecircuitsanddevelopspractical
designtechniquesforbothmanualandautomateddesign.Dealswithageneral
classofcircuitsinwhichtheoutputsdependonthepastbehaviorofthecircuit,
aswellasonthepresentvaluesofinputs.Theyarecalledsequentialcircuits.In
mostcasesaclocksignalisusedtocontroltheoperationofasequentialcircuit;
suchacircuitiscalledasynchronoussequentialcircuit.
UNIT-III
OUTCOMES:
AftersuccessfulcompletionofthisUnitstudentsshouldbeableto
Analyze,designandimplementsequentiallogiccircuitsintermsofstate
machines.
ImplementsequentialcircuitsusingVerilogcode
MATRUSRI
ENGINEERING COLLEGE
CONTENTS:
Latches
Flip Flops
Counters
Shift registers applications
OUTCOMES:
Studentswillbeabletodesignsequentiallogicmodulesinbehavioral
modeling.
MODULE-I: Behavioural modelingof
sequential logic modules
MATRUSRI
ENGINEERING COLLEGE
Latches
Flip Flops
Counters
Shift registers applications
OUTCOMES:
Studentswillbeabletodesignsequentiallogicmodulesinbehavioral
modeling.
MODULE-I: Behavioural modelingof
sequential logic modules
MATRUSRI
ENGINEERING COLLEGE
Latches
MATRUSRI
ENGINEERING COLLEGE
Clock d qn qn+1
0 x x 0
1 0 0 0
1 1 0 1
1 0 1 0
1 1 1 1
moduleDlatch(D,Clk,Q);
inputD,Clk;
outputQ;
regQ;
always@(DorClk)
if(Clk)
Q<=D;
endmodule
moduledtest_v;
regd;
regclk;
wireq;
Dlatchuut(.d(D),.clk(Clk),.q(Q));
always
#5clk=~clk;
initialbegin
#100$finish;
end
initialbegin
clk=1;d=1'b0;
#20d=1'b1;
#20d=1'b0;
end
endmodule
MATRUSRI
ENGINEERING COLLEGE
Clock d qn qn+1
0 x x 0
1 0 0 0
1 1 0 1
1 0 1 0
1 1 1 1
moduleDlatch(D,Clk,Q);
inputD,Clk;
outputQ;
regQ;
always@(DorClk)
if(Clk)
Q<=D;
endmodule
moduledtest_v;
regd;
regclk;
wireq;
Dlatchuut(.d(D),.clk(Clk),.q(Q));
always
#5clk=~clk;
initialbegin
#100$finish;
end
initialbegin
clk=1;d=1'b0;
#20d=1'b1;
#20d=1'b0;
end
endmodule
D Flipflops
MATRUSRI
ENGINEERING COLLEGE
moduleD_FF(Q,D,Clk);
outputregQ;
inputD,Clk;
always@(posedgeClk)
Q<=D;
endmodule
moduledtest_v;
regd;
regclk;
wireq;
D_FFuut(.d(D),.clk(Clk),.q(Q));
always
#5clk=~clk;
initialbegin
#100$finish;
end
initialbegin
clk=1;d=1'b0;
#20d=1'b1;
#20d=1'b0;
end
endmodule
Resetnclockdqnqn+1
1 xx 0
0 00 0
0 10 1
0 01 0
0 11 1
MATRUSRI
ENGINEERING COLLEGE
moduleD_FF(Q,D,Clk);
outputregQ;
inputD,Clk;
always@(posedgeClk)
Q<=D;
endmodule
moduledtest_v;
regd;
regclk;
wireq;
D_FFuut(.d(D),.clk(Clk),.q(Q));
always
#5clk=~clk;
initialbegin
#100$finish;
end
initialbegin
clk=1;d=1'b0;
#20d=1'b1;
#20d=1'b0;
end
endmodule
Resetnclockdqnqn+1
1 xx 0
0 00 0
0 10 1
0 01 0
0 11 1
D Flipflops
MATRUSRI
ENGINEERING COLLEGE
Dflip-flopwithsynchronousreset
moduleD_FF(Q,D,Clk,rst);
outputregQ;
inputD,Clk,rst;
always@(posedgeClk)
if(!rst)
Q<=0;
else
Q<=D;
endmodule
Dflip-flopwithasynchronousreset
moduleDFF(outputregQ,inputD,Clk,rst);
always@(posedgeClkornegedgerst)
if(!rst)
Q<=1'b0;//Sameas:if(rst==0)
else
Q<=D;
endmodule
Testbench:
moduledtest_v;
regd,clk,rst
wireq;
DFF uut(
.d(D), .clk(Clk), .rst(rst), .q(Q)
);
always#5clk=~clk;
initialbegin
#100$finish;
end
initialbegin
clk=1;rst=0;d=1'b0;
#20rstn=1;d=1'b1;
#20rst=0;d=1'b0;
end
endmodule
MATRUSRI
ENGINEERING COLLEGE
Dflip-flopwithsynchronousreset
moduleD_FF(Q,D,Clk,rst);
outputregQ;
inputD,Clk,rst;
always@(posedgeClk)
if(!rst)
Q<=0;
else
Q<=D;
endmodule
Dflip-flopwithasynchronousreset
moduleDFF(outputregQ,inputD,Clk,rst);
always@(posedgeClkornegedgerst)
if(!rst)
Q<=1'b0;//Sameas:if(rst==0)
else
Q<=D;
endmodule
Testbench:
moduledtest_v;
regd,clk,rst
wireq;
DFF uut(
.d(D), .clk(Clk), .rst(rst), .q(Q)
);
always#5clk=~clk;
initialbegin
#100$finish;
end
initialbegin
clk=1;rst=0;d=1'b0;
#20rstn=1;d=1'b1;
#20rst=0;d=1'b0;
end
endmodule
T Flipflops
MATRUSRI
ENGINEERING COLLEGE
TFlipflop
moduletff_behv(t,clk,rst,q);
inputt,clk,rst;
outputregq;
always@(posedgeclk)
if(rst==1)
q<=1'b0;
else
begin
if(t==1)
q<=~q;
else
q<=q;
end
endmodule
Testbench:
moduletfftest_v;
regt,clk,rst;
wireq;
tffuut(.t(t),.clk(clk),.rst(rst),.q
(q));
always
#5clk=~clk;
initialbegin
#100$finish;
end
initialbegin
clk=1;rst=1;t=0;
#5t=0;
#10rst=0;t=1;
#30t=0;
end
endmodule
Resetnclocktqnqn+1
1 xx0
0 000
0 101
0 011
0 110
MATRUSRI
ENGINEERING COLLEGE
TFlipflop
moduletff_behv(t,clk,rst,q);
inputt,clk,rst;
outputregq;
always@(posedgeclk)
if(rst==1)
q<=1'b0;
else
begin
if(t==1)
q<=~q;
else
q<=q;
end
endmodule
Testbench:
moduletfftest_v;
regt,clk,rst;
wireq;
tffuut(.t(t),.clk(clk),.rst(rst),.q
(q));
always
#5clk=~clk;
initialbegin
#100$finish;
end
initialbegin
clk=1;rst=1;t=0;
#5t=0;
#10rst=0;t=1;
#30t=0;
end
endmodule
Resetnclocktqnqn+1
1 xx0
0 000
0 101
0 011
0 110
JK Flipflop
MATRUSRI
ENGINEERING COLLEGE
MATRUSRI
ENGINEERING COLLEGE
JK Flipflop
MATRUSRI
ENGINEERING COLLEGE
modulejkff_behv(j,k,clk,rst,q,qb);
inputj,k,clk,rst;
outputregq;
outputqb;
assignqb=~q;
always@(posedgeclk)
begin
if(rst==1'b1)
q<=1'b0;
else
case({j,k})
2'b00:q<=q;
2'b01:q<=1'b0;
2'b10:q<=1'b1;
2'b11:q<=~q;
endcase
end
endmodule
Testbench:
modulejkfftest1_v;
regj,k,clk,rst;
wireq,qb;
jkffuut(.j(j),.k(k),.clk(clk),.rst(rst),.
q(q),.qb(qb));
always#5clk=~clk;
always#5rst=~rst;
initialbegin
#100$finish;
end
initialbegin
rst=0;j=1;k=0;clk=1;
#5j=0;k=1;
#5j=1;k=1;
#5j=1;k=0;
end
endmodule
MATRUSRI
ENGINEERING COLLEGE
modulejkff_behv(j,k,clk,rst,q,qb);
inputj,k,clk,rst;
outputregq;
outputqb;
assignqb=~q;
always@(posedgeclk)
begin
if(rst==1'b1)
q<=1'b0;
else
case({j,k})
2'b00:q<=q;
2'b01:q<=1'b0;
2'b10:q<=1'b1;
2'b11:q<=~q;
endcase
end
endmodule
Testbench:
modulejkfftest1_v;
regj,k,clk,rst;
wireq,qb;
jkffuut(.j(j),.k(k),.clk(clk),.rst(rst),.
q(q),.qb(qb));
always#5clk=~clk;
always#5rst=~rst;
initialbegin
#100$finish;
end
initialbegin
rst=0;j=1;k=0;clk=1;
#5j=0;k=1;
#5j=1;k=1;
#5j=1;k=0;
end
endmodule
SR Flipflop
MATRUSRI
ENGINEERING COLLEGE
rstclksrqnqn+1
1 xxx0
0 0000
0 0011
0 0100
0 0110
0 1001
0 1011
0 11xx
0 11xx
MATRUSRI
ENGINEERING COLLEGE
rstclksrqnqn+1
1 xxx0
0 0000
0 0011
0 0100
0 0110
0 1001
0 1011
0 11xx
0 11xx
SR Flipflop
MATRUSRI
ENGINEERING COLLEGE
modulesrff_behv(s,r,clk,rst,q);
inputs,r;
outputregq;
always@(posedgeclk)
begin
if(rst==1'b1)
q<=1'b0;
else
casex({s,r})
2'b00:q<=q;
2'b01:q<=1'b0;
2'b10:q<=1'b1;
2'b11:q<=1’bx;
endcase
end
endmodule
Testbench:
modulesrfftest1_v;
regj,k,clk,rst;
wireq;
srffuut(.s(s),.r(r),.clk(clk),.rst(rst),.
q(q));
always#5clk=~clk;
always#5rst=~rst;
initialbegin
#100$finish;
end
initialbegin
rst=0;s=1;r=0;clk=1;
#5s=0;r=1;
#5s=1;r=1;
#5s=0;r=0;
end
endmodule
MATRUSRI
ENGINEERING COLLEGE
modulesrff_behv(s,r,clk,rst,q);
inputs,r;
outputregq;
always@(posedgeclk)
begin
if(rst==1'b1)
q<=1'b0;
else
casex({s,r})
2'b00:q<=q;
2'b01:q<=1'b0;
2'b10:q<=1'b1;
2'b11:q<=1’bx;
endcase
end
endmodule
Testbench:
modulesrfftest1_v;
regj,k,clk,rst;
wireq;
srffuut(.s(s),.r(r),.clk(clk),.rst(rst),.
q(q));
always#5clk=~clk;
always#5rst=~rst;
initialbegin
#100$finish;
end
initialbegin
rst=0;s=1;r=0;clk=1;
#5s=0;r=1;
#5s=1;r=1;
#5s=0;r=0;
end
endmodule
Counter
MATRUSRI
ENGINEERING COLLEGE
Clock
Pluse
Q3Q2Q1Q0
0 00 00
1 00 01
2 00 10
3 00 11
4 01 00
5 01 01
6 01 10
7 01 11
8 10 00
9 10 01
MATRUSRI
ENGINEERING COLLEGE
Clock
Pluse
Q3Q2Q1Q0
0 00 00
1 00 01
2 00 10
3 00 11
4 01 00
5 01 01
6 01 10
7 01 11
8 10 00
9 10 01
Counter
MATRUSRI
ENGINEERING COLLEGE
moduleupdowncount(
R,clk,L,E,updwn,Q
);
parametern=8;
input[n-1]R;
inputclk,L,E,updwn;
output[n-1]Q;
reg[n-1]Q;
integerdirection;
always@(posedgeclk)
begin
if(updwn)
direction=1;
else
direction=−1;
if(L)
Q<=R;
elseif(E)
Q<=Q+direction;
end
endmodule
Testbench:
moduleupdowncounttest_v;
regclk,L,E,updwn;
reg[n-1]R
wire[n-1:0]Q;
Updowncountuut(R,clk,L,E,updwn,Q);
always#5clk=~clk;
initialbegin
#400$finish;
end
initial
begin
L=1;clk=1;updwn=0;R=8’o23;E=1;
#10L=0;
#150L=1;
#20L=0;updwn=1;
end
endmodule
MATRUSRI
ENGINEERING COLLEGE
moduleupdowncount(
R,clk,L,E,updwn,Q
);
parametern=8;
input[n-1]R;
inputclk,L,E,updwn;
output[n-1]Q;
reg[n-1]Q;
integerdirection;
always@(posedgeclk)
begin
if(updwn)
direction=1;
else
direction=−1;
if(L)
Q<=R;
elseif(E)
Q<=Q+direction;
end
endmodule
Testbench:
moduleupdowncounttest_v;
regclk,L,E,updwn;
reg[n-1]R
wire[n-1:0]Q;
Updowncountuut(R,clk,L,E,updwn,Q);
always#5clk=~clk;
initialbegin
#400$finish;
end
initial
begin
L=1;clk=1;updwn=0;R=8’o23;E=1;
#10L=0;
#150L=1;
#20L=0;updwn=1;
end
endmodule
Shift Register
MATRUSRI
ENGINEERING COLLEGE
RightShift:
moduleshift4(R,L,w,Clock,Q);
input[3:0]R;
inputL,w,Clock;
outputreg[3:0]Q;
always@(posedgeClock)
if(L)
Q<=R;
else
Q[3:0]={w,Q[3:1]};
endmodule
LeftShift:
moduleshift4(R,L,w,Clock,Q);
input[3:0]R;
inputL,w,Clock;
outputreg[3:0]Q;
always@(posedgeClock)
if(L)
Q<=R;
else
Q[3:0]={Q[2:0],w};
endmodule
Testbench:
moduleshift4_tst_v;
regL,w,Clock;
reg[3:0]R;
wire[3:0]Q;
shift4uut(R,L,w,Clock,Q);
initialbegin
R=4’b1011;
L=1;
w=1;
#20;L=0;
end
always#5Clock=~Clock;
endmodule
MATRUSRI
ENGINEERING COLLEGE
RightShift:
moduleshift4(R,L,w,Clock,Q);
input[3:0]R;
inputL,w,Clock;
outputreg[3:0]Q;
always@(posedgeClock)
if(L)
Q<=R;
else
Q[3:0]={w,Q[3:1]};
endmodule
LeftShift:
moduleshift4(R,L,w,Clock,Q);
input[3:0]R;
inputL,w,Clock;
outputreg[3:0]Q;
always@(posedgeClock)
if(L)
Q<=R;
else
Q[3:0]={Q[2:0],w};
endmodule
Testbench:
moduleshift4_tst_v;
regL,w,Clock;
reg[3:0]R;
wire[3:0]Q;
shift4uut(R,L,w,Clock,Q);
initialbegin
R=4’b1011;
L=1;
w=1;
#20;L=0;
end
always#5Clock=~Clock;
endmodule
Shift Register
MATRUSRI
ENGINEERING COLLEGE
Serial In Serial Out:
module shift (C, SI, SO);
input C,SI;
output SO;
reg[7:0] tmp;
always @(posedgeC)
begin
tmp= tmp<< 1;
tmp[0] = SI;
end
assign SO = tmp[7];
endmodule
Parallel In Parallel Out:
module pipo(pin, clk, reset, pout);
input [3:0] pin;
input clk, reset;
output reg[3:0] pout;
always @ (posedgeclkor posedgereset)
begin
if (reset)
pout <= 4'b0000;
else
pout <= pin;
end
endmodule
MATRUSRI
ENGINEERING COLLEGE
Serial In Serial Out:
module shift (C, SI, SO);
input C,SI;
output SO;
reg[7:0] tmp;
always @(posedgeC)
begin
tmp= tmp<< 1;
tmp[0] = SI;
end
assign SO = tmp[7];
endmodule
Parallel In Parallel Out:
module pipo(pin, clk, reset, pout);
input [3:0] pin;
input clk, reset;
output reg[3:0] pout;
always @ (posedgeclkor posedgereset)
begin
if (reset)
pout <= 4'b0000;
else
pout <= pin;
end
endmodule
Shift Register
MATRUSRI
ENGINEERING COLLEGE
Parallel In Serial Out:
moduleShiftregister_PISO(
Clk, Parallel_In,load,
Serial_Out);
inputClk,load;
input[3:0]Parallel_In;
outputregSerial_Out;
reg[3:0]tmp;
always@(posedgeClk)
begin
if(load)
tmp<=Parallel_In;
else
begin
Serial_Out<=tmp[3];
tmp<={tmp[2:0],1'b0};
end
end
endmodule
Serial In Parallel Out:
moduleShiftRegister_SIPO(Clk, SI, PO);
inputClk,SI;
output[7:0] PO;
reg[7:0] tmp;
always@(posedgeClk)
begin
tmp= {tmp[6:0], SI};
end
assignPO = tmp;
endmodule
MATRUSRI
ENGINEERING COLLEGE
Parallel In Serial Out:
moduleShiftregister_PISO(
Clk, Parallel_In,load,
Serial_Out);
inputClk,load;
input[3:0]Parallel_In;
outputregSerial_Out;
reg[3:0]tmp;
always@(posedgeClk)
begin
if(load)
tmp<=Parallel_In;
else
begin
Serial_Out<=tmp[3];
tmp<={tmp[2:0],1'b0};
end
end
endmodule
Serial In Parallel Out:
moduleShiftRegister_SIPO(Clk, SI, PO);
inputClk,SI;
output[7:0] PO;
reg[7:0] tmp;
always@(posedgeClk)
begin
tmp= {tmp[6:0], SI};
end
assignPO = tmp;
endmodule
1.Theoutputoflatcheswillremaininset/resetuntilthetriggerpulseis
giventochangethestate.
2.Thepurposeoftheclockinputtoaflip-flopistocausetheoutputto
assumeastatedependentonthecontrollinginputs.
3.Howmuchstoragecapacitydoeseachstageinashiftregisterrepresent?
Ans:Onebit
4.Binarycounterthatcountsreverselyiscalleddowncounter.
Questions & Answers
MATRUSRI
ENGINEERING COLLEGE
giventochangethestate.
2.Thepurposeoftheclockinputtoaflip-flopistocausetheoutputto
assumeastatedependentonthecontrollinginputs.
3.Howmuchstoragecapacitydoeseachstageinashiftregisterrepresent?
Ans:Onebit
4.Binarycounterthatcountsreverselyiscalleddowncounter.
Questions & Answers
MATRUSRI
ENGINEERING COLLEGE
CONTENTS:
Design Procedure
Moore state Model
Mealy state Model
OUTCOMES:
StudentswillbeabletodesignMealyandMooreFSMmodelsforcompletely
andincompletelyspecifiedcircuits.
MODULE-II: Synchronous Sequential
Circuits
MATRUSRI
ENGINEERING COLLEGE
Design Procedure
Moore state Model
Mealy state Model
OUTCOMES:
StudentswillbeabletodesignMealyandMooreFSMmodelsforcompletely
andincompletelyspecifiedcircuits.
MODULE-II: Synchronous Sequential
Circuits
MATRUSRI
ENGINEERING COLLEGE
Synchronous Sequential Circuits
MATRUSRI
ENGINEERING COLLEGE
A circuit whose output(s) depend on past behaviour, and present inputs
•Clock is used => synchronous sequential circuits
•No clock => asynchronous sequence circuits
Also called Finite state machine (FSM)
State elements in synchronous sequential circuits are edge triggered
•To ensure state changes only once in a single cycle.
MATRUSRI
ENGINEERING COLLEGE
A circuit whose output(s) depend on past behaviour, and present inputs
•Clock is used => synchronous sequential circuits
•No clock => asynchronous sequence circuits
Also called Finite state machine (FSM)
State elements in synchronous sequential circuits are edge triggered
•To ensure state changes only once in a single cycle.
Synchronous Sequential Circuits
MATRUSRI
ENGINEERING COLLEGE
Synchronous sequential circuits are of two types:
•Moore output depends only on state
•Mealy: output depends on state and inputs
MATRUSRI
ENGINEERING COLLEGE
Synchronous sequential circuits are of two types:
•Moore output depends only on state
•Mealy: output depends on state and inputs
Design Procedure
MATRUSRI
ENGINEERING COLLEGE
Theprocedurefordesigningsynchronoussequentialcircuitscanbe
summarizedbyalistofrecommendedsteps.
1.Fromtheworddescriptionandspecificationsofthedesiredoperation,
deriveastatediagramforthecircuit.
2.Reducethenumberofstatesifnecessary.
3.Assignbinaryvaluestothestates.
4.Obtainthebinary-codedstatetable.
5.Choosethetypeofflip-flopstobeused.
6.Derivethesimplifiedflip-flopinputequationsandoutputequations.
7.Drawthelogicdiagram
MATRUSRI
ENGINEERING COLLEGE
Theprocedurefordesigningsynchronoussequentialcircuitscanbe
summarizedbyalistofrecommendedsteps.
1.Fromtheworddescriptionandspecificationsofthedesiredoperation,
deriveastatediagramforthecircuit.
2.Reducethenumberofstatesifnecessary.
3.Assignbinaryvaluestothestates.
4.Obtainthebinary-codedstatetable.
5.Choosethetypeofflip-flopstobeused.
6.Derivethesimplifiedflip-flopinputequationsandoutputequations.
7.Drawthelogicdiagram
Designing Sequential Circuit
Moore State Model
MATRUSRI
ENGINEERING COLLEGE
Supposethatwewantacircuitwiththefollowingcharacteristics:
•Oneinputw,andoneoutputz
•Positive-edge-triggereddesign
•z=1,ifw=1duringtwoconsecutiveclockcycles
Notes:usingonlyinput,wecannotfindanexpressionforoutput
•Henceneedastateinformation–FSMClock cycle: t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10
w: 0 1 0 1 1 0 1 1 1 0 1
z: 0 0 0 0 0 1 0 1 1 0 0
Moore State Model
MATRUSRI
ENGINEERING COLLEGE
Supposethatwewantacircuitwiththefollowingcharacteristics:
•Oneinputw,andoneoutputz
•Positive-edge-triggereddesign
•z=1,ifw=1duringtwoconsecutiveclockcycles
Notes:usingonlyinput,wecannotfindanexpressionforoutput
•Henceneedastateinformation–FSMClock cycle: t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10
w: 0 1 0 1 1 0 1 1 1 0 1
z: 0 0 0 0 0 1 0 1 1 0 0
Develop State Diagram
MATRUSRI
ENGINEERING COLLEGE
The conceptually simplest method is to use a pictorial representation in the
form of a state diagram.
Optional to develop
One form to represent a FSM:
• How many states: States are circles
• Transitions between states: Transitions are directed edges
• Starting state: i.e. after reset/clear
Note in figure, reset is not treated as input: To simplify figure.
MATRUSRI
ENGINEERING COLLEGE
The conceptually simplest method is to use a pictorial representation in the
form of a state diagram.
Optional to develop
One form to represent a FSM:
• How many states: States are circles
• Transitions between states: Transitions are directed edges
• Starting state: i.e. after reset/clear
Note in figure, reset is not treated as input: To simplify figure.
Develop State Table
MATRUSRI
ENGINEERING COLLEGE
AnotherwaytodescribeaFSM
Whenimplementedinalogiccircuit,eachstateisrepresentedbyaparticular
valuation(combinationofvalues)ofstatevariables.
Itcontainsinformationon:
•Statesofthemachine
•Transitionsfromallstates,forallpossibleinputs
•Outputvalues
•Resetinformationignored:StateAisassumedtobe“start”statePresent
state
Next state Output
Z w = 0 w = 1
A
B
C
A B
A C
A C
0
0
1
MATRUSRI
ENGINEERING COLLEGE
AnotherwaytodescribeaFSM
Whenimplementedinalogiccircuit,eachstateisrepresentedbyaparticular
valuation(combinationofvalues)ofstatevariables.
Itcontainsinformationon:
•Statesofthemachine
•Transitionsfromallstates,forallpossibleinputs
•Outputvalues
•Resetinformationignored:StateAisassumedtobe“start”statePresent
state
Next state Output
Z w = 0 w = 1
A
B
C
A B
A C
A C
0
0
1
Develop State Assignment
MATRUSRI
ENGINEERING COLLEGE
Findnumberofflip/flopsneededtorepresentstate
•No.ofFFs=log2(no.ofstates)
Assigneachstateacombinationofvaluesofstatevariables
•“Stateassignedtable”
•Allunusedvariablecombinationarenormallyusedasdon’tcares
Belowistheresultingtableafterstateassignment
Noticethat:
•Outputdependsoncurrentstateonly-Mooretype
•2statevariablesaresufficienttorepresent3states
•Y1&Y2arenext-statevariables,y1&y2arepresent-statevariables
NeedtodecidetypeofFFtouseasstateelement
UseD-FFsinceitiseasiest
D1=Y1,andD2=Y2
Foreverynextstateandoutput,derivetheirfunctionfrompresentstateand
input
MATRUSRI
ENGINEERING COLLEGE
Findnumberofflip/flopsneededtorepresentstate
•No.ofFFs=log2(no.ofstates)
Assigneachstateacombinationofvaluesofstatevariables
•“Stateassignedtable”
•Allunusedvariablecombinationarenormallyusedasdon’tcares
Belowistheresultingtableafterstateassignment
Noticethat:
•Outputdependsoncurrentstateonly-Mooretype
•2statevariablesaresufficienttorepresent3states
•Y1&Y2arenext-statevariables,y1&y2arepresent-statevariables
NeedtodecidetypeofFFtouseasstateelement
UseD-FFsinceitiseasiest
D1=Y1,andD2=Y2
Foreverynextstateandoutput,derivetheirfunctionfrompresentstateand
input
Develop State Assignment
MATRUSRI
ENGINEERING COLLEGE
Y1=w.y1y2
Y2=w(y1+y2)
z=y2
•Stateassignmentshasdirectrelationtothecostofderivedimplementation
Somestateassignmentsarebetterthanothers
•Usingthenewstateassignmentamorecosteffectiverealizationinpossible
Y1=w,cheaper
Y2=wy1,cheaper
z=y2,samecost
Present state
y
2y
1
Next state Output
Zw = 0 w = 1
Y
2Y
1 Y
2Y
1
A
B
C
D
00
01
10
11
00 01
00 10
00 10
d d
0
0
1
d
Present state
y
2y
1
Next state Output
Zw = 0 w = 1
Y
2Y
1 Y
2Y
1
A
B
C
D
00
01
11
10
00 01
00 10
00 10
d d
0
0
1
d
MATRUSRI
ENGINEERING COLLEGE
Y1=w.y1y2
Y2=w(y1+y2)
z=y2
•Stateassignmentshasdirectrelationtothecostofderivedimplementation
Somestateassignmentsarebetterthanothers
•Usingthenewstateassignmentamorecosteffectiverealizationinpossible
Y1=w,cheaper
Y2=wy1,cheaper
z=y2,samecost
Present state
y
2y
1
Next state Output
Zw = 0 w = 1
Y
2Y
1 Y
2Y
1
A
B
C
D
00
01
10
11
00 01
00 10
00 10
d d
0
0
1
d
Present state
y
2y
1
Next state Output
Zw = 0 w = 1
Y
2Y
1 Y
2Y
1
A
B
C
D
00
01
11
10
00 01
00 10
00 10
d d
0
0
1
d
Function Realization
MATRUSRI
ENGINEERING COLLEGE
MATRUSRI
ENGINEERING COLLEGE
Resulting Logic Circuit
MATRUSRI
ENGINEERING COLLEGE
MATRUSRI
ENGINEERING COLLEGE
Timing Diagram of Realization
MATRUSRI
ENGINEERING COLLEGE
MATRUSRI
ENGINEERING COLLEGE
Mealy Machine Implementation
MATRUSRI
ENGINEERING COLLEGE
Outputvaluesaregeneratedusingstate&presentinputs
Statediagram StateTable
StateAssignedTable LogicDiagram
Y = D = w z = wyClock cycle: t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10
w: 0 1 0 1 1 0 1 1 1 0 1
z: 0 0 0 0 1 0 0 1 1 0 0
Present
state
Next state Output z
w = 0 w = 1 w = 0 w = 1
A
B
A B
A B
0 0
0 1
Present
state
Next state Output z
w = 0 w = 1 w = 0 w = 1
y Y Y z z
A
B
0
1
0 1
0 1
0 0
0 1
MATRUSRI
ENGINEERING COLLEGE
Outputvaluesaregeneratedusingstate&presentinputs
Statediagram StateTable
StateAssignedTable LogicDiagram
Y = D = w z = wyClock cycle: t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10
w: 0 1 0 1 1 0 1 1 1 0 1
z: 0 0 0 0 1 0 0 1 1 0 0
Present
state
Next state Output z
w = 0 w = 1 w = 0 w = 1
A
B
A B
A B
0 0
0 1
Present
state
Next state Output z
w = 0 w = 1 w = 0 w = 1
y Y Y z z
A
B
0
1
0 1
0 1
0 0
0 1
Timing Diagram of Mealy Machine
MATRUSRI
ENGINEERING COLLEGE
MealyimplementationismorecosteffectivethanMooreimplementation
•However,circuitcanbemodifiedsothatitbehaveslikeaMooremachine
Notehowoutputchangebasedonstateandinput
MATRUSRI
ENGINEERING COLLEGE
MealyimplementationismorecosteffectivethanMooreimplementation
•However,circuitcanbemodifiedsothatitbehaveslikeaMooremachine
Notehowoutputchangebasedonstateandinput
1.Moore machine produces an output over the change of transition states.
2.In mealymachine, the O/P depends upon present states and inputs.
3.The relationship that exists among the inputs, outputs, present states and
next states can be specified by either thestate tableor thestate diagram.
4.A state-transitiontable is a table showing what state a finite-state
machine will move to, based on the current state and other inputs.
Questions & Answers
MATRUSRI
ENGINEERING COLLEGE
2.In mealymachine, the O/P depends upon present states and inputs.
3.The relationship that exists among the inputs, outputs, present states and
next states can be specified by either thestate tableor thestate diagram.
4.A state-transitiontable is a table showing what state a finite-state
machine will move to, based on the current state and other inputs.
Questions & Answers
MATRUSRI
ENGINEERING COLLEGE
CONTENTS:
State Minimization
Partitioning Minimization Procedure
OUTCOMES:
StudentswillbeabletodesignamorecomplexFSMwithfewerflips-flops.
MODULE-III: State Minimization
MATRUSRI
ENGINEERING COLLEGE
State Minimization
Partitioning Minimization Procedure
OUTCOMES:
StudentswillbeabletodesignamorecomplexFSMwithfewerflips-flops.
MODULE-III: State Minimization
MATRUSRI
ENGINEERING COLLEGE
State Minimization
MATRUSRI
ENGINEERING COLLEGE
TwostatesSiandSjaresaidtobeequivalentifandonlyifforeverypossible
inputsequence,thesameoutputsequencewillbeproducedregardlessof
whetherSiorSjistheinitialstate.
Lowerno.ofstates=>lowerno.ofFFs
Solvedusing“partitioningminimizationprocedure”
Partition:Asetofstates
Apartitionconsistsofoneormoreblocks,whereeachblockcomprisesa
subsetofstatesthatmaybeequivalent,butthestatesinagivenblockare
definitelynotequivalenttothestatesinotherblocks.
Statesinapartitionmaybeequivalent
Notequivalenttostatesinotherpartitions
MATRUSRI
ENGINEERING COLLEGE
TwostatesSiandSjaresaidtobeequivalentifandonlyifforeverypossible
inputsequence,thesameoutputsequencewillbeproducedregardlessof
whetherSiorSjistheinitialstate.
Lowerno.ofstates=>lowerno.ofFFs
Solvedusing“partitioningminimizationprocedure”
Partition:Asetofstates
Apartitionconsistsofoneormoreblocks,whereeachblockcomprisesa
subsetofstatesthatmaybeequivalent,butthestatesinagivenblockare
definitelynotequivalenttothestatesinotherblocks.
Statesinapartitionmaybeequivalent
Notequivalenttostatesinotherpartitions
State Minimization
MATRUSRI
ENGINEERING COLLEGE
•P1 = (ABCDEFG)
Partition based on output z
•P2 = (ABD)(CEFG),
Partition based on 0-& 1-successor for
block (ABD) & (CEFG)
•P3 = (ABD)(CEG)(F),
Partition based on 0-& 1-successor for
block (ABD) & (CEG),
•P4 = (AD)(B)(CEG)(F)
Partition based on 0-& 1-successor for
block (AD) & (CEG), => Final
•Final Partitions: P5 = (AD)(B)(CEG)(F)
2 FFs are sufficient after state minimization instead of 3Present
state
Next state Output
z w = 0 w = 1
A
B
C
D
E
F
G
B C
D F
F E
B G
F C
E D
F G
1
1
0
1
0
0
0
Present
state
Next state Output
z w = 0 w = 1
A
B
C
F
B C
A F
F C
C A
1
1
0
0
MATRUSRI
ENGINEERING COLLEGE
•P1 = (ABCDEFG)
Partition based on output z
•P2 = (ABD)(CEFG),
Partition based on 0-& 1-successor for
block (ABD) & (CEFG)
•P3 = (ABD)(CEG)(F),
Partition based on 0-& 1-successor for
block (ABD) & (CEG),
•P4 = (AD)(B)(CEG)(F)
Partition based on 0-& 1-successor for
block (AD) & (CEG), => Final
•Final Partitions: P5 = (AD)(B)(CEG)(F)
2 FFs are sufficient after state minimization instead of 3Present
state
Next state Output
z w = 0 w = 1
A
B
C
D
E
F
G
B C
D F
F E
B G
F C
E D
F G
1
1
0
1
0
0
0
Present
state
Next state Output
z w = 0 w = 1
A
B
C
F
B C
A F
F C
C A
1
1
0
0
Incompletely Specified FSMs
MATRUSRI
ENGINEERING COLLEGE
Thepartitioningschemeforminimizationofstatesworkswellwhenall
entriesinthestatetablearespecified.FSMsofthistypearesaidtobe
completelyspecified.
Ifoneormoreentriesinthestatetablearenotspecified,correspondingto
don’t-careconditions,thentheFSMissaidtobeincompletelyspecified.
Affectsthenumberofminimizedstates
Assumex’sarezeros:
P1=(ABCDEFG)
P2=(ABDG)(CEF),
P3=(AB)(D)(G)(CE)(F),
P4=(A)(B)(D)(G)(CE)(F),
P5=P4=>6states
Assumex’sareones:
P1=(ABCDEFG)
P2=(AD)(BCEFG),
P3=(AD)(B)(CEFG),
P4=(AD)(B)(CEG)(F),
P5=P4=>4statesPresent
state
Next state Output z
w = 0 w = 1 w = 0 w = 1
A
B
C
D
E
F
G
B C
D -
F E
B G
F C
E D
F -
0 0
0 -
0 1
0 0
0 1
0 1
0 -
MATRUSRI
ENGINEERING COLLEGE
Thepartitioningschemeforminimizationofstatesworkswellwhenall
entriesinthestatetablearespecified.FSMsofthistypearesaidtobe
completelyspecified.
Ifoneormoreentriesinthestatetablearenotspecified,correspondingto
don’t-careconditions,thentheFSMissaidtobeincompletelyspecified.
Affectsthenumberofminimizedstates
Assumex’sarezeros:
P1=(ABCDEFG)
P2=(ABDG)(CEF),
P3=(AB)(D)(G)(CE)(F),
P4=(A)(B)(D)(G)(CE)(F),
P5=P4=>6states
Assumex’sareones:
P1=(ABCDEFG)
P2=(AD)(BCEFG),
P3=(AD)(B)(CEFG),
P4=(AD)(B)(CEG)(F),
P5=P4=>4statesPresent
state
Next state Output z
w = 0 w = 1 w = 0 w = 1
A
B
C
D
E
F
G
B C
D -
F E
B G
F C
E D
F -
0 0
0 -
0 1
0 0
0 1
0 1
0 -
1.StateMinimizingreducesthenumberofflips-flopsusedintheFSM.
2.StateMinimizingreducesthecomplexityofthecombinationalcircuit
neededintheFSM.
3.Bystateminimization,twodifferentFSMsmayexhibitidenticalbehavior
intermsoftheoutputsproducedinresponsetoallpossibleinputs.
4.Ifoneormoreentriesinthestatetablearenotspecified,correspondingto
don’t-careconditions,thentheFSMissaidtobeincompletelyspecified.
Questions & Answers
MATRUSRI
ENGINEERING COLLEGE
2.StateMinimizingreducesthecomplexityofthecombinationalcircuit
neededintheFSM.
3.Bystateminimization,twodifferentFSMsmayexhibitidenticalbehavior
intermsoftheoutputsproducedinresponsetoallpossibleinputs.
4.Ifoneormoreentriesinthestatetablearenotspecified,correspondingto
don’t-careconditions,thentheFSMissaidtobeincompletelyspecified.
Questions & Answers
MATRUSRI
ENGINEERING COLLEGE
CONTENTS:
Moore FSM Model
Mealy FSM Model
OUTCOMES:
Studentswillbeabletowriteaverilogcodeforanysequencedetector.
MODULE-IV: Sequence detector with
verilogHDL modeling
MATRUSRI
ENGINEERING COLLEGE
Moore FSM Model
Mealy FSM Model
OUTCOMES:
Studentswillbeabletowriteaverilogcodeforanysequencedetector.
MODULE-IV: Sequence detector with
verilogHDL modeling
MATRUSRI
ENGINEERING COLLEGE
module simple (Clock, Resetn, w, z);
input Clock, Resetn, w;
output z;
reg[2:1] y, Y;
parameter [2:1] A = 2'b00, B = 2'b01, C = 2'b10;
always @(w or y)
case (y)
A: if (w) Y = B;
else Y = A;
B: if (w) Y = C;
else Y = A;
C: if (w) Y = C;
else Y = A;
default: Y = 2'bxx;
endcase
always @(negedgeResetnor posedgeClock)
if (Resetn== 0)
y <= A;
else
y <= Y;
assign z = (y == C);
endmodule
Moore FSM Model
MATRUSRI
ENGINEERING COLLEGE
input Clock, Resetn, w;
output z;
reg[2:1] y, Y;
parameter [2:1] A = 2'b00, B = 2'b01, C = 2'b10;
always @(w or y)
case (y)
A: if (w) Y = B;
else Y = A;
B: if (w) Y = C;
else Y = A;
C: if (w) Y = C;
else Y = A;
default: Y = 2'bxx;
endcase
always @(negedgeResetnor posedgeClock)
if (Resetn== 0)
y <= A;
else
y <= Y;
assign z = (y == C);
endmodule
Moore FSM Model
MATRUSRI
ENGINEERING COLLEGE
MATRUSRI
ENGINEERING COLLEGE
module mealy (Clock, Resetn, w, z);
input Clock, Resetn, w;
output z;
regy, Y, z;
parameter A = 0, B = 1;
always @(w or y)
case (y)
A: if (w) begin z = 0; Y = B; end
else begin z = 0; Y = A; end
B: if (w) begin z = 1; Y = B; end
else begin z = 0; Y = A; end
endcase
always @(negedgeResetnor posedgeClock)
if (Resetn== 0)
y <= A;
else
y <= Y;
endmodule
Mealy FSM Model
ENGINEERING COLLEGE
module mealy (Clock, Resetn, w, z);
input Clock, Resetn, w;
output z;
regy, Y, z;
parameter A = 0, B = 1;
always @(w or y)
case (y)
A: if (w) begin z = 0; Y = B; end
else begin z = 0; Y = A; end
B: if (w) begin z = 1; Y = B; end
else begin z = 0; Y = A; end
endcase
always @(negedgeResetnor posedgeClock)
if (Resetn== 0)
y <= A;
else
y <= Y;
endmodule
Mealy FSM Model
1.Mealy machine will have same or fewer states than Moore machine.
2.In MooreMachine both output and state change synchronous to the clock
edge.
3.Moore Machine requires morehardware to design than mealy machine.
4.In Mealymachine, asynchronous output generation through the state
changes synchronous to the clock.
Questions & Answers
MATRUSRI
ENGINEERING COLLEGE
2.In MooreMachine both output and state change synchronous to the clock
edge.
3.Moore Machine requires morehardware to design than mealy machine.
4.In Mealymachine, asynchronous output generation through the state
changes synchronous to the clock.
Questions & Answers
MATRUSRI
ENGINEERING COLLEGE
CONTENTS:
Modulo –8 Counter
D Flip-flop
JK Flip-flop
Verilogcode
OUTCOMES:
Studentswillbeabletodesigndifferentcountersusingsequentialciruit
approach.
MODULE-V: Modulo-8 Counter Using the
Sequential Circuit Approach
MATRUSRI
ENGINEERING COLLEGE
Modulo –8 Counter
D Flip-flop
JK Flip-flop
Verilogcode
OUTCOMES:
Studentswillbeabletodesigndifferentcountersusingsequentialciruit
approach.
MODULE-V: Modulo-8 Counter Using the
Sequential Circuit Approach
MATRUSRI
ENGINEERING COLLEGE
Modulo-8 Counter
MATRUSRI
ENGINEERING COLLEGE
Mod8counter(0,1,..7,0,1..){MooreDesign}
StateDiagram:
Stateasignedtable
Statetable
Present
state
Next stateOutput
w= 0 w= 1
A
B
C
D
E
F
G
H
A B
B C
C D
D E
E F
F G
G H
H A
1
2
3
4
5
6
7
8
Present
state
y
2y
1y
0
Next stateOutput
z
2z
1z
0w= 0 w= 1
Y
2Y
1Y
0Y
2Y
1Y
0
A
B
C
D
E
F
G
H
000
001
010
011
100
101
110
111
0 0 0 0 0 1
0 0 1 0 1 0
0 1 0 0 1 1
0 1 1 1 0 0
1 0 0 1 0 1
1 0 1 1 1 0
1 1 0 1 1 1
1 1 1 0 0 0
000
001
010
011
100
101
110
111
MATRUSRI
ENGINEERING COLLEGE
Mod8counter(0,1,..7,0,1..){MooreDesign}
StateDiagram:
Stateasignedtable
Statetable
Present
state
Next stateOutput
w= 0 w= 1
A
B
C
D
E
F
G
H
A B
B C
C D
D E
E F
F G
G H
H A
1
2
3
4
5
6
7
8
Present
state
y
2y
1y
0
Next stateOutput
z
2z
1z
0w= 0 w= 1
Y
2Y
1Y
0Y
2Y
1Y
0
A
B
C
D
E
F
G
H
000
001
010
011
100
101
110
111
0 0 0 0 0 1
0 0 1 0 1 0
0 1 0 0 1 1
0 1 1 1 0 0
1 0 0 1 0 1
1 0 1 1 1 0
1 1 0 1 1 1
1 1 1 0 0 0
000
001
010
011
100
101
110
111
Implementation Using D-Type Flip-Flops
MATRUSRI
ENGINEERING COLLEGE
21010210210210210212022
1010101010100111
0000
yywyyywyyyywyywyyyywyyywyyyyywD
ywyywyyywywyyywywyyyywD
ywywywD
MATRUSRI
ENGINEERING COLLEGE
21010210210210210212022
1010101010100111
0000
yywyyywyyyywyywyyyywyyywyyyyywD
ywyywyyywywyyywywyyyywD
ywywywD
Implementation Using D-Type Flip-Flops
MATRUSRI
ENGINEERING COLLEGE
MATRUSRI
ENGINEERING COLLEGE
Implementation Using JK Flip-Flops
MATRUSRI
ENGINEERING COLLEGE
Excitationtable
Present
state
y
2y
1y
0
Flip-flop inputs Count
z
2z
1z
0w = 0 w = 1
Y
2Y
1Y
0J
2K
2J
1K
1J
0K
0Y
2Y
1Y
0J
2K
2J
1K
1J
0K
0
000
001
010
011
100
101
110
111
000
001
010
011
100
101
110
111
0d 0d0d
0d 0dd0
0d d0 0d
0d d0 d0
d0 0d 0d
d0 0d d0
d0 d00d
d0 d0d0
001
010
011
100
101
110
111
000
0d 0d1d
0d 1d d1
0d d0 1d
1d d1 d1
d0 0d 1d
d0 1d d1
d0 d01d
d1 d1d1
000
001
010
011
100
101
110
111
MATRUSRI
ENGINEERING COLLEGE
Excitationtable
Present
state
y
2y
1y
0
Flip-flop inputs Count
z
2z
1z
0w = 0 w = 1
Y
2Y
1Y
0J
2K
2J
1K
1J
0K
0Y
2Y
1Y
0J
2K
2J
1K
1J
0K
0
000
001
010
011
100
101
110
111
000
001
010
011
100
101
110
111
0d 0d0d
0d 0dd0
0d d0 0d
0d d0 d0
d0 0d 0d
d0 0d d0
d0 d00d
d0 d0d0
001
010
011
100
101
110
111
000
0d 0d1d
0d 1d d1
0d d0 1d
1d d1 d1
d0 0d 1d
d0 1d d1
d0 d01d
d1 d1d1
000
001
010
011
100
101
110
111
Implementation Using JK Flip-Flops
MATRUSRI
ENGINEERING COLLEGE
MATRUSRI
ENGINEERING COLLEGE
VerilogImplementation
MATRUSRI
ENGINEERING COLLEGE
moduleupdowncount(
q,reset,s,clk,m
);
outputreg[2:0]q;
inputreset,clk;
always@(posedgeclk)
begin
if(reset==1)
q<=0;
else
case(m)
0:q=q+1;
1:q=q-1;
endcase
end
endmodule
Testbench:
moduleupdowncounttest_v;
regreset,clk,m;
wire[2:0]q;
updowncountuut(
.q(q),.reset(reset),.s(s),.clk(clk),.m(m)
);
always#5clk=~clk;
initialbegin
#400$finish;
end
initialbegin
reset=1;clk=1;m=0;
#10reset=0;
#150reset=1;
#20reset=0;m=1;
end
endmodule
MATRUSRI
ENGINEERING COLLEGE
moduleupdowncount(
q,reset,s,clk,m
);
outputreg[2:0]q;
inputreset,clk;
always@(posedgeclk)
begin
if(reset==1)
q<=0;
else
case(m)
0:q=q+1;
1:q=q-1;
endcase
end
endmodule
Testbench:
moduleupdowncounttest_v;
regreset,clk,m;
wire[2:0]q;
updowncountuut(
.q(q),.reset(reset),.s(s),.clk(clk),.m(m)
);
always#5clk=~clk;
initialbegin
#400$finish;
end
initialbegin
reset=1;clk=1;m=0;
#10reset=0;
#150reset=1;
#20reset=0;m=1;
end
endmodule
1.AcounterisaMooremachine.
2.Theoutputsignalsarespecifiedasdependingonlyonthestateofthe
counteratagiventime.
3.Theflip-flopsmustbeedgetriggeredtoensurethatonlyonetransition
takesplaceduringasingleclockcycle.
4.CanattachacombinationalcircuittoaDflip-floptoconvertitintoJKflip-
flop.
Questions & Answers
MATRUSRI
ENGINEERING COLLEGE
2.Theoutputsignalsarespecifiedasdependingonlyonthestateofthe
counteratagiventime.
3.Theflip-flopsmustbeedgetriggeredtoensurethatonlyonetransition
takesplaceduringasingleclockcycle.
4.CanattachacombinationalcircuittoaDflip-floptoconvertitintoJKflip-
flop.
Questions & Answers
MATRUSRI
ENGINEERING COLLEGE
CONTENTS:
One-Hot Encoding
OUTCOMES:
StudentswillbeabletodesignFSMmodelsforcompletelyandincompletely
specifiedcircuits.
MODULE-VI: One-Hot Encoding
MATRUSRI
ENGINEERING COLLEGE
One-Hot Encoding
OUTCOMES:
StudentswillbeabletodesignFSMmodelsforcompletelyandincompletely
specifiedcircuits.
MODULE-VI: One-Hot Encoding
MATRUSRI
ENGINEERING COLLEGE
One-Hot Encoding
MATRUSRI
ENGINEERING COLLEGE
•Asanalternativestateassignment,wecanuseone-hotencoding:
UseasmanyFFsasstates
•Inone-hotencodingmethod,foreachstateallbutoneofthestatevariables
areequalto0.Thevariablewhosevalueis1isdeemedtobe“hot.”
•Usuallyleadstosimpleroutputexpressions,fastercircuits
Y
1=w͞
Y
2=wy
1
Y
3=wy͞
1
z=y3
Present state
y
3y
2y
1
Next stateOutput
Zw = 0w = 1
Y
3Y
2Y
1 Y
3Y
2Y
1
001
010
100
001 010
001 100
001 100
0
0
1Present
state
Next state Output
Z w = 0 w = 1
A
B
C
A B
A C
A C
0
0
1
MATRUSRI
ENGINEERING COLLEGE
•Asanalternativestateassignment,wecanuseone-hotencoding:
UseasmanyFFsasstates
•Inone-hotencodingmethod,foreachstateallbutoneofthestatevariables
areequalto0.Thevariablewhosevalueis1isdeemedtobe“hot.”
•Usuallyleadstosimpleroutputexpressions,fastercircuits
Y
1=w͞
Y
2=wy
1
Y
3=wy͞
1
z=y3
Present state
y
3y
2y
1
Next stateOutput
Zw = 0w = 1
Y
3Y
2Y
1 Y
3Y
2Y
1
001
010
100
001 010
001 100
001 100
0
0
1Present
state
Next state Output
Z w = 0 w = 1
A
B
C
A B
A C
A C
0
0
1
1.The variable whose value is 1 is deemed to be hot.
2.One-hot state assignment leads to simpler output expressions than do
assignments with the minimal number of state variables.
3.Simpler output expressions may lead to a fastercircuit.
Questions & Answers
MATRUSRI
ENGINEERING COLLEGE
2.One-hot state assignment leads to simpler output expressions than do
assignments with the minimal number of state variables.
3.Simpler output expressions may lead to a fastercircuit.
Questions & Answers
MATRUSRI
ENGINEERING COLLEGE
CONTENTS:
Analysis of Synchronous Circuits
OUTCOMES:
StudentswillbeabletoanalysisofvariousSynchronousCircuits.
MODULE-VII: Analysis of Synchronous
Circuits
MATRUSRI
ENGINEERING COLLEGE
Analysis of Synchronous Circuits
OUTCOMES:
StudentswillbeabletoanalysisofvariousSynchronousCircuits.
MODULE-VII: Analysis of Synchronous
Circuits
MATRUSRI
ENGINEERING COLLEGE
Analysis of Synchronous Circuits
MATRUSRI
ENGINEERING COLLEGE
Analysisisthereverseofsynthesis:Givenacircuit,findoutwhatdoesitdo
Reversesynthesissteps:
•Constructstatetable(FFs’typeisafactor)
•Symbolicstatetable
•Statediagram
State assigned table
State table21
212
211
yyz
wywyY
wyywY
Present
state
Next stateOutput
Zw= 0 w= 1
A
B
C
D
A C
A D
A B
A D
0
0
0
1
Present
state
y
1y
2
Next stateOutput
zw= 0 w= 1
Y
1Y
2 Y
1Y
2
00
01
10
11
00 10
00 11
00 01
00 11
0
0
0
1
MATRUSRI
ENGINEERING COLLEGE
Analysisisthereverseofsynthesis:Givenacircuit,findoutwhatdoesitdo
Reversesynthesissteps:
•Constructstatetable(FFs’typeisafactor)
•Symbolicstatetable
•Statediagram
State assigned table
State table21
212
211
yyz
wywyY
wyywY
Present
state
Next stateOutput
Zw= 0 w= 1
A
B
C
D
A C
A D
A B
A D
0
0
0
1
Present
state
y
1y
2
Next stateOutput
zw= 0 w= 1
Y
1Y
2 Y
1Y
2
00
01
10
11
00 10
00 11
00 01
00 11
0
0
0
1
Analysis of Synchronous Circuits
MATRUSRI
ENGINEERING COLLEGE
Excitation table State tablewK
wyJ
ywK
wJ
2
12
21
1
Present
state
y
1y
2
Next state Output
zw= 0 w= 1
J
2K
2 J
1K
1 J
2K
2 J
1K
1
00
01
10
11
01 01 00 11
01 01 00 10
01 01 10 11
01 01 10 10
0
0
0
1
Present
state
Next state Output
zw= 0 w= 1
A
B
C
D
B BA D
B BA C
B BC D
B BC C
0
0
0
1
MATRUSRI
ENGINEERING COLLEGE
Excitation table State tablewK
wyJ
ywK
wJ
2
12
21
1
Present
state
y
1y
2
Next state Output
zw= 0 w= 1
J
2K
2 J
1K
1 J
2K
2 J
1K
1
00
01
10
11
01 01 00 11
01 01 00 10
01 01 10 11
01 01 10 10
0
0
0
1
Present
state
Next state Output
zw= 0 w= 1
A
B
C
D
B BA D
B BA C
B BC D
B BC C
0
0
0
1
1.The analysis task is much simpler than the synthesis task.
2.To analyze a circuit, reverse the steps of the synthesis process.
3.To design a synchronous sequential circuit, the designer has to be able to
analyzethe behaviorof an existing circuit.
Questions & Answers
MATRUSRI
ENGINEERING COLLEGE
2.To analyze a circuit, reverse the steps of the synthesis process.
3.To design a synchronous sequential circuit, the designer has to be able to
analyzethe behaviorof an existing circuit.
Questions & Answers
MATRUSRI
ENGINEERING COLLEGE
CONTENTS:
Serial Adder
Mealy-Type FSM
Moore-Type FSM
VerilogCode
OUTCOMES:
Student will able to design and implement a FSM for serial adder
MODULE-VIII: Additional Topic
MATRUSRI
ENGINEERING COLLEGE
Serial Adder
Mealy-Type FSM
Moore-Type FSM
VerilogCode
OUTCOMES:
Student will able to design and implement a FSM for serial adder
MODULE-VIII: Additional Topic
MATRUSRI
ENGINEERING COLLEGE
Mealy-Type FSM
MATRUSRI
ENGINEERING COLLEGE
State Diagram State Table
Present
state
Next state Output
ab= 00 01 10 1100 01 10 11
G
H
G G G H
G H H H
0 1 1 0
1 0 0 1
MATRUSRI
ENGINEERING COLLEGE
State Diagram State Table
Present
state
Next state Output
ab= 00 01 10 1100 01 10 11
G
H
G G G H
G H H H
0 1 1 0
1 0 0 1
Mealy-Type FSM
MATRUSRI
ENGINEERING COLLEGE
State Assigned Table Output equations:
Circuit Diagram
Present
state
Next state Output s
ab= 00 01 10 1100 01 10 11
y Y S
0
1
0 0 0 1
0 1 1 1
0 1 1 0
1 0 0 1 ybaS
byayabY
MATRUSRI
ENGINEERING COLLEGE
State Assigned Table Output equations:
Circuit Diagram
Present
state
Next state Output s
ab= 00 01 10 1100 01 10 11
y Y S
0
1
0 0 0 1
0 1 1 1
0 1 1 0
1 0 0 1 ybaS
byayabY
Moore-Type FSM
MATRUSRI
ENGINEERING COLLEGE
State Diagram State Table
State Assigned Table
Circuit Diagram
Present
state
Next state Output
S ab = 00 01 10 11
G0
G1
H0
H1
G0 G1 G1 H0
G0 G1 G1 H0
G1 H0 H0 H1
G1 H0 H0 H1
0
1
0
1
Present
state
y
2y
1
Next state Output
sab= 00 01 10 11
Y
2Y
1
00
01
10
11
00 01 01 10
00 01 01 10
01 10 10 11
01 10 10 11
0
1
0
11
222
21
ys
byayabY
ybaY
MATRUSRI
ENGINEERING COLLEGE
State Diagram State Table
State Assigned Table
Circuit Diagram
Present
state
Next state Output
S ab = 00 01 10 11
G0
G1
H0
H1
G0 G1 G1 H0
G0 G1 G1 H0
G1 H0 H0 H1
G1 H0 H0 H1
0
1
0
1
Present
state
y
2y
1
Next state Output
sab= 00 01 10 11
Y
2Y
1
00
01
10
11
00 01 01 10
00 01 01 10
01 10 10 11
01 10 10 11
0
1
0
11
222
21
ys
byayabY
ybaY
module serialadder(A, B, Reset, Clock, Sum);
input [3:0] A, B;
input Reset, Clock;
output wire [3:0] Sum;
reg[3:0] Count;
regs, y, Y;
wire [3:0] QA, QB;
wire Run;
parameter G = 1'b0, H = 1'b1;
shift shift_A(A, Reset, 1'b1, 1'b0, Clock, QA);
shift shift_B(B, Reset, 1'b1, 1'b0, Clock, QB);
shift shift_S(4'b0, Reset, Run, s, Clock, Sum);
always @(QA, QB, y)
case (y)
G: begin
s = QA[0]^QB[0];
if (QA[0] & QB[0]) Y = H;
else Y = G;
end
VerilogCode
MATRUSRI
ENGINEERING COLLEGE
H: begin
s = QA[0]~^QB[0];
if (~QA[0] & ~QB[0])
Y = G;
else
Y = H;
end
default: Y = G;
endcase
always @(posedgeClock)
if (Reset)
y <= G;
else
y <= Y;
always @(posedgeClock)
if (Reset) Count = 4;
else if (Run) Count = Count-1;
assign Run =|Count;
endmodule
input [3:0] A, B;
input Reset, Clock;
output wire [3:0] Sum;
reg[3:0] Count;
regs, y, Y;
wire [3:0] QA, QB;
wire Run;
parameter G = 1'b0, H = 1'b1;
shift shift_A(A, Reset, 1'b1, 1'b0, Clock, QA);
shift shift_B(B, Reset, 1'b1, 1'b0, Clock, QB);
shift shift_S(4'b0, Reset, Run, s, Clock, Sum);
always @(QA, QB, y)
case (y)
G: begin
s = QA[0]^QB[0];
if (QA[0] & QB[0]) Y = H;
else Y = G;
end
VerilogCode
MATRUSRI
ENGINEERING COLLEGE
H: begin
s = QA[0]~^QB[0];
if (~QA[0] & ~QB[0])
Y = G;
else
Y = H;
end
default: Y = G;
endcase
always @(posedgeClock)
if (Reset)
y <= G;
else
y <= Y;
always @(posedgeClock)
if (Reset) Count = 4;
else if (Run) Count = Count-1;
assign Run =|Count;
endmodule
1.In a serialadder, bits are added a pair at a time.
2.Fast adders are morecomplex and moreexpensive.
3.A serial adder is a cost-effectiveand less speed.
4.Moore-type circuit is delayed by one clock cycle with respect to the Mealy-
type sequential circuit.
Questions & Answers
MATRUSRI
ENGINEERING COLLEGE
2.Fast adders are morecomplex and moreexpensive.
3.A serial adder is a cost-effectiveand less speed.
4.Moore-type circuit is delayed by one clock cycle with respect to the Mealy-
type sequential circuit.
Questions & Answers
MATRUSRI
ENGINEERING COLLEGE
Question Bank
MATRUSRI
ENGINEERING COLLEGE
Short Answer Question
S.No Question
Blooms
Taxonomy
Level
Course
Outcome
1WriteVerilogmodelforJKflipflop. L2 CO3
2AnalyzetheGated-Dlatchcircuit. L2 CO3
3ExplainaboutStateassignmentproblem L1 CO3
4BrieflyexplainOnehotencoding. L2 CO3
5Briefoutthebasicdesignstepsfordesigning
SynchronousSequentialCircuits.
L1 CO3
6WriteshortnotesonincompletelyspecifiedFSM
model.
L1 CO3
7Differentiatebetweenlatchandflipflop. L1 CO3
8ExplainPartitioningMinimizationProcedure. L1 CO3
9Explaindifferencebetweenmealyandmoore
model.
L1 CO3
MATRUSRI
ENGINEERING COLLEGE
Short Answer Question
S.No Question
Blooms
Taxonomy
Level
Course
Outcome
1WriteVerilogmodelforJKflipflop. L2 CO3
2AnalyzetheGated-Dlatchcircuit. L2 CO3
3ExplainaboutStateassignmentproblem L1 CO3
4BrieflyexplainOnehotencoding. L2 CO3
5Briefoutthebasicdesignstepsfordesigning
SynchronousSequentialCircuits.
L1 CO3
6WriteshortnotesonincompletelyspecifiedFSM
model.
L1 CO3
7Differentiatebetweenlatchandflipflop. L1 CO3
8ExplainPartitioningMinimizationProcedure. L1 CO3
9Explaindifferencebetweenmealyandmoore
model.
L1 CO3
Question Bank
MATRUSRI
ENGINEERING COLLEGE
Long Answer Question
S.No Question
Blooms
Taxonomy
Level
Course
Outcome
1Brieflyexplainaboutshiftregisterandwriteaverilogcodefor
4bitshiftrightandleftregister.
L2 CO3
2Explainthestateminimizationprocessinsynchronous
sequentialcircuits.
L5 CO3
3Designasynchronous3bitup-downcounter.Writeverilog
codewithitstestbenchandwaveforms.
L1 CO3
4Designandwriteverilogcodeformodulo-8counterusing
sequentialapproachuseTflipflopmemoryelement..
L4 CO3
5Explainserialadderwithaneatdiagramandimplementin
VeriloglanguageusingMealyandmooretypemodels.
L2 CO3
6Design sequential circuit for given state table and write verilog
code in behavioural modeling
L1 CO3 X
0 1
A
B
C
D
E
B/0 E/0
A/1 C/1
B/0 C/1
C/0 E/0
D/1 A/0
MATRUSRI
ENGINEERING COLLEGE
Long Answer Question
S.No Question
Blooms
Taxonomy
Level
Course
Outcome
1Brieflyexplainaboutshiftregisterandwriteaverilogcodefor
4bitshiftrightandleftregister.
L2 CO3
2Explainthestateminimizationprocessinsynchronous
sequentialcircuits.
L5 CO3
3Designasynchronous3bitup-downcounter.Writeverilog
codewithitstestbenchandwaveforms.
L1 CO3
4Designandwriteverilogcodeformodulo-8counterusing
sequentialapproachuseTflipflopmemoryelement..
L4 CO3
5Explainserialadderwithaneatdiagramandimplementin
VeriloglanguageusingMealyandmooretypemodels.
L2 CO3
6Design sequential circuit for given state table and write verilog
code in behavioural modeling
L1 CO3 X
0 1
A
B
C
D
E
B/0 E/0
A/1 C/1
B/0 C/1
C/0 E/0
D/1 A/0
Question Bank
MATRUSRI
ENGINEERING COLLEGE
Long Answer Question
S.No Question
Blooms
Taxonomy
Level
Course
Outcome
7Performthepartitioningprocedureonthestatetableshown
below
L2 CO3
8Analyserthegivensynchronoussequentialcircuitandwriteits
veilogcode.
L5 CO3Present
state
Next State output
input=0 input = 1
A B C 1
B D F 1
C F E 0
D B G 1
E F C 0
F E D 0
G F G 0
MATRUSRI
ENGINEERING COLLEGE
Long Answer Question
S.No Question
Blooms
Taxonomy
Level
Course
Outcome
7Performthepartitioningprocedureonthestatetableshown
below
L2 CO3
8Analyserthegivensynchronoussequentialcircuitandwriteits
veilogcode.
L5 CO3Present
state
Next State output
input=0 input = 1
A B C 1
B D F 1
C F E 0
D B G 1
E F C 0
F E D 0
G F G 0
Assignment Questions
MATRUSRI
ENGINEERING COLLEGE
1.Design a counter which moves through the sequence 0,4,2,6,1,5,3,7,0,4
and so on using synchronous sequential circuit approach.
2.Design a Mealy and Moore type Sequence detector for detecting the
sequence 1010 and Implement in verilogHDL.
3.Reduce the state table given below and draw the minimized state diagram. Present
State
Next State Output (z)
Input (x) Input (x)
X = 0 X = 1 X = 0 X = 1
A A B 0 0
B D C 0 1
C F E 0 0
D D F 0 0
E B G 0 0
F G C 0 1
G A F 0 0
MATRUSRI
ENGINEERING COLLEGE
1.Design a counter which moves through the sequence 0,4,2,6,1,5,3,7,0,4
and so on using synchronous sequential circuit approach.
2.Design a Mealy and Moore type Sequence detector for detecting the
sequence 1010 and Implement in verilogHDL.
3.Reduce the state table given below and draw the minimized state diagram. Present
State
Next State Output (z)
Input (x) Input (x)
X = 0 X = 1 X = 0 X = 1
A A B 0 0
B D C 0 1
C F E 0 0
D D F 0 0
E B G 0 0
F G C 0 1
G A F 0 0
Assignment Questions
MATRUSRI
ENGINEERING COLLEGE
4.Analyser the given synchronous sequential circuit and write its veilogcode.
5.Design synchronous sequential circuit of state machine M1 shown using D
flip –flop. Assume state assignment as A = 00, B = 01and C= 10.
PS Next State , z
x = 0x = 1
A B, 0 A, 1
B C, 0 A, 1
C A,1 B, 0
MATRUSRI
ENGINEERING COLLEGE
4.Analyser the given synchronous sequential circuit and write its veilogcode.
5.Design synchronous sequential circuit of state machine M1 shown using D
flip –flop. Assume state assignment as A = 00, B = 01and C= 10.
PS Next State , z
x = 0x = 1
A B, 0 A, 1
B C, 0 A, 1
C A,1 B, 0
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